xref: /linux/drivers/tty/serial/mcf.c (revision e3b3d0f549c1d19b94e6ac55c66643166ea649ef) 
1 // SPDX-License-Identifier: GPL-2.0+
2 /****************************************************************************/
3 
4 /*
5  *	mcf.c -- Freescale ColdFire UART driver
6  *
7  *	(C) Copyright 2003-2007, Greg Ungerer <gerg@uclinux.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  */
14 
15 /****************************************************************************/
16 
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/console.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/serial.h>
25 #include <linux/serial_core.h>
26 #include <linux/io.h>
27 #include <linux/uaccess.h>
28 #include <linux/platform_device.h>
29 #include <asm/coldfire.h>
30 #include <asm/mcfsim.h>
31 #include <asm/mcfuart.h>
32 #include <asm/nettel.h>
33 
34 /****************************************************************************/
35 
36 /*
37  *	Some boards implement the DTR/DCD lines using GPIO lines, most
38  *	don't. Dummy out the access macros for those that don't. Those
39  *	that do should define these macros somewhere in there board
40  *	specific inlude files.
41  */
42 #if !defined(mcf_getppdcd)
43 #define	mcf_getppdcd(p)		(1)
44 #endif
45 #if !defined(mcf_getppdtr)
46 #define	mcf_getppdtr(p)		(1)
47 #endif
48 #if !defined(mcf_setppdtr)
49 #define	mcf_setppdtr(p, v)	do { } while (0)
50 #endif
51 
52 /****************************************************************************/
53 
54 /*
55  *	Local per-uart structure.
56  */
57 struct mcf_uart {
58 	struct uart_port	port;
59 	unsigned int		sigs;		/* Local copy of line sigs */
60 	unsigned char		imr;		/* Local IMR mirror */
61 };
62 
63 /****************************************************************************/
64 
65 static unsigned int mcf_tx_empty(struct uart_port *port)
66 {
67 	return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
68 		TIOCSER_TEMT : 0;
69 }
70 
71 /****************************************************************************/
72 
73 static unsigned int mcf_get_mctrl(struct uart_port *port)
74 {
75 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
76 	unsigned int sigs;
77 
78 	sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
79 		0 : TIOCM_CTS;
80 	sigs |= (pp->sigs & TIOCM_RTS);
81 	sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
82 	sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
83 
84 	return sigs;
85 }
86 
87 /****************************************************************************/
88 
89 static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
90 {
91 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
92 
93 	pp->sigs = sigs;
94 	mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
95 	if (sigs & TIOCM_RTS)
96 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
97 	else
98 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
99 }
100 
101 /****************************************************************************/
102 
103 static void mcf_start_tx(struct uart_port *port)
104 {
105 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
106 
107 	if (port->rs485.flags & SER_RS485_ENABLED) {
108 		/* Enable Transmitter */
109 		writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
110 		/* Manually assert RTS */
111 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
112 	}
113 	pp->imr |= MCFUART_UIR_TXREADY;
114 	writeb(pp->imr, port->membase + MCFUART_UIMR);
115 }
116 
117 /****************************************************************************/
118 
119 static void mcf_stop_tx(struct uart_port *port)
120 {
121 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
122 
123 	pp->imr &= ~MCFUART_UIR_TXREADY;
124 	writeb(pp->imr, port->membase + MCFUART_UIMR);
125 }
126 
127 /****************************************************************************/
128 
129 static void mcf_stop_rx(struct uart_port *port)
130 {
131 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
132 
133 	pp->imr &= ~MCFUART_UIR_RXREADY;
134 	writeb(pp->imr, port->membase + MCFUART_UIMR);
135 }
136 
137 /****************************************************************************/
138 
139 static void mcf_break_ctl(struct uart_port *port, int break_state)
140 {
141 	unsigned long flags;
142 
143 	spin_lock_irqsave(&port->lock, flags);
144 	if (break_state == -1)
145 		writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
146 	else
147 		writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
148 	spin_unlock_irqrestore(&port->lock, flags);
149 }
150 
151 /****************************************************************************/
152 
153 static int mcf_startup(struct uart_port *port)
154 {
155 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
156 	unsigned long flags;
157 
158 	spin_lock_irqsave(&port->lock, flags);
159 
160 	/* Reset UART, get it into known state... */
161 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
162 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
163 
164 	/* Enable the UART transmitter and receiver */
165 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
166 		port->membase + MCFUART_UCR);
167 
168 	/* Enable RX interrupts now */
169 	pp->imr = MCFUART_UIR_RXREADY;
170 	writeb(pp->imr, port->membase + MCFUART_UIMR);
171 
172 	spin_unlock_irqrestore(&port->lock, flags);
173 
174 	return 0;
175 }
176 
177 /****************************************************************************/
178 
179 static void mcf_shutdown(struct uart_port *port)
180 {
181 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
182 	unsigned long flags;
183 
184 	spin_lock_irqsave(&port->lock, flags);
185 
186 	/* Disable all interrupts now */
187 	pp->imr = 0;
188 	writeb(pp->imr, port->membase + MCFUART_UIMR);
189 
190 	/* Disable UART transmitter and receiver */
191 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
192 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
193 
194 	spin_unlock_irqrestore(&port->lock, flags);
195 }
196 
197 /****************************************************************************/
198 
199 static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
200 	struct ktermios *old)
201 {
202 	unsigned long flags;
203 	unsigned int baud, baudclk;
204 #if defined(CONFIG_M5272)
205 	unsigned int baudfr;
206 #endif
207 	unsigned char mr1, mr2;
208 
209 	baud = uart_get_baud_rate(port, termios, old, 0, 230400);
210 #if defined(CONFIG_M5272)
211 	baudclk = (MCF_BUSCLK / baud) / 32;
212 	baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
213 #else
214 	baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
215 #endif
216 
217 	mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
218 	mr2 = 0;
219 
220 	switch (termios->c_cflag & CSIZE) {
221 	case CS5: mr1 |= MCFUART_MR1_CS5; break;
222 	case CS6: mr1 |= MCFUART_MR1_CS6; break;
223 	case CS7: mr1 |= MCFUART_MR1_CS7; break;
224 	case CS8:
225 	default:  mr1 |= MCFUART_MR1_CS8; break;
226 	}
227 
228 	if (termios->c_cflag & PARENB) {
229 		if (termios->c_cflag & CMSPAR) {
230 			if (termios->c_cflag & PARODD)
231 				mr1 |= MCFUART_MR1_PARITYMARK;
232 			else
233 				mr1 |= MCFUART_MR1_PARITYSPACE;
234 		} else {
235 			if (termios->c_cflag & PARODD)
236 				mr1 |= MCFUART_MR1_PARITYODD;
237 			else
238 				mr1 |= MCFUART_MR1_PARITYEVEN;
239 		}
240 	} else {
241 		mr1 |= MCFUART_MR1_PARITYNONE;
242 	}
243 
244 	/*
245 	 * FIXME: port->read_status_mask and port->ignore_status_mask
246 	 * need to be initialized based on termios settings for
247 	 * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
248 	 */
249 
250 	if (termios->c_cflag & CSTOPB)
251 		mr2 |= MCFUART_MR2_STOP2;
252 	else
253 		mr2 |= MCFUART_MR2_STOP1;
254 
255 	if (termios->c_cflag & CRTSCTS) {
256 		mr1 |= MCFUART_MR1_RXRTS;
257 		mr2 |= MCFUART_MR2_TXCTS;
258 	}
259 
260 	spin_lock_irqsave(&port->lock, flags);
261 	if (port->rs485.flags & SER_RS485_ENABLED) {
262 		dev_dbg(port->dev, "Setting UART to RS485\n");
263 		mr2 |= MCFUART_MR2_TXRTS;
264 	}
265 
266 	uart_update_timeout(port, termios->c_cflag, baud);
267 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
268 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
269 	writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
270 	writeb(mr1, port->membase + MCFUART_UMR);
271 	writeb(mr2, port->membase + MCFUART_UMR);
272 	writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
273 	writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
274 #if defined(CONFIG_M5272)
275 	writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
276 #endif
277 	writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
278 		port->membase + MCFUART_UCSR);
279 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
280 		port->membase + MCFUART_UCR);
281 	spin_unlock_irqrestore(&port->lock, flags);
282 }
283 
284 /****************************************************************************/
285 
286 static void mcf_rx_chars(struct mcf_uart *pp)
287 {
288 	struct uart_port *port = &pp->port;
289 	unsigned char status, ch, flag;
290 
291 	while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
292 		ch = readb(port->membase + MCFUART_URB);
293 		flag = TTY_NORMAL;
294 		port->icount.rx++;
295 
296 		if (status & MCFUART_USR_RXERR) {
297 			writeb(MCFUART_UCR_CMDRESETERR,
298 				port->membase + MCFUART_UCR);
299 
300 			if (status & MCFUART_USR_RXBREAK) {
301 				port->icount.brk++;
302 				if (uart_handle_break(port))
303 					continue;
304 			} else if (status & MCFUART_USR_RXPARITY) {
305 				port->icount.parity++;
306 			} else if (status & MCFUART_USR_RXOVERRUN) {
307 				port->icount.overrun++;
308 			} else if (status & MCFUART_USR_RXFRAMING) {
309 				port->icount.frame++;
310 			}
311 
312 			status &= port->read_status_mask;
313 
314 			if (status & MCFUART_USR_RXBREAK)
315 				flag = TTY_BREAK;
316 			else if (status & MCFUART_USR_RXPARITY)
317 				flag = TTY_PARITY;
318 			else if (status & MCFUART_USR_RXFRAMING)
319 				flag = TTY_FRAME;
320 		}
321 
322 		if (uart_handle_sysrq_char(port, ch))
323 			continue;
324 		uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
325 	}
326 
327 	spin_unlock(&port->lock);
328 	tty_flip_buffer_push(&port->state->port);
329 	spin_lock(&port->lock);
330 }
331 
332 /****************************************************************************/
333 
334 static void mcf_tx_chars(struct mcf_uart *pp)
335 {
336 	struct uart_port *port = &pp->port;
337 	struct circ_buf *xmit = &port->state->xmit;
338 
339 	if (port->x_char) {
340 		/* Send special char - probably flow control */
341 		writeb(port->x_char, port->membase + MCFUART_UTB);
342 		port->x_char = 0;
343 		port->icount.tx++;
344 		return;
345 	}
346 
347 	while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
348 		if (xmit->head == xmit->tail)
349 			break;
350 		writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
351 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
352 		port->icount.tx++;
353 	}
354 
355 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
356 		uart_write_wakeup(port);
357 
358 	if (xmit->head == xmit->tail) {
359 		pp->imr &= ~MCFUART_UIR_TXREADY;
360 		writeb(pp->imr, port->membase + MCFUART_UIMR);
361 		/* Disable TX to negate RTS automatically */
362 		if (port->rs485.flags & SER_RS485_ENABLED)
363 			writeb(MCFUART_UCR_TXDISABLE,
364 				port->membase + MCFUART_UCR);
365 	}
366 }
367 
368 /****************************************************************************/
369 
370 static irqreturn_t mcf_interrupt(int irq, void *data)
371 {
372 	struct uart_port *port = data;
373 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
374 	unsigned int isr;
375 	irqreturn_t ret = IRQ_NONE;
376 
377 	isr = readb(port->membase + MCFUART_UISR) & pp->imr;
378 
379 	spin_lock(&port->lock);
380 	if (isr & MCFUART_UIR_RXREADY) {
381 		mcf_rx_chars(pp);
382 		ret = IRQ_HANDLED;
383 	}
384 	if (isr & MCFUART_UIR_TXREADY) {
385 		mcf_tx_chars(pp);
386 		ret = IRQ_HANDLED;
387 	}
388 	spin_unlock(&port->lock);
389 
390 	return ret;
391 }
392 
393 /****************************************************************************/
394 
395 static void mcf_config_port(struct uart_port *port, int flags)
396 {
397 	port->type = PORT_MCF;
398 	port->fifosize = MCFUART_TXFIFOSIZE;
399 
400 	/* Clear mask, so no surprise interrupts. */
401 	writeb(0, port->membase + MCFUART_UIMR);
402 
403 	if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
404 		printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
405 			"interrupt vector=%d\n", port->line, port->irq);
406 }
407 
408 /****************************************************************************/
409 
410 static const char *mcf_type(struct uart_port *port)
411 {
412 	return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
413 }
414 
415 /****************************************************************************/
416 
417 static int mcf_request_port(struct uart_port *port)
418 {
419 	/* UARTs always present */
420 	return 0;
421 }
422 
423 /****************************************************************************/
424 
425 static void mcf_release_port(struct uart_port *port)
426 {
427 	/* Nothing to release... */
428 }
429 
430 /****************************************************************************/
431 
432 static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
433 {
434 	if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
435 		return -EINVAL;
436 	return 0;
437 }
438 
439 /****************************************************************************/
440 
441 /* Enable or disable the RS485 support */
442 static int mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
443 {
444 	unsigned char mr1, mr2;
445 
446 	/* Get mode registers */
447 	mr1 = readb(port->membase + MCFUART_UMR);
448 	mr2 = readb(port->membase + MCFUART_UMR);
449 	if (rs485->flags & SER_RS485_ENABLED) {
450 		dev_dbg(port->dev, "Setting UART to RS485\n");
451 		/* Automatically negate RTS after TX completes */
452 		mr2 |= MCFUART_MR2_TXRTS;
453 	} else {
454 		dev_dbg(port->dev, "Setting UART to RS232\n");
455 		mr2 &= ~MCFUART_MR2_TXRTS;
456 	}
457 	writeb(mr1, port->membase + MCFUART_UMR);
458 	writeb(mr2, port->membase + MCFUART_UMR);
459 	port->rs485 = *rs485;
460 
461 	return 0;
462 }
463 
464 /****************************************************************************/
465 
466 /*
467  *	Define the basic serial functions we support.
468  */
469 static const struct uart_ops mcf_uart_ops = {
470 	.tx_empty	= mcf_tx_empty,
471 	.get_mctrl	= mcf_get_mctrl,
472 	.set_mctrl	= mcf_set_mctrl,
473 	.start_tx	= mcf_start_tx,
474 	.stop_tx	= mcf_stop_tx,
475 	.stop_rx	= mcf_stop_rx,
476 	.break_ctl	= mcf_break_ctl,
477 	.startup	= mcf_startup,
478 	.shutdown	= mcf_shutdown,
479 	.set_termios	= mcf_set_termios,
480 	.type		= mcf_type,
481 	.request_port	= mcf_request_port,
482 	.release_port	= mcf_release_port,
483 	.config_port	= mcf_config_port,
484 	.verify_port	= mcf_verify_port,
485 };
486 
487 static struct mcf_uart mcf_ports[4];
488 
489 #define	MCF_MAXPORTS	ARRAY_SIZE(mcf_ports)
490 
491 /****************************************************************************/
492 #if defined(CONFIG_SERIAL_MCF_CONSOLE)
493 /****************************************************************************/
494 
495 int __init early_mcf_setup(struct mcf_platform_uart *platp)
496 {
497 	struct uart_port *port;
498 	int i;
499 
500 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
501 		port = &mcf_ports[i].port;
502 
503 		port->line = i;
504 		port->type = PORT_MCF;
505 		port->mapbase = platp[i].mapbase;
506 		port->membase = (platp[i].membase) ? platp[i].membase :
507 			(unsigned char __iomem *) port->mapbase;
508 		port->iotype = SERIAL_IO_MEM;
509 		port->irq = platp[i].irq;
510 		port->uartclk = MCF_BUSCLK;
511 		port->flags = UPF_BOOT_AUTOCONF;
512 		port->rs485_config = mcf_config_rs485;
513 		port->ops = &mcf_uart_ops;
514 	}
515 
516 	return 0;
517 }
518 
519 /****************************************************************************/
520 
521 static void mcf_console_putc(struct console *co, const char c)
522 {
523 	struct uart_port *port = &(mcf_ports + co->index)->port;
524 	int i;
525 
526 	for (i = 0; (i < 0x10000); i++) {
527 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
528 			break;
529 	}
530 	writeb(c, port->membase + MCFUART_UTB);
531 	for (i = 0; (i < 0x10000); i++) {
532 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
533 			break;
534 	}
535 }
536 
537 /****************************************************************************/
538 
539 static void mcf_console_write(struct console *co, const char *s, unsigned int count)
540 {
541 	for (; (count); count--, s++) {
542 		mcf_console_putc(co, *s);
543 		if (*s == '\n')
544 			mcf_console_putc(co, '\r');
545 	}
546 }
547 
548 /****************************************************************************/
549 
550 static int __init mcf_console_setup(struct console *co, char *options)
551 {
552 	struct uart_port *port;
553 	int baud = CONFIG_SERIAL_MCF_BAUDRATE;
554 	int bits = 8;
555 	int parity = 'n';
556 	int flow = 'n';
557 
558 	if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
559 		co->index = 0;
560 	port = &mcf_ports[co->index].port;
561 	if (port->membase == 0)
562 		return -ENODEV;
563 
564 	if (options)
565 		uart_parse_options(options, &baud, &parity, &bits, &flow);
566 
567 	return uart_set_options(port, co, baud, parity, bits, flow);
568 }
569 
570 /****************************************************************************/
571 
572 static struct uart_driver mcf_driver;
573 
574 static struct console mcf_console = {
575 	.name		= "ttyS",
576 	.write		= mcf_console_write,
577 	.device		= uart_console_device,
578 	.setup		= mcf_console_setup,
579 	.flags		= CON_PRINTBUFFER,
580 	.index		= -1,
581 	.data		= &mcf_driver,
582 };
583 
584 static int __init mcf_console_init(void)
585 {
586 	register_console(&mcf_console);
587 	return 0;
588 }
589 
590 console_initcall(mcf_console_init);
591 
592 #define	MCF_CONSOLE	&mcf_console
593 
594 /****************************************************************************/
595 #else
596 /****************************************************************************/
597 
598 #define	MCF_CONSOLE	NULL
599 
600 /****************************************************************************/
601 #endif /* CONFIG_SERIAL_MCF_CONSOLE */
602 /****************************************************************************/
603 
604 /*
605  *	Define the mcf UART driver structure.
606  */
607 static struct uart_driver mcf_driver = {
608 	.owner		= THIS_MODULE,
609 	.driver_name	= "mcf",
610 	.dev_name	= "ttyS",
611 	.major		= TTY_MAJOR,
612 	.minor		= 64,
613 	.nr		= MCF_MAXPORTS,
614 	.cons		= MCF_CONSOLE,
615 };
616 
617 /****************************************************************************/
618 
619 static int mcf_probe(struct platform_device *pdev)
620 {
621 	struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev);
622 	struct uart_port *port;
623 	int i;
624 
625 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
626 		port = &mcf_ports[i].port;
627 
628 		port->line = i;
629 		port->type = PORT_MCF;
630 		port->mapbase = platp[i].mapbase;
631 		port->membase = (platp[i].membase) ? platp[i].membase :
632 			(unsigned char __iomem *) platp[i].mapbase;
633 		port->dev = &pdev->dev;
634 		port->iotype = SERIAL_IO_MEM;
635 		port->irq = platp[i].irq;
636 		port->uartclk = MCF_BUSCLK;
637 		port->ops = &mcf_uart_ops;
638 		port->flags = UPF_BOOT_AUTOCONF;
639 		port->rs485_config = mcf_config_rs485;
640 
641 		uart_add_one_port(&mcf_driver, port);
642 	}
643 
644 	return 0;
645 }
646 
647 /****************************************************************************/
648 
649 static int mcf_remove(struct platform_device *pdev)
650 {
651 	struct uart_port *port;
652 	int i;
653 
654 	for (i = 0; (i < MCF_MAXPORTS); i++) {
655 		port = &mcf_ports[i].port;
656 		if (port)
657 			uart_remove_one_port(&mcf_driver, port);
658 	}
659 
660 	return 0;
661 }
662 
663 /****************************************************************************/
664 
665 static struct platform_driver mcf_platform_driver = {
666 	.probe		= mcf_probe,
667 	.remove		= mcf_remove,
668 	.driver		= {
669 		.name	= "mcfuart",
670 	},
671 };
672 
673 /****************************************************************************/
674 
675 static int __init mcf_init(void)
676 {
677 	int rc;
678 
679 	printk("ColdFire internal UART serial driver\n");
680 
681 	rc = uart_register_driver(&mcf_driver);
682 	if (rc)
683 		return rc;
684 	rc = platform_driver_register(&mcf_platform_driver);
685 	if (rc) {
686 		uart_unregister_driver(&mcf_driver);
687 		return rc;
688 	}
689 	return 0;
690 }
691 
692 /****************************************************************************/
693 
694 static void __exit mcf_exit(void)
695 {
696 	platform_driver_unregister(&mcf_platform_driver);
697 	uart_unregister_driver(&mcf_driver);
698 }
699 
700 /****************************************************************************/
701 
702 module_init(mcf_init);
703 module_exit(mcf_exit);
704 
705 MODULE_AUTHOR("Greg Ungerer <gerg@uclinux.org>");
706 MODULE_DESCRIPTION("Freescale ColdFire UART driver");
707 MODULE_LICENSE("GPL");
708 MODULE_ALIAS("platform:mcfuart");
709 
710 /****************************************************************************/
711