1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bitops.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/i2c.h> 19 #include <linux/kconfig.h> 20 #include <linux/module.h> 21 #include <linux/property.h> 22 #include <linux/regmap.h> 23 #include <linux/serial_core.h> 24 #include <linux/serial.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 #include <linux/spi/spi.h> 28 #include <linux/uaccess.h> 29 30 #define MAX310X_NAME "max310x" 31 #define MAX310X_MAJOR 204 32 #define MAX310X_MINOR 209 33 #define MAX310X_UART_NRMAX 16 34 #define MAX310X_MAX_PORTS 4 /* Maximum number of UART ports per IC. */ 35 36 /* MAX310X register definitions */ 37 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 38 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 39 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 40 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 41 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 42 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 43 #define MAX310X_REG_05 (0x05) 44 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 45 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 46 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 47 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 48 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 49 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 50 #define MAX310X_LCR_REG (0x0b) /* LCR */ 51 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 52 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 53 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 54 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 55 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 56 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 57 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 58 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 59 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 60 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 61 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 62 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 63 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 64 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 65 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 66 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 67 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 68 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 69 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 70 #define MAX310X_REG_1F (0x1f) 71 #define MAX310X_EXTREG_START (0x20) /* Only relevant in SPI mode. */ 72 73 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 74 75 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 76 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 77 78 /* Extended registers */ 79 #define MAX310X_REVID_EXTREG (0x25) /* Revision ID 80 * (extended addressing space) 81 */ 82 /* IRQ register bits */ 83 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 84 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 85 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 86 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 87 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 88 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 89 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 90 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 91 92 /* LSR register bits */ 93 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 94 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 95 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 96 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 97 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 98 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 99 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 100 101 /* Special character register bits */ 102 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 103 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 104 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 105 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 106 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 107 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 108 109 /* Status register bits */ 110 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 111 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 112 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 113 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 114 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 115 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 116 117 /* MODE1 register bits */ 118 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 119 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 120 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 121 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 122 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 123 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 124 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 125 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 126 127 /* MODE2 register bits */ 128 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 129 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 130 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 131 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 132 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 133 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 134 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 135 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 136 137 /* LCR register bits */ 138 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 139 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 140 * 141 * Word length bits table: 142 * 00 -> 5 bit words 143 * 01 -> 6 bit words 144 * 10 -> 7 bit words 145 * 11 -> 8 bit words 146 */ 147 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 148 * 149 * STOP length bit table: 150 * 0 -> 1 stop bit 151 * 1 -> 1-1.5 stop bits if 152 * word length is 5, 153 * 2 stop bits otherwise 154 */ 155 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 156 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 157 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 158 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 159 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 160 161 /* IRDA register bits */ 162 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 163 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 164 165 /* Flow control trigger level register masks */ 166 #define MAX310X_FLOWLVL_HALT_MASK GENMASK(3, 0) /* Flow control halt level */ 167 #define MAX310X_FLOWLVL_RES_MASK GENMASK(7, 4) /* Flow control resume level */ 168 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 169 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 170 171 /* FIFO interrupt trigger level register masks */ 172 #define MAX310X_FIFOTRIGLVL_TX_MASK GENMASK(3, 0) /* TX FIFO trigger level */ 173 #define MAX310X_FIFOTRIGLVL_RX_MASK GENMASK(7, 4) /* RX FIFO trigger level */ 174 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 175 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 176 177 /* Flow control register bits */ 178 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 179 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 180 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 181 * are used in conjunction with 182 * XOFF2 for definition of 183 * special character 184 */ 185 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 186 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 187 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 188 * 189 * SWFLOW bits 1 & 0 table: 190 * 00 -> no transmitter flow 191 * control 192 * 01 -> receiver compares 193 * XON2 and XOFF2 194 * and controls 195 * transmitter 196 * 10 -> receiver compares 197 * XON1 and XOFF1 198 * and controls 199 * transmitter 200 * 11 -> receiver compares 201 * XON1, XON2, XOFF1 and 202 * XOFF2 and controls 203 * transmitter 204 */ 205 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 206 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 207 * 208 * SWFLOW bits 3 & 2 table: 209 * 00 -> no received flow 210 * control 211 * 01 -> transmitter generates 212 * XON2 and XOFF2 213 * 10 -> transmitter generates 214 * XON1 and XOFF1 215 * 11 -> transmitter generates 216 * XON1, XON2, XOFF1 and 217 * XOFF2 218 */ 219 220 /* PLL configuration register masks */ 221 #define MAX310X_PLLCFG_PREDIV_MASK GENMASK(5, 0) /* PLL predivision value */ 222 #define MAX310X_PLLCFG_PLLFACTOR_MASK GENMASK(7, 6) /* PLL multiplication factor */ 223 224 /* Baud rate generator configuration register bits */ 225 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 226 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 227 228 /* Clock source register bits */ 229 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 230 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 231 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 232 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 233 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 234 235 /* Global commands */ 236 #define MAX310X_EXTREG_ENBL (0xce) 237 #define MAX310X_EXTREG_DSBL (0xcd) 238 239 /* Misc definitions */ 240 #define MAX310X_FIFO_SIZE (128) 241 #define MAX310x_REV_MASK GENMASK(7, 3) 242 #define MAX310X_WRITE_BIT 0x80 243 244 /* Port startup definitions */ 245 #define MAX310X_PORT_STARTUP_SLEEP_US 10000 /* Delay between retries */ 246 #define MAX310X_PORT_STARTUP_TIMEOUT_US (20 * MAX310X_PORT_STARTUP_SLEEP_US) /* Total timeout */ 247 248 /* Crystal-related definitions */ 249 #define MAX310X_XTAL_SLEEP_US 10000 /* Delay between retries */ 250 #define MAX310X_XTAL_TIMEOUT_US (20 * MAX310X_XTAL_SLEEP_US) /* Total timeout */ 251 252 /* MAX3107 specific */ 253 #define MAX3107_REV_ID (0xa0) 254 255 /* MAX3109 specific */ 256 #define MAX3109_REV_ID (0xc0) 257 258 /* MAX14830 specific */ 259 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 260 #define MAX14830_REV_ID (0xb0) 261 262 struct max310x_clk_config_t { 263 u8 prediv; /* Predivider */ 264 u8 pll_mult; /* PLL multiplier */ 265 unsigned int fref; /* 266 * Reference clock for fractional baud rate generator: 267 * PLL enabled: (freq / prediv) x pll_mult 268 * PLL disabled: freq 269 */ 270 unsigned int err; /* Computed error for selected parameters */ 271 }; 272 273 struct max310x_if_cfg { 274 int (*extended_reg_enable)(struct device *dev, bool enable); 275 u8 rev_id_offset; 276 }; 277 278 struct max310x_devtype { 279 struct { 280 unsigned short min; 281 unsigned short max; 282 } slave_addr; /* Relevant only in I2C mode. */ 283 int nr; 284 char name[9]; 285 u8 mode1; 286 u8 rev_id_val; 287 u8 rev_id_reg; /* Relevant only if rev_id_val is defined. */ 288 u8 power_reg; /* Register address for power/sleep control. */ 289 u8 power_bit; /* Bit for sleep or power-off mode (active high). */ 290 }; 291 292 struct max310x_one { 293 struct uart_port port; 294 struct work_struct tx_work; 295 struct work_struct md_work; 296 struct work_struct rs_work; 297 struct regmap *regmap; 298 299 u8 rx_buf[MAX310X_FIFO_SIZE]; 300 }; 301 #define to_max310x_port(_port) \ 302 container_of(_port, struct max310x_one, port) 303 304 struct max310x_port { 305 const struct max310x_devtype *devtype; 306 const struct max310x_if_cfg *if_cfg; 307 struct regmap *regmap; 308 struct clk *clk; 309 #ifdef CONFIG_GPIOLIB 310 struct gpio_chip gpio; 311 #endif 312 struct max310x_one p[]; 313 }; 314 315 static struct uart_driver max310x_uart = { 316 .owner = THIS_MODULE, 317 .driver_name = MAX310X_NAME, 318 .dev_name = "ttyMAX", 319 .major = MAX310X_MAJOR, 320 .minor = MAX310X_MINOR, 321 .nr = MAX310X_UART_NRMAX, 322 }; 323 324 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 325 326 static u8 max310x_port_read(struct uart_port *port, u8 reg) 327 { 328 struct max310x_one *one = to_max310x_port(port); 329 unsigned int val = 0; 330 331 regmap_read(one->regmap, reg, &val); 332 333 return val; 334 } 335 336 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 337 { 338 struct max310x_one *one = to_max310x_port(port); 339 340 regmap_write(one->regmap, reg, val); 341 } 342 343 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 344 { 345 struct max310x_one *one = to_max310x_port(port); 346 347 regmap_update_bits(one->regmap, reg, mask, val); 348 } 349 350 static int max310x_detect(struct device *dev) 351 { 352 struct max310x_port *s = dev_get_drvdata(dev); 353 unsigned int val = 0; 354 int ret; 355 356 /* Check if variant supports REV ID register: */ 357 if (s->devtype->rev_id_val) { 358 u8 rev_id_reg = s->devtype->rev_id_reg; 359 360 /* Check if REV ID is in extended addressing space: */ 361 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { 362 ret = s->if_cfg->extended_reg_enable(dev, true); 363 if (ret) 364 return ret; 365 366 /* Adjust REV ID extended addressing space address: */ 367 if (s->if_cfg->rev_id_offset) 368 rev_id_reg -= s->if_cfg->rev_id_offset; 369 } 370 371 regmap_read(s->regmap, rev_id_reg, &val); 372 373 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { 374 ret = s->if_cfg->extended_reg_enable(dev, false); 375 if (ret) 376 return ret; 377 } 378 379 if (((val & MAX310x_REV_MASK) != s->devtype->rev_id_val)) 380 return dev_err_probe(dev, -ENODEV, 381 "%s ID 0x%02x does not match\n", 382 s->devtype->name, val); 383 } else { 384 /* 385 * For variant without REV ID register, just check default value 386 * from clocksource register to make sure everything works. 387 */ 388 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 389 if (ret) 390 return ret; 391 392 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) 393 return dev_err_probe(dev, -ENODEV, 394 "%s not present\n", 395 s->devtype->name); 396 } 397 398 return 0; 399 } 400 401 static void max310x_power(struct uart_port *port, int on) 402 { 403 struct max310x_port *s = dev_get_drvdata(port->dev); 404 405 max310x_port_update(port, s->devtype->power_reg, s->devtype->power_bit, 406 on ? 0 : s->devtype->power_bit); 407 if (on) 408 msleep(50); 409 } 410 411 static const struct max310x_devtype max3107_devtype = { 412 .name = "MAX3107", 413 .nr = 1, 414 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 415 .rev_id_val = MAX3107_REV_ID, 416 .rev_id_reg = MAX310X_REVID_REG, 417 .power_reg = MAX310X_MODE1_REG, 418 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 419 .slave_addr = { 420 .min = 0x2c, 421 .max = 0x2f, 422 }, 423 }; 424 425 static const struct max310x_devtype max3108_devtype = { 426 .name = "MAX3108", 427 .nr = 1, 428 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 429 .rev_id_val = 0, /* Unsupported. */ 430 .rev_id_reg = 0, /* Irrelevant when rev_id_val is not defined. */ 431 .power_reg = MAX310X_MODE1_REG, 432 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 433 .slave_addr = { 434 .min = 0x60, 435 .max = 0x6f, 436 }, 437 }; 438 439 static const struct max310x_devtype max3109_devtype = { 440 .name = "MAX3109", 441 .nr = 2, 442 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 443 .rev_id_val = MAX3109_REV_ID, 444 .rev_id_reg = MAX310X_REVID_EXTREG, 445 .power_reg = MAX310X_MODE1_REG, 446 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 447 .slave_addr = { 448 .min = 0x60, 449 .max = 0x6f, 450 }, 451 }; 452 453 static const struct max310x_devtype max14830_devtype = { 454 .name = "MAX14830", 455 .nr = 4, 456 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 457 .rev_id_val = MAX14830_REV_ID, 458 .rev_id_reg = MAX310X_REVID_EXTREG, 459 .power_reg = MAX310X_BRGCFG_REG, 460 .power_bit = MAX14830_BRGCFG_CLKDIS_BIT, 461 .slave_addr = { 462 .min = 0x60, 463 .max = 0x6f, 464 }, 465 }; 466 467 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 468 { 469 switch (reg) { 470 case MAX310X_IRQSTS_REG: 471 case MAX310X_LSR_IRQSTS_REG: 472 case MAX310X_SPCHR_IRQSTS_REG: 473 case MAX310X_STS_IRQSTS_REG: 474 case MAX310X_TXFIFOLVL_REG: 475 case MAX310X_RXFIFOLVL_REG: 476 return false; 477 default: 478 return true; 479 } 480 } 481 482 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 483 { 484 switch (reg) { 485 case MAX310X_RHR_REG: 486 case MAX310X_IRQSTS_REG: 487 case MAX310X_LSR_IRQSTS_REG: 488 case MAX310X_SPCHR_IRQSTS_REG: 489 case MAX310X_STS_IRQSTS_REG: 490 case MAX310X_TXFIFOLVL_REG: 491 case MAX310X_RXFIFOLVL_REG: 492 case MAX310X_GPIODATA_REG: 493 case MAX310X_BRGDIVLSB_REG: 494 case MAX310X_REG_05: 495 case MAX310X_REG_1F: 496 return true; 497 default: 498 return false; 499 } 500 } 501 502 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 503 { 504 switch (reg) { 505 case MAX310X_RHR_REG: 506 case MAX310X_IRQSTS_REG: 507 case MAX310X_SPCHR_IRQSTS_REG: 508 case MAX310X_STS_IRQSTS_REG: 509 return true; 510 default: 511 return false; 512 } 513 } 514 515 static bool max310x_reg_noinc(struct device *dev, unsigned int reg) 516 { 517 return reg == MAX310X_RHR_REG; 518 } 519 520 static int max310x_set_baud(struct uart_port *port, int baud) 521 { 522 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 523 524 /* 525 * Calculate the integer divisor first. Select a proper mode 526 * in case if the requested baud is too high for the pre-defined 527 * clocks frequency. 528 */ 529 div = port->uartclk / baud; 530 if (div < 8) { 531 /* Mode x4 */ 532 c = 4; 533 mode = MAX310X_BRGCFG_4XMODE_BIT; 534 } else if (div < 16) { 535 /* Mode x2 */ 536 c = 8; 537 mode = MAX310X_BRGCFG_2XMODE_BIT; 538 } else { 539 c = 16; 540 } 541 542 /* Calculate the divisor in accordance with the fraction coefficient */ 543 div /= c; 544 F = c*baud; 545 546 /* Calculate the baud rate fraction */ 547 if (div > 0) 548 frac = (16*(port->uartclk % F)) / F; 549 else 550 div = 1; 551 552 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 553 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 554 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 555 556 /* Return the actual baud rate we just programmed */ 557 return (16*port->uartclk) / (c*(16*div + frac)); 558 } 559 560 static void max310x_try_cfg(unsigned int fdiv, u8 div, u8 pll_mult, 561 struct max310x_clk_config_t *cfg) 562 { 563 unsigned int fmul = fdiv * pll_mult; 564 unsigned int err; 565 566 /* Use high-enough baudrate to calculate error */ 567 err = fmul % (460800 * 16); 568 569 if (cfg->err > err) { 570 cfg->err = err; 571 cfg->pll_mult = pll_mult; 572 cfg->prediv = div; 573 cfg->fref = fmul; 574 } 575 } 576 577 static u8 max310x_pll_mult_to_id(u8 pll_mult) 578 { 579 switch (pll_mult) { 580 case 144: return 3; 581 case 96: return 2; 582 case 48: return 1; 583 case 6: 584 default: return 0; 585 } 586 } 587 588 /* 589 * From table 7 in datasheet: PLLFactor Selector Guide 590 * 591 * +-----------+----------------+-------------------+-------------------+ 592 * | PLLFactor | MULTIPLICATION | fPLLIN | fREF | 593 * | (1 & 0) | FACTOR +---------+---------+---------+---------+ 594 * | | | MIN | MAX | MIN | MAX | 595 * +-----------+----------------+---------+---------+---------+---------+ 596 * | 0 | 6 | 500kHz | 800kHz | 3MHz | 4.8MHz | 597 * +-----------+----------------+---------+---------+---------+---------+ 598 * | 1 | 48 | 850kHz | 1.2MHz | 40.8MHz | 56MHz | 599 * +-----------+----------------+---------+---------+---------+---------+ 600 * | 2 | 96 | 425kHz | 1MHz | 40.8MHz | 96MHz | 601 * +-----------+----------------+---------+---------+---------+---------+ 602 * | 3 | 144 | 390kHz | 667kHz | 56MHz | 96MHz | 603 * +-----------+----------------+---------+---------+---------+---------+ 604 */ 605 static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 606 unsigned int freq, unsigned int *fref, bool xtal) 607 { 608 unsigned int div, fdiv, clksrc, val; 609 struct max310x_clk_config_t cfg; 610 611 cfg.err = UINT_MAX; 612 cfg.prediv = 0; 613 cfg.fref = freq; 614 615 /* First, update error without PLL */ 616 max310x_try_cfg(freq, 1, 1, &cfg); 617 618 /* Try all possible PLL dividers */ 619 for (div = 1; (div <= 63) && cfg.err; div++) { 620 fdiv = DIV_ROUND_CLOSEST(freq, div); 621 622 if ((fdiv >= 500000) && (fdiv <= 800000)) 623 max310x_try_cfg(fdiv, div, 6, &cfg); /* PLL x6 */ 624 else if ((fdiv >= 850000) && (fdiv <= 1200000)) 625 max310x_try_cfg(fdiv, div, 48, &cfg); /* PLL x48 */ 626 627 if ((fdiv >= 425000) && (fdiv <= 1000000)) 628 max310x_try_cfg(fdiv, div, 96, &cfg); /* PLL x96 */ 629 630 if ((fdiv >= 390000) && (fdiv <= 667000)) 631 max310x_try_cfg(fdiv, div, 144, &cfg); /* PLL x144 */ 632 } 633 634 /* Configure clock source */ 635 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 636 637 /* Configure PLL */ 638 if (cfg.prediv) { 639 u8 pll_id = max310x_pll_mult_to_id(cfg.pll_mult); 640 641 clksrc |= MAX310X_CLKSRC_PLL_BIT; 642 val = FIELD_PREP(MAX310X_PLLCFG_PLLFACTOR_MASK, pll_id) | 643 FIELD_PREP(MAX310X_PLLCFG_PREDIV_MASK, cfg.prediv); 644 regmap_write(s->regmap, MAX310X_PLLCFG_REG, val); 645 } else 646 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 647 648 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 649 650 /* Wait for crystal */ 651 if (xtal) { 652 int ret; 653 654 ret = regmap_read_poll_timeout(s->regmap, MAX310X_STS_IRQSTS_REG, 655 val, val & MAX310X_STS_CLKREADY_BIT, 656 MAX310X_XTAL_SLEEP_US, 657 MAX310X_XTAL_TIMEOUT_US); 658 if (ret) 659 return dev_err_probe(dev, -EAGAIN, 660 "clock is not stable\n"); 661 } 662 663 *fref = cfg.fref; 664 665 return 0; 666 } 667 668 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 669 { 670 struct max310x_one *one = to_max310x_port(port); 671 672 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); 673 } 674 675 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 676 { 677 struct max310x_one *one = to_max310x_port(port); 678 679 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 680 } 681 682 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 683 { 684 struct max310x_one *one = to_max310x_port(port); 685 unsigned int sts, i; 686 u8 ch, flag; 687 688 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 689 /* 690 * We are just reading, happily ignoring any error conditions. 691 * Break condition, parity checking, framing errors -- they 692 * are all ignored. That means that we can do a batch-read. 693 * 694 * There is a small opportunity for race if the RX FIFO 695 * overruns while we're reading the buffer; the datasheets says 696 * that the LSR register applies to the "current" character. 697 * That's also the reason why we cannot do batched reads when 698 * asked to check the individual statuses. 699 */ 700 701 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 702 max310x_batch_read(port, one->rx_buf, rxlen); 703 704 port->icount.rx += rxlen; 705 flag = TTY_NORMAL; 706 sts &= port->read_status_mask; 707 708 if (sts & MAX310X_LSR_RXOVR_BIT) { 709 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 710 port->icount.overrun++; 711 } 712 713 for (i = 0; i < (rxlen - 1); ++i) 714 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 715 716 /* 717 * Handle the overrun case for the last character only, since 718 * the RxFIFO overflow happens after it is pushed to the FIFO 719 * tail. 720 */ 721 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 722 one->rx_buf[rxlen-1], flag); 723 724 } else { 725 if (unlikely(rxlen >= port->fifosize)) { 726 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 727 port->icount.buf_overrun++; 728 /* Ensure sanity of RX level */ 729 rxlen = port->fifosize; 730 } 731 732 while (rxlen--) { 733 ch = max310x_port_read(port, MAX310X_RHR_REG); 734 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 735 736 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 737 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 738 739 port->icount.rx++; 740 flag = TTY_NORMAL; 741 742 if (unlikely(sts)) { 743 if (sts & MAX310X_LSR_RXBRK_BIT) { 744 port->icount.brk++; 745 if (uart_handle_break(port)) 746 continue; 747 } else if (sts & MAX310X_LSR_RXPAR_BIT) 748 port->icount.parity++; 749 else if (sts & MAX310X_LSR_FRERR_BIT) 750 port->icount.frame++; 751 else if (sts & MAX310X_LSR_RXOVR_BIT) 752 port->icount.overrun++; 753 754 sts &= port->read_status_mask; 755 if (sts & MAX310X_LSR_RXBRK_BIT) 756 flag = TTY_BREAK; 757 else if (sts & MAX310X_LSR_RXPAR_BIT) 758 flag = TTY_PARITY; 759 else if (sts & MAX310X_LSR_FRERR_BIT) 760 flag = TTY_FRAME; 761 else if (sts & MAX310X_LSR_RXOVR_BIT) 762 flag = TTY_OVERRUN; 763 } 764 765 if (uart_handle_sysrq_char(port, ch)) 766 continue; 767 768 if (sts & port->ignore_status_mask) 769 continue; 770 771 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 772 } 773 } 774 775 tty_flip_buffer_push(&port->state->port); 776 } 777 778 static void max310x_handle_tx(struct uart_port *port) 779 { 780 struct tty_port *tport = &port->state->port; 781 782 if (unlikely(port->x_char)) { 783 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 784 port->icount.tx++; 785 port->x_char = 0; 786 return; 787 } 788 789 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) 790 return; 791 792 /* 793 * It's a circ buffer -- wrap around. 794 * We could do that in one SPI transaction, but meh. 795 */ 796 while (!kfifo_is_empty(&tport->xmit_fifo)) { 797 unsigned int txlen, to_send; 798 unsigned char *tail; 799 800 /* Limit to space available in TX FIFO */ 801 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 802 txlen = port->fifosize - txlen; 803 if (!txlen) 804 break; 805 806 to_send = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen); 807 max310x_batch_write(port, tail, to_send); 808 uart_xmit_advance(port, to_send); 809 } 810 811 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 812 uart_write_wakeup(port); 813 } 814 815 static void max310x_start_tx(struct uart_port *port) 816 { 817 struct max310x_one *one = to_max310x_port(port); 818 819 schedule_work(&one->tx_work); 820 } 821 822 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 823 { 824 struct uart_port *port = &s->p[portno].port; 825 irqreturn_t res = IRQ_NONE; 826 827 do { 828 unsigned int ists, lsr, rxlen; 829 830 /* Read IRQ status & RX FIFO level */ 831 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 832 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 833 if (!ists && !rxlen) 834 break; 835 836 res = IRQ_HANDLED; 837 838 if (ists & MAX310X_IRQ_CTS_BIT) { 839 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 840 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 841 } 842 if (rxlen) 843 max310x_handle_rx(port, rxlen); 844 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 845 max310x_start_tx(port); 846 } while (1); 847 848 return res; 849 } 850 851 static irqreturn_t max310x_ist(int irq, void *dev_id) 852 { 853 struct max310x_port *s = (struct max310x_port *)dev_id; 854 bool handled = false; 855 856 if (s->devtype->nr > 1) { 857 bool done; 858 859 do { 860 unsigned int val = ~0; 861 unsigned long irq; 862 unsigned int port; 863 864 done = true; 865 866 WARN_ON_ONCE(regmap_read(s->regmap, 867 MAX310X_GLOBALIRQ_REG, &val)); 868 869 irq = val; 870 871 for_each_clear_bit(port, &irq, s->devtype->nr) { 872 done = false; 873 874 if (max310x_port_irq(s, port) == IRQ_HANDLED) 875 handled = true; 876 } 877 878 } while (!done); 879 } else { 880 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 881 handled = true; 882 } 883 884 return IRQ_RETVAL(handled); 885 } 886 887 static void max310x_tx_proc(struct work_struct *ws) 888 { 889 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 890 891 max310x_handle_tx(&one->port); 892 } 893 894 static unsigned int max310x_tx_empty(struct uart_port *port) 895 { 896 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 897 898 return lvl ? 0 : TIOCSER_TEMT; 899 } 900 901 static unsigned int max310x_get_mctrl(struct uart_port *port) 902 { 903 /* 904 * DCD and DSR are not wired and CTS/RTS is handled automatically 905 * so just indicate DSR and CAR asserted 906 */ 907 return TIOCM_DSR | TIOCM_CAR; 908 } 909 910 static void max310x_md_proc(struct work_struct *ws) 911 { 912 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 913 914 max310x_port_update(&one->port, MAX310X_MODE2_REG, 915 MAX310X_MODE2_LOOPBACK_BIT, 916 (one->port.mctrl & TIOCM_LOOP) ? 917 MAX310X_MODE2_LOOPBACK_BIT : 0); 918 } 919 920 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 921 { 922 struct max310x_one *one = to_max310x_port(port); 923 924 schedule_work(&one->md_work); 925 } 926 927 static void max310x_break_ctl(struct uart_port *port, int break_state) 928 { 929 max310x_port_update(port, MAX310X_LCR_REG, 930 MAX310X_LCR_TXBREAK_BIT, 931 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 932 } 933 934 static void max310x_set_termios(struct uart_port *port, 935 struct ktermios *termios, 936 const struct ktermios *old) 937 { 938 unsigned int lcr = 0, flow = 0; 939 int baud; 940 941 /* Mask termios capabilities we don't support */ 942 termios->c_cflag &= ~CMSPAR; 943 944 /* Word size */ 945 switch (termios->c_cflag & CSIZE) { 946 case CS5: 947 break; 948 case CS6: 949 lcr = MAX310X_LCR_LENGTH0_BIT; 950 break; 951 case CS7: 952 lcr = MAX310X_LCR_LENGTH1_BIT; 953 break; 954 case CS8: 955 default: 956 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 957 break; 958 } 959 960 /* Parity */ 961 if (termios->c_cflag & PARENB) { 962 lcr |= MAX310X_LCR_PARITY_BIT; 963 if (!(termios->c_cflag & PARODD)) 964 lcr |= MAX310X_LCR_EVENPARITY_BIT; 965 } 966 967 /* Stop bits */ 968 if (termios->c_cflag & CSTOPB) 969 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 970 971 /* Update LCR register */ 972 max310x_port_write(port, MAX310X_LCR_REG, lcr); 973 974 /* Set read status mask */ 975 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 976 if (termios->c_iflag & INPCK) 977 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 978 MAX310X_LSR_FRERR_BIT; 979 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 980 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 981 982 /* Set status ignore mask */ 983 port->ignore_status_mask = 0; 984 if (termios->c_iflag & IGNBRK) 985 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 986 if (!(termios->c_cflag & CREAD)) 987 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 988 MAX310X_LSR_RXOVR_BIT | 989 MAX310X_LSR_FRERR_BIT | 990 MAX310X_LSR_RXBRK_BIT; 991 992 /* Configure flow control */ 993 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 994 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 995 996 /* 997 * Disable transmitter before enabling AutoCTS or auto transmitter 998 * flow control 999 */ 1000 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 1001 max310x_port_update(port, MAX310X_MODE1_REG, 1002 MAX310X_MODE1_TXDIS_BIT, 1003 MAX310X_MODE1_TXDIS_BIT); 1004 } 1005 1006 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 1007 1008 if (termios->c_cflag & CRTSCTS) { 1009 /* Enable AUTORTS and AUTOCTS */ 1010 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1011 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 1012 MAX310X_FLOWCTRL_AUTORTS_BIT; 1013 } 1014 if (termios->c_iflag & IXON) 1015 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 1016 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1017 if (termios->c_iflag & IXOFF) { 1018 port->status |= UPSTAT_AUTOXOFF; 1019 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 1020 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1021 } 1022 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 1023 1024 /* 1025 * Enable transmitter after disabling AutoCTS and auto transmitter 1026 * flow control 1027 */ 1028 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 1029 max310x_port_update(port, MAX310X_MODE1_REG, 1030 MAX310X_MODE1_TXDIS_BIT, 1031 0); 1032 } 1033 1034 /* Get baud rate generator configuration */ 1035 baud = uart_get_baud_rate(port, termios, old, 1036 port->uartclk / 16 / 0xffff, 1037 port->uartclk / 4); 1038 1039 /* Setup baudrate generator */ 1040 baud = max310x_set_baud(port, baud); 1041 1042 /* Update timeout according to new baud rate */ 1043 uart_update_timeout(port, termios->c_cflag, baud); 1044 } 1045 1046 static void max310x_rs_proc(struct work_struct *ws) 1047 { 1048 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1049 unsigned int delay, mode1 = 0, mode2 = 0; 1050 1051 delay = (one->port.rs485.delay_rts_before_send << 4) | 1052 one->port.rs485.delay_rts_after_send; 1053 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1054 1055 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1056 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1057 1058 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1059 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1060 } 1061 1062 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1063 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1064 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1065 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1066 } 1067 1068 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1069 struct serial_rs485 *rs485) 1070 { 1071 struct max310x_one *one = to_max310x_port(port); 1072 1073 if ((rs485->delay_rts_before_send > 0x0f) || 1074 (rs485->delay_rts_after_send > 0x0f)) 1075 return -ERANGE; 1076 1077 port->rs485 = *rs485; 1078 1079 schedule_work(&one->rs_work); 1080 1081 return 0; 1082 } 1083 1084 static int max310x_startup(struct uart_port *port) 1085 { 1086 unsigned int val; 1087 1088 max310x_power(port, 1); 1089 1090 /* Configure MODE1 register */ 1091 max310x_port_update(port, MAX310X_MODE1_REG, 1092 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1093 1094 /* Configure MODE2 register & Reset FIFOs*/ 1095 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1096 max310x_port_write(port, MAX310X_MODE2_REG, val); 1097 max310x_port_update(port, MAX310X_MODE2_REG, 1098 MAX310X_MODE2_FIFORST_BIT, 0); 1099 1100 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1101 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1102 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1103 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1104 1105 if (port->rs485.flags & SER_RS485_ENABLED) { 1106 max310x_port_update(port, MAX310X_MODE1_REG, 1107 MAX310X_MODE1_TRNSCVCTRL_BIT, 1108 MAX310X_MODE1_TRNSCVCTRL_BIT); 1109 1110 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1111 max310x_port_update(port, MAX310X_MODE2_REG, 1112 MAX310X_MODE2_ECHOSUPR_BIT, 1113 MAX310X_MODE2_ECHOSUPR_BIT); 1114 } 1115 1116 /* 1117 * Configure flow control levels: 1118 * resume: 48 1119 * halt: 96 1120 */ 1121 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1122 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1123 1124 /* Clear IRQ status register */ 1125 max310x_port_read(port, MAX310X_IRQSTS_REG); 1126 1127 /* Enable RX, TX, CTS change interrupts */ 1128 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1129 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1130 1131 return 0; 1132 } 1133 1134 static void max310x_shutdown(struct uart_port *port) 1135 { 1136 /* Disable all interrupts */ 1137 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1138 1139 max310x_power(port, 0); 1140 } 1141 1142 static const char *max310x_type(struct uart_port *port) 1143 { 1144 struct max310x_port *s = dev_get_drvdata(port->dev); 1145 1146 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1147 } 1148 1149 static int max310x_request_port(struct uart_port *port) 1150 { 1151 /* Do nothing */ 1152 return 0; 1153 } 1154 1155 static void max310x_config_port(struct uart_port *port, int flags) 1156 { 1157 if (flags & UART_CONFIG_TYPE) 1158 port->type = PORT_MAX310X; 1159 } 1160 1161 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1162 { 1163 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1164 return -EINVAL; 1165 if (s->irq != port->irq) 1166 return -EINVAL; 1167 1168 return 0; 1169 } 1170 1171 static void max310x_null_void(struct uart_port *port) 1172 { 1173 /* Do nothing */ 1174 } 1175 1176 static const struct uart_ops max310x_ops = { 1177 .tx_empty = max310x_tx_empty, 1178 .set_mctrl = max310x_set_mctrl, 1179 .get_mctrl = max310x_get_mctrl, 1180 .stop_tx = max310x_null_void, 1181 .start_tx = max310x_start_tx, 1182 .stop_rx = max310x_null_void, 1183 .break_ctl = max310x_break_ctl, 1184 .startup = max310x_startup, 1185 .shutdown = max310x_shutdown, 1186 .set_termios = max310x_set_termios, 1187 .type = max310x_type, 1188 .request_port = max310x_request_port, 1189 .release_port = max310x_null_void, 1190 .config_port = max310x_config_port, 1191 .verify_port = max310x_verify_port, 1192 }; 1193 1194 static int __maybe_unused max310x_suspend(struct device *dev) 1195 { 1196 struct max310x_port *s = dev_get_drvdata(dev); 1197 int i; 1198 1199 for (i = 0; i < s->devtype->nr; i++) { 1200 uart_suspend_port(&max310x_uart, &s->p[i].port); 1201 max310x_power(&s->p[i].port, 0); 1202 } 1203 1204 return 0; 1205 } 1206 1207 static int __maybe_unused max310x_resume(struct device *dev) 1208 { 1209 struct max310x_port *s = dev_get_drvdata(dev); 1210 int i; 1211 1212 for (i = 0; i < s->devtype->nr; i++) { 1213 max310x_power(&s->p[i].port, 1); 1214 uart_resume_port(&max310x_uart, &s->p[i].port); 1215 } 1216 1217 return 0; 1218 } 1219 1220 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1221 1222 #ifdef CONFIG_GPIOLIB 1223 static int max310x_gpio_get(struct gpio_chip *chip, unsigned int offset) 1224 { 1225 unsigned int val; 1226 struct max310x_port *s = gpiochip_get_data(chip); 1227 struct uart_port *port = &s->p[offset / 4].port; 1228 1229 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1230 1231 return !!((val >> 4) & (1 << (offset % 4))); 1232 } 1233 1234 static int max310x_gpio_set(struct gpio_chip *chip, unsigned int offset, 1235 int value) 1236 { 1237 struct max310x_port *s = gpiochip_get_data(chip); 1238 struct uart_port *port = &s->p[offset / 4].port; 1239 1240 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1241 value ? 1 << (offset % 4) : 0); 1242 1243 return 0; 1244 } 1245 1246 static int max310x_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1247 { 1248 struct max310x_port *s = gpiochip_get_data(chip); 1249 struct uart_port *port = &s->p[offset / 4].port; 1250 unsigned int val; 1251 1252 val = max310x_port_read(port, MAX310X_GPIOCFG_REG); 1253 1254 return val & BIT(offset % 4) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1255 } 1256 1257 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1258 { 1259 struct max310x_port *s = gpiochip_get_data(chip); 1260 struct uart_port *port = &s->p[offset / 4].port; 1261 1262 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1263 1264 return 0; 1265 } 1266 1267 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1268 unsigned int offset, int value) 1269 { 1270 struct max310x_port *s = gpiochip_get_data(chip); 1271 struct uart_port *port = &s->p[offset / 4].port; 1272 1273 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1274 value ? 1 << (offset % 4) : 0); 1275 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1276 1 << (offset % 4)); 1277 1278 return 0; 1279 } 1280 1281 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1282 unsigned long config) 1283 { 1284 struct max310x_port *s = gpiochip_get_data(chip); 1285 struct uart_port *port = &s->p[offset / 4].port; 1286 1287 switch (pinconf_to_config_param(config)) { 1288 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1289 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1290 1 << ((offset % 4) + 4), 1291 1 << ((offset % 4) + 4)); 1292 return 0; 1293 case PIN_CONFIG_DRIVE_PUSH_PULL: 1294 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1295 1 << ((offset % 4) + 4), 0); 1296 return 0; 1297 default: 1298 return -ENOTSUPP; 1299 } 1300 } 1301 #endif 1302 1303 static const struct serial_rs485 max310x_rs485_supported = { 1304 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1305 .delay_rts_before_send = 1, 1306 .delay_rts_after_send = 1, 1307 }; 1308 1309 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1310 const struct max310x_if_cfg *if_cfg, 1311 struct regmap *regmaps[], int irq) 1312 { 1313 unsigned int fmin, fmax, freq; 1314 int i, ret; 1315 struct max310x_port *s; 1316 unsigned int uartclk = 0; 1317 bool xtal; 1318 1319 for (i = 0; i < devtype->nr; i++) 1320 if (IS_ERR(regmaps[i])) 1321 return PTR_ERR(regmaps[i]); 1322 1323 /* Alloc port structure */ 1324 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1325 if (!s) 1326 return -ENOMEM; 1327 1328 /* Always ask for fixed clock rate from a property. */ 1329 device_property_read_u32(dev, "clock-frequency", &uartclk); 1330 1331 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1332 if (xtal) 1333 s->clk = devm_clk_get_optional(dev, "xtal"); 1334 else 1335 s->clk = devm_clk_get_optional(dev, "osc"); 1336 if (IS_ERR(s->clk)) 1337 return PTR_ERR(s->clk); 1338 1339 ret = clk_prepare_enable(s->clk); 1340 if (ret) 1341 return ret; 1342 1343 freq = clk_get_rate(s->clk); 1344 if (freq == 0) 1345 freq = uartclk; 1346 if (freq == 0) { 1347 ret = dev_err_probe(dev, -EINVAL, "Cannot get clock rate\n"); 1348 goto out_clk; 1349 } 1350 1351 if (xtal) { 1352 fmin = 1000000; 1353 fmax = 4000000; 1354 } else { 1355 fmin = 500000; 1356 fmax = 35000000; 1357 } 1358 1359 /* Check frequency limits */ 1360 if (freq < fmin || freq > fmax) { 1361 ret = -ERANGE; 1362 goto out_clk; 1363 } 1364 1365 s->regmap = regmaps[0]; 1366 s->devtype = devtype; 1367 s->if_cfg = if_cfg; 1368 dev_set_drvdata(dev, s); 1369 1370 /* Check device to ensure we are talking to what we expect */ 1371 ret = max310x_detect(dev); 1372 if (ret) 1373 goto out_clk; 1374 1375 for (i = 0; i < devtype->nr; i++) { 1376 unsigned int val; 1377 1378 /* Reset port */ 1379 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1380 MAX310X_MODE2_RST_BIT); 1381 /* Clear port reset */ 1382 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1383 1384 /* Wait for port startup */ 1385 ret = regmap_read_poll_timeout(regmaps[i], MAX310X_BRGDIVLSB_REG, 1386 val, val == 0x01, 1387 MAX310X_PORT_STARTUP_SLEEP_US, 1388 MAX310X_PORT_STARTUP_TIMEOUT_US); 1389 if (ret) { 1390 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n"); 1391 goto out_uart; 1392 } 1393 1394 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1395 } 1396 1397 ret = max310x_set_ref_clk(dev, s, freq, &uartclk, xtal); 1398 if (ret < 0) 1399 goto out_uart; 1400 1401 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1402 1403 for (i = 0; i < devtype->nr; i++) { 1404 unsigned int line; 1405 1406 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1407 if (line == MAX310X_UART_NRMAX) { 1408 ret = -ERANGE; 1409 goto out_uart; 1410 } 1411 1412 /* Initialize port data */ 1413 s->p[i].port.line = line; 1414 s->p[i].port.dev = dev; 1415 s->p[i].port.irq = irq; 1416 s->p[i].port.type = PORT_MAX310X; 1417 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1418 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1419 s->p[i].port.iotype = UPIO_PORT; 1420 s->p[i].port.iobase = i; 1421 /* 1422 * Use all ones as membase to make sure uart_configure_port() in 1423 * serial_core.c does not abort for SPI/I2C devices where the 1424 * membase address is not applicable. 1425 */ 1426 s->p[i].port.membase = (void __iomem *)~0; 1427 s->p[i].port.uartclk = uartclk; 1428 s->p[i].port.rs485_config = max310x_rs485_config; 1429 s->p[i].port.rs485_supported = max310x_rs485_supported; 1430 s->p[i].port.ops = &max310x_ops; 1431 s->p[i].regmap = regmaps[i]; 1432 1433 /* Disable all interrupts */ 1434 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1435 /* Clear IRQ status register */ 1436 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1437 /* Initialize queue for start TX */ 1438 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1439 /* Initialize queue for changing LOOPBACK mode */ 1440 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1441 /* Initialize queue for changing RS485 mode */ 1442 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1443 1444 /* Register port */ 1445 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1446 if (ret) 1447 goto out_uart; 1448 1449 set_bit(line, max310x_lines); 1450 1451 /* Go to suspend mode */ 1452 max310x_power(&s->p[i].port, 0); 1453 } 1454 1455 #ifdef CONFIG_GPIOLIB 1456 /* Setup GPIO controller */ 1457 s->gpio.owner = THIS_MODULE; 1458 s->gpio.parent = dev; 1459 s->gpio.label = devtype->name; 1460 s->gpio.get_direction = max310x_gpio_get_direction; 1461 s->gpio.direction_input = max310x_gpio_direction_input; 1462 s->gpio.get = max310x_gpio_get; 1463 s->gpio.direction_output= max310x_gpio_direction_output; 1464 s->gpio.set = max310x_gpio_set; 1465 s->gpio.set_config = max310x_gpio_set_config; 1466 s->gpio.base = -1; 1467 s->gpio.ngpio = devtype->nr * 4; 1468 s->gpio.can_sleep = 1; 1469 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1470 if (ret) 1471 goto out_uart; 1472 #endif 1473 1474 /* Setup interrupt */ 1475 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1476 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1477 if (!ret) 1478 return 0; 1479 1480 dev_err(dev, "Unable to request IRQ %i\n", irq); 1481 1482 out_uart: 1483 for (i = 0; i < devtype->nr; i++) { 1484 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) 1485 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1486 } 1487 1488 out_clk: 1489 clk_disable_unprepare(s->clk); 1490 1491 return ret; 1492 } 1493 1494 static void max310x_remove(struct device *dev) 1495 { 1496 struct max310x_port *s = dev_get_drvdata(dev); 1497 int i; 1498 1499 for (i = 0; i < s->devtype->nr; i++) { 1500 cancel_work_sync(&s->p[i].tx_work); 1501 cancel_work_sync(&s->p[i].md_work); 1502 cancel_work_sync(&s->p[i].rs_work); 1503 1504 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) 1505 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1506 1507 max310x_power(&s->p[i].port, 0); 1508 } 1509 1510 clk_disable_unprepare(s->clk); 1511 } 1512 1513 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1514 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1515 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1516 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1517 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1518 { } 1519 }; 1520 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1521 1522 static const char *max310x_regmap_name(u8 port_id) 1523 { 1524 switch (port_id) { 1525 case 0: return "port0"; 1526 case 1: return "port1"; 1527 case 2: return "port2"; 1528 case 3: return "port3"; 1529 default: 1530 WARN_ON(true); 1531 return NULL; 1532 } 1533 } 1534 1535 #if IS_ENABLED(CONFIG_SPI_MASTER) 1536 1537 static struct regmap_config regcfg = { 1538 .reg_bits = 8, 1539 .val_bits = 8, 1540 .write_flag_mask = MAX310X_WRITE_BIT, 1541 .cache_type = REGCACHE_MAPLE, 1542 .max_register = MAX310X_REG_1F, 1543 .writeable_reg = max310x_reg_writeable, 1544 .volatile_reg = max310x_reg_volatile, 1545 .precious_reg = max310x_reg_precious, 1546 .writeable_noinc_reg = max310x_reg_noinc, 1547 .readable_noinc_reg = max310x_reg_noinc, 1548 .max_raw_read = MAX310X_FIFO_SIZE, 1549 .max_raw_write = MAX310X_FIFO_SIZE, 1550 }; 1551 1552 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1553 { 1554 struct max310x_port *s = dev_get_drvdata(dev); 1555 1556 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1557 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1558 } 1559 1560 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1561 .extended_reg_enable = max310x_spi_extended_reg_enable, 1562 .rev_id_offset = MAX310X_EXTREG_START, 1563 }; 1564 1565 static int max310x_spi_probe(struct spi_device *spi) 1566 { 1567 const struct max310x_devtype *devtype; 1568 struct regmap *regmaps[MAX310X_MAX_PORTS]; 1569 unsigned int i; 1570 int ret; 1571 1572 /* Setup SPI bus */ 1573 spi->bits_per_word = 8; 1574 spi->mode = spi->mode ? : SPI_MODE_0; 1575 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1576 ret = spi_setup(spi); 1577 if (ret) 1578 return ret; 1579 1580 devtype = spi_get_device_match_data(spi); 1581 if (!devtype) 1582 return dev_err_probe(&spi->dev, -ENODEV, "Failed to match device\n"); 1583 1584 for (i = 0; i < devtype->nr; i++) { 1585 u8 port_mask = i * 0x20; 1586 1587 regcfg.name = max310x_regmap_name(i); 1588 regcfg.read_flag_mask = port_mask; 1589 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1590 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1591 } 1592 1593 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1594 } 1595 1596 static void max310x_spi_remove(struct spi_device *spi) 1597 { 1598 max310x_remove(&spi->dev); 1599 } 1600 1601 static const struct spi_device_id max310x_id_table[] = { 1602 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1603 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1604 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1605 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1606 { } 1607 }; 1608 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1609 1610 static struct spi_driver max310x_spi_driver = { 1611 .driver = { 1612 .name = MAX310X_NAME, 1613 .of_match_table = max310x_dt_ids, 1614 .pm = &max310x_pm_ops, 1615 }, 1616 .probe = max310x_spi_probe, 1617 .remove = max310x_spi_remove, 1618 .id_table = max310x_id_table, 1619 }; 1620 #endif 1621 1622 #if IS_ENABLED(CONFIG_I2C) 1623 1624 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1625 { 1626 return 0; 1627 } 1628 1629 static struct regmap_config regcfg_i2c = { 1630 .reg_bits = 8, 1631 .val_bits = 8, 1632 .cache_type = REGCACHE_MAPLE, 1633 .writeable_reg = max310x_reg_writeable, 1634 .volatile_reg = max310x_reg_volatile, 1635 .precious_reg = max310x_reg_precious, 1636 .max_register = MAX310X_REVID_EXTREG, 1637 .writeable_noinc_reg = max310x_reg_noinc, 1638 .readable_noinc_reg = max310x_reg_noinc, 1639 .max_raw_read = MAX310X_FIFO_SIZE, 1640 .max_raw_write = MAX310X_FIFO_SIZE, 1641 }; 1642 1643 static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1644 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1645 .rev_id_offset = 0, /* No offset in I2C mode. */ 1646 }; 1647 1648 static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1649 unsigned int nr) 1650 { 1651 /* 1652 * For MAX14830 and MAX3109, the slave address depends on what the 1653 * A0 and A1 pins are tied to. 1654 * See Table I2C Address Map of the datasheet. 1655 * Based on that table, the following formulas were determined: 1656 * UART1 - UART0 = 0x10 1657 * UART2 - UART1 = 0x20 + 0x10 1658 * UART3 - UART2 = 0x10 1659 */ 1660 1661 addr -= nr * 0x10; 1662 1663 if (nr >= 2) 1664 addr -= 0x20; 1665 1666 return addr; 1667 } 1668 1669 static int max310x_i2c_probe(struct i2c_client *client) 1670 { 1671 const struct max310x_devtype *devtype; 1672 struct i2c_client *port_client; 1673 struct regmap *regmaps[MAX310X_MAX_PORTS]; 1674 unsigned int i; 1675 u8 port_addr; 1676 1677 devtype = i2c_get_match_data(client); 1678 if (!devtype) 1679 return dev_err_probe(&client->dev, -ENODEV, "Failed to match device\n"); 1680 1681 if (client->addr < devtype->slave_addr.min || 1682 client->addr > devtype->slave_addr.max) 1683 return dev_err_probe(&client->dev, -EINVAL, 1684 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1685 client->addr, devtype->slave_addr.min, 1686 devtype->slave_addr.max); 1687 1688 regcfg_i2c.name = max310x_regmap_name(0); 1689 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1690 1691 for (i = 1; i < devtype->nr; i++) { 1692 port_addr = max310x_i2c_slave_addr(client->addr, i); 1693 port_client = devm_i2c_new_dummy_device(&client->dev, 1694 client->adapter, 1695 port_addr); 1696 if (IS_ERR(port_client)) 1697 return PTR_ERR(port_client); 1698 1699 regcfg_i2c.name = max310x_regmap_name(i); 1700 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1701 } 1702 1703 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1704 regmaps, client->irq); 1705 } 1706 1707 static void max310x_i2c_remove(struct i2c_client *client) 1708 { 1709 max310x_remove(&client->dev); 1710 } 1711 1712 static const struct i2c_device_id max310x_i2c_id_table[] = { 1713 { .name = "max3107", .driver_data = (kernel_ulong_t)&max3107_devtype }, 1714 { .name = "max3108", .driver_data = (kernel_ulong_t)&max3108_devtype }, 1715 { .name = "max3109", .driver_data = (kernel_ulong_t)&max3109_devtype }, 1716 { .name = "max14830", .driver_data = (kernel_ulong_t)&max14830_devtype }, 1717 { } 1718 }; 1719 MODULE_DEVICE_TABLE(i2c, max310x_i2c_id_table); 1720 1721 static struct i2c_driver max310x_i2c_driver = { 1722 .driver = { 1723 .name = MAX310X_NAME, 1724 .of_match_table = max310x_dt_ids, 1725 .pm = &max310x_pm_ops, 1726 }, 1727 .probe = max310x_i2c_probe, 1728 .remove = max310x_i2c_remove, 1729 .id_table = max310x_i2c_id_table, 1730 }; 1731 #endif 1732 1733 static int __init max310x_uart_init(void) 1734 { 1735 int ret; 1736 1737 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1738 1739 ret = uart_register_driver(&max310x_uart); 1740 if (ret) 1741 return ret; 1742 1743 #if IS_ENABLED(CONFIG_SPI_MASTER) 1744 ret = spi_register_driver(&max310x_spi_driver); 1745 if (ret) 1746 goto err_spi_register; 1747 #endif 1748 1749 #if IS_ENABLED(CONFIG_I2C) 1750 ret = i2c_add_driver(&max310x_i2c_driver); 1751 if (ret) 1752 goto err_i2c_register; 1753 #endif 1754 1755 return 0; 1756 1757 #if IS_ENABLED(CONFIG_I2C) 1758 err_i2c_register: 1759 #endif 1760 #if IS_ENABLED(CONFIG_SPI_MASTER) 1761 spi_unregister_driver(&max310x_spi_driver); 1762 err_spi_register: 1763 #endif 1764 uart_unregister_driver(&max310x_uart); 1765 1766 return ret; 1767 } 1768 module_init(max310x_uart_init); 1769 1770 static void __exit max310x_uart_exit(void) 1771 { 1772 #if IS_ENABLED(CONFIG_I2C) 1773 i2c_del_driver(&max310x_i2c_driver); 1774 #endif 1775 1776 #if IS_ENABLED(CONFIG_SPI_MASTER) 1777 spi_unregister_driver(&max310x_spi_driver); 1778 #endif 1779 1780 uart_unregister_driver(&max310x_uart); 1781 } 1782 module_exit(max310x_uart_exit); 1783 1784 MODULE_LICENSE("GPL"); 1785 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1786 MODULE_DESCRIPTION("MAX310X serial driver"); 1787