1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bitops.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/i2c.h> 19 #include <linux/kconfig.h> 20 #include <linux/module.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/serial_core.h> 25 #include <linux/serial.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/spi/spi.h> 29 #include <linux/uaccess.h> 30 31 #define MAX310X_NAME "max310x" 32 #define MAX310X_MAJOR 204 33 #define MAX310X_MINOR 209 34 #define MAX310X_UART_NRMAX 16 35 #define MAX310X_MAX_PORTS 4 /* Maximum number of UART ports per IC. */ 36 37 /* MAX310X register definitions */ 38 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 39 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 40 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 41 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 42 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 43 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 44 #define MAX310X_REG_05 (0x05) 45 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 46 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 47 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 48 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 49 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 50 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 51 #define MAX310X_LCR_REG (0x0b) /* LCR */ 52 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 53 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 54 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 55 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 56 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 57 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 58 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 59 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 60 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 61 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 62 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 63 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 64 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 65 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 66 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 67 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 68 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 69 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 70 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 71 #define MAX310X_REG_1F (0x1f) 72 #define MAX310X_EXTREG_START (0x20) /* Only relevant in SPI mode. */ 73 74 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 75 76 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 77 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 78 79 /* Extended registers */ 80 #define MAX310X_REVID_EXTREG (0x25) /* Revision ID 81 * (extended addressing space) 82 */ 83 /* IRQ register bits */ 84 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 85 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 86 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 87 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 88 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 89 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 90 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 91 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 92 93 /* LSR register bits */ 94 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 95 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 96 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 97 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 98 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 99 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 100 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 101 102 /* Special character register bits */ 103 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 104 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 105 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 106 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 107 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 108 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 109 110 /* Status register bits */ 111 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 112 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 113 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 114 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 115 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 116 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 117 118 /* MODE1 register bits */ 119 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 120 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 121 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 122 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 123 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 124 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 125 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 126 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 127 128 /* MODE2 register bits */ 129 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 130 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 131 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 132 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 133 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 134 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 135 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 136 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 137 138 /* LCR register bits */ 139 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 140 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 141 * 142 * Word length bits table: 143 * 00 -> 5 bit words 144 * 01 -> 6 bit words 145 * 10 -> 7 bit words 146 * 11 -> 8 bit words 147 */ 148 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 149 * 150 * STOP length bit table: 151 * 0 -> 1 stop bit 152 * 1 -> 1-1.5 stop bits if 153 * word length is 5, 154 * 2 stop bits otherwise 155 */ 156 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 157 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 158 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 159 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 160 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 161 162 /* IRDA register bits */ 163 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 164 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 165 166 /* Flow control trigger level register masks */ 167 #define MAX310X_FLOWLVL_HALT_MASK GENMASK(3, 0) /* Flow control halt level */ 168 #define MAX310X_FLOWLVL_RES_MASK GENMASK(7, 4) /* Flow control resume level */ 169 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 170 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 171 172 /* FIFO interrupt trigger level register masks */ 173 #define MAX310X_FIFOTRIGLVL_TX_MASK GENMASK(3, 0) /* TX FIFO trigger level */ 174 #define MAX310X_FIFOTRIGLVL_RX_MASK GENMASK(7, 4) /* RX FIFO trigger level */ 175 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 176 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 177 178 /* Flow control register bits */ 179 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 180 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 181 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 182 * are used in conjunction with 183 * XOFF2 for definition of 184 * special character 185 */ 186 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 187 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 188 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 189 * 190 * SWFLOW bits 1 & 0 table: 191 * 00 -> no transmitter flow 192 * control 193 * 01 -> receiver compares 194 * XON2 and XOFF2 195 * and controls 196 * transmitter 197 * 10 -> receiver compares 198 * XON1 and XOFF1 199 * and controls 200 * transmitter 201 * 11 -> receiver compares 202 * XON1, XON2, XOFF1 and 203 * XOFF2 and controls 204 * transmitter 205 */ 206 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 207 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 208 * 209 * SWFLOW bits 3 & 2 table: 210 * 00 -> no received flow 211 * control 212 * 01 -> transmitter generates 213 * XON2 and XOFF2 214 * 10 -> transmitter generates 215 * XON1 and XOFF1 216 * 11 -> transmitter generates 217 * XON1, XON2, XOFF1 and 218 * XOFF2 219 */ 220 221 /* PLL configuration register masks */ 222 #define MAX310X_PLLCFG_PREDIV_MASK GENMASK(5, 0) /* PLL predivision value */ 223 #define MAX310X_PLLCFG_PLLFACTOR_MASK GENMASK(7, 6) /* PLL multiplication factor */ 224 225 /* Baud rate generator configuration register bits */ 226 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 227 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 228 229 /* Clock source register bits */ 230 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 231 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 232 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 233 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 234 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 235 236 /* Global commands */ 237 #define MAX310X_EXTREG_ENBL (0xce) 238 #define MAX310X_EXTREG_DSBL (0xcd) 239 240 /* Misc definitions */ 241 #define MAX310X_FIFO_SIZE (128) 242 #define MAX310x_REV_MASK GENMASK(7, 3) 243 #define MAX310X_WRITE_BIT 0x80 244 245 /* Port startup definitions */ 246 #define MAX310X_PORT_STARTUP_SLEEP_US 10000 /* Delay between retries */ 247 #define MAX310X_PORT_STARTUP_TIMEOUT_US (20 * MAX310X_PORT_STARTUP_SLEEP_US) /* Total timeout */ 248 249 /* Crystal-related definitions */ 250 #define MAX310X_XTAL_SLEEP_US 10000 /* Delay between retries */ 251 #define MAX310X_XTAL_TIMEOUT_US (20 * MAX310X_XTAL_SLEEP_US) /* Total timeout */ 252 253 /* MAX3107 specific */ 254 #define MAX3107_REV_ID (0xa0) 255 256 /* MAX3109 specific */ 257 #define MAX3109_REV_ID (0xc0) 258 259 /* MAX14830 specific */ 260 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 261 #define MAX14830_REV_ID (0xb0) 262 263 struct max310x_clk_config_t { 264 u8 prediv; /* Predivider */ 265 u8 pll_mult; /* PLL multiplier */ 266 unsigned int fref; /* 267 * Reference clock for fractional baud rate generator: 268 * PLL enabled: (freq / prediv) x pll_mult 269 * PLL disabled: freq 270 */ 271 unsigned int err; /* Computed error for selected parameters */ 272 }; 273 274 struct max310x_if_cfg { 275 int (*extended_reg_enable)(struct device *dev, bool enable); 276 u8 rev_id_offset; 277 }; 278 279 struct max310x_devtype { 280 struct { 281 unsigned short min; 282 unsigned short max; 283 } slave_addr; /* Relevant only in I2C mode. */ 284 int nr; 285 char name[9]; 286 u8 mode1; 287 u8 rev_id_val; 288 u8 rev_id_reg; /* Relevant only if rev_id_val is defined. */ 289 u8 power_reg; /* Register address for power/sleep control. */ 290 u8 power_bit; /* Bit for sleep or power-off mode (active high). */ 291 }; 292 293 struct max310x_one { 294 struct uart_port port; 295 struct work_struct tx_work; 296 struct work_struct md_work; 297 struct work_struct rs_work; 298 struct regmap *regmap; 299 300 u8 rx_buf[MAX310X_FIFO_SIZE]; 301 }; 302 #define to_max310x_port(_port) \ 303 container_of(_port, struct max310x_one, port) 304 305 struct max310x_port { 306 const struct max310x_devtype *devtype; 307 const struct max310x_if_cfg *if_cfg; 308 struct regmap *regmap; 309 struct clk *clk; 310 #ifdef CONFIG_GPIOLIB 311 struct gpio_chip gpio; 312 #endif 313 struct max310x_one p[]; 314 }; 315 316 static struct uart_driver max310x_uart = { 317 .owner = THIS_MODULE, 318 .driver_name = MAX310X_NAME, 319 .dev_name = "ttyMAX", 320 .major = MAX310X_MAJOR, 321 .minor = MAX310X_MINOR, 322 .nr = MAX310X_UART_NRMAX, 323 }; 324 325 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 326 327 static u8 max310x_port_read(struct uart_port *port, u8 reg) 328 { 329 struct max310x_one *one = to_max310x_port(port); 330 unsigned int val = 0; 331 332 regmap_read(one->regmap, reg, &val); 333 334 return val; 335 } 336 337 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 338 { 339 struct max310x_one *one = to_max310x_port(port); 340 341 regmap_write(one->regmap, reg, val); 342 } 343 344 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 345 { 346 struct max310x_one *one = to_max310x_port(port); 347 348 regmap_update_bits(one->regmap, reg, mask, val); 349 } 350 351 static int max310x_detect(struct device *dev) 352 { 353 struct max310x_port *s = dev_get_drvdata(dev); 354 unsigned int val = 0; 355 int ret; 356 357 /* Check if variant supports REV ID register: */ 358 if (s->devtype->rev_id_val) { 359 u8 rev_id_reg = s->devtype->rev_id_reg; 360 361 /* Check if REV ID is in extended addressing space: */ 362 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { 363 ret = s->if_cfg->extended_reg_enable(dev, true); 364 if (ret) 365 return ret; 366 367 /* Adjust REV ID extended addressing space address: */ 368 if (s->if_cfg->rev_id_offset) 369 rev_id_reg -= s->if_cfg->rev_id_offset; 370 } 371 372 regmap_read(s->regmap, rev_id_reg, &val); 373 374 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { 375 ret = s->if_cfg->extended_reg_enable(dev, false); 376 if (ret) 377 return ret; 378 } 379 380 if (((val & MAX310x_REV_MASK) != s->devtype->rev_id_val)) 381 return dev_err_probe(dev, -ENODEV, 382 "%s ID 0x%02x does not match\n", 383 s->devtype->name, val); 384 } else { 385 /* 386 * For variant without REV ID register, just check default value 387 * from clocksource register to make sure everything works. 388 */ 389 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 390 if (ret) 391 return ret; 392 393 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) 394 return dev_err_probe(dev, -ENODEV, 395 "%s not present\n", 396 s->devtype->name); 397 } 398 399 return 0; 400 } 401 402 static void max310x_power(struct uart_port *port, int on) 403 { 404 struct max310x_port *s = dev_get_drvdata(port->dev); 405 406 max310x_port_update(port, s->devtype->power_reg, s->devtype->power_bit, 407 on ? 0 : s->devtype->power_bit); 408 if (on) 409 msleep(50); 410 } 411 412 static const struct max310x_devtype max3107_devtype = { 413 .name = "MAX3107", 414 .nr = 1, 415 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 416 .rev_id_val = MAX3107_REV_ID, 417 .rev_id_reg = MAX310X_REVID_REG, 418 .power_reg = MAX310X_MODE1_REG, 419 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 420 .slave_addr = { 421 .min = 0x2c, 422 .max = 0x2f, 423 }, 424 }; 425 426 static const struct max310x_devtype max3108_devtype = { 427 .name = "MAX3108", 428 .nr = 1, 429 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 430 .rev_id_val = 0, /* Unsupported. */ 431 .rev_id_reg = 0, /* Irrelevant when rev_id_val is not defined. */ 432 .power_reg = MAX310X_MODE1_REG, 433 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 434 .slave_addr = { 435 .min = 0x60, 436 .max = 0x6f, 437 }, 438 }; 439 440 static const struct max310x_devtype max3109_devtype = { 441 .name = "MAX3109", 442 .nr = 2, 443 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 444 .rev_id_val = MAX3109_REV_ID, 445 .rev_id_reg = MAX310X_REVID_EXTREG, 446 .power_reg = MAX310X_MODE1_REG, 447 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 448 .slave_addr = { 449 .min = 0x60, 450 .max = 0x6f, 451 }, 452 }; 453 454 static const struct max310x_devtype max14830_devtype = { 455 .name = "MAX14830", 456 .nr = 4, 457 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 458 .rev_id_val = MAX14830_REV_ID, 459 .rev_id_reg = MAX310X_REVID_EXTREG, 460 .power_reg = MAX310X_BRGCFG_REG, 461 .power_bit = MAX14830_BRGCFG_CLKDIS_BIT, 462 .slave_addr = { 463 .min = 0x60, 464 .max = 0x6f, 465 }, 466 }; 467 468 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 469 { 470 switch (reg) { 471 case MAX310X_IRQSTS_REG: 472 case MAX310X_LSR_IRQSTS_REG: 473 case MAX310X_SPCHR_IRQSTS_REG: 474 case MAX310X_STS_IRQSTS_REG: 475 case MAX310X_TXFIFOLVL_REG: 476 case MAX310X_RXFIFOLVL_REG: 477 return false; 478 default: 479 return true; 480 } 481 } 482 483 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 484 { 485 switch (reg) { 486 case MAX310X_RHR_REG: 487 case MAX310X_IRQSTS_REG: 488 case MAX310X_LSR_IRQSTS_REG: 489 case MAX310X_SPCHR_IRQSTS_REG: 490 case MAX310X_STS_IRQSTS_REG: 491 case MAX310X_TXFIFOLVL_REG: 492 case MAX310X_RXFIFOLVL_REG: 493 case MAX310X_GPIODATA_REG: 494 case MAX310X_BRGDIVLSB_REG: 495 case MAX310X_REG_05: 496 case MAX310X_REG_1F: 497 return true; 498 default: 499 return false; 500 } 501 } 502 503 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 504 { 505 switch (reg) { 506 case MAX310X_RHR_REG: 507 case MAX310X_IRQSTS_REG: 508 case MAX310X_SPCHR_IRQSTS_REG: 509 case MAX310X_STS_IRQSTS_REG: 510 return true; 511 default: 512 return false; 513 } 514 } 515 516 static bool max310x_reg_noinc(struct device *dev, unsigned int reg) 517 { 518 return reg == MAX310X_RHR_REG; 519 } 520 521 static int max310x_set_baud(struct uart_port *port, int baud) 522 { 523 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 524 525 /* 526 * Calculate the integer divisor first. Select a proper mode 527 * in case if the requested baud is too high for the pre-defined 528 * clocks frequency. 529 */ 530 div = port->uartclk / baud; 531 if (div < 8) { 532 /* Mode x4 */ 533 c = 4; 534 mode = MAX310X_BRGCFG_4XMODE_BIT; 535 } else if (div < 16) { 536 /* Mode x2 */ 537 c = 8; 538 mode = MAX310X_BRGCFG_2XMODE_BIT; 539 } else { 540 c = 16; 541 } 542 543 /* Calculate the divisor in accordance with the fraction coefficient */ 544 div /= c; 545 F = c*baud; 546 547 /* Calculate the baud rate fraction */ 548 if (div > 0) 549 frac = (16*(port->uartclk % F)) / F; 550 else 551 div = 1; 552 553 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 554 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 555 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 556 557 /* Return the actual baud rate we just programmed */ 558 return (16*port->uartclk) / (c*(16*div + frac)); 559 } 560 561 static void max310x_try_cfg(unsigned int fdiv, u8 div, u8 pll_mult, 562 struct max310x_clk_config_t *cfg) 563 { 564 unsigned int fmul = fdiv * pll_mult; 565 unsigned int err; 566 567 /* Use high-enough baudrate to calculate error */ 568 err = fmul % (460800 * 16); 569 570 if (cfg->err > err) { 571 cfg->err = err; 572 cfg->pll_mult = pll_mult; 573 cfg->prediv = div; 574 cfg->fref = fmul; 575 } 576 } 577 578 static u8 max310x_pll_mult_to_id(u8 pll_mult) 579 { 580 switch (pll_mult) { 581 case 144: return 3; 582 case 96: return 2; 583 case 48: return 1; 584 case 6: 585 default: return 0; 586 } 587 } 588 589 /* 590 * From table 7 in datasheet: PLLFactor Selector Guide 591 * 592 * +-----------+----------------+-------------------+-------------------+ 593 * | PLLFactor | MULTIPLICATION | fPLLIN | fREF | 594 * | (1 & 0) | FACTOR +---------+---------+---------+---------+ 595 * | | | MIN | MAX | MIN | MAX | 596 * +-----------+----------------+---------+---------+---------+---------+ 597 * | 0 | 6 | 500kHz | 800kHz | 3MHz | 4.8MHz | 598 * +-----------+----------------+---------+---------+---------+---------+ 599 * | 1 | 48 | 850kHz | 1.2MHz | 40.8MHz | 56MHz | 600 * +-----------+----------------+---------+---------+---------+---------+ 601 * | 2 | 96 | 425kHz | 1MHz | 40.8MHz | 96MHz | 602 * +-----------+----------------+---------+---------+---------+---------+ 603 * | 3 | 144 | 390kHz | 667kHz | 56MHz | 96MHz | 604 * +-----------+----------------+---------+---------+---------+---------+ 605 */ 606 static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 607 unsigned int freq, unsigned int *fref, bool xtal) 608 { 609 unsigned int div, fdiv, clksrc, val; 610 struct max310x_clk_config_t cfg; 611 612 cfg.err = UINT_MAX; 613 cfg.prediv = 0; 614 cfg.fref = freq; 615 616 /* First, update error without PLL */ 617 max310x_try_cfg(freq, 1, 1, &cfg); 618 619 /* Try all possible PLL dividers */ 620 for (div = 1; (div <= 63) && cfg.err; div++) { 621 fdiv = DIV_ROUND_CLOSEST(freq, div); 622 623 if ((fdiv >= 500000) && (fdiv <= 800000)) 624 max310x_try_cfg(fdiv, div, 6, &cfg); /* PLL x6 */ 625 else if ((fdiv >= 850000) && (fdiv <= 1200000)) 626 max310x_try_cfg(fdiv, div, 48, &cfg); /* PLL x48 */ 627 628 if ((fdiv >= 425000) && (fdiv <= 1000000)) 629 max310x_try_cfg(fdiv, div, 96, &cfg); /* PLL x96 */ 630 631 if ((fdiv >= 390000) && (fdiv <= 667000)) 632 max310x_try_cfg(fdiv, div, 144, &cfg); /* PLL x144 */ 633 } 634 635 /* Configure clock source */ 636 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 637 638 /* Configure PLL */ 639 if (cfg.prediv) { 640 u8 pll_id = max310x_pll_mult_to_id(cfg.pll_mult); 641 642 clksrc |= MAX310X_CLKSRC_PLL_BIT; 643 val = FIELD_PREP(MAX310X_PLLCFG_PLLFACTOR_MASK, pll_id) | 644 FIELD_PREP(MAX310X_PLLCFG_PREDIV_MASK, cfg.prediv); 645 regmap_write(s->regmap, MAX310X_PLLCFG_REG, val); 646 } else 647 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 648 649 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 650 651 /* Wait for crystal */ 652 if (xtal) { 653 int ret; 654 655 ret = regmap_read_poll_timeout(s->regmap, MAX310X_STS_IRQSTS_REG, 656 val, val & MAX310X_STS_CLKREADY_BIT, 657 MAX310X_XTAL_SLEEP_US, 658 MAX310X_XTAL_TIMEOUT_US); 659 if (ret) 660 return dev_err_probe(dev, -EAGAIN, 661 "clock is not stable\n"); 662 } 663 664 *fref = cfg.fref; 665 666 return 0; 667 } 668 669 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 670 { 671 struct max310x_one *one = to_max310x_port(port); 672 673 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); 674 } 675 676 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 677 { 678 struct max310x_one *one = to_max310x_port(port); 679 680 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 681 } 682 683 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 684 { 685 struct max310x_one *one = to_max310x_port(port); 686 unsigned int sts, i; 687 u8 ch, flag; 688 689 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 690 /* 691 * We are just reading, happily ignoring any error conditions. 692 * Break condition, parity checking, framing errors -- they 693 * are all ignored. That means that we can do a batch-read. 694 * 695 * There is a small opportunity for race if the RX FIFO 696 * overruns while we're reading the buffer; the datasheets says 697 * that the LSR register applies to the "current" character. 698 * That's also the reason why we cannot do batched reads when 699 * asked to check the individual statuses. 700 */ 701 702 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 703 max310x_batch_read(port, one->rx_buf, rxlen); 704 705 port->icount.rx += rxlen; 706 flag = TTY_NORMAL; 707 sts &= port->read_status_mask; 708 709 if (sts & MAX310X_LSR_RXOVR_BIT) { 710 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 711 port->icount.overrun++; 712 } 713 714 for (i = 0; i < (rxlen - 1); ++i) 715 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 716 717 /* 718 * Handle the overrun case for the last character only, since 719 * the RxFIFO overflow happens after it is pushed to the FIFO 720 * tail. 721 */ 722 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 723 one->rx_buf[rxlen-1], flag); 724 725 } else { 726 if (unlikely(rxlen >= port->fifosize)) { 727 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 728 port->icount.buf_overrun++; 729 /* Ensure sanity of RX level */ 730 rxlen = port->fifosize; 731 } 732 733 while (rxlen--) { 734 ch = max310x_port_read(port, MAX310X_RHR_REG); 735 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 736 737 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 738 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 739 740 port->icount.rx++; 741 flag = TTY_NORMAL; 742 743 if (unlikely(sts)) { 744 if (sts & MAX310X_LSR_RXBRK_BIT) { 745 port->icount.brk++; 746 if (uart_handle_break(port)) 747 continue; 748 } else if (sts & MAX310X_LSR_RXPAR_BIT) 749 port->icount.parity++; 750 else if (sts & MAX310X_LSR_FRERR_BIT) 751 port->icount.frame++; 752 else if (sts & MAX310X_LSR_RXOVR_BIT) 753 port->icount.overrun++; 754 755 sts &= port->read_status_mask; 756 if (sts & MAX310X_LSR_RXBRK_BIT) 757 flag = TTY_BREAK; 758 else if (sts & MAX310X_LSR_RXPAR_BIT) 759 flag = TTY_PARITY; 760 else if (sts & MAX310X_LSR_FRERR_BIT) 761 flag = TTY_FRAME; 762 else if (sts & MAX310X_LSR_RXOVR_BIT) 763 flag = TTY_OVERRUN; 764 } 765 766 if (uart_handle_sysrq_char(port, ch)) 767 continue; 768 769 if (sts & port->ignore_status_mask) 770 continue; 771 772 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 773 } 774 } 775 776 tty_flip_buffer_push(&port->state->port); 777 } 778 779 static void max310x_handle_tx(struct uart_port *port) 780 { 781 struct tty_port *tport = &port->state->port; 782 783 if (unlikely(port->x_char)) { 784 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 785 port->icount.tx++; 786 port->x_char = 0; 787 return; 788 } 789 790 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) 791 return; 792 793 /* 794 * It's a circ buffer -- wrap around. 795 * We could do that in one SPI transaction, but meh. 796 */ 797 while (!kfifo_is_empty(&tport->xmit_fifo)) { 798 unsigned int txlen, to_send; 799 unsigned char *tail; 800 801 /* Limit to space available in TX FIFO */ 802 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 803 txlen = port->fifosize - txlen; 804 if (!txlen) 805 break; 806 807 to_send = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen); 808 max310x_batch_write(port, tail, to_send); 809 uart_xmit_advance(port, to_send); 810 } 811 812 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 813 uart_write_wakeup(port); 814 } 815 816 static void max310x_start_tx(struct uart_port *port) 817 { 818 struct max310x_one *one = to_max310x_port(port); 819 820 schedule_work(&one->tx_work); 821 } 822 823 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 824 { 825 struct uart_port *port = &s->p[portno].port; 826 irqreturn_t res = IRQ_NONE; 827 828 do { 829 unsigned int ists, lsr, rxlen; 830 831 /* Read IRQ status & RX FIFO level */ 832 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 833 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 834 if (!ists && !rxlen) 835 break; 836 837 res = IRQ_HANDLED; 838 839 if (ists & MAX310X_IRQ_CTS_BIT) { 840 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 841 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 842 } 843 if (rxlen) 844 max310x_handle_rx(port, rxlen); 845 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 846 max310x_start_tx(port); 847 } while (1); 848 849 return res; 850 } 851 852 static irqreturn_t max310x_ist(int irq, void *dev_id) 853 { 854 struct max310x_port *s = (struct max310x_port *)dev_id; 855 bool handled = false; 856 857 if (s->devtype->nr > 1) { 858 bool done; 859 860 do { 861 unsigned int val = ~0; 862 unsigned long irq; 863 unsigned int port; 864 865 done = true; 866 867 WARN_ON_ONCE(regmap_read(s->regmap, 868 MAX310X_GLOBALIRQ_REG, &val)); 869 870 irq = val; 871 872 for_each_clear_bit(port, &irq, s->devtype->nr) { 873 done = false; 874 875 if (max310x_port_irq(s, port) == IRQ_HANDLED) 876 handled = true; 877 } 878 879 } while (!done); 880 } else { 881 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 882 handled = true; 883 } 884 885 return IRQ_RETVAL(handled); 886 } 887 888 static void max310x_tx_proc(struct work_struct *ws) 889 { 890 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 891 892 max310x_handle_tx(&one->port); 893 } 894 895 static unsigned int max310x_tx_empty(struct uart_port *port) 896 { 897 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 898 899 return lvl ? 0 : TIOCSER_TEMT; 900 } 901 902 static unsigned int max310x_get_mctrl(struct uart_port *port) 903 { 904 /* 905 * DCD and DSR are not wired and CTS/RTS is handled automatically 906 * so just indicate DSR and CAR asserted 907 */ 908 return TIOCM_DSR | TIOCM_CAR; 909 } 910 911 static void max310x_md_proc(struct work_struct *ws) 912 { 913 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 914 915 max310x_port_update(&one->port, MAX310X_MODE2_REG, 916 MAX310X_MODE2_LOOPBACK_BIT, 917 (one->port.mctrl & TIOCM_LOOP) ? 918 MAX310X_MODE2_LOOPBACK_BIT : 0); 919 } 920 921 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 922 { 923 struct max310x_one *one = to_max310x_port(port); 924 925 schedule_work(&one->md_work); 926 } 927 928 static void max310x_break_ctl(struct uart_port *port, int break_state) 929 { 930 max310x_port_update(port, MAX310X_LCR_REG, 931 MAX310X_LCR_TXBREAK_BIT, 932 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 933 } 934 935 static void max310x_set_termios(struct uart_port *port, 936 struct ktermios *termios, 937 const struct ktermios *old) 938 { 939 unsigned int lcr = 0, flow = 0; 940 int baud; 941 942 /* Mask termios capabilities we don't support */ 943 termios->c_cflag &= ~CMSPAR; 944 945 /* Word size */ 946 switch (termios->c_cflag & CSIZE) { 947 case CS5: 948 break; 949 case CS6: 950 lcr = MAX310X_LCR_LENGTH0_BIT; 951 break; 952 case CS7: 953 lcr = MAX310X_LCR_LENGTH1_BIT; 954 break; 955 case CS8: 956 default: 957 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 958 break; 959 } 960 961 /* Parity */ 962 if (termios->c_cflag & PARENB) { 963 lcr |= MAX310X_LCR_PARITY_BIT; 964 if (!(termios->c_cflag & PARODD)) 965 lcr |= MAX310X_LCR_EVENPARITY_BIT; 966 } 967 968 /* Stop bits */ 969 if (termios->c_cflag & CSTOPB) 970 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 971 972 /* Update LCR register */ 973 max310x_port_write(port, MAX310X_LCR_REG, lcr); 974 975 /* Set read status mask */ 976 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 977 if (termios->c_iflag & INPCK) 978 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 979 MAX310X_LSR_FRERR_BIT; 980 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 981 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 982 983 /* Set status ignore mask */ 984 port->ignore_status_mask = 0; 985 if (termios->c_iflag & IGNBRK) 986 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 987 if (!(termios->c_cflag & CREAD)) 988 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 989 MAX310X_LSR_RXOVR_BIT | 990 MAX310X_LSR_FRERR_BIT | 991 MAX310X_LSR_RXBRK_BIT; 992 993 /* Configure flow control */ 994 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 995 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 996 997 /* 998 * Disable transmitter before enabling AutoCTS or auto transmitter 999 * flow control 1000 */ 1001 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 1002 max310x_port_update(port, MAX310X_MODE1_REG, 1003 MAX310X_MODE1_TXDIS_BIT, 1004 MAX310X_MODE1_TXDIS_BIT); 1005 } 1006 1007 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 1008 1009 if (termios->c_cflag & CRTSCTS) { 1010 /* Enable AUTORTS and AUTOCTS */ 1011 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1012 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 1013 MAX310X_FLOWCTRL_AUTORTS_BIT; 1014 } 1015 if (termios->c_iflag & IXON) 1016 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 1017 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1018 if (termios->c_iflag & IXOFF) { 1019 port->status |= UPSTAT_AUTOXOFF; 1020 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 1021 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1022 } 1023 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 1024 1025 /* 1026 * Enable transmitter after disabling AutoCTS and auto transmitter 1027 * flow control 1028 */ 1029 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 1030 max310x_port_update(port, MAX310X_MODE1_REG, 1031 MAX310X_MODE1_TXDIS_BIT, 1032 0); 1033 } 1034 1035 /* Get baud rate generator configuration */ 1036 baud = uart_get_baud_rate(port, termios, old, 1037 port->uartclk / 16 / 0xffff, 1038 port->uartclk / 4); 1039 1040 /* Setup baudrate generator */ 1041 baud = max310x_set_baud(port, baud); 1042 1043 /* Update timeout according to new baud rate */ 1044 uart_update_timeout(port, termios->c_cflag, baud); 1045 } 1046 1047 static void max310x_rs_proc(struct work_struct *ws) 1048 { 1049 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1050 unsigned int delay, mode1 = 0, mode2 = 0; 1051 1052 delay = (one->port.rs485.delay_rts_before_send << 4) | 1053 one->port.rs485.delay_rts_after_send; 1054 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1055 1056 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1057 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1058 1059 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1060 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1061 } 1062 1063 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1064 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1065 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1066 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1067 } 1068 1069 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1070 struct serial_rs485 *rs485) 1071 { 1072 struct max310x_one *one = to_max310x_port(port); 1073 1074 if ((rs485->delay_rts_before_send > 0x0f) || 1075 (rs485->delay_rts_after_send > 0x0f)) 1076 return -ERANGE; 1077 1078 port->rs485 = *rs485; 1079 1080 schedule_work(&one->rs_work); 1081 1082 return 0; 1083 } 1084 1085 static int max310x_startup(struct uart_port *port) 1086 { 1087 unsigned int val; 1088 1089 max310x_power(port, 1); 1090 1091 /* Configure MODE1 register */ 1092 max310x_port_update(port, MAX310X_MODE1_REG, 1093 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1094 1095 /* Configure MODE2 register & Reset FIFOs*/ 1096 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1097 max310x_port_write(port, MAX310X_MODE2_REG, val); 1098 max310x_port_update(port, MAX310X_MODE2_REG, 1099 MAX310X_MODE2_FIFORST_BIT, 0); 1100 1101 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1102 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1103 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1104 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1105 1106 if (port->rs485.flags & SER_RS485_ENABLED) { 1107 max310x_port_update(port, MAX310X_MODE1_REG, 1108 MAX310X_MODE1_TRNSCVCTRL_BIT, 1109 MAX310X_MODE1_TRNSCVCTRL_BIT); 1110 1111 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1112 max310x_port_update(port, MAX310X_MODE2_REG, 1113 MAX310X_MODE2_ECHOSUPR_BIT, 1114 MAX310X_MODE2_ECHOSUPR_BIT); 1115 } 1116 1117 /* 1118 * Configure flow control levels: 1119 * resume: 48 1120 * halt: 96 1121 */ 1122 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1123 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1124 1125 /* Clear IRQ status register */ 1126 max310x_port_read(port, MAX310X_IRQSTS_REG); 1127 1128 /* Enable RX, TX, CTS change interrupts */ 1129 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1130 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1131 1132 return 0; 1133 } 1134 1135 static void max310x_shutdown(struct uart_port *port) 1136 { 1137 /* Disable all interrupts */ 1138 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1139 1140 max310x_power(port, 0); 1141 } 1142 1143 static const char *max310x_type(struct uart_port *port) 1144 { 1145 struct max310x_port *s = dev_get_drvdata(port->dev); 1146 1147 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1148 } 1149 1150 static int max310x_request_port(struct uart_port *port) 1151 { 1152 /* Do nothing */ 1153 return 0; 1154 } 1155 1156 static void max310x_config_port(struct uart_port *port, int flags) 1157 { 1158 if (flags & UART_CONFIG_TYPE) 1159 port->type = PORT_MAX310X; 1160 } 1161 1162 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1163 { 1164 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1165 return -EINVAL; 1166 if (s->irq != port->irq) 1167 return -EINVAL; 1168 1169 return 0; 1170 } 1171 1172 static void max310x_null_void(struct uart_port *port) 1173 { 1174 /* Do nothing */ 1175 } 1176 1177 static const struct uart_ops max310x_ops = { 1178 .tx_empty = max310x_tx_empty, 1179 .set_mctrl = max310x_set_mctrl, 1180 .get_mctrl = max310x_get_mctrl, 1181 .stop_tx = max310x_null_void, 1182 .start_tx = max310x_start_tx, 1183 .stop_rx = max310x_null_void, 1184 .break_ctl = max310x_break_ctl, 1185 .startup = max310x_startup, 1186 .shutdown = max310x_shutdown, 1187 .set_termios = max310x_set_termios, 1188 .type = max310x_type, 1189 .request_port = max310x_request_port, 1190 .release_port = max310x_null_void, 1191 .config_port = max310x_config_port, 1192 .verify_port = max310x_verify_port, 1193 }; 1194 1195 static int __maybe_unused max310x_suspend(struct device *dev) 1196 { 1197 struct max310x_port *s = dev_get_drvdata(dev); 1198 int i; 1199 1200 for (i = 0; i < s->devtype->nr; i++) { 1201 uart_suspend_port(&max310x_uart, &s->p[i].port); 1202 max310x_power(&s->p[i].port, 0); 1203 } 1204 1205 return 0; 1206 } 1207 1208 static int __maybe_unused max310x_resume(struct device *dev) 1209 { 1210 struct max310x_port *s = dev_get_drvdata(dev); 1211 int i; 1212 1213 for (i = 0; i < s->devtype->nr; i++) { 1214 max310x_power(&s->p[i].port, 1); 1215 uart_resume_port(&max310x_uart, &s->p[i].port); 1216 } 1217 1218 return 0; 1219 } 1220 1221 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1222 1223 #ifdef CONFIG_GPIOLIB 1224 static int max310x_gpio_get(struct gpio_chip *chip, unsigned int offset) 1225 { 1226 unsigned int val; 1227 struct max310x_port *s = gpiochip_get_data(chip); 1228 struct uart_port *port = &s->p[offset / 4].port; 1229 1230 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1231 1232 return !!((val >> 4) & (1 << (offset % 4))); 1233 } 1234 1235 static int max310x_gpio_set(struct gpio_chip *chip, unsigned int offset, 1236 int value) 1237 { 1238 struct max310x_port *s = gpiochip_get_data(chip); 1239 struct uart_port *port = &s->p[offset / 4].port; 1240 1241 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1242 value ? 1 << (offset % 4) : 0); 1243 1244 return 0; 1245 } 1246 1247 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1248 { 1249 struct max310x_port *s = gpiochip_get_data(chip); 1250 struct uart_port *port = &s->p[offset / 4].port; 1251 1252 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1253 1254 return 0; 1255 } 1256 1257 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1258 unsigned int offset, int value) 1259 { 1260 struct max310x_port *s = gpiochip_get_data(chip); 1261 struct uart_port *port = &s->p[offset / 4].port; 1262 1263 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1264 value ? 1 << (offset % 4) : 0); 1265 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1266 1 << (offset % 4)); 1267 1268 return 0; 1269 } 1270 1271 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1272 unsigned long config) 1273 { 1274 struct max310x_port *s = gpiochip_get_data(chip); 1275 struct uart_port *port = &s->p[offset / 4].port; 1276 1277 switch (pinconf_to_config_param(config)) { 1278 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1279 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1280 1 << ((offset % 4) + 4), 1281 1 << ((offset % 4) + 4)); 1282 return 0; 1283 case PIN_CONFIG_DRIVE_PUSH_PULL: 1284 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1285 1 << ((offset % 4) + 4), 0); 1286 return 0; 1287 default: 1288 return -ENOTSUPP; 1289 } 1290 } 1291 #endif 1292 1293 static const struct serial_rs485 max310x_rs485_supported = { 1294 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1295 .delay_rts_before_send = 1, 1296 .delay_rts_after_send = 1, 1297 }; 1298 1299 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1300 const struct max310x_if_cfg *if_cfg, 1301 struct regmap *regmaps[], int irq) 1302 { 1303 unsigned int fmin, fmax, freq; 1304 int i, ret; 1305 struct max310x_port *s; 1306 unsigned int uartclk = 0; 1307 bool xtal; 1308 1309 for (i = 0; i < devtype->nr; i++) 1310 if (IS_ERR(regmaps[i])) 1311 return PTR_ERR(regmaps[i]); 1312 1313 /* Alloc port structure */ 1314 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1315 if (!s) 1316 return -ENOMEM; 1317 1318 /* Always ask for fixed clock rate from a property. */ 1319 device_property_read_u32(dev, "clock-frequency", &uartclk); 1320 1321 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1322 if (xtal) 1323 s->clk = devm_clk_get_optional(dev, "xtal"); 1324 else 1325 s->clk = devm_clk_get_optional(dev, "osc"); 1326 if (IS_ERR(s->clk)) 1327 return PTR_ERR(s->clk); 1328 1329 ret = clk_prepare_enable(s->clk); 1330 if (ret) 1331 return ret; 1332 1333 freq = clk_get_rate(s->clk); 1334 if (freq == 0) 1335 freq = uartclk; 1336 if (freq == 0) { 1337 ret = dev_err_probe(dev, -EINVAL, "Cannot get clock rate\n"); 1338 goto out_clk; 1339 } 1340 1341 if (xtal) { 1342 fmin = 1000000; 1343 fmax = 4000000; 1344 } else { 1345 fmin = 500000; 1346 fmax = 35000000; 1347 } 1348 1349 /* Check frequency limits */ 1350 if (freq < fmin || freq > fmax) { 1351 ret = -ERANGE; 1352 goto out_clk; 1353 } 1354 1355 s->regmap = regmaps[0]; 1356 s->devtype = devtype; 1357 s->if_cfg = if_cfg; 1358 dev_set_drvdata(dev, s); 1359 1360 /* Check device to ensure we are talking to what we expect */ 1361 ret = max310x_detect(dev); 1362 if (ret) 1363 goto out_clk; 1364 1365 for (i = 0; i < devtype->nr; i++) { 1366 unsigned int val; 1367 1368 /* Reset port */ 1369 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1370 MAX310X_MODE2_RST_BIT); 1371 /* Clear port reset */ 1372 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1373 1374 /* Wait for port startup */ 1375 ret = regmap_read_poll_timeout(regmaps[i], MAX310X_BRGDIVLSB_REG, 1376 val, val == 0x01, 1377 MAX310X_PORT_STARTUP_SLEEP_US, 1378 MAX310X_PORT_STARTUP_TIMEOUT_US); 1379 if (ret) { 1380 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n"); 1381 goto out_uart; 1382 } 1383 1384 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1385 } 1386 1387 ret = max310x_set_ref_clk(dev, s, freq, &uartclk, xtal); 1388 if (ret < 0) 1389 goto out_uart; 1390 1391 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1392 1393 for (i = 0; i < devtype->nr; i++) { 1394 unsigned int line; 1395 1396 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1397 if (line == MAX310X_UART_NRMAX) { 1398 ret = -ERANGE; 1399 goto out_uart; 1400 } 1401 1402 /* Initialize port data */ 1403 s->p[i].port.line = line; 1404 s->p[i].port.dev = dev; 1405 s->p[i].port.irq = irq; 1406 s->p[i].port.type = PORT_MAX310X; 1407 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1408 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1409 s->p[i].port.iotype = UPIO_PORT; 1410 s->p[i].port.iobase = i; 1411 /* 1412 * Use all ones as membase to make sure uart_configure_port() in 1413 * serial_core.c does not abort for SPI/I2C devices where the 1414 * membase address is not applicable. 1415 */ 1416 s->p[i].port.membase = (void __iomem *)~0; 1417 s->p[i].port.uartclk = uartclk; 1418 s->p[i].port.rs485_config = max310x_rs485_config; 1419 s->p[i].port.rs485_supported = max310x_rs485_supported; 1420 s->p[i].port.ops = &max310x_ops; 1421 s->p[i].regmap = regmaps[i]; 1422 1423 /* Disable all interrupts */ 1424 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1425 /* Clear IRQ status register */ 1426 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1427 /* Initialize queue for start TX */ 1428 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1429 /* Initialize queue for changing LOOPBACK mode */ 1430 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1431 /* Initialize queue for changing RS485 mode */ 1432 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1433 1434 /* Register port */ 1435 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1436 if (ret) 1437 goto out_uart; 1438 1439 set_bit(line, max310x_lines); 1440 1441 /* Go to suspend mode */ 1442 max310x_power(&s->p[i].port, 0); 1443 } 1444 1445 #ifdef CONFIG_GPIOLIB 1446 /* Setup GPIO controller */ 1447 s->gpio.owner = THIS_MODULE; 1448 s->gpio.parent = dev; 1449 s->gpio.label = devtype->name; 1450 s->gpio.direction_input = max310x_gpio_direction_input; 1451 s->gpio.get = max310x_gpio_get; 1452 s->gpio.direction_output= max310x_gpio_direction_output; 1453 s->gpio.set = max310x_gpio_set; 1454 s->gpio.set_config = max310x_gpio_set_config; 1455 s->gpio.base = -1; 1456 s->gpio.ngpio = devtype->nr * 4; 1457 s->gpio.can_sleep = 1; 1458 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1459 if (ret) 1460 goto out_uart; 1461 #endif 1462 1463 /* Setup interrupt */ 1464 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1465 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1466 if (!ret) 1467 return 0; 1468 1469 dev_err(dev, "Unable to request IRQ %i\n", irq); 1470 1471 out_uart: 1472 for (i = 0; i < devtype->nr; i++) { 1473 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) 1474 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1475 } 1476 1477 out_clk: 1478 clk_disable_unprepare(s->clk); 1479 1480 return ret; 1481 } 1482 1483 static void max310x_remove(struct device *dev) 1484 { 1485 struct max310x_port *s = dev_get_drvdata(dev); 1486 int i; 1487 1488 for (i = 0; i < s->devtype->nr; i++) { 1489 cancel_work_sync(&s->p[i].tx_work); 1490 cancel_work_sync(&s->p[i].md_work); 1491 cancel_work_sync(&s->p[i].rs_work); 1492 1493 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) 1494 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1495 1496 max310x_power(&s->p[i].port, 0); 1497 } 1498 1499 clk_disable_unprepare(s->clk); 1500 } 1501 1502 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1503 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1504 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1505 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1506 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1507 { } 1508 }; 1509 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1510 1511 static const char *max310x_regmap_name(u8 port_id) 1512 { 1513 switch (port_id) { 1514 case 0: return "port0"; 1515 case 1: return "port1"; 1516 case 2: return "port2"; 1517 case 3: return "port3"; 1518 default: 1519 WARN_ON(true); 1520 return NULL; 1521 } 1522 } 1523 1524 #if IS_ENABLED(CONFIG_SPI_MASTER) 1525 1526 static struct regmap_config regcfg = { 1527 .reg_bits = 8, 1528 .val_bits = 8, 1529 .write_flag_mask = MAX310X_WRITE_BIT, 1530 .cache_type = REGCACHE_MAPLE, 1531 .max_register = MAX310X_REG_1F, 1532 .writeable_reg = max310x_reg_writeable, 1533 .volatile_reg = max310x_reg_volatile, 1534 .precious_reg = max310x_reg_precious, 1535 .writeable_noinc_reg = max310x_reg_noinc, 1536 .readable_noinc_reg = max310x_reg_noinc, 1537 .max_raw_read = MAX310X_FIFO_SIZE, 1538 .max_raw_write = MAX310X_FIFO_SIZE, 1539 }; 1540 1541 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1542 { 1543 struct max310x_port *s = dev_get_drvdata(dev); 1544 1545 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1546 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1547 } 1548 1549 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1550 .extended_reg_enable = max310x_spi_extended_reg_enable, 1551 .rev_id_offset = MAX310X_EXTREG_START, 1552 }; 1553 1554 static int max310x_spi_probe(struct spi_device *spi) 1555 { 1556 const struct max310x_devtype *devtype; 1557 struct regmap *regmaps[MAX310X_MAX_PORTS]; 1558 unsigned int i; 1559 int ret; 1560 1561 /* Setup SPI bus */ 1562 spi->bits_per_word = 8; 1563 spi->mode = spi->mode ? : SPI_MODE_0; 1564 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1565 ret = spi_setup(spi); 1566 if (ret) 1567 return ret; 1568 1569 devtype = spi_get_device_match_data(spi); 1570 if (!devtype) 1571 return dev_err_probe(&spi->dev, -ENODEV, "Failed to match device\n"); 1572 1573 for (i = 0; i < devtype->nr; i++) { 1574 u8 port_mask = i * 0x20; 1575 1576 regcfg.name = max310x_regmap_name(i); 1577 regcfg.read_flag_mask = port_mask; 1578 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1579 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1580 } 1581 1582 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1583 } 1584 1585 static void max310x_spi_remove(struct spi_device *spi) 1586 { 1587 max310x_remove(&spi->dev); 1588 } 1589 1590 static const struct spi_device_id max310x_id_table[] = { 1591 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1592 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1593 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1594 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1595 { } 1596 }; 1597 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1598 1599 static struct spi_driver max310x_spi_driver = { 1600 .driver = { 1601 .name = MAX310X_NAME, 1602 .of_match_table = max310x_dt_ids, 1603 .pm = &max310x_pm_ops, 1604 }, 1605 .probe = max310x_spi_probe, 1606 .remove = max310x_spi_remove, 1607 .id_table = max310x_id_table, 1608 }; 1609 #endif 1610 1611 #if IS_ENABLED(CONFIG_I2C) 1612 1613 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1614 { 1615 return 0; 1616 } 1617 1618 static struct regmap_config regcfg_i2c = { 1619 .reg_bits = 8, 1620 .val_bits = 8, 1621 .cache_type = REGCACHE_MAPLE, 1622 .writeable_reg = max310x_reg_writeable, 1623 .volatile_reg = max310x_reg_volatile, 1624 .precious_reg = max310x_reg_precious, 1625 .max_register = MAX310X_REVID_EXTREG, 1626 .writeable_noinc_reg = max310x_reg_noinc, 1627 .readable_noinc_reg = max310x_reg_noinc, 1628 .max_raw_read = MAX310X_FIFO_SIZE, 1629 .max_raw_write = MAX310X_FIFO_SIZE, 1630 }; 1631 1632 static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1633 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1634 .rev_id_offset = 0, /* No offset in I2C mode. */ 1635 }; 1636 1637 static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1638 unsigned int nr) 1639 { 1640 /* 1641 * For MAX14830 and MAX3109, the slave address depends on what the 1642 * A0 and A1 pins are tied to. 1643 * See Table I2C Address Map of the datasheet. 1644 * Based on that table, the following formulas were determined: 1645 * UART1 - UART0 = 0x10 1646 * UART2 - UART1 = 0x20 + 0x10 1647 * UART3 - UART2 = 0x10 1648 */ 1649 1650 addr -= nr * 0x10; 1651 1652 if (nr >= 2) 1653 addr -= 0x20; 1654 1655 return addr; 1656 } 1657 1658 static int max310x_i2c_probe(struct i2c_client *client) 1659 { 1660 const struct max310x_devtype *devtype; 1661 struct i2c_client *port_client; 1662 struct regmap *regmaps[MAX310X_MAX_PORTS]; 1663 unsigned int i; 1664 u8 port_addr; 1665 1666 devtype = i2c_get_match_data(client); 1667 if (!devtype) 1668 return dev_err_probe(&client->dev, -ENODEV, "Failed to match device\n"); 1669 1670 if (client->addr < devtype->slave_addr.min || 1671 client->addr > devtype->slave_addr.max) 1672 return dev_err_probe(&client->dev, -EINVAL, 1673 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1674 client->addr, devtype->slave_addr.min, 1675 devtype->slave_addr.max); 1676 1677 regcfg_i2c.name = max310x_regmap_name(0); 1678 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1679 1680 for (i = 1; i < devtype->nr; i++) { 1681 port_addr = max310x_i2c_slave_addr(client->addr, i); 1682 port_client = devm_i2c_new_dummy_device(&client->dev, 1683 client->adapter, 1684 port_addr); 1685 if (IS_ERR(port_client)) 1686 return PTR_ERR(port_client); 1687 1688 regcfg_i2c.name = max310x_regmap_name(i); 1689 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1690 } 1691 1692 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1693 regmaps, client->irq); 1694 } 1695 1696 static void max310x_i2c_remove(struct i2c_client *client) 1697 { 1698 max310x_remove(&client->dev); 1699 } 1700 1701 static const struct i2c_device_id max310x_i2c_id_table[] = { 1702 { .name = "max3107", .driver_data = (kernel_ulong_t)&max3107_devtype }, 1703 { .name = "max3108", .driver_data = (kernel_ulong_t)&max3108_devtype }, 1704 { .name = "max3109", .driver_data = (kernel_ulong_t)&max3109_devtype }, 1705 { .name = "max14830", .driver_data = (kernel_ulong_t)&max14830_devtype }, 1706 { } 1707 }; 1708 MODULE_DEVICE_TABLE(i2c, max310x_i2c_id_table); 1709 1710 static struct i2c_driver max310x_i2c_driver = { 1711 .driver = { 1712 .name = MAX310X_NAME, 1713 .of_match_table = max310x_dt_ids, 1714 .pm = &max310x_pm_ops, 1715 }, 1716 .probe = max310x_i2c_probe, 1717 .remove = max310x_i2c_remove, 1718 .id_table = max310x_i2c_id_table, 1719 }; 1720 #endif 1721 1722 static int __init max310x_uart_init(void) 1723 { 1724 int ret; 1725 1726 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1727 1728 ret = uart_register_driver(&max310x_uart); 1729 if (ret) 1730 return ret; 1731 1732 #if IS_ENABLED(CONFIG_SPI_MASTER) 1733 ret = spi_register_driver(&max310x_spi_driver); 1734 if (ret) 1735 goto err_spi_register; 1736 #endif 1737 1738 #if IS_ENABLED(CONFIG_I2C) 1739 ret = i2c_add_driver(&max310x_i2c_driver); 1740 if (ret) 1741 goto err_i2c_register; 1742 #endif 1743 1744 return 0; 1745 1746 #if IS_ENABLED(CONFIG_I2C) 1747 err_i2c_register: 1748 #endif 1749 #if IS_ENABLED(CONFIG_SPI_MASTER) 1750 spi_unregister_driver(&max310x_spi_driver); 1751 err_spi_register: 1752 #endif 1753 uart_unregister_driver(&max310x_uart); 1754 1755 return ret; 1756 } 1757 module_init(max310x_uart_init); 1758 1759 static void __exit max310x_uart_exit(void) 1760 { 1761 #if IS_ENABLED(CONFIG_I2C) 1762 i2c_del_driver(&max310x_i2c_driver); 1763 #endif 1764 1765 #if IS_ENABLED(CONFIG_SPI_MASTER) 1766 spi_unregister_driver(&max310x_spi_driver); 1767 #endif 1768 1769 uart_unregister_driver(&max310x_uart); 1770 } 1771 module_exit(max310x_uart_exit); 1772 1773 MODULE_LICENSE("GPL"); 1774 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1775 MODULE_DESCRIPTION("MAX310X serial driver"); 1776