1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/i2c.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spi/spi.h> 27 #include <linux/uaccess.h> 28 29 #define MAX310X_NAME "max310x" 30 #define MAX310X_MAJOR 204 31 #define MAX310X_MINOR 209 32 #define MAX310X_UART_NRMAX 16 33 #define MAX310X_MAX_PORTS 4 /* Maximum number of UART ports per IC. */ 34 35 /* MAX310X register definitions */ 36 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 37 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 38 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 39 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 40 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 41 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 42 #define MAX310X_REG_05 (0x05) 43 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 44 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 45 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 46 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 47 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 48 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 49 #define MAX310X_LCR_REG (0x0b) /* LCR */ 50 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 51 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 52 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 53 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 54 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 55 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 56 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 57 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 58 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 59 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 60 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 61 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 62 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 63 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 64 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 65 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 66 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 67 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 68 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 69 #define MAX310X_REG_1F (0x1f) 70 #define MAX310X_EXTREG_START (0x20) /* Only relevant in SPI mode. */ 71 72 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 73 74 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 75 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 76 77 /* Extended registers */ 78 #define MAX310X_REVID_EXTREG (0x25) /* Revision ID 79 * (extended addressing space) 80 */ 81 /* IRQ register bits */ 82 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 83 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 84 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 85 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 86 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 87 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 88 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 89 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 90 91 /* LSR register bits */ 92 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 93 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 94 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 95 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 96 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 97 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 98 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 99 100 /* Special character register bits */ 101 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 102 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 103 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 104 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 105 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 106 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 107 108 /* Status register bits */ 109 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 110 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 111 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 112 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 113 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 114 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 115 116 /* MODE1 register bits */ 117 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 118 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 119 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 120 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 121 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 122 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 123 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 124 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 125 126 /* MODE2 register bits */ 127 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 128 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 129 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 130 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 131 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 132 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 133 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 134 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 135 136 /* LCR register bits */ 137 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 138 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 139 * 140 * Word length bits table: 141 * 00 -> 5 bit words 142 * 01 -> 6 bit words 143 * 10 -> 7 bit words 144 * 11 -> 8 bit words 145 */ 146 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 147 * 148 * STOP length bit table: 149 * 0 -> 1 stop bit 150 * 1 -> 1-1.5 stop bits if 151 * word length is 5, 152 * 2 stop bits otherwise 153 */ 154 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 155 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 156 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 157 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 158 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 159 160 /* IRDA register bits */ 161 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 162 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 163 164 /* Flow control trigger level register masks */ 165 #define MAX310X_FLOWLVL_HALT_MASK GENMASK(3, 0) /* Flow control halt level */ 166 #define MAX310X_FLOWLVL_RES_MASK GENMASK(7, 4) /* Flow control resume level */ 167 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 168 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 169 170 /* FIFO interrupt trigger level register masks */ 171 #define MAX310X_FIFOTRIGLVL_TX_MASK GENMASK(3, 0) /* TX FIFO trigger level */ 172 #define MAX310X_FIFOTRIGLVL_RX_MASK GENMASK(7, 4) /* RX FIFO trigger level */ 173 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 174 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 175 176 /* Flow control register bits */ 177 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 178 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 179 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 180 * are used in conjunction with 181 * XOFF2 for definition of 182 * special character 183 */ 184 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 185 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 186 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 187 * 188 * SWFLOW bits 1 & 0 table: 189 * 00 -> no transmitter flow 190 * control 191 * 01 -> receiver compares 192 * XON2 and XOFF2 193 * and controls 194 * transmitter 195 * 10 -> receiver compares 196 * XON1 and XOFF1 197 * and controls 198 * transmitter 199 * 11 -> receiver compares 200 * XON1, XON2, XOFF1 and 201 * XOFF2 and controls 202 * transmitter 203 */ 204 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 205 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 206 * 207 * SWFLOW bits 3 & 2 table: 208 * 00 -> no received flow 209 * control 210 * 01 -> transmitter generates 211 * XON2 and XOFF2 212 * 10 -> transmitter generates 213 * XON1 and XOFF1 214 * 11 -> transmitter generates 215 * XON1, XON2, XOFF1 and 216 * XOFF2 217 */ 218 219 /* PLL configuration register masks */ 220 #define MAX310X_PLLCFG_PREDIV_MASK GENMASK(5, 0) /* PLL predivision value */ 221 #define MAX310X_PLLCFG_PLLFACTOR_MASK GENMASK(7, 6) /* PLL multiplication factor */ 222 223 /* Baud rate generator configuration register bits */ 224 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 225 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 226 227 /* Clock source register bits */ 228 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 229 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 230 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 231 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 232 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 233 234 /* Global commands */ 235 #define MAX310X_EXTREG_ENBL (0xce) 236 #define MAX310X_EXTREG_DSBL (0xcd) 237 238 /* Misc definitions */ 239 #define MAX310X_FIFO_SIZE (128) 240 #define MAX310x_REV_MASK GENMASK(7, 3) 241 #define MAX310X_WRITE_BIT 0x80 242 243 /* Port startup definitions */ 244 #define MAX310X_PORT_STARTUP_WAIT_RETRIES 20 /* Number of retries */ 245 #define MAX310X_PORT_STARTUP_WAIT_DELAY_MS 10 /* Delay between retries */ 246 247 /* Crystal-related definitions */ 248 #define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */ 249 #define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */ 250 251 /* MAX3107 specific */ 252 #define MAX3107_REV_ID (0xa0) 253 254 /* MAX3109 specific */ 255 #define MAX3109_REV_ID (0xc0) 256 257 /* MAX14830 specific */ 258 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 259 #define MAX14830_REV_ID (0xb0) 260 261 struct max310x_if_cfg { 262 int (*extended_reg_enable)(struct device *dev, bool enable); 263 u8 rev_id_offset; 264 }; 265 266 struct max310x_devtype { 267 struct { 268 unsigned short min; 269 unsigned short max; 270 } slave_addr; /* Relevant only in I2C mode. */ 271 int nr; 272 char name[9]; 273 u8 mode1; 274 u8 rev_id_val; 275 u8 rev_id_reg; /* Relevant only if rev_id_val is defined. */ 276 u8 power_reg; /* Register address for power/sleep control. */ 277 u8 power_bit; /* Bit for sleep or power-off mode (active high). */ 278 }; 279 280 struct max310x_one { 281 struct uart_port port; 282 struct work_struct tx_work; 283 struct work_struct md_work; 284 struct work_struct rs_work; 285 struct regmap *regmap; 286 287 u8 rx_buf[MAX310X_FIFO_SIZE]; 288 }; 289 #define to_max310x_port(_port) \ 290 container_of(_port, struct max310x_one, port) 291 292 struct max310x_port { 293 const struct max310x_devtype *devtype; 294 const struct max310x_if_cfg *if_cfg; 295 struct regmap *regmap; 296 struct clk *clk; 297 #ifdef CONFIG_GPIOLIB 298 struct gpio_chip gpio; 299 #endif 300 struct max310x_one p[]; 301 }; 302 303 static struct uart_driver max310x_uart = { 304 .owner = THIS_MODULE, 305 .driver_name = MAX310X_NAME, 306 .dev_name = "ttyMAX", 307 .major = MAX310X_MAJOR, 308 .minor = MAX310X_MINOR, 309 .nr = MAX310X_UART_NRMAX, 310 }; 311 312 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 313 314 static u8 max310x_port_read(struct uart_port *port, u8 reg) 315 { 316 struct max310x_one *one = to_max310x_port(port); 317 unsigned int val = 0; 318 319 regmap_read(one->regmap, reg, &val); 320 321 return val; 322 } 323 324 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 325 { 326 struct max310x_one *one = to_max310x_port(port); 327 328 regmap_write(one->regmap, reg, val); 329 } 330 331 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 332 { 333 struct max310x_one *one = to_max310x_port(port); 334 335 regmap_update_bits(one->regmap, reg, mask, val); 336 } 337 338 static int max310x_detect(struct device *dev) 339 { 340 struct max310x_port *s = dev_get_drvdata(dev); 341 unsigned int val = 0; 342 int ret; 343 344 /* Check if variant supports REV ID register: */ 345 if (s->devtype->rev_id_val) { 346 u8 rev_id_reg = s->devtype->rev_id_reg; 347 348 /* Check if REV ID is in extended addressing space: */ 349 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { 350 ret = s->if_cfg->extended_reg_enable(dev, true); 351 if (ret) 352 return ret; 353 354 /* Adjust REV ID extended addressing space address: */ 355 if (s->if_cfg->rev_id_offset) 356 rev_id_reg -= s->if_cfg->rev_id_offset; 357 } 358 359 regmap_read(s->regmap, rev_id_reg, &val); 360 361 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { 362 ret = s->if_cfg->extended_reg_enable(dev, false); 363 if (ret) 364 return ret; 365 } 366 367 if (((val & MAX310x_REV_MASK) != s->devtype->rev_id_val)) 368 return dev_err_probe(dev, -ENODEV, 369 "%s ID 0x%02x does not match\n", 370 s->devtype->name, val); 371 } else { 372 /* 373 * For variant without REV ID register, just check default value 374 * from clocksource register to make sure everything works. 375 */ 376 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 377 if (ret) 378 return ret; 379 380 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) 381 return dev_err_probe(dev, -ENODEV, 382 "%s not present\n", 383 s->devtype->name); 384 } 385 386 return 0; 387 } 388 389 static void max310x_power(struct uart_port *port, int on) 390 { 391 struct max310x_port *s = dev_get_drvdata(port->dev); 392 393 max310x_port_update(port, s->devtype->power_reg, s->devtype->power_bit, 394 on ? 0 : s->devtype->power_bit); 395 if (on) 396 msleep(50); 397 } 398 399 static const struct max310x_devtype max3107_devtype = { 400 .name = "MAX3107", 401 .nr = 1, 402 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 403 .rev_id_val = MAX3107_REV_ID, 404 .rev_id_reg = MAX310X_REVID_REG, 405 .power_reg = MAX310X_MODE1_REG, 406 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 407 .slave_addr = { 408 .min = 0x2c, 409 .max = 0x2f, 410 }, 411 }; 412 413 static const struct max310x_devtype max3108_devtype = { 414 .name = "MAX3108", 415 .nr = 1, 416 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 417 .rev_id_val = 0, /* Unsupported. */ 418 .rev_id_reg = 0, /* Irrelevant when rev_id_val is not defined. */ 419 .power_reg = MAX310X_MODE1_REG, 420 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 421 .slave_addr = { 422 .min = 0x60, 423 .max = 0x6f, 424 }, 425 }; 426 427 static const struct max310x_devtype max3109_devtype = { 428 .name = "MAX3109", 429 .nr = 2, 430 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 431 .rev_id_val = MAX3109_REV_ID, 432 .rev_id_reg = MAX310X_REVID_EXTREG, 433 .power_reg = MAX310X_MODE1_REG, 434 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 435 .slave_addr = { 436 .min = 0x60, 437 .max = 0x6f, 438 }, 439 }; 440 441 static const struct max310x_devtype max14830_devtype = { 442 .name = "MAX14830", 443 .nr = 4, 444 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 445 .rev_id_val = MAX14830_REV_ID, 446 .rev_id_reg = MAX310X_REVID_EXTREG, 447 .power_reg = MAX310X_BRGCFG_REG, 448 .power_bit = MAX14830_BRGCFG_CLKDIS_BIT, 449 .slave_addr = { 450 .min = 0x60, 451 .max = 0x6f, 452 }, 453 }; 454 455 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 456 { 457 switch (reg) { 458 case MAX310X_IRQSTS_REG: 459 case MAX310X_LSR_IRQSTS_REG: 460 case MAX310X_SPCHR_IRQSTS_REG: 461 case MAX310X_STS_IRQSTS_REG: 462 case MAX310X_TXFIFOLVL_REG: 463 case MAX310X_RXFIFOLVL_REG: 464 return false; 465 default: 466 return true; 467 } 468 } 469 470 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 471 { 472 switch (reg) { 473 case MAX310X_RHR_REG: 474 case MAX310X_IRQSTS_REG: 475 case MAX310X_LSR_IRQSTS_REG: 476 case MAX310X_SPCHR_IRQSTS_REG: 477 case MAX310X_STS_IRQSTS_REG: 478 case MAX310X_TXFIFOLVL_REG: 479 case MAX310X_RXFIFOLVL_REG: 480 case MAX310X_GPIODATA_REG: 481 case MAX310X_BRGDIVLSB_REG: 482 case MAX310X_REG_05: 483 case MAX310X_REG_1F: 484 return true; 485 default: 486 return false; 487 } 488 } 489 490 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 491 { 492 switch (reg) { 493 case MAX310X_RHR_REG: 494 case MAX310X_IRQSTS_REG: 495 case MAX310X_SPCHR_IRQSTS_REG: 496 case MAX310X_STS_IRQSTS_REG: 497 return true; 498 default: 499 return false; 500 } 501 } 502 503 static bool max310x_reg_noinc(struct device *dev, unsigned int reg) 504 { 505 return reg == MAX310X_RHR_REG; 506 } 507 508 static int max310x_set_baud(struct uart_port *port, int baud) 509 { 510 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 511 512 /* 513 * Calculate the integer divisor first. Select a proper mode 514 * in case if the requested baud is too high for the pre-defined 515 * clocks frequency. 516 */ 517 div = port->uartclk / baud; 518 if (div < 8) { 519 /* Mode x4 */ 520 c = 4; 521 mode = MAX310X_BRGCFG_4XMODE_BIT; 522 } else if (div < 16) { 523 /* Mode x2 */ 524 c = 8; 525 mode = MAX310X_BRGCFG_2XMODE_BIT; 526 } else { 527 c = 16; 528 } 529 530 /* Calculate the divisor in accordance with the fraction coefficient */ 531 div /= c; 532 F = c*baud; 533 534 /* Calculate the baud rate fraction */ 535 if (div > 0) 536 frac = (16*(port->uartclk % F)) / F; 537 else 538 div = 1; 539 540 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 541 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 542 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 543 544 /* Return the actual baud rate we just programmed */ 545 return (16*port->uartclk) / (c*(16*div + frac)); 546 } 547 548 static int max310x_update_best_err(unsigned long f, long *besterr) 549 { 550 /* Use baudrate 115200 for calculate error */ 551 long err = f % (460800 * 16); 552 553 if ((*besterr < 0) || (*besterr > err)) { 554 *besterr = err; 555 return 0; 556 } 557 558 return 1; 559 } 560 561 static s32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 562 unsigned long freq, bool xtal) 563 { 564 unsigned int div, clksrc, pllcfg = 0; 565 long besterr = -1; 566 unsigned long fdiv, fmul, bestfreq = freq; 567 568 /* First, update error without PLL */ 569 max310x_update_best_err(freq, &besterr); 570 571 /* Try all possible PLL dividers */ 572 for (div = 1; (div <= 63) && besterr; div++) { 573 fdiv = DIV_ROUND_CLOSEST(freq, div); 574 575 /* Try multiplier 6 */ 576 fmul = fdiv * 6; 577 if ((fdiv >= 500000) && (fdiv <= 800000)) 578 if (!max310x_update_best_err(fmul, &besterr)) { 579 pllcfg = (0 << 6) | div; 580 bestfreq = fmul; 581 } 582 /* Try multiplier 48 */ 583 fmul = fdiv * 48; 584 if ((fdiv >= 850000) && (fdiv <= 1200000)) 585 if (!max310x_update_best_err(fmul, &besterr)) { 586 pllcfg = (1 << 6) | div; 587 bestfreq = fmul; 588 } 589 /* Try multiplier 96 */ 590 fmul = fdiv * 96; 591 if ((fdiv >= 425000) && (fdiv <= 1000000)) 592 if (!max310x_update_best_err(fmul, &besterr)) { 593 pllcfg = (2 << 6) | div; 594 bestfreq = fmul; 595 } 596 /* Try multiplier 144 */ 597 fmul = fdiv * 144; 598 if ((fdiv >= 390000) && (fdiv <= 667000)) 599 if (!max310x_update_best_err(fmul, &besterr)) { 600 pllcfg = (3 << 6) | div; 601 bestfreq = fmul; 602 } 603 } 604 605 /* Configure clock source */ 606 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 607 608 /* Configure PLL */ 609 if (pllcfg) { 610 clksrc |= MAX310X_CLKSRC_PLL_BIT; 611 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 612 } else 613 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 614 615 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 616 617 /* Wait for crystal */ 618 if (xtal) { 619 bool stable = false; 620 unsigned int try = 0, val = 0; 621 622 do { 623 msleep(MAX310X_XTAL_WAIT_DELAY_MS); 624 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 625 626 if (val & MAX310X_STS_CLKREADY_BIT) 627 stable = true; 628 } while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES)); 629 630 if (!stable) 631 return dev_err_probe(dev, -EAGAIN, 632 "clock is not stable\n"); 633 } 634 635 return bestfreq; 636 } 637 638 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 639 { 640 struct max310x_one *one = to_max310x_port(port); 641 642 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); 643 } 644 645 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 646 { 647 struct max310x_one *one = to_max310x_port(port); 648 649 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 650 } 651 652 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 653 { 654 struct max310x_one *one = to_max310x_port(port); 655 unsigned int sts, i; 656 u8 ch, flag; 657 658 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 659 /* 660 * We are just reading, happily ignoring any error conditions. 661 * Break condition, parity checking, framing errors -- they 662 * are all ignored. That means that we can do a batch-read. 663 * 664 * There is a small opportunity for race if the RX FIFO 665 * overruns while we're reading the buffer; the datasheets says 666 * that the LSR register applies to the "current" character. 667 * That's also the reason why we cannot do batched reads when 668 * asked to check the individual statuses. 669 */ 670 671 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 672 max310x_batch_read(port, one->rx_buf, rxlen); 673 674 port->icount.rx += rxlen; 675 flag = TTY_NORMAL; 676 sts &= port->read_status_mask; 677 678 if (sts & MAX310X_LSR_RXOVR_BIT) { 679 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 680 port->icount.overrun++; 681 } 682 683 for (i = 0; i < (rxlen - 1); ++i) 684 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 685 686 /* 687 * Handle the overrun case for the last character only, since 688 * the RxFIFO overflow happens after it is pushed to the FIFO 689 * tail. 690 */ 691 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 692 one->rx_buf[rxlen-1], flag); 693 694 } else { 695 if (unlikely(rxlen >= port->fifosize)) { 696 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 697 port->icount.buf_overrun++; 698 /* Ensure sanity of RX level */ 699 rxlen = port->fifosize; 700 } 701 702 while (rxlen--) { 703 ch = max310x_port_read(port, MAX310X_RHR_REG); 704 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 705 706 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 707 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 708 709 port->icount.rx++; 710 flag = TTY_NORMAL; 711 712 if (unlikely(sts)) { 713 if (sts & MAX310X_LSR_RXBRK_BIT) { 714 port->icount.brk++; 715 if (uart_handle_break(port)) 716 continue; 717 } else if (sts & MAX310X_LSR_RXPAR_BIT) 718 port->icount.parity++; 719 else if (sts & MAX310X_LSR_FRERR_BIT) 720 port->icount.frame++; 721 else if (sts & MAX310X_LSR_RXOVR_BIT) 722 port->icount.overrun++; 723 724 sts &= port->read_status_mask; 725 if (sts & MAX310X_LSR_RXBRK_BIT) 726 flag = TTY_BREAK; 727 else if (sts & MAX310X_LSR_RXPAR_BIT) 728 flag = TTY_PARITY; 729 else if (sts & MAX310X_LSR_FRERR_BIT) 730 flag = TTY_FRAME; 731 else if (sts & MAX310X_LSR_RXOVR_BIT) 732 flag = TTY_OVERRUN; 733 } 734 735 if (uart_handle_sysrq_char(port, ch)) 736 continue; 737 738 if (sts & port->ignore_status_mask) 739 continue; 740 741 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 742 } 743 } 744 745 tty_flip_buffer_push(&port->state->port); 746 } 747 748 static void max310x_handle_tx(struct uart_port *port) 749 { 750 struct circ_buf *xmit = &port->state->xmit; 751 unsigned int txlen, to_send, until_end; 752 753 if (unlikely(port->x_char)) { 754 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 755 port->icount.tx++; 756 port->x_char = 0; 757 return; 758 } 759 760 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 761 return; 762 763 /* Get length of data pending in circular buffer */ 764 to_send = uart_circ_chars_pending(xmit); 765 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 766 if (likely(to_send)) { 767 /* Limit to space available in TX FIFO */ 768 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 769 txlen = port->fifosize - txlen; 770 to_send = (to_send > txlen) ? txlen : to_send; 771 772 if (until_end < to_send) { 773 /* 774 * It's a circ buffer -- wrap around. 775 * We could do that in one SPI transaction, but meh. 776 */ 777 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 778 max310x_batch_write(port, xmit->buf, to_send - until_end); 779 } else { 780 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 781 } 782 uart_xmit_advance(port, to_send); 783 } 784 785 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 786 uart_write_wakeup(port); 787 } 788 789 static void max310x_start_tx(struct uart_port *port) 790 { 791 struct max310x_one *one = to_max310x_port(port); 792 793 schedule_work(&one->tx_work); 794 } 795 796 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 797 { 798 struct uart_port *port = &s->p[portno].port; 799 irqreturn_t res = IRQ_NONE; 800 801 do { 802 unsigned int ists, lsr, rxlen; 803 804 /* Read IRQ status & RX FIFO level */ 805 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 806 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 807 if (!ists && !rxlen) 808 break; 809 810 res = IRQ_HANDLED; 811 812 if (ists & MAX310X_IRQ_CTS_BIT) { 813 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 814 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 815 } 816 if (rxlen) 817 max310x_handle_rx(port, rxlen); 818 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 819 max310x_start_tx(port); 820 } while (1); 821 822 return res; 823 } 824 825 static irqreturn_t max310x_ist(int irq, void *dev_id) 826 { 827 struct max310x_port *s = (struct max310x_port *)dev_id; 828 bool handled = false; 829 830 if (s->devtype->nr > 1) { 831 do { 832 unsigned int val = ~0; 833 834 WARN_ON_ONCE(regmap_read(s->regmap, 835 MAX310X_GLOBALIRQ_REG, &val)); 836 val = ((1 << s->devtype->nr) - 1) & ~val; 837 if (!val) 838 break; 839 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 840 handled = true; 841 } while (1); 842 } else { 843 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 844 handled = true; 845 } 846 847 return IRQ_RETVAL(handled); 848 } 849 850 static void max310x_tx_proc(struct work_struct *ws) 851 { 852 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 853 854 max310x_handle_tx(&one->port); 855 } 856 857 static unsigned int max310x_tx_empty(struct uart_port *port) 858 { 859 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 860 861 return lvl ? 0 : TIOCSER_TEMT; 862 } 863 864 static unsigned int max310x_get_mctrl(struct uart_port *port) 865 { 866 /* 867 * DCD and DSR are not wired and CTS/RTS is handled automatically 868 * so just indicate DSR and CAR asserted 869 */ 870 return TIOCM_DSR | TIOCM_CAR; 871 } 872 873 static void max310x_md_proc(struct work_struct *ws) 874 { 875 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 876 877 max310x_port_update(&one->port, MAX310X_MODE2_REG, 878 MAX310X_MODE2_LOOPBACK_BIT, 879 (one->port.mctrl & TIOCM_LOOP) ? 880 MAX310X_MODE2_LOOPBACK_BIT : 0); 881 } 882 883 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 884 { 885 struct max310x_one *one = to_max310x_port(port); 886 887 schedule_work(&one->md_work); 888 } 889 890 static void max310x_break_ctl(struct uart_port *port, int break_state) 891 { 892 max310x_port_update(port, MAX310X_LCR_REG, 893 MAX310X_LCR_TXBREAK_BIT, 894 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 895 } 896 897 static void max310x_set_termios(struct uart_port *port, 898 struct ktermios *termios, 899 const struct ktermios *old) 900 { 901 unsigned int lcr = 0, flow = 0; 902 int baud; 903 904 /* Mask termios capabilities we don't support */ 905 termios->c_cflag &= ~CMSPAR; 906 907 /* Word size */ 908 switch (termios->c_cflag & CSIZE) { 909 case CS5: 910 break; 911 case CS6: 912 lcr = MAX310X_LCR_LENGTH0_BIT; 913 break; 914 case CS7: 915 lcr = MAX310X_LCR_LENGTH1_BIT; 916 break; 917 case CS8: 918 default: 919 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 920 break; 921 } 922 923 /* Parity */ 924 if (termios->c_cflag & PARENB) { 925 lcr |= MAX310X_LCR_PARITY_BIT; 926 if (!(termios->c_cflag & PARODD)) 927 lcr |= MAX310X_LCR_EVENPARITY_BIT; 928 } 929 930 /* Stop bits */ 931 if (termios->c_cflag & CSTOPB) 932 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 933 934 /* Update LCR register */ 935 max310x_port_write(port, MAX310X_LCR_REG, lcr); 936 937 /* Set read status mask */ 938 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 939 if (termios->c_iflag & INPCK) 940 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 941 MAX310X_LSR_FRERR_BIT; 942 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 943 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 944 945 /* Set status ignore mask */ 946 port->ignore_status_mask = 0; 947 if (termios->c_iflag & IGNBRK) 948 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 949 if (!(termios->c_cflag & CREAD)) 950 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 951 MAX310X_LSR_RXOVR_BIT | 952 MAX310X_LSR_FRERR_BIT | 953 MAX310X_LSR_RXBRK_BIT; 954 955 /* Configure flow control */ 956 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 957 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 958 959 /* 960 * Disable transmitter before enabling AutoCTS or auto transmitter 961 * flow control 962 */ 963 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 964 max310x_port_update(port, MAX310X_MODE1_REG, 965 MAX310X_MODE1_TXDIS_BIT, 966 MAX310X_MODE1_TXDIS_BIT); 967 } 968 969 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 970 971 if (termios->c_cflag & CRTSCTS) { 972 /* Enable AUTORTS and AUTOCTS */ 973 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 974 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 975 MAX310X_FLOWCTRL_AUTORTS_BIT; 976 } 977 if (termios->c_iflag & IXON) 978 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 979 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 980 if (termios->c_iflag & IXOFF) { 981 port->status |= UPSTAT_AUTOXOFF; 982 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 983 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 984 } 985 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 986 987 /* 988 * Enable transmitter after disabling AutoCTS and auto transmitter 989 * flow control 990 */ 991 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 992 max310x_port_update(port, MAX310X_MODE1_REG, 993 MAX310X_MODE1_TXDIS_BIT, 994 0); 995 } 996 997 /* Get baud rate generator configuration */ 998 baud = uart_get_baud_rate(port, termios, old, 999 port->uartclk / 16 / 0xffff, 1000 port->uartclk / 4); 1001 1002 /* Setup baudrate generator */ 1003 baud = max310x_set_baud(port, baud); 1004 1005 /* Update timeout according to new baud rate */ 1006 uart_update_timeout(port, termios->c_cflag, baud); 1007 } 1008 1009 static void max310x_rs_proc(struct work_struct *ws) 1010 { 1011 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1012 unsigned int delay, mode1 = 0, mode2 = 0; 1013 1014 delay = (one->port.rs485.delay_rts_before_send << 4) | 1015 one->port.rs485.delay_rts_after_send; 1016 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1017 1018 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1019 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1020 1021 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1022 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1023 } 1024 1025 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1026 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1027 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1028 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1029 } 1030 1031 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1032 struct serial_rs485 *rs485) 1033 { 1034 struct max310x_one *one = to_max310x_port(port); 1035 1036 if ((rs485->delay_rts_before_send > 0x0f) || 1037 (rs485->delay_rts_after_send > 0x0f)) 1038 return -ERANGE; 1039 1040 port->rs485 = *rs485; 1041 1042 schedule_work(&one->rs_work); 1043 1044 return 0; 1045 } 1046 1047 static int max310x_startup(struct uart_port *port) 1048 { 1049 unsigned int val; 1050 1051 max310x_power(port, 1); 1052 1053 /* Configure MODE1 register */ 1054 max310x_port_update(port, MAX310X_MODE1_REG, 1055 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1056 1057 /* Configure MODE2 register & Reset FIFOs*/ 1058 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1059 max310x_port_write(port, MAX310X_MODE2_REG, val); 1060 max310x_port_update(port, MAX310X_MODE2_REG, 1061 MAX310X_MODE2_FIFORST_BIT, 0); 1062 1063 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1064 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1065 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1066 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1067 1068 if (port->rs485.flags & SER_RS485_ENABLED) { 1069 max310x_port_update(port, MAX310X_MODE1_REG, 1070 MAX310X_MODE1_TRNSCVCTRL_BIT, 1071 MAX310X_MODE1_TRNSCVCTRL_BIT); 1072 1073 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1074 max310x_port_update(port, MAX310X_MODE2_REG, 1075 MAX310X_MODE2_ECHOSUPR_BIT, 1076 MAX310X_MODE2_ECHOSUPR_BIT); 1077 } 1078 1079 /* 1080 * Configure flow control levels: 1081 * resume: 48 1082 * halt: 96 1083 */ 1084 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1085 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1086 1087 /* Clear IRQ status register */ 1088 max310x_port_read(port, MAX310X_IRQSTS_REG); 1089 1090 /* Enable RX, TX, CTS change interrupts */ 1091 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1092 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1093 1094 return 0; 1095 } 1096 1097 static void max310x_shutdown(struct uart_port *port) 1098 { 1099 /* Disable all interrupts */ 1100 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1101 1102 max310x_power(port, 0); 1103 } 1104 1105 static const char *max310x_type(struct uart_port *port) 1106 { 1107 struct max310x_port *s = dev_get_drvdata(port->dev); 1108 1109 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1110 } 1111 1112 static int max310x_request_port(struct uart_port *port) 1113 { 1114 /* Do nothing */ 1115 return 0; 1116 } 1117 1118 static void max310x_config_port(struct uart_port *port, int flags) 1119 { 1120 if (flags & UART_CONFIG_TYPE) 1121 port->type = PORT_MAX310X; 1122 } 1123 1124 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1125 { 1126 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1127 return -EINVAL; 1128 if (s->irq != port->irq) 1129 return -EINVAL; 1130 1131 return 0; 1132 } 1133 1134 static void max310x_null_void(struct uart_port *port) 1135 { 1136 /* Do nothing */ 1137 } 1138 1139 static const struct uart_ops max310x_ops = { 1140 .tx_empty = max310x_tx_empty, 1141 .set_mctrl = max310x_set_mctrl, 1142 .get_mctrl = max310x_get_mctrl, 1143 .stop_tx = max310x_null_void, 1144 .start_tx = max310x_start_tx, 1145 .stop_rx = max310x_null_void, 1146 .break_ctl = max310x_break_ctl, 1147 .startup = max310x_startup, 1148 .shutdown = max310x_shutdown, 1149 .set_termios = max310x_set_termios, 1150 .type = max310x_type, 1151 .request_port = max310x_request_port, 1152 .release_port = max310x_null_void, 1153 .config_port = max310x_config_port, 1154 .verify_port = max310x_verify_port, 1155 }; 1156 1157 static int __maybe_unused max310x_suspend(struct device *dev) 1158 { 1159 struct max310x_port *s = dev_get_drvdata(dev); 1160 int i; 1161 1162 for (i = 0; i < s->devtype->nr; i++) { 1163 uart_suspend_port(&max310x_uart, &s->p[i].port); 1164 max310x_power(&s->p[i].port, 0); 1165 } 1166 1167 return 0; 1168 } 1169 1170 static int __maybe_unused max310x_resume(struct device *dev) 1171 { 1172 struct max310x_port *s = dev_get_drvdata(dev); 1173 int i; 1174 1175 for (i = 0; i < s->devtype->nr; i++) { 1176 max310x_power(&s->p[i].port, 1); 1177 uart_resume_port(&max310x_uart, &s->p[i].port); 1178 } 1179 1180 return 0; 1181 } 1182 1183 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1184 1185 #ifdef CONFIG_GPIOLIB 1186 static int max310x_gpio_get(struct gpio_chip *chip, unsigned int offset) 1187 { 1188 unsigned int val; 1189 struct max310x_port *s = gpiochip_get_data(chip); 1190 struct uart_port *port = &s->p[offset / 4].port; 1191 1192 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1193 1194 return !!((val >> 4) & (1 << (offset % 4))); 1195 } 1196 1197 static void max310x_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1198 { 1199 struct max310x_port *s = gpiochip_get_data(chip); 1200 struct uart_port *port = &s->p[offset / 4].port; 1201 1202 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1203 value ? 1 << (offset % 4) : 0); 1204 } 1205 1206 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1207 { 1208 struct max310x_port *s = gpiochip_get_data(chip); 1209 struct uart_port *port = &s->p[offset / 4].port; 1210 1211 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1212 1213 return 0; 1214 } 1215 1216 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1217 unsigned int offset, int value) 1218 { 1219 struct max310x_port *s = gpiochip_get_data(chip); 1220 struct uart_port *port = &s->p[offset / 4].port; 1221 1222 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1223 value ? 1 << (offset % 4) : 0); 1224 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1225 1 << (offset % 4)); 1226 1227 return 0; 1228 } 1229 1230 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1231 unsigned long config) 1232 { 1233 struct max310x_port *s = gpiochip_get_data(chip); 1234 struct uart_port *port = &s->p[offset / 4].port; 1235 1236 switch (pinconf_to_config_param(config)) { 1237 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1238 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1239 1 << ((offset % 4) + 4), 1240 1 << ((offset % 4) + 4)); 1241 return 0; 1242 case PIN_CONFIG_DRIVE_PUSH_PULL: 1243 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1244 1 << ((offset % 4) + 4), 0); 1245 return 0; 1246 default: 1247 return -ENOTSUPP; 1248 } 1249 } 1250 #endif 1251 1252 static const struct serial_rs485 max310x_rs485_supported = { 1253 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1254 .delay_rts_before_send = 1, 1255 .delay_rts_after_send = 1, 1256 }; 1257 1258 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1259 const struct max310x_if_cfg *if_cfg, 1260 struct regmap *regmaps[], int irq) 1261 { 1262 int i, ret, fmin, fmax, freq; 1263 struct max310x_port *s; 1264 s32 uartclk = 0; 1265 bool xtal; 1266 1267 for (i = 0; i < devtype->nr; i++) 1268 if (IS_ERR(regmaps[i])) 1269 return PTR_ERR(regmaps[i]); 1270 1271 /* Alloc port structure */ 1272 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1273 if (!s) 1274 return dev_err_probe(dev, -ENOMEM, 1275 "Error allocating port structure\n"); 1276 1277 /* Always ask for fixed clock rate from a property. */ 1278 device_property_read_u32(dev, "clock-frequency", &uartclk); 1279 1280 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1281 if (xtal) 1282 s->clk = devm_clk_get_optional(dev, "xtal"); 1283 else 1284 s->clk = devm_clk_get_optional(dev, "osc"); 1285 if (IS_ERR(s->clk)) 1286 return PTR_ERR(s->clk); 1287 1288 ret = clk_prepare_enable(s->clk); 1289 if (ret) 1290 return ret; 1291 1292 freq = clk_get_rate(s->clk); 1293 if (freq == 0) 1294 freq = uartclk; 1295 if (freq == 0) { 1296 ret = dev_err_probe(dev, -EINVAL, "Cannot get clock rate\n"); 1297 goto out_clk; 1298 } 1299 1300 if (xtal) { 1301 fmin = 1000000; 1302 fmax = 4000000; 1303 } else { 1304 fmin = 500000; 1305 fmax = 35000000; 1306 } 1307 1308 /* Check frequency limits */ 1309 if (freq < fmin || freq > fmax) { 1310 ret = -ERANGE; 1311 goto out_clk; 1312 } 1313 1314 s->regmap = regmaps[0]; 1315 s->devtype = devtype; 1316 s->if_cfg = if_cfg; 1317 dev_set_drvdata(dev, s); 1318 1319 /* Check device to ensure we are talking to what we expect */ 1320 ret = max310x_detect(dev); 1321 if (ret) 1322 goto out_clk; 1323 1324 for (i = 0; i < devtype->nr; i++) { 1325 bool started = false; 1326 unsigned int try = 0, val = 0; 1327 1328 /* Reset port */ 1329 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1330 MAX310X_MODE2_RST_BIT); 1331 /* Clear port reset */ 1332 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1333 1334 /* Wait for port startup */ 1335 do { 1336 msleep(MAX310X_PORT_STARTUP_WAIT_DELAY_MS); 1337 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &val); 1338 1339 if (val == 0x01) 1340 started = true; 1341 } while (!started && (++try < MAX310X_PORT_STARTUP_WAIT_RETRIES)); 1342 1343 if (!started) { 1344 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n"); 1345 goto out_uart; 1346 } 1347 1348 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1349 } 1350 1351 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1352 if (uartclk < 0) { 1353 ret = uartclk; 1354 goto out_uart; 1355 } 1356 1357 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1358 1359 for (i = 0; i < devtype->nr; i++) { 1360 unsigned int line; 1361 1362 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1363 if (line == MAX310X_UART_NRMAX) { 1364 ret = -ERANGE; 1365 goto out_uart; 1366 } 1367 1368 /* Initialize port data */ 1369 s->p[i].port.line = line; 1370 s->p[i].port.dev = dev; 1371 s->p[i].port.irq = irq; 1372 s->p[i].port.type = PORT_MAX310X; 1373 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1374 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1375 s->p[i].port.iotype = UPIO_PORT; 1376 s->p[i].port.iobase = i; 1377 /* 1378 * Use all ones as membase to make sure uart_configure_port() in 1379 * serial_core.c does not abort for SPI/I2C devices where the 1380 * membase address is not applicable. 1381 */ 1382 s->p[i].port.membase = (void __iomem *)~0; 1383 s->p[i].port.uartclk = uartclk; 1384 s->p[i].port.rs485_config = max310x_rs485_config; 1385 s->p[i].port.rs485_supported = max310x_rs485_supported; 1386 s->p[i].port.ops = &max310x_ops; 1387 s->p[i].regmap = regmaps[i]; 1388 1389 /* Disable all interrupts */ 1390 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1391 /* Clear IRQ status register */ 1392 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1393 /* Initialize queue for start TX */ 1394 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1395 /* Initialize queue for changing LOOPBACK mode */ 1396 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1397 /* Initialize queue for changing RS485 mode */ 1398 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1399 1400 /* Register port */ 1401 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1402 if (ret) 1403 goto out_uart; 1404 1405 set_bit(line, max310x_lines); 1406 1407 /* Go to suspend mode */ 1408 max310x_power(&s->p[i].port, 0); 1409 } 1410 1411 #ifdef CONFIG_GPIOLIB 1412 /* Setup GPIO controller */ 1413 s->gpio.owner = THIS_MODULE; 1414 s->gpio.parent = dev; 1415 s->gpio.label = devtype->name; 1416 s->gpio.direction_input = max310x_gpio_direction_input; 1417 s->gpio.get = max310x_gpio_get; 1418 s->gpio.direction_output= max310x_gpio_direction_output; 1419 s->gpio.set = max310x_gpio_set; 1420 s->gpio.set_config = max310x_gpio_set_config; 1421 s->gpio.base = -1; 1422 s->gpio.ngpio = devtype->nr * 4; 1423 s->gpio.can_sleep = 1; 1424 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1425 if (ret) 1426 goto out_uart; 1427 #endif 1428 1429 /* Setup interrupt */ 1430 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1431 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1432 if (!ret) 1433 return 0; 1434 1435 dev_err(dev, "Unable to request IRQ %i\n", irq); 1436 1437 out_uart: 1438 for (i = 0; i < devtype->nr; i++) { 1439 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) 1440 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1441 } 1442 1443 out_clk: 1444 clk_disable_unprepare(s->clk); 1445 1446 return ret; 1447 } 1448 1449 static void max310x_remove(struct device *dev) 1450 { 1451 struct max310x_port *s = dev_get_drvdata(dev); 1452 int i; 1453 1454 for (i = 0; i < s->devtype->nr; i++) { 1455 cancel_work_sync(&s->p[i].tx_work); 1456 cancel_work_sync(&s->p[i].md_work); 1457 cancel_work_sync(&s->p[i].rs_work); 1458 1459 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) 1460 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1461 1462 max310x_power(&s->p[i].port, 0); 1463 } 1464 1465 clk_disable_unprepare(s->clk); 1466 } 1467 1468 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1469 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1470 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1471 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1472 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1473 { } 1474 }; 1475 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1476 1477 static struct regmap_config regcfg = { 1478 .reg_bits = 8, 1479 .val_bits = 8, 1480 .write_flag_mask = MAX310X_WRITE_BIT, 1481 .cache_type = REGCACHE_RBTREE, 1482 .max_register = MAX310X_REG_1F, 1483 .writeable_reg = max310x_reg_writeable, 1484 .volatile_reg = max310x_reg_volatile, 1485 .precious_reg = max310x_reg_precious, 1486 .writeable_noinc_reg = max310x_reg_noinc, 1487 .readable_noinc_reg = max310x_reg_noinc, 1488 .max_raw_read = MAX310X_FIFO_SIZE, 1489 .max_raw_write = MAX310X_FIFO_SIZE, 1490 }; 1491 1492 static const char *max310x_regmap_name(u8 port_id) 1493 { 1494 switch (port_id) { 1495 case 0: return "port0"; 1496 case 1: return "port1"; 1497 case 2: return "port2"; 1498 case 3: return "port3"; 1499 default: 1500 WARN_ON(true); 1501 return NULL; 1502 } 1503 } 1504 1505 #ifdef CONFIG_SPI_MASTER 1506 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1507 { 1508 struct max310x_port *s = dev_get_drvdata(dev); 1509 1510 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1511 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1512 } 1513 1514 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1515 .extended_reg_enable = max310x_spi_extended_reg_enable, 1516 .rev_id_offset = MAX310X_EXTREG_START, 1517 }; 1518 1519 static int max310x_spi_probe(struct spi_device *spi) 1520 { 1521 const struct max310x_devtype *devtype; 1522 struct regmap *regmaps[MAX310X_MAX_PORTS]; 1523 unsigned int i; 1524 int ret; 1525 1526 /* Setup SPI bus */ 1527 spi->bits_per_word = 8; 1528 spi->mode = spi->mode ? : SPI_MODE_0; 1529 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1530 ret = spi_setup(spi); 1531 if (ret) 1532 return ret; 1533 1534 devtype = spi_get_device_match_data(spi); 1535 if (!devtype) 1536 return dev_err_probe(&spi->dev, -ENODEV, "Failed to match device\n"); 1537 1538 for (i = 0; i < devtype->nr; i++) { 1539 u8 port_mask = i * 0x20; 1540 1541 regcfg.name = max310x_regmap_name(i); 1542 regcfg.read_flag_mask = port_mask; 1543 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1544 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1545 } 1546 1547 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1548 } 1549 1550 static void max310x_spi_remove(struct spi_device *spi) 1551 { 1552 max310x_remove(&spi->dev); 1553 } 1554 1555 static const struct spi_device_id max310x_id_table[] = { 1556 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1557 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1558 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1559 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1560 { } 1561 }; 1562 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1563 1564 static struct spi_driver max310x_spi_driver = { 1565 .driver = { 1566 .name = MAX310X_NAME, 1567 .of_match_table = max310x_dt_ids, 1568 .pm = &max310x_pm_ops, 1569 }, 1570 .probe = max310x_spi_probe, 1571 .remove = max310x_spi_remove, 1572 .id_table = max310x_id_table, 1573 }; 1574 #endif 1575 1576 #ifdef CONFIG_I2C 1577 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1578 { 1579 return 0; 1580 } 1581 1582 static struct regmap_config regcfg_i2c = { 1583 .reg_bits = 8, 1584 .val_bits = 8, 1585 .cache_type = REGCACHE_RBTREE, 1586 .writeable_reg = max310x_reg_writeable, 1587 .volatile_reg = max310x_reg_volatile, 1588 .precious_reg = max310x_reg_precious, 1589 .max_register = MAX310X_REVID_EXTREG, 1590 .writeable_noinc_reg = max310x_reg_noinc, 1591 .readable_noinc_reg = max310x_reg_noinc, 1592 .max_raw_read = MAX310X_FIFO_SIZE, 1593 .max_raw_write = MAX310X_FIFO_SIZE, 1594 }; 1595 1596 static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1597 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1598 .rev_id_offset = 0, /* No offset in I2C mode. */ 1599 }; 1600 1601 static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1602 unsigned int nr) 1603 { 1604 /* 1605 * For MAX14830 and MAX3109, the slave address depends on what the 1606 * A0 and A1 pins are tied to. 1607 * See Table I2C Address Map of the datasheet. 1608 * Based on that table, the following formulas were determined: 1609 * UART1 - UART0 = 0x10 1610 * UART2 - UART1 = 0x20 + 0x10 1611 * UART3 - UART2 = 0x10 1612 */ 1613 1614 addr -= nr * 0x10; 1615 1616 if (nr >= 2) 1617 addr -= 0x20; 1618 1619 return addr; 1620 } 1621 1622 static int max310x_i2c_probe(struct i2c_client *client) 1623 { 1624 const struct max310x_devtype *devtype; 1625 struct i2c_client *port_client; 1626 struct regmap *regmaps[MAX310X_MAX_PORTS]; 1627 unsigned int i; 1628 u8 port_addr; 1629 1630 devtype = i2c_get_match_data(client); 1631 if (!devtype) 1632 return dev_err_probe(&client->dev, -ENODEV, "Failed to match device\n"); 1633 1634 if (client->addr < devtype->slave_addr.min || 1635 client->addr > devtype->slave_addr.max) 1636 return dev_err_probe(&client->dev, -EINVAL, 1637 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1638 client->addr, devtype->slave_addr.min, 1639 devtype->slave_addr.max); 1640 1641 regcfg_i2c.name = max310x_regmap_name(0); 1642 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1643 1644 for (i = 1; i < devtype->nr; i++) { 1645 port_addr = max310x_i2c_slave_addr(client->addr, i); 1646 port_client = devm_i2c_new_dummy_device(&client->dev, 1647 client->adapter, 1648 port_addr); 1649 1650 regcfg_i2c.name = max310x_regmap_name(i); 1651 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1652 } 1653 1654 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1655 regmaps, client->irq); 1656 } 1657 1658 static void max310x_i2c_remove(struct i2c_client *client) 1659 { 1660 max310x_remove(&client->dev); 1661 } 1662 1663 static const struct i2c_device_id max310x_i2c_id_table[] = { 1664 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1665 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1666 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1667 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1668 { } 1669 }; 1670 MODULE_DEVICE_TABLE(i2c, max310x_i2c_id_table); 1671 1672 static struct i2c_driver max310x_i2c_driver = { 1673 .driver = { 1674 .name = MAX310X_NAME, 1675 .of_match_table = max310x_dt_ids, 1676 .pm = &max310x_pm_ops, 1677 }, 1678 .probe = max310x_i2c_probe, 1679 .remove = max310x_i2c_remove, 1680 .id_table = max310x_i2c_id_table, 1681 }; 1682 #endif 1683 1684 static int __init max310x_uart_init(void) 1685 { 1686 int ret; 1687 1688 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1689 1690 ret = uart_register_driver(&max310x_uart); 1691 if (ret) 1692 return ret; 1693 1694 #ifdef CONFIG_SPI_MASTER 1695 ret = spi_register_driver(&max310x_spi_driver); 1696 if (ret) 1697 goto err_spi_register; 1698 #endif 1699 1700 #ifdef CONFIG_I2C 1701 ret = i2c_add_driver(&max310x_i2c_driver); 1702 if (ret) 1703 goto err_i2c_register; 1704 #endif 1705 1706 return 0; 1707 1708 #ifdef CONFIG_I2C 1709 err_i2c_register: 1710 spi_unregister_driver(&max310x_spi_driver); 1711 #endif 1712 1713 err_spi_register: 1714 uart_unregister_driver(&max310x_uart); 1715 1716 return ret; 1717 } 1718 module_init(max310x_uart_init); 1719 1720 static void __exit max310x_uart_exit(void) 1721 { 1722 #ifdef CONFIG_I2C 1723 i2c_del_driver(&max310x_i2c_driver); 1724 #endif 1725 1726 #ifdef CONFIG_SPI_MASTER 1727 spi_unregister_driver(&max310x_spi_driver); 1728 #endif 1729 1730 uart_unregister_driver(&max310x_uart); 1731 } 1732 module_exit(max310x_uart_exit); 1733 1734 MODULE_LICENSE("GPL"); 1735 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1736 MODULE_DESCRIPTION("MAX310X serial driver"); 1737