1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/i2c.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spi/spi.h> 27 #include <linux/uaccess.h> 28 29 #define MAX310X_NAME "max310x" 30 #define MAX310X_MAJOR 204 31 #define MAX310X_MINOR 209 32 #define MAX310X_UART_NRMAX 16 33 #define MAX310X_MAX_PORTS 4 /* Maximum number of UART ports per IC. */ 34 35 /* MAX310X register definitions */ 36 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 37 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 38 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 39 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 40 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 41 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 42 #define MAX310X_REG_05 (0x05) 43 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 44 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 45 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 46 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 47 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 48 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 49 #define MAX310X_LCR_REG (0x0b) /* LCR */ 50 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 51 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 52 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 53 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 54 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 55 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 56 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 57 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 58 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 59 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 60 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 61 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 62 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 63 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 64 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 65 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 66 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 67 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 68 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 69 #define MAX310X_REG_1F (0x1f) 70 #define MAX310X_EXTREG_START (0x20) /* Only relevant in SPI mode. */ 71 72 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 73 74 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 75 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 76 77 /* Extended registers */ 78 #define MAX310X_REVID_EXTREG (0x25) /* Revision ID 79 * (extended addressing space) 80 */ 81 /* IRQ register bits */ 82 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 83 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 84 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 85 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 86 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 87 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 88 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 89 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 90 91 /* LSR register bits */ 92 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 93 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 94 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 95 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 96 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 97 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 98 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 99 100 /* Special character register bits */ 101 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 102 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 103 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 104 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 105 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 106 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 107 108 /* Status register bits */ 109 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 110 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 111 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 112 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 113 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 114 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 115 116 /* MODE1 register bits */ 117 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 118 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 119 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 120 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 121 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 122 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 123 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 124 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 125 126 /* MODE2 register bits */ 127 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 128 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 129 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 130 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 131 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 132 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 133 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 134 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 135 136 /* LCR register bits */ 137 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 138 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 139 * 140 * Word length bits table: 141 * 00 -> 5 bit words 142 * 01 -> 6 bit words 143 * 10 -> 7 bit words 144 * 11 -> 8 bit words 145 */ 146 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 147 * 148 * STOP length bit table: 149 * 0 -> 1 stop bit 150 * 1 -> 1-1.5 stop bits if 151 * word length is 5, 152 * 2 stop bits otherwise 153 */ 154 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 155 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 156 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 157 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 158 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 159 160 /* IRDA register bits */ 161 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 162 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 163 164 /* Flow control trigger level register masks */ 165 #define MAX310X_FLOWLVL_HALT_MASK GENMASK(3, 0) /* Flow control halt level */ 166 #define MAX310X_FLOWLVL_RES_MASK GENMASK(7, 4) /* Flow control resume level */ 167 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 168 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 169 170 /* FIFO interrupt trigger level register masks */ 171 #define MAX310X_FIFOTRIGLVL_TX_MASK GENMASK(3, 0) /* TX FIFO trigger level */ 172 #define MAX310X_FIFOTRIGLVL_RX_MASK GENMASK(7, 4) /* RX FIFO trigger level */ 173 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 174 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 175 176 /* Flow control register bits */ 177 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 178 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 179 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 180 * are used in conjunction with 181 * XOFF2 for definition of 182 * special character 183 */ 184 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 185 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 186 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 187 * 188 * SWFLOW bits 1 & 0 table: 189 * 00 -> no transmitter flow 190 * control 191 * 01 -> receiver compares 192 * XON2 and XOFF2 193 * and controls 194 * transmitter 195 * 10 -> receiver compares 196 * XON1 and XOFF1 197 * and controls 198 * transmitter 199 * 11 -> receiver compares 200 * XON1, XON2, XOFF1 and 201 * XOFF2 and controls 202 * transmitter 203 */ 204 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 205 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 206 * 207 * SWFLOW bits 3 & 2 table: 208 * 00 -> no received flow 209 * control 210 * 01 -> transmitter generates 211 * XON2 and XOFF2 212 * 10 -> transmitter generates 213 * XON1 and XOFF1 214 * 11 -> transmitter generates 215 * XON1, XON2, XOFF1 and 216 * XOFF2 217 */ 218 219 /* PLL configuration register masks */ 220 #define MAX310X_PLLCFG_PREDIV_MASK GENMASK(5, 0) /* PLL predivision value */ 221 #define MAX310X_PLLCFG_PLLFACTOR_MASK GENMASK(7, 6) /* PLL multiplication factor */ 222 223 /* Baud rate generator configuration register bits */ 224 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 225 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 226 227 /* Clock source register bits */ 228 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 229 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 230 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 231 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 232 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 233 234 /* Global commands */ 235 #define MAX310X_EXTREG_ENBL (0xce) 236 #define MAX310X_EXTREG_DSBL (0xcd) 237 238 /* Misc definitions */ 239 #define MAX310X_FIFO_SIZE (128) 240 #define MAX310x_REV_MASK GENMASK(7, 3) 241 #define MAX310X_WRITE_BIT 0x80 242 243 /* Port startup definitions */ 244 #define MAX310X_PORT_STARTUP_WAIT_RETRIES 20 /* Number of retries */ 245 #define MAX310X_PORT_STARTUP_WAIT_DELAY_MS 10 /* Delay between retries */ 246 247 /* Crystal-related definitions */ 248 #define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */ 249 #define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */ 250 251 /* MAX3107 specific */ 252 #define MAX3107_REV_ID (0xa0) 253 254 /* MAX3109 specific */ 255 #define MAX3109_REV_ID (0xc0) 256 257 /* MAX14830 specific */ 258 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 259 #define MAX14830_REV_ID (0xb0) 260 261 struct max310x_if_cfg { 262 int (*extended_reg_enable)(struct device *dev, bool enable); 263 u8 rev_id_offset; 264 }; 265 266 struct max310x_devtype { 267 struct { 268 unsigned short min; 269 unsigned short max; 270 } slave_addr; /* Relevant only in I2C mode. */ 271 int nr; 272 char name[9]; 273 u8 mode1; 274 u8 rev_id_val; 275 u8 rev_id_reg; /* Relevant only if rev_id_val is defined. */ 276 u8 power_reg; /* Register address for power/sleep control. */ 277 u8 power_bit; /* Bit for sleep or power-off mode (active high). */ 278 }; 279 280 struct max310x_one { 281 struct uart_port port; 282 struct work_struct tx_work; 283 struct work_struct md_work; 284 struct work_struct rs_work; 285 struct regmap *regmap; 286 287 u8 rx_buf[MAX310X_FIFO_SIZE]; 288 }; 289 #define to_max310x_port(_port) \ 290 container_of(_port, struct max310x_one, port) 291 292 struct max310x_port { 293 const struct max310x_devtype *devtype; 294 const struct max310x_if_cfg *if_cfg; 295 struct regmap *regmap; 296 struct clk *clk; 297 #ifdef CONFIG_GPIOLIB 298 struct gpio_chip gpio; 299 #endif 300 struct max310x_one p[]; 301 }; 302 303 static struct uart_driver max310x_uart = { 304 .owner = THIS_MODULE, 305 .driver_name = MAX310X_NAME, 306 .dev_name = "ttyMAX", 307 .major = MAX310X_MAJOR, 308 .minor = MAX310X_MINOR, 309 .nr = MAX310X_UART_NRMAX, 310 }; 311 312 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 313 314 static u8 max310x_port_read(struct uart_port *port, u8 reg) 315 { 316 struct max310x_one *one = to_max310x_port(port); 317 unsigned int val = 0; 318 319 regmap_read(one->regmap, reg, &val); 320 321 return val; 322 } 323 324 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 325 { 326 struct max310x_one *one = to_max310x_port(port); 327 328 regmap_write(one->regmap, reg, val); 329 } 330 331 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 332 { 333 struct max310x_one *one = to_max310x_port(port); 334 335 regmap_update_bits(one->regmap, reg, mask, val); 336 } 337 338 static int max310x_detect(struct device *dev) 339 { 340 struct max310x_port *s = dev_get_drvdata(dev); 341 unsigned int val = 0; 342 int ret; 343 344 /* Check if variant supports REV ID register: */ 345 if (s->devtype->rev_id_val) { 346 u8 rev_id_reg = s->devtype->rev_id_reg; 347 348 /* Check if REV ID is in extended addressing space: */ 349 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { 350 ret = s->if_cfg->extended_reg_enable(dev, true); 351 if (ret) 352 return ret; 353 354 /* Adjust REV ID extended addressing space address: */ 355 if (s->if_cfg->rev_id_offset) 356 rev_id_reg -= s->if_cfg->rev_id_offset; 357 } 358 359 regmap_read(s->regmap, rev_id_reg, &val); 360 361 if (s->devtype->rev_id_reg >= MAX310X_EXTREG_START) { 362 ret = s->if_cfg->extended_reg_enable(dev, false); 363 if (ret) 364 return ret; 365 } 366 367 if (((val & MAX310x_REV_MASK) != s->devtype->rev_id_val)) 368 return dev_err_probe(dev, -ENODEV, 369 "%s ID 0x%02x does not match\n", 370 s->devtype->name, val); 371 } else { 372 /* 373 * For variant without REV ID register, just check default value 374 * from clocksource register to make sure everything works. 375 */ 376 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 377 if (ret) 378 return ret; 379 380 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) 381 return dev_err_probe(dev, -ENODEV, 382 "%s not present\n", 383 s->devtype->name); 384 } 385 386 return 0; 387 } 388 389 static void max310x_power(struct uart_port *port, int on) 390 { 391 struct max310x_port *s = dev_get_drvdata(port->dev); 392 393 max310x_port_update(port, s->devtype->power_reg, s->devtype->power_bit, 394 on ? 0 : s->devtype->power_bit); 395 if (on) 396 msleep(50); 397 } 398 399 static const struct max310x_devtype max3107_devtype = { 400 .name = "MAX3107", 401 .nr = 1, 402 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 403 .rev_id_val = MAX3107_REV_ID, 404 .rev_id_reg = MAX310X_REVID_REG, 405 .power_reg = MAX310X_MODE1_REG, 406 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 407 .slave_addr = { 408 .min = 0x2c, 409 .max = 0x2f, 410 }, 411 }; 412 413 static const struct max310x_devtype max3108_devtype = { 414 .name = "MAX3108", 415 .nr = 1, 416 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 417 .rev_id_val = 0, /* Unsupported. */ 418 .rev_id_reg = 0, /* Irrelevant when rev_id_val is not defined. */ 419 .power_reg = MAX310X_MODE1_REG, 420 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 421 .slave_addr = { 422 .min = 0x60, 423 .max = 0x6f, 424 }, 425 }; 426 427 static const struct max310x_devtype max3109_devtype = { 428 .name = "MAX3109", 429 .nr = 2, 430 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 431 .rev_id_val = MAX3109_REV_ID, 432 .rev_id_reg = MAX310X_REVID_EXTREG, 433 .power_reg = MAX310X_MODE1_REG, 434 .power_bit = MAX310X_MODE1_FORCESLEEP_BIT, 435 .slave_addr = { 436 .min = 0x60, 437 .max = 0x6f, 438 }, 439 }; 440 441 static const struct max310x_devtype max14830_devtype = { 442 .name = "MAX14830", 443 .nr = 4, 444 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 445 .rev_id_val = MAX14830_REV_ID, 446 .rev_id_reg = MAX310X_REVID_EXTREG, 447 .power_reg = MAX310X_BRGCFG_REG, 448 .power_bit = MAX14830_BRGCFG_CLKDIS_BIT, 449 .slave_addr = { 450 .min = 0x60, 451 .max = 0x6f, 452 }, 453 }; 454 455 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 456 { 457 switch (reg) { 458 case MAX310X_IRQSTS_REG: 459 case MAX310X_LSR_IRQSTS_REG: 460 case MAX310X_SPCHR_IRQSTS_REG: 461 case MAX310X_STS_IRQSTS_REG: 462 case MAX310X_TXFIFOLVL_REG: 463 case MAX310X_RXFIFOLVL_REG: 464 return false; 465 default: 466 return true; 467 } 468 } 469 470 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 471 { 472 switch (reg) { 473 case MAX310X_RHR_REG: 474 case MAX310X_IRQSTS_REG: 475 case MAX310X_LSR_IRQSTS_REG: 476 case MAX310X_SPCHR_IRQSTS_REG: 477 case MAX310X_STS_IRQSTS_REG: 478 case MAX310X_TXFIFOLVL_REG: 479 case MAX310X_RXFIFOLVL_REG: 480 case MAX310X_GPIODATA_REG: 481 case MAX310X_BRGDIVLSB_REG: 482 case MAX310X_REG_05: 483 case MAX310X_REG_1F: 484 return true; 485 default: 486 return false; 487 } 488 } 489 490 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 491 { 492 switch (reg) { 493 case MAX310X_RHR_REG: 494 case MAX310X_IRQSTS_REG: 495 case MAX310X_SPCHR_IRQSTS_REG: 496 case MAX310X_STS_IRQSTS_REG: 497 return true; 498 default: 499 return false; 500 } 501 } 502 503 static bool max310x_reg_noinc(struct device *dev, unsigned int reg) 504 { 505 return reg == MAX310X_RHR_REG; 506 } 507 508 static int max310x_set_baud(struct uart_port *port, int baud) 509 { 510 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 511 512 /* 513 * Calculate the integer divisor first. Select a proper mode 514 * in case if the requested baud is too high for the pre-defined 515 * clocks frequency. 516 */ 517 div = port->uartclk / baud; 518 if (div < 8) { 519 /* Mode x4 */ 520 c = 4; 521 mode = MAX310X_BRGCFG_4XMODE_BIT; 522 } else if (div < 16) { 523 /* Mode x2 */ 524 c = 8; 525 mode = MAX310X_BRGCFG_2XMODE_BIT; 526 } else { 527 c = 16; 528 } 529 530 /* Calculate the divisor in accordance with the fraction coefficient */ 531 div /= c; 532 F = c*baud; 533 534 /* Calculate the baud rate fraction */ 535 if (div > 0) 536 frac = (16*(port->uartclk % F)) / F; 537 else 538 div = 1; 539 540 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 541 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 542 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 543 544 /* Return the actual baud rate we just programmed */ 545 return (16*port->uartclk) / (c*(16*div + frac)); 546 } 547 548 static int max310x_update_best_err(unsigned long f, long *besterr) 549 { 550 /* Use baudrate 115200 for calculate error */ 551 long err = f % (460800 * 16); 552 553 if ((*besterr < 0) || (*besterr > err)) { 554 *besterr = err; 555 return 0; 556 } 557 558 return 1; 559 } 560 561 static s32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 562 unsigned long freq, bool xtal) 563 { 564 unsigned int div, clksrc, pllcfg = 0; 565 long besterr = -1; 566 unsigned long fdiv, fmul, bestfreq = freq; 567 568 /* First, update error without PLL */ 569 max310x_update_best_err(freq, &besterr); 570 571 /* Try all possible PLL dividers */ 572 for (div = 1; (div <= 63) && besterr; div++) { 573 fdiv = DIV_ROUND_CLOSEST(freq, div); 574 575 /* Try multiplier 6 */ 576 fmul = fdiv * 6; 577 if ((fdiv >= 500000) && (fdiv <= 800000)) 578 if (!max310x_update_best_err(fmul, &besterr)) { 579 pllcfg = (0 << 6) | div; 580 bestfreq = fmul; 581 } 582 /* Try multiplier 48 */ 583 fmul = fdiv * 48; 584 if ((fdiv >= 850000) && (fdiv <= 1200000)) 585 if (!max310x_update_best_err(fmul, &besterr)) { 586 pllcfg = (1 << 6) | div; 587 bestfreq = fmul; 588 } 589 /* Try multiplier 96 */ 590 fmul = fdiv * 96; 591 if ((fdiv >= 425000) && (fdiv <= 1000000)) 592 if (!max310x_update_best_err(fmul, &besterr)) { 593 pllcfg = (2 << 6) | div; 594 bestfreq = fmul; 595 } 596 /* Try multiplier 144 */ 597 fmul = fdiv * 144; 598 if ((fdiv >= 390000) && (fdiv <= 667000)) 599 if (!max310x_update_best_err(fmul, &besterr)) { 600 pllcfg = (3 << 6) | div; 601 bestfreq = fmul; 602 } 603 } 604 605 /* Configure clock source */ 606 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 607 608 /* Configure PLL */ 609 if (pllcfg) { 610 clksrc |= MAX310X_CLKSRC_PLL_BIT; 611 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 612 } else 613 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 614 615 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 616 617 /* Wait for crystal */ 618 if (xtal) { 619 bool stable = false; 620 unsigned int try = 0, val = 0; 621 622 do { 623 msleep(MAX310X_XTAL_WAIT_DELAY_MS); 624 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 625 626 if (val & MAX310X_STS_CLKREADY_BIT) 627 stable = true; 628 } while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES)); 629 630 if (!stable) 631 return dev_err_probe(dev, -EAGAIN, 632 "clock is not stable\n"); 633 } 634 635 return bestfreq; 636 } 637 638 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 639 { 640 struct max310x_one *one = to_max310x_port(port); 641 642 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); 643 } 644 645 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 646 { 647 struct max310x_one *one = to_max310x_port(port); 648 649 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 650 } 651 652 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 653 { 654 struct max310x_one *one = to_max310x_port(port); 655 unsigned int sts, i; 656 u8 ch, flag; 657 658 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 659 /* 660 * We are just reading, happily ignoring any error conditions. 661 * Break condition, parity checking, framing errors -- they 662 * are all ignored. That means that we can do a batch-read. 663 * 664 * There is a small opportunity for race if the RX FIFO 665 * overruns while we're reading the buffer; the datasheets says 666 * that the LSR register applies to the "current" character. 667 * That's also the reason why we cannot do batched reads when 668 * asked to check the individual statuses. 669 */ 670 671 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 672 max310x_batch_read(port, one->rx_buf, rxlen); 673 674 port->icount.rx += rxlen; 675 flag = TTY_NORMAL; 676 sts &= port->read_status_mask; 677 678 if (sts & MAX310X_LSR_RXOVR_BIT) { 679 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 680 port->icount.overrun++; 681 } 682 683 for (i = 0; i < (rxlen - 1); ++i) 684 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 685 686 /* 687 * Handle the overrun case for the last character only, since 688 * the RxFIFO overflow happens after it is pushed to the FIFO 689 * tail. 690 */ 691 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 692 one->rx_buf[rxlen-1], flag); 693 694 } else { 695 if (unlikely(rxlen >= port->fifosize)) { 696 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 697 port->icount.buf_overrun++; 698 /* Ensure sanity of RX level */ 699 rxlen = port->fifosize; 700 } 701 702 while (rxlen--) { 703 ch = max310x_port_read(port, MAX310X_RHR_REG); 704 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 705 706 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 707 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 708 709 port->icount.rx++; 710 flag = TTY_NORMAL; 711 712 if (unlikely(sts)) { 713 if (sts & MAX310X_LSR_RXBRK_BIT) { 714 port->icount.brk++; 715 if (uart_handle_break(port)) 716 continue; 717 } else if (sts & MAX310X_LSR_RXPAR_BIT) 718 port->icount.parity++; 719 else if (sts & MAX310X_LSR_FRERR_BIT) 720 port->icount.frame++; 721 else if (sts & MAX310X_LSR_RXOVR_BIT) 722 port->icount.overrun++; 723 724 sts &= port->read_status_mask; 725 if (sts & MAX310X_LSR_RXBRK_BIT) 726 flag = TTY_BREAK; 727 else if (sts & MAX310X_LSR_RXPAR_BIT) 728 flag = TTY_PARITY; 729 else if (sts & MAX310X_LSR_FRERR_BIT) 730 flag = TTY_FRAME; 731 else if (sts & MAX310X_LSR_RXOVR_BIT) 732 flag = TTY_OVERRUN; 733 } 734 735 if (uart_handle_sysrq_char(port, ch)) 736 continue; 737 738 if (sts & port->ignore_status_mask) 739 continue; 740 741 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 742 } 743 } 744 745 tty_flip_buffer_push(&port->state->port); 746 } 747 748 static void max310x_handle_tx(struct uart_port *port) 749 { 750 struct tty_port *tport = &port->state->port; 751 unsigned int txlen, to_send; 752 unsigned char *tail; 753 754 if (unlikely(port->x_char)) { 755 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 756 port->icount.tx++; 757 port->x_char = 0; 758 return; 759 } 760 761 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) 762 return; 763 764 /* 765 * It's a circ buffer -- wrap around. 766 * We could do that in one SPI transaction, but meh. 767 */ 768 while (!kfifo_is_empty(&tport->xmit_fifo)) { 769 /* Limit to space available in TX FIFO */ 770 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 771 txlen = port->fifosize - txlen; 772 if (!txlen) 773 break; 774 775 to_send = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen); 776 max310x_batch_write(port, tail, to_send); 777 uart_xmit_advance(port, to_send); 778 } 779 780 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 781 uart_write_wakeup(port); 782 } 783 784 static void max310x_start_tx(struct uart_port *port) 785 { 786 struct max310x_one *one = to_max310x_port(port); 787 788 schedule_work(&one->tx_work); 789 } 790 791 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 792 { 793 struct uart_port *port = &s->p[portno].port; 794 irqreturn_t res = IRQ_NONE; 795 796 do { 797 unsigned int ists, lsr, rxlen; 798 799 /* Read IRQ status & RX FIFO level */ 800 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 801 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 802 if (!ists && !rxlen) 803 break; 804 805 res = IRQ_HANDLED; 806 807 if (ists & MAX310X_IRQ_CTS_BIT) { 808 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 809 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 810 } 811 if (rxlen) 812 max310x_handle_rx(port, rxlen); 813 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 814 max310x_start_tx(port); 815 } while (1); 816 817 return res; 818 } 819 820 static irqreturn_t max310x_ist(int irq, void *dev_id) 821 { 822 struct max310x_port *s = (struct max310x_port *)dev_id; 823 bool handled = false; 824 825 if (s->devtype->nr > 1) { 826 do { 827 unsigned int val = ~0; 828 829 WARN_ON_ONCE(regmap_read(s->regmap, 830 MAX310X_GLOBALIRQ_REG, &val)); 831 val = ((1 << s->devtype->nr) - 1) & ~val; 832 if (!val) 833 break; 834 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 835 handled = true; 836 } while (1); 837 } else { 838 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 839 handled = true; 840 } 841 842 return IRQ_RETVAL(handled); 843 } 844 845 static void max310x_tx_proc(struct work_struct *ws) 846 { 847 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 848 849 max310x_handle_tx(&one->port); 850 } 851 852 static unsigned int max310x_tx_empty(struct uart_port *port) 853 { 854 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 855 856 return lvl ? 0 : TIOCSER_TEMT; 857 } 858 859 static unsigned int max310x_get_mctrl(struct uart_port *port) 860 { 861 /* 862 * DCD and DSR are not wired and CTS/RTS is handled automatically 863 * so just indicate DSR and CAR asserted 864 */ 865 return TIOCM_DSR | TIOCM_CAR; 866 } 867 868 static void max310x_md_proc(struct work_struct *ws) 869 { 870 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 871 872 max310x_port_update(&one->port, MAX310X_MODE2_REG, 873 MAX310X_MODE2_LOOPBACK_BIT, 874 (one->port.mctrl & TIOCM_LOOP) ? 875 MAX310X_MODE2_LOOPBACK_BIT : 0); 876 } 877 878 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 879 { 880 struct max310x_one *one = to_max310x_port(port); 881 882 schedule_work(&one->md_work); 883 } 884 885 static void max310x_break_ctl(struct uart_port *port, int break_state) 886 { 887 max310x_port_update(port, MAX310X_LCR_REG, 888 MAX310X_LCR_TXBREAK_BIT, 889 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 890 } 891 892 static void max310x_set_termios(struct uart_port *port, 893 struct ktermios *termios, 894 const struct ktermios *old) 895 { 896 unsigned int lcr = 0, flow = 0; 897 int baud; 898 899 /* Mask termios capabilities we don't support */ 900 termios->c_cflag &= ~CMSPAR; 901 902 /* Word size */ 903 switch (termios->c_cflag & CSIZE) { 904 case CS5: 905 break; 906 case CS6: 907 lcr = MAX310X_LCR_LENGTH0_BIT; 908 break; 909 case CS7: 910 lcr = MAX310X_LCR_LENGTH1_BIT; 911 break; 912 case CS8: 913 default: 914 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 915 break; 916 } 917 918 /* Parity */ 919 if (termios->c_cflag & PARENB) { 920 lcr |= MAX310X_LCR_PARITY_BIT; 921 if (!(termios->c_cflag & PARODD)) 922 lcr |= MAX310X_LCR_EVENPARITY_BIT; 923 } 924 925 /* Stop bits */ 926 if (termios->c_cflag & CSTOPB) 927 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 928 929 /* Update LCR register */ 930 max310x_port_write(port, MAX310X_LCR_REG, lcr); 931 932 /* Set read status mask */ 933 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 934 if (termios->c_iflag & INPCK) 935 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 936 MAX310X_LSR_FRERR_BIT; 937 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 938 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 939 940 /* Set status ignore mask */ 941 port->ignore_status_mask = 0; 942 if (termios->c_iflag & IGNBRK) 943 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 944 if (!(termios->c_cflag & CREAD)) 945 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 946 MAX310X_LSR_RXOVR_BIT | 947 MAX310X_LSR_FRERR_BIT | 948 MAX310X_LSR_RXBRK_BIT; 949 950 /* Configure flow control */ 951 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 952 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 953 954 /* 955 * Disable transmitter before enabling AutoCTS or auto transmitter 956 * flow control 957 */ 958 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 959 max310x_port_update(port, MAX310X_MODE1_REG, 960 MAX310X_MODE1_TXDIS_BIT, 961 MAX310X_MODE1_TXDIS_BIT); 962 } 963 964 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 965 966 if (termios->c_cflag & CRTSCTS) { 967 /* Enable AUTORTS and AUTOCTS */ 968 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 969 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 970 MAX310X_FLOWCTRL_AUTORTS_BIT; 971 } 972 if (termios->c_iflag & IXON) 973 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 974 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 975 if (termios->c_iflag & IXOFF) { 976 port->status |= UPSTAT_AUTOXOFF; 977 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 978 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 979 } 980 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 981 982 /* 983 * Enable transmitter after disabling AutoCTS and auto transmitter 984 * flow control 985 */ 986 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 987 max310x_port_update(port, MAX310X_MODE1_REG, 988 MAX310X_MODE1_TXDIS_BIT, 989 0); 990 } 991 992 /* Get baud rate generator configuration */ 993 baud = uart_get_baud_rate(port, termios, old, 994 port->uartclk / 16 / 0xffff, 995 port->uartclk / 4); 996 997 /* Setup baudrate generator */ 998 baud = max310x_set_baud(port, baud); 999 1000 /* Update timeout according to new baud rate */ 1001 uart_update_timeout(port, termios->c_cflag, baud); 1002 } 1003 1004 static void max310x_rs_proc(struct work_struct *ws) 1005 { 1006 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1007 unsigned int delay, mode1 = 0, mode2 = 0; 1008 1009 delay = (one->port.rs485.delay_rts_before_send << 4) | 1010 one->port.rs485.delay_rts_after_send; 1011 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1012 1013 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1014 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1015 1016 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1017 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1018 } 1019 1020 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1021 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1022 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1023 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1024 } 1025 1026 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1027 struct serial_rs485 *rs485) 1028 { 1029 struct max310x_one *one = to_max310x_port(port); 1030 1031 if ((rs485->delay_rts_before_send > 0x0f) || 1032 (rs485->delay_rts_after_send > 0x0f)) 1033 return -ERANGE; 1034 1035 port->rs485 = *rs485; 1036 1037 schedule_work(&one->rs_work); 1038 1039 return 0; 1040 } 1041 1042 static int max310x_startup(struct uart_port *port) 1043 { 1044 unsigned int val; 1045 1046 max310x_power(port, 1); 1047 1048 /* Configure MODE1 register */ 1049 max310x_port_update(port, MAX310X_MODE1_REG, 1050 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1051 1052 /* Configure MODE2 register & Reset FIFOs*/ 1053 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1054 max310x_port_write(port, MAX310X_MODE2_REG, val); 1055 max310x_port_update(port, MAX310X_MODE2_REG, 1056 MAX310X_MODE2_FIFORST_BIT, 0); 1057 1058 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1059 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1060 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1061 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1062 1063 if (port->rs485.flags & SER_RS485_ENABLED) { 1064 max310x_port_update(port, MAX310X_MODE1_REG, 1065 MAX310X_MODE1_TRNSCVCTRL_BIT, 1066 MAX310X_MODE1_TRNSCVCTRL_BIT); 1067 1068 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1069 max310x_port_update(port, MAX310X_MODE2_REG, 1070 MAX310X_MODE2_ECHOSUPR_BIT, 1071 MAX310X_MODE2_ECHOSUPR_BIT); 1072 } 1073 1074 /* 1075 * Configure flow control levels: 1076 * resume: 48 1077 * halt: 96 1078 */ 1079 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1080 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1081 1082 /* Clear IRQ status register */ 1083 max310x_port_read(port, MAX310X_IRQSTS_REG); 1084 1085 /* Enable RX, TX, CTS change interrupts */ 1086 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1087 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1088 1089 return 0; 1090 } 1091 1092 static void max310x_shutdown(struct uart_port *port) 1093 { 1094 /* Disable all interrupts */ 1095 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1096 1097 max310x_power(port, 0); 1098 } 1099 1100 static const char *max310x_type(struct uart_port *port) 1101 { 1102 struct max310x_port *s = dev_get_drvdata(port->dev); 1103 1104 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1105 } 1106 1107 static int max310x_request_port(struct uart_port *port) 1108 { 1109 /* Do nothing */ 1110 return 0; 1111 } 1112 1113 static void max310x_config_port(struct uart_port *port, int flags) 1114 { 1115 if (flags & UART_CONFIG_TYPE) 1116 port->type = PORT_MAX310X; 1117 } 1118 1119 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1120 { 1121 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1122 return -EINVAL; 1123 if (s->irq != port->irq) 1124 return -EINVAL; 1125 1126 return 0; 1127 } 1128 1129 static void max310x_null_void(struct uart_port *port) 1130 { 1131 /* Do nothing */ 1132 } 1133 1134 static const struct uart_ops max310x_ops = { 1135 .tx_empty = max310x_tx_empty, 1136 .set_mctrl = max310x_set_mctrl, 1137 .get_mctrl = max310x_get_mctrl, 1138 .stop_tx = max310x_null_void, 1139 .start_tx = max310x_start_tx, 1140 .stop_rx = max310x_null_void, 1141 .break_ctl = max310x_break_ctl, 1142 .startup = max310x_startup, 1143 .shutdown = max310x_shutdown, 1144 .set_termios = max310x_set_termios, 1145 .type = max310x_type, 1146 .request_port = max310x_request_port, 1147 .release_port = max310x_null_void, 1148 .config_port = max310x_config_port, 1149 .verify_port = max310x_verify_port, 1150 }; 1151 1152 static int __maybe_unused max310x_suspend(struct device *dev) 1153 { 1154 struct max310x_port *s = dev_get_drvdata(dev); 1155 int i; 1156 1157 for (i = 0; i < s->devtype->nr; i++) { 1158 uart_suspend_port(&max310x_uart, &s->p[i].port); 1159 max310x_power(&s->p[i].port, 0); 1160 } 1161 1162 return 0; 1163 } 1164 1165 static int __maybe_unused max310x_resume(struct device *dev) 1166 { 1167 struct max310x_port *s = dev_get_drvdata(dev); 1168 int i; 1169 1170 for (i = 0; i < s->devtype->nr; i++) { 1171 max310x_power(&s->p[i].port, 1); 1172 uart_resume_port(&max310x_uart, &s->p[i].port); 1173 } 1174 1175 return 0; 1176 } 1177 1178 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1179 1180 #ifdef CONFIG_GPIOLIB 1181 static int max310x_gpio_get(struct gpio_chip *chip, unsigned int offset) 1182 { 1183 unsigned int val; 1184 struct max310x_port *s = gpiochip_get_data(chip); 1185 struct uart_port *port = &s->p[offset / 4].port; 1186 1187 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1188 1189 return !!((val >> 4) & (1 << (offset % 4))); 1190 } 1191 1192 static void max310x_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1193 { 1194 struct max310x_port *s = gpiochip_get_data(chip); 1195 struct uart_port *port = &s->p[offset / 4].port; 1196 1197 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1198 value ? 1 << (offset % 4) : 0); 1199 } 1200 1201 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1202 { 1203 struct max310x_port *s = gpiochip_get_data(chip); 1204 struct uart_port *port = &s->p[offset / 4].port; 1205 1206 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1207 1208 return 0; 1209 } 1210 1211 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1212 unsigned int offset, int value) 1213 { 1214 struct max310x_port *s = gpiochip_get_data(chip); 1215 struct uart_port *port = &s->p[offset / 4].port; 1216 1217 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1218 value ? 1 << (offset % 4) : 0); 1219 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1220 1 << (offset % 4)); 1221 1222 return 0; 1223 } 1224 1225 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1226 unsigned long config) 1227 { 1228 struct max310x_port *s = gpiochip_get_data(chip); 1229 struct uart_port *port = &s->p[offset / 4].port; 1230 1231 switch (pinconf_to_config_param(config)) { 1232 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1233 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1234 1 << ((offset % 4) + 4), 1235 1 << ((offset % 4) + 4)); 1236 return 0; 1237 case PIN_CONFIG_DRIVE_PUSH_PULL: 1238 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1239 1 << ((offset % 4) + 4), 0); 1240 return 0; 1241 default: 1242 return -ENOTSUPP; 1243 } 1244 } 1245 #endif 1246 1247 static const struct serial_rs485 max310x_rs485_supported = { 1248 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1249 .delay_rts_before_send = 1, 1250 .delay_rts_after_send = 1, 1251 }; 1252 1253 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1254 const struct max310x_if_cfg *if_cfg, 1255 struct regmap *regmaps[], int irq) 1256 { 1257 int i, ret, fmin, fmax, freq; 1258 struct max310x_port *s; 1259 s32 uartclk = 0; 1260 bool xtal; 1261 1262 for (i = 0; i < devtype->nr; i++) 1263 if (IS_ERR(regmaps[i])) 1264 return PTR_ERR(regmaps[i]); 1265 1266 /* Alloc port structure */ 1267 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1268 if (!s) 1269 return dev_err_probe(dev, -ENOMEM, 1270 "Error allocating port structure\n"); 1271 1272 /* Always ask for fixed clock rate from a property. */ 1273 device_property_read_u32(dev, "clock-frequency", &uartclk); 1274 1275 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1276 if (xtal) 1277 s->clk = devm_clk_get_optional(dev, "xtal"); 1278 else 1279 s->clk = devm_clk_get_optional(dev, "osc"); 1280 if (IS_ERR(s->clk)) 1281 return PTR_ERR(s->clk); 1282 1283 ret = clk_prepare_enable(s->clk); 1284 if (ret) 1285 return ret; 1286 1287 freq = clk_get_rate(s->clk); 1288 if (freq == 0) 1289 freq = uartclk; 1290 if (freq == 0) { 1291 ret = dev_err_probe(dev, -EINVAL, "Cannot get clock rate\n"); 1292 goto out_clk; 1293 } 1294 1295 if (xtal) { 1296 fmin = 1000000; 1297 fmax = 4000000; 1298 } else { 1299 fmin = 500000; 1300 fmax = 35000000; 1301 } 1302 1303 /* Check frequency limits */ 1304 if (freq < fmin || freq > fmax) { 1305 ret = -ERANGE; 1306 goto out_clk; 1307 } 1308 1309 s->regmap = regmaps[0]; 1310 s->devtype = devtype; 1311 s->if_cfg = if_cfg; 1312 dev_set_drvdata(dev, s); 1313 1314 /* Check device to ensure we are talking to what we expect */ 1315 ret = max310x_detect(dev); 1316 if (ret) 1317 goto out_clk; 1318 1319 for (i = 0; i < devtype->nr; i++) { 1320 bool started = false; 1321 unsigned int try = 0, val = 0; 1322 1323 /* Reset port */ 1324 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1325 MAX310X_MODE2_RST_BIT); 1326 /* Clear port reset */ 1327 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1328 1329 /* Wait for port startup */ 1330 do { 1331 msleep(MAX310X_PORT_STARTUP_WAIT_DELAY_MS); 1332 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &val); 1333 1334 if (val == 0x01) 1335 started = true; 1336 } while (!started && (++try < MAX310X_PORT_STARTUP_WAIT_RETRIES)); 1337 1338 if (!started) { 1339 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n"); 1340 goto out_uart; 1341 } 1342 1343 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1344 } 1345 1346 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1347 if (uartclk < 0) { 1348 ret = uartclk; 1349 goto out_uart; 1350 } 1351 1352 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1353 1354 for (i = 0; i < devtype->nr; i++) { 1355 unsigned int line; 1356 1357 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1358 if (line == MAX310X_UART_NRMAX) { 1359 ret = -ERANGE; 1360 goto out_uart; 1361 } 1362 1363 /* Initialize port data */ 1364 s->p[i].port.line = line; 1365 s->p[i].port.dev = dev; 1366 s->p[i].port.irq = irq; 1367 s->p[i].port.type = PORT_MAX310X; 1368 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1369 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1370 s->p[i].port.iotype = UPIO_PORT; 1371 s->p[i].port.iobase = i; 1372 /* 1373 * Use all ones as membase to make sure uart_configure_port() in 1374 * serial_core.c does not abort for SPI/I2C devices where the 1375 * membase address is not applicable. 1376 */ 1377 s->p[i].port.membase = (void __iomem *)~0; 1378 s->p[i].port.uartclk = uartclk; 1379 s->p[i].port.rs485_config = max310x_rs485_config; 1380 s->p[i].port.rs485_supported = max310x_rs485_supported; 1381 s->p[i].port.ops = &max310x_ops; 1382 s->p[i].regmap = regmaps[i]; 1383 1384 /* Disable all interrupts */ 1385 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1386 /* Clear IRQ status register */ 1387 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1388 /* Initialize queue for start TX */ 1389 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1390 /* Initialize queue for changing LOOPBACK mode */ 1391 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1392 /* Initialize queue for changing RS485 mode */ 1393 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1394 1395 /* Register port */ 1396 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1397 if (ret) 1398 goto out_uart; 1399 1400 set_bit(line, max310x_lines); 1401 1402 /* Go to suspend mode */ 1403 max310x_power(&s->p[i].port, 0); 1404 } 1405 1406 #ifdef CONFIG_GPIOLIB 1407 /* Setup GPIO controller */ 1408 s->gpio.owner = THIS_MODULE; 1409 s->gpio.parent = dev; 1410 s->gpio.label = devtype->name; 1411 s->gpio.direction_input = max310x_gpio_direction_input; 1412 s->gpio.get = max310x_gpio_get; 1413 s->gpio.direction_output= max310x_gpio_direction_output; 1414 s->gpio.set = max310x_gpio_set; 1415 s->gpio.set_config = max310x_gpio_set_config; 1416 s->gpio.base = -1; 1417 s->gpio.ngpio = devtype->nr * 4; 1418 s->gpio.can_sleep = 1; 1419 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1420 if (ret) 1421 goto out_uart; 1422 #endif 1423 1424 /* Setup interrupt */ 1425 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1426 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1427 if (!ret) 1428 return 0; 1429 1430 dev_err(dev, "Unable to request IRQ %i\n", irq); 1431 1432 out_uart: 1433 for (i = 0; i < devtype->nr; i++) { 1434 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) 1435 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1436 } 1437 1438 out_clk: 1439 clk_disable_unprepare(s->clk); 1440 1441 return ret; 1442 } 1443 1444 static void max310x_remove(struct device *dev) 1445 { 1446 struct max310x_port *s = dev_get_drvdata(dev); 1447 int i; 1448 1449 for (i = 0; i < s->devtype->nr; i++) { 1450 cancel_work_sync(&s->p[i].tx_work); 1451 cancel_work_sync(&s->p[i].md_work); 1452 cancel_work_sync(&s->p[i].rs_work); 1453 1454 if (test_and_clear_bit(s->p[i].port.line, max310x_lines)) 1455 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1456 1457 max310x_power(&s->p[i].port, 0); 1458 } 1459 1460 clk_disable_unprepare(s->clk); 1461 } 1462 1463 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1464 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1465 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1466 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1467 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1468 { } 1469 }; 1470 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1471 1472 static struct regmap_config regcfg = { 1473 .reg_bits = 8, 1474 .val_bits = 8, 1475 .write_flag_mask = MAX310X_WRITE_BIT, 1476 .cache_type = REGCACHE_MAPLE, 1477 .max_register = MAX310X_REG_1F, 1478 .writeable_reg = max310x_reg_writeable, 1479 .volatile_reg = max310x_reg_volatile, 1480 .precious_reg = max310x_reg_precious, 1481 .writeable_noinc_reg = max310x_reg_noinc, 1482 .readable_noinc_reg = max310x_reg_noinc, 1483 .max_raw_read = MAX310X_FIFO_SIZE, 1484 .max_raw_write = MAX310X_FIFO_SIZE, 1485 }; 1486 1487 static const char *max310x_regmap_name(u8 port_id) 1488 { 1489 switch (port_id) { 1490 case 0: return "port0"; 1491 case 1: return "port1"; 1492 case 2: return "port2"; 1493 case 3: return "port3"; 1494 default: 1495 WARN_ON(true); 1496 return NULL; 1497 } 1498 } 1499 1500 #ifdef CONFIG_SPI_MASTER 1501 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1502 { 1503 struct max310x_port *s = dev_get_drvdata(dev); 1504 1505 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1506 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1507 } 1508 1509 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1510 .extended_reg_enable = max310x_spi_extended_reg_enable, 1511 .rev_id_offset = MAX310X_EXTREG_START, 1512 }; 1513 1514 static int max310x_spi_probe(struct spi_device *spi) 1515 { 1516 const struct max310x_devtype *devtype; 1517 struct regmap *regmaps[MAX310X_MAX_PORTS]; 1518 unsigned int i; 1519 int ret; 1520 1521 /* Setup SPI bus */ 1522 spi->bits_per_word = 8; 1523 spi->mode = spi->mode ? : SPI_MODE_0; 1524 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1525 ret = spi_setup(spi); 1526 if (ret) 1527 return ret; 1528 1529 devtype = spi_get_device_match_data(spi); 1530 if (!devtype) 1531 return dev_err_probe(&spi->dev, -ENODEV, "Failed to match device\n"); 1532 1533 for (i = 0; i < devtype->nr; i++) { 1534 u8 port_mask = i * 0x20; 1535 1536 regcfg.name = max310x_regmap_name(i); 1537 regcfg.read_flag_mask = port_mask; 1538 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1539 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1540 } 1541 1542 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1543 } 1544 1545 static void max310x_spi_remove(struct spi_device *spi) 1546 { 1547 max310x_remove(&spi->dev); 1548 } 1549 1550 static const struct spi_device_id max310x_id_table[] = { 1551 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1552 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1553 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1554 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1555 { } 1556 }; 1557 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1558 1559 static struct spi_driver max310x_spi_driver = { 1560 .driver = { 1561 .name = MAX310X_NAME, 1562 .of_match_table = max310x_dt_ids, 1563 .pm = &max310x_pm_ops, 1564 }, 1565 .probe = max310x_spi_probe, 1566 .remove = max310x_spi_remove, 1567 .id_table = max310x_id_table, 1568 }; 1569 #endif 1570 1571 #ifdef CONFIG_I2C 1572 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1573 { 1574 return 0; 1575 } 1576 1577 static struct regmap_config regcfg_i2c = { 1578 .reg_bits = 8, 1579 .val_bits = 8, 1580 .cache_type = REGCACHE_MAPLE, 1581 .writeable_reg = max310x_reg_writeable, 1582 .volatile_reg = max310x_reg_volatile, 1583 .precious_reg = max310x_reg_precious, 1584 .max_register = MAX310X_REVID_EXTREG, 1585 .writeable_noinc_reg = max310x_reg_noinc, 1586 .readable_noinc_reg = max310x_reg_noinc, 1587 .max_raw_read = MAX310X_FIFO_SIZE, 1588 .max_raw_write = MAX310X_FIFO_SIZE, 1589 }; 1590 1591 static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1592 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1593 .rev_id_offset = 0, /* No offset in I2C mode. */ 1594 }; 1595 1596 static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1597 unsigned int nr) 1598 { 1599 /* 1600 * For MAX14830 and MAX3109, the slave address depends on what the 1601 * A0 and A1 pins are tied to. 1602 * See Table I2C Address Map of the datasheet. 1603 * Based on that table, the following formulas were determined: 1604 * UART1 - UART0 = 0x10 1605 * UART2 - UART1 = 0x20 + 0x10 1606 * UART3 - UART2 = 0x10 1607 */ 1608 1609 addr -= nr * 0x10; 1610 1611 if (nr >= 2) 1612 addr -= 0x20; 1613 1614 return addr; 1615 } 1616 1617 static int max310x_i2c_probe(struct i2c_client *client) 1618 { 1619 const struct max310x_devtype *devtype; 1620 struct i2c_client *port_client; 1621 struct regmap *regmaps[MAX310X_MAX_PORTS]; 1622 unsigned int i; 1623 u8 port_addr; 1624 1625 devtype = i2c_get_match_data(client); 1626 if (!devtype) 1627 return dev_err_probe(&client->dev, -ENODEV, "Failed to match device\n"); 1628 1629 if (client->addr < devtype->slave_addr.min || 1630 client->addr > devtype->slave_addr.max) 1631 return dev_err_probe(&client->dev, -EINVAL, 1632 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1633 client->addr, devtype->slave_addr.min, 1634 devtype->slave_addr.max); 1635 1636 regcfg_i2c.name = max310x_regmap_name(0); 1637 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1638 1639 for (i = 1; i < devtype->nr; i++) { 1640 port_addr = max310x_i2c_slave_addr(client->addr, i); 1641 port_client = devm_i2c_new_dummy_device(&client->dev, 1642 client->adapter, 1643 port_addr); 1644 1645 regcfg_i2c.name = max310x_regmap_name(i); 1646 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1647 } 1648 1649 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1650 regmaps, client->irq); 1651 } 1652 1653 static void max310x_i2c_remove(struct i2c_client *client) 1654 { 1655 max310x_remove(&client->dev); 1656 } 1657 1658 static const struct i2c_device_id max310x_i2c_id_table[] = { 1659 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1660 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1661 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1662 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1663 { } 1664 }; 1665 MODULE_DEVICE_TABLE(i2c, max310x_i2c_id_table); 1666 1667 static struct i2c_driver max310x_i2c_driver = { 1668 .driver = { 1669 .name = MAX310X_NAME, 1670 .of_match_table = max310x_dt_ids, 1671 .pm = &max310x_pm_ops, 1672 }, 1673 .probe = max310x_i2c_probe, 1674 .remove = max310x_i2c_remove, 1675 .id_table = max310x_i2c_id_table, 1676 }; 1677 #endif 1678 1679 static int __init max310x_uart_init(void) 1680 { 1681 int ret; 1682 1683 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1684 1685 ret = uart_register_driver(&max310x_uart); 1686 if (ret) 1687 return ret; 1688 1689 #ifdef CONFIG_SPI_MASTER 1690 ret = spi_register_driver(&max310x_spi_driver); 1691 if (ret) 1692 goto err_spi_register; 1693 #endif 1694 1695 #ifdef CONFIG_I2C 1696 ret = i2c_add_driver(&max310x_i2c_driver); 1697 if (ret) 1698 goto err_i2c_register; 1699 #endif 1700 1701 return 0; 1702 1703 #ifdef CONFIG_I2C 1704 err_i2c_register: 1705 spi_unregister_driver(&max310x_spi_driver); 1706 #endif 1707 1708 err_spi_register: 1709 uart_unregister_driver(&max310x_uart); 1710 1711 return ret; 1712 } 1713 module_init(max310x_uart_init); 1714 1715 static void __exit max310x_uart_exit(void) 1716 { 1717 #ifdef CONFIG_I2C 1718 i2c_del_driver(&max310x_i2c_driver); 1719 #endif 1720 1721 #ifdef CONFIG_SPI_MASTER 1722 spi_unregister_driver(&max310x_spi_driver); 1723 #endif 1724 1725 uart_unregister_driver(&max310x_uart); 1726 } 1727 module_exit(max310x_uart_exit); 1728 1729 MODULE_LICENSE("GPL"); 1730 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1731 MODULE_DESCRIPTION("MAX310X serial driver"); 1732