1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 4 * 5 * Copyright (C) 2004 Infineon IFAP DC COM CPE 6 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> 7 * Copyright (C) 2007 John Crispin <john@phrozen.org> 8 * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/console.h> 14 #include <linux/device.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/lantiq.h> 19 #include <linux/module.h> 20 #include <linux/of_platform.h> 21 #include <linux/serial.h> 22 #include <linux/serial_core.h> 23 #include <linux/slab.h> 24 #include <linux/sysrq.h> 25 #include <linux/tty.h> 26 #include <linux/tty_flip.h> 27 28 #define PORT_LTQ_ASC 111 29 #define MAXPORTS 2 30 #define UART_DUMMY_UER_RX 1 31 #define DRVNAME "lantiq,asc" 32 #ifdef __BIG_ENDIAN 33 #define LTQ_ASC_TBUF (0x0020 + 3) 34 #define LTQ_ASC_RBUF (0x0024 + 3) 35 #else 36 #define LTQ_ASC_TBUF 0x0020 37 #define LTQ_ASC_RBUF 0x0024 38 #endif 39 #define LTQ_ASC_FSTAT 0x0048 40 #define LTQ_ASC_WHBSTATE 0x0018 41 #define LTQ_ASC_STATE 0x0014 42 #define LTQ_ASC_IRNCR 0x00F8 43 #define LTQ_ASC_CLC 0x0000 44 #define LTQ_ASC_ID 0x0008 45 #define LTQ_ASC_PISEL 0x0004 46 #define LTQ_ASC_TXFCON 0x0044 47 #define LTQ_ASC_RXFCON 0x0040 48 #define LTQ_ASC_CON 0x0010 49 #define LTQ_ASC_BG 0x0050 50 #define LTQ_ASC_IRNREN 0x00F4 51 52 #define ASC_IRNREN_TX 0x1 53 #define ASC_IRNREN_RX 0x2 54 #define ASC_IRNREN_ERR 0x4 55 #define ASC_IRNREN_TX_BUF 0x8 56 #define ASC_IRNCR_TIR 0x1 57 #define ASC_IRNCR_RIR 0x2 58 #define ASC_IRNCR_EIR 0x4 59 #define ASC_IRNCR_MASK GENMASK(2, 0) 60 61 #define ASCOPT_CSIZE 0x3 62 #define TXFIFO_FL 1 63 #define RXFIFO_FL 1 64 #define ASCCLC_DISS 0x2 65 #define ASCCLC_RMCMASK 0x0000FF00 66 #define ASCCLC_RMCOFFSET 8 67 #define ASCCON_M_8ASYNC 0x0 68 #define ASCCON_M_7ASYNC 0x2 69 #define ASCCON_ODD 0x00000020 70 #define ASCCON_STP 0x00000080 71 #define ASCCON_BRS 0x00000100 72 #define ASCCON_FDE 0x00000200 73 #define ASCCON_R 0x00008000 74 #define ASCCON_FEN 0x00020000 75 #define ASCCON_ROEN 0x00080000 76 #define ASCCON_TOEN 0x00100000 77 #define ASCSTATE_PE 0x00010000 78 #define ASCSTATE_FE 0x00020000 79 #define ASCSTATE_ROE 0x00080000 80 #define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) 81 #define ASCWHBSTATE_CLRREN 0x00000001 82 #define ASCWHBSTATE_SETREN 0x00000002 83 #define ASCWHBSTATE_CLRPE 0x00000004 84 #define ASCWHBSTATE_CLRFE 0x00000008 85 #define ASCWHBSTATE_CLRROE 0x00000020 86 #define ASCTXFCON_TXFEN 0x0001 87 #define ASCTXFCON_TXFFLU 0x0002 88 #define ASCTXFCON_TXFITLMASK 0x3F00 89 #define ASCTXFCON_TXFITLOFF 8 90 #define ASCRXFCON_RXFEN 0x0001 91 #define ASCRXFCON_RXFFLU 0x0002 92 #define ASCRXFCON_RXFITLMASK 0x3F00 93 #define ASCRXFCON_RXFITLOFF 8 94 #define ASCFSTAT_RXFFLMASK 0x003F 95 #define ASCFSTAT_TXFFLMASK 0x3F00 96 #define ASCFSTAT_TXFREEMASK 0x3F000000 97 98 static struct ltq_uart_port *lqasc_port[MAXPORTS]; 99 static struct uart_driver lqasc_reg; 100 101 struct ltq_soc_data { 102 int (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port); 103 int (*request_irq)(struct uart_port *port); 104 void (*free_irq)(struct uart_port *port); 105 }; 106 107 struct ltq_uart_port { 108 struct uart_port port; 109 /* clock used to derive divider */ 110 struct clk *freqclk; 111 /* clock gating of the ASC core */ 112 struct clk *clk; 113 unsigned int tx_irq; 114 unsigned int rx_irq; 115 unsigned int err_irq; 116 unsigned int common_irq; 117 spinlock_t lock; /* exclusive access for multi core */ 118 119 const struct ltq_soc_data *soc; 120 }; 121 122 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) 123 { 124 u32 tmp = __raw_readl(reg); 125 126 __raw_writel((tmp & ~clear) | set, reg); 127 } 128 129 static inline struct 130 ltq_uart_port *to_ltq_uart_port(struct uart_port *port) 131 { 132 return container_of(port, struct ltq_uart_port, port); 133 } 134 135 static void 136 lqasc_stop_tx(struct uart_port *port) 137 { 138 return; 139 } 140 141 static bool lqasc_tx_ready(struct uart_port *port) 142 { 143 u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT); 144 145 return FIELD_GET(ASCFSTAT_TXFREEMASK, fstat); 146 } 147 148 static void 149 lqasc_start_tx(struct uart_port *port) 150 { 151 unsigned long flags; 152 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 153 u8 ch; 154 155 spin_lock_irqsave(<q_port->lock, flags); 156 uart_port_tx(port, ch, 157 lqasc_tx_ready(port), 158 writeb(ch, port->membase + LTQ_ASC_TBUF)); 159 spin_unlock_irqrestore(<q_port->lock, flags); 160 return; 161 } 162 163 static void 164 lqasc_stop_rx(struct uart_port *port) 165 { 166 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 167 } 168 169 static int 170 lqasc_rx_chars(struct uart_port *port) 171 { 172 struct tty_port *tport = &port->state->port; 173 unsigned int ch = 0, rsr = 0, fifocnt; 174 175 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 176 ASCFSTAT_RXFFLMASK; 177 while (fifocnt--) { 178 u8 flag = TTY_NORMAL; 179 ch = readb(port->membase + LTQ_ASC_RBUF); 180 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) 181 & ASCSTATE_ANY) | UART_DUMMY_UER_RX; 182 tty_flip_buffer_push(tport); 183 port->icount.rx++; 184 185 /* 186 * Note that the error handling code is 187 * out of the main execution path 188 */ 189 if (rsr & ASCSTATE_ANY) { 190 if (rsr & ASCSTATE_PE) { 191 port->icount.parity++; 192 asc_update_bits(0, ASCWHBSTATE_CLRPE, 193 port->membase + LTQ_ASC_WHBSTATE); 194 } else if (rsr & ASCSTATE_FE) { 195 port->icount.frame++; 196 asc_update_bits(0, ASCWHBSTATE_CLRFE, 197 port->membase + LTQ_ASC_WHBSTATE); 198 } 199 if (rsr & ASCSTATE_ROE) { 200 port->icount.overrun++; 201 asc_update_bits(0, ASCWHBSTATE_CLRROE, 202 port->membase + LTQ_ASC_WHBSTATE); 203 } 204 205 rsr &= port->read_status_mask; 206 207 if (rsr & ASCSTATE_PE) 208 flag = TTY_PARITY; 209 else if (rsr & ASCSTATE_FE) 210 flag = TTY_FRAME; 211 } 212 213 if ((rsr & port->ignore_status_mask) == 0) 214 tty_insert_flip_char(tport, ch, flag); 215 216 if (rsr & ASCSTATE_ROE) 217 /* 218 * Overrun is special, since it's reported 219 * immediately, and doesn't affect the current 220 * character 221 */ 222 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 223 } 224 225 if (ch != 0) 226 tty_flip_buffer_push(tport); 227 228 return 0; 229 } 230 231 static irqreturn_t 232 lqasc_tx_int(int irq, void *_port) 233 { 234 unsigned long flags; 235 struct uart_port *port = (struct uart_port *)_port; 236 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 237 238 spin_lock_irqsave(<q_port->lock, flags); 239 __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); 240 spin_unlock_irqrestore(<q_port->lock, flags); 241 lqasc_start_tx(port); 242 return IRQ_HANDLED; 243 } 244 245 static irqreturn_t 246 lqasc_err_int(int irq, void *_port) 247 { 248 unsigned long flags; 249 struct uart_port *port = (struct uart_port *)_port; 250 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 251 252 spin_lock_irqsave(<q_port->lock, flags); 253 /* clear any pending interrupts */ 254 asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | 255 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); 256 spin_unlock_irqrestore(<q_port->lock, flags); 257 return IRQ_HANDLED; 258 } 259 260 static irqreturn_t 261 lqasc_rx_int(int irq, void *_port) 262 { 263 unsigned long flags; 264 struct uart_port *port = (struct uart_port *)_port; 265 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 266 267 spin_lock_irqsave(<q_port->lock, flags); 268 __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); 269 lqasc_rx_chars(port); 270 spin_unlock_irqrestore(<q_port->lock, flags); 271 return IRQ_HANDLED; 272 } 273 274 static irqreturn_t lqasc_irq(int irq, void *p) 275 { 276 unsigned long flags; 277 u32 stat; 278 struct uart_port *port = p; 279 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 280 281 spin_lock_irqsave(<q_port->lock, flags); 282 stat = readl(port->membase + LTQ_ASC_IRNCR); 283 spin_unlock_irqrestore(<q_port->lock, flags); 284 if (!(stat & ASC_IRNCR_MASK)) 285 return IRQ_NONE; 286 287 if (stat & ASC_IRNCR_TIR) 288 lqasc_tx_int(irq, p); 289 290 if (stat & ASC_IRNCR_RIR) 291 lqasc_rx_int(irq, p); 292 293 if (stat & ASC_IRNCR_EIR) 294 lqasc_err_int(irq, p); 295 296 return IRQ_HANDLED; 297 } 298 299 static unsigned int 300 lqasc_tx_empty(struct uart_port *port) 301 { 302 int status; 303 status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 304 ASCFSTAT_TXFFLMASK; 305 return status ? 0 : TIOCSER_TEMT; 306 } 307 308 static unsigned int 309 lqasc_get_mctrl(struct uart_port *port) 310 { 311 return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; 312 } 313 314 static void 315 lqasc_set_mctrl(struct uart_port *port, u_int mctrl) 316 { 317 } 318 319 static void 320 lqasc_break_ctl(struct uart_port *port, int break_state) 321 { 322 } 323 324 static int 325 lqasc_startup(struct uart_port *port) 326 { 327 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 328 int retval; 329 unsigned long flags; 330 331 if (!IS_ERR(ltq_port->clk)) 332 clk_prepare_enable(ltq_port->clk); 333 port->uartclk = clk_get_rate(ltq_port->freqclk); 334 335 spin_lock_irqsave(<q_port->lock, flags); 336 asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), 337 port->membase + LTQ_ASC_CLC); 338 339 __raw_writel(0, port->membase + LTQ_ASC_PISEL); 340 __raw_writel( 341 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | 342 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, 343 port->membase + LTQ_ASC_TXFCON); 344 __raw_writel( 345 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) 346 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, 347 port->membase + LTQ_ASC_RXFCON); 348 /* make sure other settings are written to hardware before 349 * setting enable bits 350 */ 351 wmb(); 352 asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | 353 ASCCON_ROEN, port->membase + LTQ_ASC_CON); 354 355 spin_unlock_irqrestore(<q_port->lock, flags); 356 357 retval = ltq_port->soc->request_irq(port); 358 if (retval) 359 return retval; 360 361 __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, 362 port->membase + LTQ_ASC_IRNREN); 363 return retval; 364 } 365 366 static void 367 lqasc_shutdown(struct uart_port *port) 368 { 369 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 370 unsigned long flags; 371 372 ltq_port->soc->free_irq(port); 373 374 spin_lock_irqsave(<q_port->lock, flags); 375 __raw_writel(0, port->membase + LTQ_ASC_CON); 376 asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, 377 port->membase + LTQ_ASC_RXFCON); 378 asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, 379 port->membase + LTQ_ASC_TXFCON); 380 spin_unlock_irqrestore(<q_port->lock, flags); 381 if (!IS_ERR(ltq_port->clk)) 382 clk_disable_unprepare(ltq_port->clk); 383 } 384 385 static void 386 lqasc_set_termios(struct uart_port *port, struct ktermios *new, 387 const struct ktermios *old) 388 { 389 unsigned int cflag; 390 unsigned int iflag; 391 unsigned int divisor; 392 unsigned int baud; 393 unsigned int con = 0; 394 unsigned long flags; 395 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 396 397 cflag = new->c_cflag; 398 iflag = new->c_iflag; 399 400 switch (cflag & CSIZE) { 401 case CS7: 402 con = ASCCON_M_7ASYNC; 403 break; 404 405 case CS5: 406 case CS6: 407 default: 408 new->c_cflag &= ~ CSIZE; 409 new->c_cflag |= CS8; 410 con = ASCCON_M_8ASYNC; 411 break; 412 } 413 414 cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 415 416 if (cflag & CSTOPB) 417 con |= ASCCON_STP; 418 419 if (cflag & PARENB) { 420 if (!(cflag & PARODD)) 421 con &= ~ASCCON_ODD; 422 else 423 con |= ASCCON_ODD; 424 } 425 426 port->read_status_mask = ASCSTATE_ROE; 427 if (iflag & INPCK) 428 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 429 430 port->ignore_status_mask = 0; 431 if (iflag & IGNPAR) 432 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; 433 434 if (iflag & IGNBRK) { 435 /* 436 * If we're ignoring parity and break indicators, 437 * ignore overruns too (for real raw support). 438 */ 439 if (iflag & IGNPAR) 440 port->ignore_status_mask |= ASCSTATE_ROE; 441 } 442 443 if ((cflag & CREAD) == 0) 444 port->ignore_status_mask |= UART_DUMMY_UER_RX; 445 446 /* set error signals - framing, parity and overrun, enable receiver */ 447 con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; 448 449 spin_lock_irqsave(<q_port->lock, flags); 450 451 /* set up CON */ 452 asc_update_bits(0, con, port->membase + LTQ_ASC_CON); 453 454 /* Set baud rate - take a divider of 2 into account */ 455 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 456 divisor = uart_get_divisor(port, baud); 457 divisor = divisor / 2 - 1; 458 459 /* disable the baudrate generator */ 460 asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON); 461 462 /* make sure the fractional divider is off */ 463 asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); 464 465 /* set up to use divisor of 2 */ 466 asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); 467 468 /* now we can write the new baudrate into the register */ 469 __raw_writel(divisor, port->membase + LTQ_ASC_BG); 470 471 /* turn the baudrate generator back on */ 472 asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); 473 474 /* enable rx */ 475 __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); 476 477 spin_unlock_irqrestore(<q_port->lock, flags); 478 479 /* Don't rewrite B0 */ 480 if (tty_termios_baud_rate(new)) 481 tty_termios_encode_baud_rate(new, baud, baud); 482 483 uart_update_timeout(port, cflag, baud); 484 } 485 486 static const char* 487 lqasc_type(struct uart_port *port) 488 { 489 if (port->type == PORT_LTQ_ASC) 490 return DRVNAME; 491 else 492 return NULL; 493 } 494 495 static void 496 lqasc_release_port(struct uart_port *port) 497 { 498 struct platform_device *pdev = to_platform_device(port->dev); 499 500 if (port->flags & UPF_IOREMAP) { 501 devm_iounmap(&pdev->dev, port->membase); 502 port->membase = NULL; 503 } 504 } 505 506 static int 507 lqasc_request_port(struct uart_port *port) 508 { 509 struct platform_device *pdev = to_platform_device(port->dev); 510 struct resource *res; 511 int size; 512 513 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 514 if (!res) { 515 dev_err(&pdev->dev, "cannot obtain I/O memory region"); 516 return -ENODEV; 517 } 518 size = resource_size(res); 519 520 res = devm_request_mem_region(&pdev->dev, res->start, 521 size, dev_name(&pdev->dev)); 522 if (!res) { 523 dev_err(&pdev->dev, "cannot request I/O memory region"); 524 return -EBUSY; 525 } 526 527 if (port->flags & UPF_IOREMAP) { 528 port->membase = devm_ioremap(&pdev->dev, 529 port->mapbase, size); 530 if (port->membase == NULL) 531 return -ENOMEM; 532 } 533 return 0; 534 } 535 536 static void 537 lqasc_config_port(struct uart_port *port, int flags) 538 { 539 if (flags & UART_CONFIG_TYPE) { 540 port->type = PORT_LTQ_ASC; 541 lqasc_request_port(port); 542 } 543 } 544 545 static int 546 lqasc_verify_port(struct uart_port *port, 547 struct serial_struct *ser) 548 { 549 int ret = 0; 550 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC) 551 ret = -EINVAL; 552 if (ser->irq < 0 || ser->irq >= NR_IRQS) 553 ret = -EINVAL; 554 if (ser->baud_base < 9600) 555 ret = -EINVAL; 556 return ret; 557 } 558 559 static const struct uart_ops lqasc_pops = { 560 .tx_empty = lqasc_tx_empty, 561 .set_mctrl = lqasc_set_mctrl, 562 .get_mctrl = lqasc_get_mctrl, 563 .stop_tx = lqasc_stop_tx, 564 .start_tx = lqasc_start_tx, 565 .stop_rx = lqasc_stop_rx, 566 .break_ctl = lqasc_break_ctl, 567 .startup = lqasc_startup, 568 .shutdown = lqasc_shutdown, 569 .set_termios = lqasc_set_termios, 570 .type = lqasc_type, 571 .release_port = lqasc_release_port, 572 .request_port = lqasc_request_port, 573 .config_port = lqasc_config_port, 574 .verify_port = lqasc_verify_port, 575 }; 576 577 #ifdef CONFIG_SERIAL_LANTIQ_CONSOLE 578 static void 579 lqasc_console_putchar(struct uart_port *port, unsigned char ch) 580 { 581 if (!port->membase) 582 return; 583 584 while (!lqasc_tx_ready(port)) 585 ; 586 587 writeb(ch, port->membase + LTQ_ASC_TBUF); 588 } 589 590 static void lqasc_serial_port_write(struct uart_port *port, const char *s, 591 u_int count) 592 { 593 uart_console_write(port, s, count, lqasc_console_putchar); 594 } 595 596 static void 597 lqasc_console_write(struct console *co, const char *s, u_int count) 598 { 599 struct ltq_uart_port *ltq_port; 600 unsigned long flags; 601 602 if (co->index >= MAXPORTS) 603 return; 604 605 ltq_port = lqasc_port[co->index]; 606 if (!ltq_port) 607 return; 608 609 spin_lock_irqsave(<q_port->lock, flags); 610 lqasc_serial_port_write(<q_port->port, s, count); 611 spin_unlock_irqrestore(<q_port->lock, flags); 612 } 613 614 static int __init 615 lqasc_console_setup(struct console *co, char *options) 616 { 617 struct ltq_uart_port *ltq_port; 618 struct uart_port *port; 619 int baud = 115200; 620 int bits = 8; 621 int parity = 'n'; 622 int flow = 'n'; 623 624 if (co->index >= MAXPORTS) 625 return -ENODEV; 626 627 ltq_port = lqasc_port[co->index]; 628 if (!ltq_port) 629 return -ENODEV; 630 631 port = <q_port->port; 632 633 if (!IS_ERR(ltq_port->clk)) 634 clk_prepare_enable(ltq_port->clk); 635 636 port->uartclk = clk_get_rate(ltq_port->freqclk); 637 638 if (options) 639 uart_parse_options(options, &baud, &parity, &bits, &flow); 640 return uart_set_options(port, co, baud, parity, bits, flow); 641 } 642 643 static struct console lqasc_console = { 644 .name = "ttyLTQ", 645 .write = lqasc_console_write, 646 .device = uart_console_device, 647 .setup = lqasc_console_setup, 648 .flags = CON_PRINTBUFFER, 649 .index = -1, 650 .data = &lqasc_reg, 651 }; 652 653 static int __init 654 lqasc_console_init(void) 655 { 656 register_console(&lqasc_console); 657 return 0; 658 } 659 console_initcall(lqasc_console_init); 660 661 static void lqasc_serial_early_console_write(struct console *co, 662 const char *s, 663 u_int count) 664 { 665 struct earlycon_device *dev = co->data; 666 667 lqasc_serial_port_write(&dev->port, s, count); 668 } 669 670 static int __init 671 lqasc_serial_early_console_setup(struct earlycon_device *device, 672 const char *opt) 673 { 674 if (!device->port.membase) 675 return -ENODEV; 676 677 device->con->write = lqasc_serial_early_console_write; 678 return 0; 679 } 680 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup); 681 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup); 682 683 #define LANTIQ_SERIAL_CONSOLE (&lqasc_console) 684 685 #else 686 687 #define LANTIQ_SERIAL_CONSOLE NULL 688 689 #endif /* CONFIG_SERIAL_LANTIQ_CONSOLE */ 690 691 static struct uart_driver lqasc_reg = { 692 .owner = THIS_MODULE, 693 .driver_name = DRVNAME, 694 .dev_name = "ttyLTQ", 695 .major = 0, 696 .minor = 0, 697 .nr = MAXPORTS, 698 .cons = LANTIQ_SERIAL_CONSOLE, 699 }; 700 701 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port) 702 { 703 struct uart_port *port = <q_port->port; 704 struct platform_device *pdev = to_platform_device(dev); 705 int irq; 706 707 irq = platform_get_irq(pdev, 0); 708 if (irq < 0) 709 return irq; 710 ltq_port->tx_irq = irq; 711 irq = platform_get_irq(pdev, 1); 712 if (irq < 0) 713 return irq; 714 ltq_port->rx_irq = irq; 715 irq = platform_get_irq(pdev, 2); 716 if (irq < 0) 717 return irq; 718 ltq_port->err_irq = irq; 719 720 port->irq = ltq_port->tx_irq; 721 722 return 0; 723 } 724 725 static int request_irq_lantiq(struct uart_port *port) 726 { 727 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 728 int retval; 729 730 retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, 731 0, "asc_tx", port); 732 if (retval) { 733 dev_err(port->dev, "failed to request asc_tx\n"); 734 return retval; 735 } 736 737 retval = request_irq(ltq_port->rx_irq, lqasc_rx_int, 738 0, "asc_rx", port); 739 if (retval) { 740 dev_err(port->dev, "failed to request asc_rx\n"); 741 goto err1; 742 } 743 744 retval = request_irq(ltq_port->err_irq, lqasc_err_int, 745 0, "asc_err", port); 746 if (retval) { 747 dev_err(port->dev, "failed to request asc_err\n"); 748 goto err2; 749 } 750 return 0; 751 752 err2: 753 free_irq(ltq_port->rx_irq, port); 754 err1: 755 free_irq(ltq_port->tx_irq, port); 756 return retval; 757 } 758 759 static void free_irq_lantiq(struct uart_port *port) 760 { 761 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 762 763 free_irq(ltq_port->tx_irq, port); 764 free_irq(ltq_port->rx_irq, port); 765 free_irq(ltq_port->err_irq, port); 766 } 767 768 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port) 769 { 770 struct uart_port *port = <q_port->port; 771 int ret; 772 773 ret = platform_get_irq(to_platform_device(dev), 0); 774 if (ret < 0) { 775 dev_err(dev, "failed to fetch IRQ for serial port\n"); 776 return ret; 777 } 778 ltq_port->common_irq = ret; 779 port->irq = ret; 780 781 return 0; 782 } 783 784 static int request_irq_intel(struct uart_port *port) 785 { 786 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 787 int retval; 788 789 retval = request_irq(ltq_port->common_irq, lqasc_irq, 0, 790 "asc_irq", port); 791 if (retval) 792 dev_err(port->dev, "failed to request asc_irq\n"); 793 794 return retval; 795 } 796 797 static void free_irq_intel(struct uart_port *port) 798 { 799 struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); 800 801 free_irq(ltq_port->common_irq, port); 802 } 803 804 static int lqasc_probe(struct platform_device *pdev) 805 { 806 struct device_node *node = pdev->dev.of_node; 807 struct ltq_uart_port *ltq_port; 808 struct uart_port *port; 809 struct resource *mmres; 810 int line; 811 int ret; 812 813 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 814 if (!mmres) { 815 dev_err(&pdev->dev, 816 "failed to get memory for serial port\n"); 817 return -ENODEV; 818 } 819 820 ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port), 821 GFP_KERNEL); 822 if (!ltq_port) 823 return -ENOMEM; 824 825 port = <q_port->port; 826 827 ltq_port->soc = of_device_get_match_data(&pdev->dev); 828 ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port); 829 if (ret) 830 return ret; 831 832 /* get serial id */ 833 line = of_alias_get_id(node, "serial"); 834 if (line < 0) { 835 if (IS_ENABLED(CONFIG_LANTIQ)) { 836 if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC)) 837 line = 0; 838 else 839 line = 1; 840 } else { 841 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", 842 line); 843 return line; 844 } 845 } 846 847 if (lqasc_port[line]) { 848 dev_err(&pdev->dev, "port %d already allocated\n", line); 849 return -EBUSY; 850 } 851 852 port->iotype = SERIAL_IO_MEM; 853 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 854 port->ops = &lqasc_pops; 855 port->fifosize = 16; 856 port->type = PORT_LTQ_ASC; 857 port->line = line; 858 port->dev = &pdev->dev; 859 /* unused, just to be backward-compatible */ 860 port->mapbase = mmres->start; 861 862 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 863 ltq_port->freqclk = clk_get_fpi(); 864 else 865 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq"); 866 867 868 if (IS_ERR(ltq_port->freqclk)) { 869 pr_err("failed to get fpi clk\n"); 870 return -ENOENT; 871 } 872 873 /* not all asc ports have clock gates, lets ignore the return code */ 874 if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK)) 875 ltq_port->clk = clk_get(&pdev->dev, NULL); 876 else 877 ltq_port->clk = devm_clk_get(&pdev->dev, "asc"); 878 879 spin_lock_init(<q_port->lock); 880 lqasc_port[line] = ltq_port; 881 platform_set_drvdata(pdev, ltq_port); 882 883 ret = uart_add_one_port(&lqasc_reg, port); 884 885 return ret; 886 } 887 888 static int lqasc_remove(struct platform_device *pdev) 889 { 890 struct uart_port *port = platform_get_drvdata(pdev); 891 892 return uart_remove_one_port(&lqasc_reg, port); 893 } 894 895 static const struct ltq_soc_data soc_data_lantiq = { 896 .fetch_irq = fetch_irq_lantiq, 897 .request_irq = request_irq_lantiq, 898 .free_irq = free_irq_lantiq, 899 }; 900 901 static const struct ltq_soc_data soc_data_intel = { 902 .fetch_irq = fetch_irq_intel, 903 .request_irq = request_irq_intel, 904 .free_irq = free_irq_intel, 905 }; 906 907 static const struct of_device_id ltq_asc_match[] = { 908 { .compatible = "lantiq,asc", .data = &soc_data_lantiq }, 909 { .compatible = "intel,lgm-asc", .data = &soc_data_intel }, 910 {}, 911 }; 912 MODULE_DEVICE_TABLE(of, ltq_asc_match); 913 914 static struct platform_driver lqasc_driver = { 915 .probe = lqasc_probe, 916 .remove = lqasc_remove, 917 .driver = { 918 .name = DRVNAME, 919 .of_match_table = ltq_asc_match, 920 }, 921 }; 922 923 static int __init 924 init_lqasc(void) 925 { 926 int ret; 927 928 ret = uart_register_driver(&lqasc_reg); 929 if (ret != 0) 930 return ret; 931 932 ret = platform_driver_register(&lqasc_driver); 933 if (ret != 0) 934 uart_unregister_driver(&lqasc_reg); 935 936 return ret; 937 } 938 939 static void __exit exit_lqasc(void) 940 { 941 platform_driver_unregister(&lqasc_driver); 942 uart_unregister_driver(&lqasc_reg); 943 } 944 945 module_init(init_lqasc); 946 module_exit(exit_lqasc); 947 948 MODULE_DESCRIPTION("Serial driver for Lantiq & Intel gateway SoCs"); 949 MODULE_LICENSE("GPL v2"); 950