1 // SPDX-License-Identifier: GPL-2.0+ 2 /************************************************************************ 3 * Copyright 2003 Digi International (www.digi.com) 4 * 5 * Copyright (C) 2004 IBM Corporation. All rights reserved. 6 * 7 * Contact Information: 8 * Scott H Kilau <Scott_Kilau@digi.com> 9 * Wendy Xiong <wendyx@us.ibm.com> 10 * 11 ***********************************************************************/ 12 #include <linux/delay.h> /* For udelay */ 13 #include <linux/serial_reg.h> /* For the various UART offsets */ 14 #include <linux/tty.h> 15 #include <linux/pci.h> 16 #include <asm/io.h> 17 18 #include "jsm.h" /* Driver main header file */ 19 20 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 21 22 /* 23 * This function allows calls to ensure that all outstanding 24 * PCI writes have been completed, by doing a PCI read against 25 * a non-destructive, read-only location on the Neo card. 26 * 27 * In this case, we are reading the DVID (Read-only Device Identification) 28 * value of the Neo card. 29 */ 30 static inline void neo_pci_posting_flush(struct jsm_board *bd) 31 { 32 readb(bd->re_map_membase + 0x8D); 33 } 34 35 static void neo_set_cts_flow_control(struct jsm_channel *ch) 36 { 37 u8 ier, efr; 38 ier = readb(&ch->ch_neo_uart->ier); 39 efr = readb(&ch->ch_neo_uart->efr); 40 41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); 42 43 /* Turn on auto CTS flow control */ 44 ier |= (UART_17158_IER_CTSDSR); 45 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 46 47 /* Turn off auto Xon flow control */ 48 efr &= ~(UART_17158_EFR_IXON); 49 50 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 51 writeb(0, &ch->ch_neo_uart->efr); 52 53 /* Turn on UART enhanced bits */ 54 writeb(efr, &ch->ch_neo_uart->efr); 55 56 /* Turn on table D, with 8 char hi/low watermarks */ 57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 58 59 /* Feed the UART our trigger levels */ 60 writeb(8, &ch->ch_neo_uart->tfifo); 61 ch->ch_t_tlevel = 8; 62 63 writeb(ier, &ch->ch_neo_uart->ier); 64 } 65 66 static void neo_set_rts_flow_control(struct jsm_channel *ch) 67 { 68 u8 ier, efr; 69 ier = readb(&ch->ch_neo_uart->ier); 70 efr = readb(&ch->ch_neo_uart->efr); 71 72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); 73 74 /* Turn on auto RTS flow control */ 75 ier |= (UART_17158_IER_RTSDTR); 76 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 77 78 /* Turn off auto Xoff flow control */ 79 ier &= ~(UART_17158_IER_XOFF); 80 efr &= ~(UART_17158_EFR_IXOFF); 81 82 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 83 writeb(0, &ch->ch_neo_uart->efr); 84 85 /* Turn on UART enhanced bits */ 86 writeb(efr, &ch->ch_neo_uart->efr); 87 88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 89 ch->ch_r_watermark = 4; 90 91 writeb(56, &ch->ch_neo_uart->rfifo); 92 ch->ch_r_tlevel = 56; 93 94 writeb(ier, &ch->ch_neo_uart->ier); 95 96 /* 97 * From the Neo UART spec sheet: 98 * The auto RTS/DTR function must be started by asserting 99 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 100 * it is enabled. 101 */ 102 ch->ch_mostat |= (UART_MCR_RTS); 103 } 104 105 106 static void neo_set_ixon_flow_control(struct jsm_channel *ch) 107 { 108 u8 ier, efr; 109 ier = readb(&ch->ch_neo_uart->ier); 110 efr = readb(&ch->ch_neo_uart->efr); 111 112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); 113 114 /* Turn off auto CTS flow control */ 115 ier &= ~(UART_17158_IER_CTSDSR); 116 efr &= ~(UART_17158_EFR_CTSDSR); 117 118 /* Turn on auto Xon flow control */ 119 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 120 121 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 122 writeb(0, &ch->ch_neo_uart->efr); 123 124 /* Turn on UART enhanced bits */ 125 writeb(efr, &ch->ch_neo_uart->efr); 126 127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 128 ch->ch_r_watermark = 4; 129 130 writeb(32, &ch->ch_neo_uart->rfifo); 131 ch->ch_r_tlevel = 32; 132 133 /* Tell UART what start/stop chars it should be looking for */ 134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 135 writeb(0, &ch->ch_neo_uart->xonchar2); 136 137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 138 writeb(0, &ch->ch_neo_uart->xoffchar2); 139 140 writeb(ier, &ch->ch_neo_uart->ier); 141 } 142 143 static void neo_set_ixoff_flow_control(struct jsm_channel *ch) 144 { 145 u8 ier, efr; 146 ier = readb(&ch->ch_neo_uart->ier); 147 efr = readb(&ch->ch_neo_uart->efr); 148 149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); 150 151 /* Turn off auto RTS flow control */ 152 ier &= ~(UART_17158_IER_RTSDTR); 153 efr &= ~(UART_17158_EFR_RTSDTR); 154 155 /* Turn on auto Xoff flow control */ 156 ier |= (UART_17158_IER_XOFF); 157 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 158 159 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 160 writeb(0, &ch->ch_neo_uart->efr); 161 162 /* Turn on UART enhanced bits */ 163 writeb(efr, &ch->ch_neo_uart->efr); 164 165 /* Turn on table D, with 8 char hi/low watermarks */ 166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 167 168 writeb(8, &ch->ch_neo_uart->tfifo); 169 ch->ch_t_tlevel = 8; 170 171 /* Tell UART what start/stop chars it should be looking for */ 172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 173 writeb(0, &ch->ch_neo_uart->xonchar2); 174 175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 176 writeb(0, &ch->ch_neo_uart->xoffchar2); 177 178 writeb(ier, &ch->ch_neo_uart->ier); 179 } 180 181 static void neo_set_no_input_flow_control(struct jsm_channel *ch) 182 { 183 u8 ier, efr; 184 ier = readb(&ch->ch_neo_uart->ier); 185 efr = readb(&ch->ch_neo_uart->efr); 186 187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); 188 189 /* Turn off auto RTS flow control */ 190 ier &= ~(UART_17158_IER_RTSDTR); 191 efr &= ~(UART_17158_EFR_RTSDTR); 192 193 /* Turn off auto Xoff flow control */ 194 ier &= ~(UART_17158_IER_XOFF); 195 if (ch->ch_c_iflag & IXON) 196 efr &= ~(UART_17158_EFR_IXOFF); 197 else 198 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 199 200 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 201 writeb(0, &ch->ch_neo_uart->efr); 202 203 /* Turn on UART enhanced bits */ 204 writeb(efr, &ch->ch_neo_uart->efr); 205 206 /* Turn on table D, with 8 char hi/low watermarks */ 207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 208 209 ch->ch_r_watermark = 0; 210 211 writeb(16, &ch->ch_neo_uart->tfifo); 212 ch->ch_t_tlevel = 16; 213 214 writeb(16, &ch->ch_neo_uart->rfifo); 215 ch->ch_r_tlevel = 16; 216 217 writeb(ier, &ch->ch_neo_uart->ier); 218 } 219 220 static void neo_set_no_output_flow_control(struct jsm_channel *ch) 221 { 222 u8 ier, efr; 223 ier = readb(&ch->ch_neo_uart->ier); 224 efr = readb(&ch->ch_neo_uart->efr); 225 226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); 227 228 /* Turn off auto CTS flow control */ 229 ier &= ~(UART_17158_IER_CTSDSR); 230 efr &= ~(UART_17158_EFR_CTSDSR); 231 232 /* Turn off auto Xon flow control */ 233 if (ch->ch_c_iflag & IXOFF) 234 efr &= ~(UART_17158_EFR_IXON); 235 else 236 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 237 238 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 239 writeb(0, &ch->ch_neo_uart->efr); 240 241 /* Turn on UART enhanced bits */ 242 writeb(efr, &ch->ch_neo_uart->efr); 243 244 /* Turn on table D, with 8 char hi/low watermarks */ 245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 246 247 ch->ch_r_watermark = 0; 248 249 writeb(16, &ch->ch_neo_uart->tfifo); 250 ch->ch_t_tlevel = 16; 251 252 writeb(16, &ch->ch_neo_uart->rfifo); 253 ch->ch_r_tlevel = 16; 254 255 writeb(ier, &ch->ch_neo_uart->ier); 256 } 257 258 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch) 259 { 260 261 /* if hardware flow control is set, then skip this whole thing */ 262 if (ch->ch_c_cflag & CRTSCTS) 263 return; 264 265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n"); 266 267 /* Tell UART what start/stop chars it should be looking for */ 268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 269 writeb(0, &ch->ch_neo_uart->xonchar2); 270 271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 272 writeb(0, &ch->ch_neo_uart->xoffchar2); 273 } 274 275 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch) 276 { 277 int qleft = 0; 278 u8 linestatus = 0; 279 u8 error_mask = 0; 280 int n = 0; 281 int total = 0; 282 u16 head; 283 u16 tail; 284 285 /* cache head and tail of queue */ 286 head = ch->ch_r_head & RQUEUEMASK; 287 tail = ch->ch_r_tail & RQUEUEMASK; 288 289 /* Get our cached LSR */ 290 linestatus = ch->ch_cached_lsr; 291 ch->ch_cached_lsr = 0; 292 293 /* Store how much space we have left in the queue */ 294 if ((qleft = tail - head - 1) < 0) 295 qleft += RQUEUEMASK + 1; 296 297 /* 298 * If the UART is not in FIFO mode, force the FIFO copy to 299 * NOT be run, by setting total to 0. 300 * 301 * On the other hand, if the UART IS in FIFO mode, then ask 302 * the UART to give us an approximation of data it has RX'ed. 303 */ 304 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 305 total = 0; 306 else { 307 total = readb(&ch->ch_neo_uart->rfifo); 308 309 /* 310 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 311 * 312 * This resolves a problem/bug with the Exar chip that sometimes 313 * returns a bogus value in the rfifo register. 314 * The count can be any where from 0-3 bytes "off". 315 * Bizarre, but true. 316 */ 317 total -= 3; 318 } 319 320 /* 321 * Finally, bound the copy to make sure we don't overflow 322 * our own queue... 323 * The byte by byte copy loop below this loop this will 324 * deal with the queue overflow possibility. 325 */ 326 total = min(total, qleft); 327 328 while (total > 0) { 329 /* 330 * Grab the linestatus register, we need to check 331 * to see if there are any errors in the FIFO. 332 */ 333 linestatus = readb(&ch->ch_neo_uart->lsr); 334 335 /* 336 * Break out if there is a FIFO error somewhere. 337 * This will allow us to go byte by byte down below, 338 * finding the exact location of the error. 339 */ 340 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 341 break; 342 343 /* Make sure we don't go over the end of our queue */ 344 n = min(((u32) total), (RQUEUESIZE - (u32) head)); 345 346 /* 347 * Cut down n even further if needed, this is to fix 348 * a problem with memcpy_fromio() with the Neo on the 349 * IBM pSeries platform. 350 * 15 bytes max appears to be the magic number. 351 */ 352 n = min((u32) n, (u32) 12); 353 354 /* 355 * Since we are grabbing the linestatus register, which 356 * will reset some bits after our read, we need to ensure 357 * we don't miss our TX FIFO emptys. 358 */ 359 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 360 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 361 362 linestatus = 0; 363 364 /* Copy data from uart to the queue */ 365 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 366 /* 367 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed 368 * that all the data currently in the FIFO is free of 369 * breaks and parity/frame/orun errors. 370 */ 371 memset(ch->ch_equeue + head, 0, n); 372 373 /* Add to and flip head if needed */ 374 head = (head + n) & RQUEUEMASK; 375 total -= n; 376 qleft -= n; 377 ch->ch_rxcount += n; 378 } 379 380 /* 381 * Create a mask to determine whether we should 382 * insert the character (if any) into our queue. 383 */ 384 if (ch->ch_c_iflag & IGNBRK) 385 error_mask |= UART_LSR_BI; 386 387 /* 388 * Now cleanup any leftover bytes still in the UART. 389 * Also deal with any possible queue overflow here as well. 390 */ 391 while (1) { 392 393 /* 394 * Its possible we have a linestatus from the loop above 395 * this, so we "OR" on any extra bits. 396 */ 397 linestatus |= readb(&ch->ch_neo_uart->lsr); 398 399 /* 400 * If the chip tells us there is no more data pending to 401 * be read, we can then leave. 402 * But before we do, cache the linestatus, just in case. 403 */ 404 if (!(linestatus & UART_LSR_DR)) { 405 ch->ch_cached_lsr = linestatus; 406 break; 407 } 408 409 /* No need to store this bit */ 410 linestatus &= ~UART_LSR_DR; 411 412 /* 413 * Since we are grabbing the linestatus register, which 414 * will reset some bits after our read, we need to ensure 415 * we don't miss our TX FIFO emptys. 416 */ 417 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 418 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 419 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 420 } 421 422 /* 423 * Discard character if we are ignoring the error mask. 424 */ 425 if (linestatus & error_mask) { 426 u8 discard; 427 linestatus = 0; 428 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 429 continue; 430 } 431 432 /* 433 * If our queue is full, we have no choice but to drop some data. 434 * The assumption is that HWFLOW or SWFLOW should have stopped 435 * things way way before we got to this point. 436 * 437 * I decided that I wanted to ditch the oldest data first, 438 * I hope thats okay with everyone? Yes? Good. 439 */ 440 while (qleft < 1) { 441 jsm_dbg(READ, &ch->ch_bd->pci_dev, 442 "Queue full, dropping DATA:%x LSR:%x\n", 443 ch->ch_rqueue[tail], ch->ch_equeue[tail]); 444 445 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; 446 ch->ch_err_overrun++; 447 qleft++; 448 } 449 450 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 451 ch->ch_equeue[head] = (u8) linestatus; 452 453 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n", 454 ch->ch_rqueue[head], ch->ch_equeue[head]); 455 456 /* Ditch any remaining linestatus value. */ 457 linestatus = 0; 458 459 /* Add to and flip head if needed */ 460 head = (head + 1) & RQUEUEMASK; 461 462 qleft--; 463 ch->ch_rxcount++; 464 } 465 466 /* 467 * Write new final heads to channel structure. 468 */ 469 ch->ch_r_head = head & RQUEUEMASK; 470 ch->ch_e_head = head & EQUEUEMASK; 471 jsm_input(ch); 472 } 473 474 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch) 475 { 476 u16 head; 477 u16 tail; 478 int n; 479 int s; 480 int qlen; 481 u32 len_written = 0; 482 struct circ_buf *circ; 483 484 if (!ch) 485 return; 486 487 circ = &ch->uart_port.state->xmit; 488 489 /* No data to write to the UART */ 490 if (uart_circ_empty(circ)) 491 return; 492 493 /* If port is "stopped", don't send any data to the UART */ 494 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) 495 return; 496 /* 497 * If FIFOs are disabled. Send data directly to txrx register 498 */ 499 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 500 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); 501 502 ch->ch_cached_lsr |= lsrbits; 503 if (ch->ch_cached_lsr & UART_LSR_THRE) { 504 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 505 506 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx); 507 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, 508 "Tx data: %x\n", circ->buf[circ->tail]); 509 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1); 510 ch->ch_txcount++; 511 } 512 return; 513 } 514 515 /* 516 * We have to do it this way, because of the EXAR TXFIFO count bug. 517 */ 518 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 519 return; 520 521 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 522 523 /* cache head and tail of queue */ 524 head = circ->head & (UART_XMIT_SIZE - 1); 525 tail = circ->tail & (UART_XMIT_SIZE - 1); 526 qlen = uart_circ_chars_pending(circ); 527 528 /* Find minimum of the FIFO space, versus queue length */ 529 n = min(n, qlen); 530 531 while (n > 0) { 532 533 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; 534 s = min(s, n); 535 536 if (s <= 0) 537 break; 538 539 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s); 540 /* Add and flip queue if needed */ 541 tail = (tail + s) & (UART_XMIT_SIZE - 1); 542 n -= s; 543 ch->ch_txcount += s; 544 len_written += s; 545 } 546 547 /* Update the final tail */ 548 circ->tail = tail & (UART_XMIT_SIZE - 1); 549 550 if (len_written >= ch->ch_t_tlevel) 551 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 552 553 if (uart_circ_empty(circ)) 554 uart_write_wakeup(&ch->uart_port); 555 } 556 557 static void neo_parse_modem(struct jsm_channel *ch, u8 signals) 558 { 559 u8 msignals = signals; 560 561 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 562 "neo_parse_modem: port: %d msignals: %x\n", 563 ch->ch_portnum, msignals); 564 565 /* Scrub off lower bits. They signify delta's, which I don't care about */ 566 /* Keep DDCD and DDSR though */ 567 msignals &= 0xf8; 568 569 if (msignals & UART_MSR_DDCD) 570 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); 571 if (msignals & UART_MSR_DDSR) 572 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); 573 if (msignals & UART_MSR_DCD) 574 ch->ch_mistat |= UART_MSR_DCD; 575 else 576 ch->ch_mistat &= ~UART_MSR_DCD; 577 578 if (msignals & UART_MSR_DSR) 579 ch->ch_mistat |= UART_MSR_DSR; 580 else 581 ch->ch_mistat &= ~UART_MSR_DSR; 582 583 if (msignals & UART_MSR_RI) 584 ch->ch_mistat |= UART_MSR_RI; 585 else 586 ch->ch_mistat &= ~UART_MSR_RI; 587 588 if (msignals & UART_MSR_CTS) 589 ch->ch_mistat |= UART_MSR_CTS; 590 else 591 ch->ch_mistat &= ~UART_MSR_CTS; 592 593 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 594 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", 595 ch->ch_portnum, 596 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), 597 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), 598 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), 599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), 600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), 601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); 602 } 603 604 /* Make the UART raise any of the output signals we want up */ 605 static void neo_assert_modem_signals(struct jsm_channel *ch) 606 { 607 if (!ch) 608 return; 609 610 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 611 612 /* flush write operation */ 613 neo_pci_posting_flush(ch->ch_bd); 614 } 615 616 /* 617 * Flush the WRITE FIFO on the Neo. 618 * 619 * NOTE: Channel lock MUST be held before calling this function! 620 */ 621 static void neo_flush_uart_write(struct jsm_channel *ch) 622 { 623 u8 tmp = 0; 624 int i = 0; 625 626 if (!ch) 627 return; 628 629 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 630 631 for (i = 0; i < 10; i++) { 632 633 /* Check to see if the UART feels it completely flushed the FIFO. */ 634 tmp = readb(&ch->ch_neo_uart->isr_fcr); 635 if (tmp & UART_FCR_CLEAR_XMIT) { 636 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 637 "Still flushing TX UART... i: %d\n", i); 638 udelay(10); 639 } 640 else 641 break; 642 } 643 644 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 645 } 646 647 648 /* 649 * Flush the READ FIFO on the Neo. 650 * 651 * NOTE: Channel lock MUST be held before calling this function! 652 */ 653 static void neo_flush_uart_read(struct jsm_channel *ch) 654 { 655 u8 tmp = 0; 656 int i = 0; 657 658 if (!ch) 659 return; 660 661 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 662 663 for (i = 0; i < 10; i++) { 664 665 /* Check to see if the UART feels it completely flushed the FIFO. */ 666 tmp = readb(&ch->ch_neo_uart->isr_fcr); 667 if (tmp & 2) { 668 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 669 "Still flushing RX UART... i: %d\n", i); 670 udelay(10); 671 } 672 else 673 break; 674 } 675 } 676 677 /* 678 * No locks are assumed to be held when calling this function. 679 */ 680 static void neo_clear_break(struct jsm_channel *ch) 681 { 682 unsigned long lock_flags; 683 684 spin_lock_irqsave(&ch->ch_lock, lock_flags); 685 686 /* Turn break off, and unset some variables */ 687 if (ch->ch_flags & CH_BREAK_SENDING) { 688 u8 temp = readb(&ch->ch_neo_uart->lcr); 689 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 690 691 ch->ch_flags &= ~(CH_BREAK_SENDING); 692 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 693 "clear break Finishing UART_LCR_SBC! finished: %lx\n", 694 jiffies); 695 696 /* flush write operation */ 697 neo_pci_posting_flush(ch->ch_bd); 698 } 699 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 700 } 701 702 /* 703 * Parse the ISR register. 704 */ 705 static void neo_parse_isr(struct jsm_board *brd, u32 port) 706 { 707 struct jsm_channel *ch; 708 u8 isr; 709 u8 cause; 710 unsigned long lock_flags; 711 712 if (!brd) 713 return; 714 715 if (port >= brd->maxports) 716 return; 717 718 ch = brd->channels[port]; 719 if (!ch) 720 return; 721 722 /* Here we try to figure out what caused the interrupt to happen */ 723 while (1) { 724 725 isr = readb(&ch->ch_neo_uart->isr_fcr); 726 727 /* Bail if no pending interrupt */ 728 if (isr & UART_IIR_NO_INT) 729 break; 730 731 /* 732 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 733 */ 734 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 735 736 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n", 737 __FILE__, __LINE__, isr); 738 739 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 740 /* Read data from uart -> queue */ 741 neo_copy_data_from_uart_to_queue(ch); 742 743 /* Call our tty layer to enforce queue flow control if needed. */ 744 spin_lock_irqsave(&ch->ch_lock, lock_flags); 745 jsm_check_queue_flow_control(ch); 746 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 747 } 748 749 if (isr & UART_IIR_THRI) { 750 /* Transfer data (if any) from Write Queue -> UART. */ 751 spin_lock_irqsave(&ch->ch_lock, lock_flags); 752 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 753 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 754 neo_copy_data_from_queue_to_uart(ch); 755 } 756 757 if (isr & UART_17158_IIR_XONXOFF) { 758 cause = readb(&ch->ch_neo_uart->xoffchar1); 759 760 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 761 "Port %d. Got ISR_XONXOFF: cause:%x\n", 762 port, cause); 763 764 /* 765 * Since the UART detected either an XON or 766 * XOFF match, we need to figure out which 767 * one it was, so we can suspend or resume data flow. 768 */ 769 spin_lock_irqsave(&ch->ch_lock, lock_flags); 770 if (cause == UART_17158_XON_DETECT) { 771 /* Is output stopped right now, if so, resume it */ 772 if (brd->channels[port]->ch_flags & CH_STOP) { 773 ch->ch_flags &= ~(CH_STOP); 774 } 775 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 776 "Port %d. XON detected in incoming data\n", 777 port); 778 } 779 else if (cause == UART_17158_XOFF_DETECT) { 780 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 781 ch->ch_flags |= CH_STOP; 782 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 783 "Setting CH_STOP\n"); 784 } 785 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 786 "Port: %d. XOFF detected in incoming data\n", 787 port); 788 } 789 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 790 } 791 792 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 793 /* 794 * If we get here, this means the hardware is doing auto flow control. 795 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 796 */ 797 cause = readb(&ch->ch_neo_uart->mcr); 798 799 /* Which pin is doing auto flow? RTS or DTR? */ 800 spin_lock_irqsave(&ch->ch_lock, lock_flags); 801 if ((cause & 0x4) == 0) { 802 if (cause & UART_MCR_RTS) 803 ch->ch_mostat |= UART_MCR_RTS; 804 else 805 ch->ch_mostat &= ~(UART_MCR_RTS); 806 } else { 807 if (cause & UART_MCR_DTR) 808 ch->ch_mostat |= UART_MCR_DTR; 809 else 810 ch->ch_mostat &= ~(UART_MCR_DTR); 811 } 812 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 813 } 814 815 /* Parse any modem signal changes */ 816 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 817 "MOD_STAT: sending to parse_modem_sigs\n"); 818 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 819 } 820 } 821 822 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port) 823 { 824 struct jsm_channel *ch; 825 int linestatus; 826 unsigned long lock_flags; 827 828 if (!brd) 829 return; 830 831 if (port >= brd->maxports) 832 return; 833 834 ch = brd->channels[port]; 835 if (!ch) 836 return; 837 838 linestatus = readb(&ch->ch_neo_uart->lsr); 839 840 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n", 841 __FILE__, __LINE__, port, linestatus); 842 843 ch->ch_cached_lsr |= linestatus; 844 845 if (ch->ch_cached_lsr & UART_LSR_DR) { 846 /* Read data from uart -> queue */ 847 neo_copy_data_from_uart_to_queue(ch); 848 spin_lock_irqsave(&ch->ch_lock, lock_flags); 849 jsm_check_queue_flow_control(ch); 850 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 851 } 852 853 /* 854 * This is a special flag. It indicates that at least 1 855 * RX error (parity, framing, or break) has happened. 856 * Mark this in our struct, which will tell me that I have 857 *to do the special RX+LSR read for this FIFO load. 858 */ 859 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 860 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 861 "%s:%d Port: %d Got an RX error, need to parse LSR\n", 862 __FILE__, __LINE__, port); 863 864 /* 865 * The next 3 tests should *NOT* happen, as the above test 866 * should encapsulate all 3... At least, thats what Exar says. 867 */ 868 869 if (linestatus & UART_LSR_PE) { 870 ch->ch_err_parity++; 871 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n", 872 __FILE__, __LINE__, port); 873 } 874 875 if (linestatus & UART_LSR_FE) { 876 ch->ch_err_frame++; 877 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n", 878 __FILE__, __LINE__, port); 879 } 880 881 if (linestatus & UART_LSR_BI) { 882 ch->ch_err_break++; 883 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 884 "%s:%d Port: %d. BRK INTR!\n", 885 __FILE__, __LINE__, port); 886 } 887 888 if (linestatus & UART_LSR_OE) { 889 /* 890 * Rx Oruns. Exar says that an orun will NOT corrupt 891 * the FIFO. It will just replace the holding register 892 * with this new data byte. So basically just ignore this. 893 * Probably we should eventually have an orun stat in our driver... 894 */ 895 ch->ch_err_overrun++; 896 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 897 "%s:%d Port: %d. Rx Overrun!\n", 898 __FILE__, __LINE__, port); 899 } 900 901 if (linestatus & UART_LSR_THRE) { 902 spin_lock_irqsave(&ch->ch_lock, lock_flags); 903 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 904 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 905 906 /* Transfer data (if any) from Write Queue -> UART. */ 907 neo_copy_data_from_queue_to_uart(ch); 908 } 909 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 910 spin_lock_irqsave(&ch->ch_lock, lock_flags); 911 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 912 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 913 914 /* Transfer data (if any) from Write Queue -> UART. */ 915 neo_copy_data_from_queue_to_uart(ch); 916 } 917 } 918 919 /* 920 * neo_param() 921 * Send any/all changes to the line to the UART. 922 */ 923 static void neo_param(struct jsm_channel *ch) 924 { 925 u8 lcr = 0; 926 u8 uart_lcr, ier; 927 u32 baud; 928 int quot; 929 struct jsm_board *bd; 930 931 bd = ch->ch_bd; 932 if (!bd) 933 return; 934 935 /* 936 * If baud rate is zero, flush queues, and set mval to drop DTR. 937 */ 938 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 939 ch->ch_r_head = ch->ch_r_tail = 0; 940 ch->ch_e_head = ch->ch_e_tail = 0; 941 942 neo_flush_uart_write(ch); 943 neo_flush_uart_read(ch); 944 945 ch->ch_flags |= (CH_BAUD0); 946 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 947 neo_assert_modem_signals(ch); 948 return; 949 950 } else { 951 int i; 952 unsigned int cflag; 953 static struct { 954 unsigned int rate; 955 unsigned int cflag; 956 } baud_rates[] = { 957 { 921600, B921600 }, 958 { 460800, B460800 }, 959 { 230400, B230400 }, 960 { 115200, B115200 }, 961 { 57600, B57600 }, 962 { 38400, B38400 }, 963 { 19200, B19200 }, 964 { 9600, B9600 }, 965 { 4800, B4800 }, 966 { 2400, B2400 }, 967 { 1200, B1200 }, 968 { 600, B600 }, 969 { 300, B300 }, 970 { 200, B200 }, 971 { 150, B150 }, 972 { 134, B134 }, 973 { 110, B110 }, 974 { 75, B75 }, 975 { 50, B50 }, 976 }; 977 978 cflag = C_BAUD(ch->uart_port.state->port.tty); 979 baud = 9600; 980 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { 981 if (baud_rates[i].cflag == cflag) { 982 baud = baud_rates[i].rate; 983 break; 984 } 985 } 986 987 if (ch->ch_flags & CH_BAUD0) 988 ch->ch_flags &= ~(CH_BAUD0); 989 } 990 991 if (ch->ch_c_cflag & PARENB) 992 lcr |= UART_LCR_PARITY; 993 994 if (!(ch->ch_c_cflag & PARODD)) 995 lcr |= UART_LCR_EPAR; 996 997 /* 998 * Not all platforms support mark/space parity, 999 * so this will hide behind an ifdef. 1000 */ 1001 #ifdef CMSPAR 1002 if (ch->ch_c_cflag & CMSPAR) 1003 lcr |= UART_LCR_SPAR; 1004 #endif 1005 1006 if (ch->ch_c_cflag & CSTOPB) 1007 lcr |= UART_LCR_STOP; 1008 1009 switch (ch->ch_c_cflag & CSIZE) { 1010 case CS5: 1011 lcr |= UART_LCR_WLEN5; 1012 break; 1013 case CS6: 1014 lcr |= UART_LCR_WLEN6; 1015 break; 1016 case CS7: 1017 lcr |= UART_LCR_WLEN7; 1018 break; 1019 case CS8: 1020 default: 1021 lcr |= UART_LCR_WLEN8; 1022 break; 1023 } 1024 1025 ier = readb(&ch->ch_neo_uart->ier); 1026 uart_lcr = readb(&ch->ch_neo_uart->lcr); 1027 1028 quot = ch->ch_bd->bd_dividend / baud; 1029 1030 if (quot != 0) { 1031 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 1032 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 1033 writeb((quot >> 8), &ch->ch_neo_uart->ier); 1034 writeb(lcr, &ch->ch_neo_uart->lcr); 1035 } 1036 1037 if (uart_lcr != lcr) 1038 writeb(lcr, &ch->ch_neo_uart->lcr); 1039 1040 if (ch->ch_c_cflag & CREAD) 1041 ier |= (UART_IER_RDI | UART_IER_RLSI); 1042 1043 ier |= (UART_IER_THRI | UART_IER_MSI); 1044 1045 writeb(ier, &ch->ch_neo_uart->ier); 1046 1047 /* Set new start/stop chars */ 1048 neo_set_new_start_stop_chars(ch); 1049 1050 if (ch->ch_c_cflag & CRTSCTS) 1051 neo_set_cts_flow_control(ch); 1052 else if (ch->ch_c_iflag & IXON) { 1053 /* If start/stop is set to disable, then we should disable flow control */ 1054 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1055 neo_set_no_output_flow_control(ch); 1056 else 1057 neo_set_ixon_flow_control(ch); 1058 } 1059 else 1060 neo_set_no_output_flow_control(ch); 1061 1062 if (ch->ch_c_cflag & CRTSCTS) 1063 neo_set_rts_flow_control(ch); 1064 else if (ch->ch_c_iflag & IXOFF) { 1065 /* If start/stop is set to disable, then we should disable flow control */ 1066 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1067 neo_set_no_input_flow_control(ch); 1068 else 1069 neo_set_ixoff_flow_control(ch); 1070 } 1071 else 1072 neo_set_no_input_flow_control(ch); 1073 /* 1074 * Adjust the RX FIFO Trigger level if baud is less than 9600. 1075 * Not exactly elegant, but this is needed because of the Exar chip's 1076 * delay on firing off the RX FIFO interrupt on slower baud rates. 1077 */ 1078 if (baud < 9600) { 1079 writeb(1, &ch->ch_neo_uart->rfifo); 1080 ch->ch_r_tlevel = 1; 1081 } 1082 1083 neo_assert_modem_signals(ch); 1084 1085 /* Get current status of the modem signals now */ 1086 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 1087 return; 1088 } 1089 1090 /* 1091 * jsm_neo_intr() 1092 * 1093 * Neo specific interrupt handler. 1094 */ 1095 static irqreturn_t neo_intr(int irq, void *voidbrd) 1096 { 1097 struct jsm_board *brd = voidbrd; 1098 struct jsm_channel *ch; 1099 int port = 0; 1100 int type = 0; 1101 int current_port; 1102 u32 tmp; 1103 u32 uart_poll; 1104 unsigned long lock_flags; 1105 unsigned long lock_flags2; 1106 int outofloop_count = 0; 1107 1108 /* Lock out the slow poller from running on this board. */ 1109 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); 1110 1111 /* 1112 * Read in "extended" IRQ information from the 32bit Neo register. 1113 * Bits 0-7: What port triggered the interrupt. 1114 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 1115 */ 1116 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 1117 1118 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", 1119 __FILE__, __LINE__, uart_poll); 1120 1121 if (!uart_poll) { 1122 jsm_dbg(INTR, &brd->pci_dev, 1123 "Kernel interrupted to me, but no pending interrupts...\n"); 1124 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1125 return IRQ_NONE; 1126 } 1127 1128 /* At this point, we have at least SOMETHING to service, dig further... */ 1129 1130 current_port = 0; 1131 1132 /* Loop on each port */ 1133 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){ 1134 1135 tmp = uart_poll; 1136 outofloop_count++; 1137 1138 /* Check current port to see if it has interrupt pending */ 1139 if ((tmp & jsm_offset_table[current_port]) != 0) { 1140 port = current_port; 1141 type = tmp >> (8 + (port * 3)); 1142 type &= 0x7; 1143 } else { 1144 current_port++; 1145 continue; 1146 } 1147 1148 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n", 1149 __FILE__, __LINE__, port, type); 1150 1151 /* Remove this port + type from uart_poll */ 1152 uart_poll &= ~(jsm_offset_table[port]); 1153 1154 if (!type) { 1155 /* If no type, just ignore it, and move onto next port */ 1156 jsm_dbg(INTR, &brd->pci_dev, 1157 "Interrupt with no type! port: %d\n", port); 1158 continue; 1159 } 1160 1161 /* Switch on type of interrupt we have */ 1162 switch (type) { 1163 1164 case UART_17158_RXRDY_TIMEOUT: 1165 /* 1166 * RXRDY Time-out is cleared by reading data in the 1167 * RX FIFO until it falls below the trigger level. 1168 */ 1169 1170 /* Verify the port is in range. */ 1171 if (port >= brd->nasync) 1172 continue; 1173 1174 ch = brd->channels[port]; 1175 if (!ch) 1176 continue; 1177 1178 neo_copy_data_from_uart_to_queue(ch); 1179 1180 /* Call our tty layer to enforce queue flow control if needed. */ 1181 spin_lock_irqsave(&ch->ch_lock, lock_flags2); 1182 jsm_check_queue_flow_control(ch); 1183 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); 1184 1185 continue; 1186 1187 case UART_17158_RX_LINE_STATUS: 1188 /* 1189 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 1190 */ 1191 neo_parse_lsr(brd, port); 1192 continue; 1193 1194 case UART_17158_TXRDY: 1195 /* 1196 * TXRDY interrupt clears after reading ISR register for the UART channel. 1197 */ 1198 1199 /* 1200 * Yes, this is odd... 1201 * Why would I check EVERY possibility of type of 1202 * interrupt, when we know its TXRDY??? 1203 * Becuz for some reason, even tho we got triggered for TXRDY, 1204 * it seems to be occasionally wrong. Instead of TX, which 1205 * it should be, I was getting things like RXDY too. Weird. 1206 */ 1207 neo_parse_isr(brd, port); 1208 continue; 1209 1210 case UART_17158_MSR: 1211 /* 1212 * MSR or flow control was seen. 1213 */ 1214 neo_parse_isr(brd, port); 1215 continue; 1216 1217 default: 1218 /* 1219 * The UART triggered us with a bogus interrupt type. 1220 * It appears the Exar chip, when REALLY bogged down, will throw 1221 * these once and awhile. 1222 * Its harmless, just ignore it and move on. 1223 */ 1224 jsm_dbg(INTR, &brd->pci_dev, 1225 "%s:%d Unknown Interrupt type: %x\n", 1226 __FILE__, __LINE__, type); 1227 continue; 1228 } 1229 } 1230 1231 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1232 1233 jsm_dbg(INTR, &brd->pci_dev, "finish\n"); 1234 return IRQ_HANDLED; 1235 } 1236 1237 /* 1238 * Neo specific way of turning off the receiver. 1239 * Used as a way to enforce queue flow control when in 1240 * hardware flow control mode. 1241 */ 1242 static void neo_disable_receiver(struct jsm_channel *ch) 1243 { 1244 u8 tmp = readb(&ch->ch_neo_uart->ier); 1245 tmp &= ~(UART_IER_RDI); 1246 writeb(tmp, &ch->ch_neo_uart->ier); 1247 1248 /* flush write operation */ 1249 neo_pci_posting_flush(ch->ch_bd); 1250 } 1251 1252 1253 /* 1254 * Neo specific way of turning on the receiver. 1255 * Used as a way to un-enforce queue flow control when in 1256 * hardware flow control mode. 1257 */ 1258 static void neo_enable_receiver(struct jsm_channel *ch) 1259 { 1260 u8 tmp = readb(&ch->ch_neo_uart->ier); 1261 tmp |= (UART_IER_RDI); 1262 writeb(tmp, &ch->ch_neo_uart->ier); 1263 1264 /* flush write operation */ 1265 neo_pci_posting_flush(ch->ch_bd); 1266 } 1267 1268 static void neo_send_start_character(struct jsm_channel *ch) 1269 { 1270 if (!ch) 1271 return; 1272 1273 if (ch->ch_startc != __DISABLED_CHAR) { 1274 ch->ch_xon_sends++; 1275 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1276 1277 /* flush write operation */ 1278 neo_pci_posting_flush(ch->ch_bd); 1279 } 1280 } 1281 1282 static void neo_send_stop_character(struct jsm_channel *ch) 1283 { 1284 if (!ch) 1285 return; 1286 1287 if (ch->ch_stopc != __DISABLED_CHAR) { 1288 ch->ch_xoff_sends++; 1289 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1290 1291 /* flush write operation */ 1292 neo_pci_posting_flush(ch->ch_bd); 1293 } 1294 } 1295 1296 /* 1297 * neo_uart_init 1298 */ 1299 static void neo_uart_init(struct jsm_channel *ch) 1300 { 1301 writeb(0, &ch->ch_neo_uart->ier); 1302 writeb(0, &ch->ch_neo_uart->efr); 1303 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1304 1305 /* Clear out UART and FIFO */ 1306 readb(&ch->ch_neo_uart->txrx); 1307 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1308 readb(&ch->ch_neo_uart->lsr); 1309 readb(&ch->ch_neo_uart->msr); 1310 1311 ch->ch_flags |= CH_FIFO_ENABLED; 1312 1313 /* Assert any signals we want up */ 1314 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1315 } 1316 1317 /* 1318 * Make the UART completely turn off. 1319 */ 1320 static void neo_uart_off(struct jsm_channel *ch) 1321 { 1322 /* Turn off UART enhanced bits */ 1323 writeb(0, &ch->ch_neo_uart->efr); 1324 1325 /* Stop all interrupts from occurring. */ 1326 writeb(0, &ch->ch_neo_uart->ier); 1327 } 1328 1329 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch) 1330 { 1331 u8 left = 0; 1332 u8 lsr = readb(&ch->ch_neo_uart->lsr); 1333 1334 /* We must cache the LSR as some of the bits get reset once read... */ 1335 ch->ch_cached_lsr |= lsr; 1336 1337 /* Determine whether the Transmitter is empty or not */ 1338 if (!(lsr & UART_LSR_TEMT)) 1339 left = 1; 1340 else { 1341 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1342 left = 0; 1343 } 1344 1345 return left; 1346 } 1347 1348 /* Channel lock MUST be held by the calling function! */ 1349 static void neo_send_break(struct jsm_channel *ch) 1350 { 1351 /* 1352 * Set the time we should stop sending the break. 1353 * If we are already sending a break, toss away the existing 1354 * time to stop, and use this new value instead. 1355 */ 1356 1357 /* Tell the UART to start sending the break */ 1358 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1359 u8 temp = readb(&ch->ch_neo_uart->lcr); 1360 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1361 ch->ch_flags |= (CH_BREAK_SENDING); 1362 1363 /* flush write operation */ 1364 neo_pci_posting_flush(ch->ch_bd); 1365 } 1366 } 1367 1368 /* 1369 * neo_send_immediate_char. 1370 * 1371 * Sends a specific character as soon as possible to the UART, 1372 * jumping over any bytes that might be in the write queue. 1373 * 1374 * The channel lock MUST be held by the calling function. 1375 */ 1376 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c) 1377 { 1378 if (!ch) 1379 return; 1380 1381 writeb(c, &ch->ch_neo_uart->txrx); 1382 1383 /* flush write operation */ 1384 neo_pci_posting_flush(ch->ch_bd); 1385 } 1386 1387 struct board_ops jsm_neo_ops = { 1388 .intr = neo_intr, 1389 .uart_init = neo_uart_init, 1390 .uart_off = neo_uart_off, 1391 .param = neo_param, 1392 .assert_modem_signals = neo_assert_modem_signals, 1393 .flush_uart_write = neo_flush_uart_write, 1394 .flush_uart_read = neo_flush_uart_read, 1395 .disable_receiver = neo_disable_receiver, 1396 .enable_receiver = neo_enable_receiver, 1397 .send_break = neo_send_break, 1398 .clear_break = neo_clear_break, 1399 .send_start_character = neo_send_start_character, 1400 .send_stop_character = neo_send_stop_character, 1401 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 1402 .get_uart_bytes_left = neo_get_uart_bytes_left, 1403 .send_immediate_char = neo_send_immediate_char 1404 }; 1405