1ab4382d2SGreg Kroah-Hartman /************************************************************************ 2ab4382d2SGreg Kroah-Hartman * Copyright 2003 Digi International (www.digi.com) 3ab4382d2SGreg Kroah-Hartman * 4ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 IBM Corporation. All rights reserved. 5ab4382d2SGreg Kroah-Hartman * 6ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 7ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 8ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2, or (at your option) 9ab4382d2SGreg Kroah-Hartman * any later version. 10ab4382d2SGreg Kroah-Hartman * 11ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 12ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 13ab4382d2SGreg Kroah-Hartman * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 14ab4382d2SGreg Kroah-Hartman * PURPOSE. See the GNU General Public License for more details. 15ab4382d2SGreg Kroah-Hartman * 16ab4382d2SGreg Kroah-Hartman * You should have received a copy of the GNU General Public License 17ab4382d2SGreg Kroah-Hartman * along with this program; if not, write to the Free Software 18ab4382d2SGreg Kroah-Hartman * Foundation, Inc., 59 * Temple Place - Suite 330, Boston, 19ab4382d2SGreg Kroah-Hartman * MA 02111-1307, USA. 20ab4382d2SGreg Kroah-Hartman * 21ab4382d2SGreg Kroah-Hartman * Contact Information: 22ab4382d2SGreg Kroah-Hartman * Scott H Kilau <Scott_Kilau@digi.com> 23ab4382d2SGreg Kroah-Hartman * Wendy Xiong <wendyx@us.ibm.com> 24ab4382d2SGreg Kroah-Hartman * 25ab4382d2SGreg Kroah-Hartman ***********************************************************************/ 26ab4382d2SGreg Kroah-Hartman 27ab4382d2SGreg Kroah-Hartman #ifndef __JSM_DRIVER_H 28ab4382d2SGreg Kroah-Hartman #define __JSM_DRIVER_H 29ab4382d2SGreg Kroah-Hartman 30ab4382d2SGreg Kroah-Hartman #include <linux/kernel.h> 31ab4382d2SGreg Kroah-Hartman #include <linux/types.h> /* To pick up the varions Linux types */ 32ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 33ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 34ab4382d2SGreg Kroah-Hartman #include <linux/device.h> 35ab4382d2SGreg Kroah-Hartman 36ab4382d2SGreg Kroah-Hartman /* 37ab4382d2SGreg Kroah-Hartman * Debugging levels can be set using debug insmod variable 38ab4382d2SGreg Kroah-Hartman * They can also be compiled out completely. 39ab4382d2SGreg Kroah-Hartman */ 40ab4382d2SGreg Kroah-Hartman enum { 41ab4382d2SGreg Kroah-Hartman DBG_INIT = 0x01, 42ab4382d2SGreg Kroah-Hartman DBG_BASIC = 0x02, 43ab4382d2SGreg Kroah-Hartman DBG_CORE = 0x04, 44ab4382d2SGreg Kroah-Hartman DBG_OPEN = 0x08, 45ab4382d2SGreg Kroah-Hartman DBG_CLOSE = 0x10, 46ab4382d2SGreg Kroah-Hartman DBG_READ = 0x20, 47ab4382d2SGreg Kroah-Hartman DBG_WRITE = 0x40, 48ab4382d2SGreg Kroah-Hartman DBG_IOCTL = 0x80, 49ab4382d2SGreg Kroah-Hartman DBG_PROC = 0x100, 50ab4382d2SGreg Kroah-Hartman DBG_PARAM = 0x200, 51ab4382d2SGreg Kroah-Hartman DBG_PSCAN = 0x400, 52ab4382d2SGreg Kroah-Hartman DBG_EVENT = 0x800, 53ab4382d2SGreg Kroah-Hartman DBG_DRAIN = 0x1000, 54ab4382d2SGreg Kroah-Hartman DBG_MSIGS = 0x2000, 55ab4382d2SGreg Kroah-Hartman DBG_MGMT = 0x4000, 56ab4382d2SGreg Kroah-Hartman DBG_INTR = 0x8000, 57ab4382d2SGreg Kroah-Hartman DBG_CARR = 0x10000, 58ab4382d2SGreg Kroah-Hartman }; 59ab4382d2SGreg Kroah-Hartman 60669fef46SJoe Perches #define jsm_dbg(nlevel, pdev, fmt, ...) \ 61669fef46SJoe Perches do { \ 62669fef46SJoe Perches if (DBG_##nlevel & jsm_debug) \ 63669fef46SJoe Perches dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \ 64669fef46SJoe Perches } while (0) 65ab4382d2SGreg Kroah-Hartman 66ab4382d2SGreg Kroah-Hartman #define MAXLINES 256 67ab4382d2SGreg Kroah-Hartman #define MAXPORTS 8 68ab4382d2SGreg Kroah-Hartman #define MAX_STOPS_SENT 5 69ab4382d2SGreg Kroah-Hartman 70293b2265SBill Pemberton /* Board ids */ 71293b2265SBill Pemberton #define PCI_DEVICE_ID_NEO_4 0x00B0 72293b2265SBill Pemberton #define PCI_DEVICE_ID_NEO_1_422 0x00CC 73293b2265SBill Pemberton #define PCI_DEVICE_ID_NEO_1_422_485 0x00CD 74293b2265SBill Pemberton #define PCI_DEVICE_ID_NEO_2_422_485 0x00CE 75293b2265SBill Pemberton #define PCIE_DEVICE_ID_NEO_8 0x00F0 76293b2265SBill Pemberton #define PCIE_DEVICE_ID_NEO_4 0x00F1 77293b2265SBill Pemberton #define PCIE_DEVICE_ID_NEO_4RJ45 0x00F2 78293b2265SBill Pemberton #define PCIE_DEVICE_ID_NEO_8RJ45 0x00F3 79293b2265SBill Pemberton 80ab4382d2SGreg Kroah-Hartman /* Board type definitions */ 81ab4382d2SGreg Kroah-Hartman 82ab4382d2SGreg Kroah-Hartman #define T_NEO 0000 83ab4382d2SGreg Kroah-Hartman #define T_CLASSIC 0001 84ab4382d2SGreg Kroah-Hartman #define T_PCIBUS 0400 85ab4382d2SGreg Kroah-Hartman 86ab4382d2SGreg Kroah-Hartman /* Board State Definitions */ 87ab4382d2SGreg Kroah-Hartman 88ab4382d2SGreg Kroah-Hartman #define BD_RUNNING 0x0 89ab4382d2SGreg Kroah-Hartman #define BD_REASON 0x7f 90ab4382d2SGreg Kroah-Hartman #define BD_NOTFOUND 0x1 91ab4382d2SGreg Kroah-Hartman #define BD_NOIOPORT 0x2 92ab4382d2SGreg Kroah-Hartman #define BD_NOMEM 0x3 93ab4382d2SGreg Kroah-Hartman #define BD_NOBIOS 0x4 94ab4382d2SGreg Kroah-Hartman #define BD_NOFEP 0x5 95ab4382d2SGreg Kroah-Hartman #define BD_FAILED 0x6 96ab4382d2SGreg Kroah-Hartman #define BD_ALLOCATED 0x7 97ab4382d2SGreg Kroah-Hartman #define BD_TRIBOOT 0x8 98ab4382d2SGreg Kroah-Hartman #define BD_BADKME 0x80 99ab4382d2SGreg Kroah-Hartman 100ab4382d2SGreg Kroah-Hartman 101ab4382d2SGreg Kroah-Hartman /* 4 extra for alignment play space */ 102ab4382d2SGreg Kroah-Hartman #define WRITEBUFLEN ((4096) + 4) 103ab4382d2SGreg Kroah-Hartman 104ab4382d2SGreg Kroah-Hartman #define JSM_VERSION "jsm: 1.2-1-INKERNEL" 105ab4382d2SGreg Kroah-Hartman #define JSM_PARTNUM "40002438_A-INKERNEL" 106ab4382d2SGreg Kroah-Hartman 107ab4382d2SGreg Kroah-Hartman struct jsm_board; 108ab4382d2SGreg Kroah-Hartman struct jsm_channel; 109ab4382d2SGreg Kroah-Hartman 110ab4382d2SGreg Kroah-Hartman /************************************************************************ 111ab4382d2SGreg Kroah-Hartman * Per board operations structure * 112ab4382d2SGreg Kroah-Hartman ************************************************************************/ 113ab4382d2SGreg Kroah-Hartman struct board_ops { 114ab4382d2SGreg Kroah-Hartman irq_handler_t intr; 115ab4382d2SGreg Kroah-Hartman void (*uart_init) (struct jsm_channel *ch); 116ab4382d2SGreg Kroah-Hartman void (*uart_off) (struct jsm_channel *ch); 117ab4382d2SGreg Kroah-Hartman void (*param) (struct jsm_channel *ch); 118ab4382d2SGreg Kroah-Hartman void (*assert_modem_signals) (struct jsm_channel *ch); 119ab4382d2SGreg Kroah-Hartman void (*flush_uart_write) (struct jsm_channel *ch); 120ab4382d2SGreg Kroah-Hartman void (*flush_uart_read) (struct jsm_channel *ch); 121ab4382d2SGreg Kroah-Hartman void (*disable_receiver) (struct jsm_channel *ch); 122ab4382d2SGreg Kroah-Hartman void (*enable_receiver) (struct jsm_channel *ch); 123ab4382d2SGreg Kroah-Hartman void (*send_break) (struct jsm_channel *ch); 124ab4382d2SGreg Kroah-Hartman void (*clear_break) (struct jsm_channel *ch, int); 125ab4382d2SGreg Kroah-Hartman void (*send_start_character) (struct jsm_channel *ch); 126ab4382d2SGreg Kroah-Hartman void (*send_stop_character) (struct jsm_channel *ch); 127ab4382d2SGreg Kroah-Hartman void (*copy_data_from_queue_to_uart) (struct jsm_channel *ch); 128ab4382d2SGreg Kroah-Hartman u32 (*get_uart_bytes_left) (struct jsm_channel *ch); 129ab4382d2SGreg Kroah-Hartman void (*send_immediate_char) (struct jsm_channel *ch, unsigned char); 130ab4382d2SGreg Kroah-Hartman }; 131ab4382d2SGreg Kroah-Hartman 132ab4382d2SGreg Kroah-Hartman 133ab4382d2SGreg Kroah-Hartman /* 134ab4382d2SGreg Kroah-Hartman * Per-board information 135ab4382d2SGreg Kroah-Hartman */ 136ab4382d2SGreg Kroah-Hartman struct jsm_board 137ab4382d2SGreg Kroah-Hartman { 138ab4382d2SGreg Kroah-Hartman int boardnum; /* Board number: 0-32 */ 139ab4382d2SGreg Kroah-Hartman 140ab4382d2SGreg Kroah-Hartman int type; /* Type of board */ 141ab4382d2SGreg Kroah-Hartman u8 rev; /* PCI revision ID */ 142ab4382d2SGreg Kroah-Hartman struct pci_dev *pci_dev; 143ab4382d2SGreg Kroah-Hartman u32 maxports; /* MAX ports this board can handle */ 144ab4382d2SGreg Kroah-Hartman 145ab4382d2SGreg Kroah-Hartman spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and 146ab4382d2SGreg Kroah-Hartman * the interrupt routine from each other. 147ab4382d2SGreg Kroah-Hartman */ 148ab4382d2SGreg Kroah-Hartman 149ab4382d2SGreg Kroah-Hartman u32 nasync; /* Number of ports on card */ 150ab4382d2SGreg Kroah-Hartman 151ab4382d2SGreg Kroah-Hartman u32 irq; /* Interrupt request number */ 152ab4382d2SGreg Kroah-Hartman 153ab4382d2SGreg Kroah-Hartman u64 membase; /* Start of base memory of the card */ 154ab4382d2SGreg Kroah-Hartman u64 membase_end; /* End of base memory of the card */ 155ab4382d2SGreg Kroah-Hartman 156ab4382d2SGreg Kroah-Hartman u8 __iomem *re_map_membase;/* Remapped memory of the card */ 157ab4382d2SGreg Kroah-Hartman 158ab4382d2SGreg Kroah-Hartman u64 iobase; /* Start of io base of the card */ 159ab4382d2SGreg Kroah-Hartman u64 iobase_end; /* End of io base of the card */ 160ab4382d2SGreg Kroah-Hartman 161ab4382d2SGreg Kroah-Hartman u32 bd_uart_offset; /* Space between each UART */ 162ab4382d2SGreg Kroah-Hartman 163ab4382d2SGreg Kroah-Hartman struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */ 164ab4382d2SGreg Kroah-Hartman 165ab4382d2SGreg Kroah-Hartman u32 bd_dividend; /* Board/UARTs specific dividend */ 166ab4382d2SGreg Kroah-Hartman 167ab4382d2SGreg Kroah-Hartman struct board_ops *bd_ops; 168ab4382d2SGreg Kroah-Hartman 169ab4382d2SGreg Kroah-Hartman struct list_head jsm_board_entry; 170ab4382d2SGreg Kroah-Hartman }; 171ab4382d2SGreg Kroah-Hartman 172ab4382d2SGreg Kroah-Hartman /************************************************************************ 173ab4382d2SGreg Kroah-Hartman * Device flag definitions for ch_flags. 174ab4382d2SGreg Kroah-Hartman ************************************************************************/ 175ab4382d2SGreg Kroah-Hartman #define CH_PRON 0x0001 /* Printer on string */ 176ab4382d2SGreg Kroah-Hartman #define CH_STOP 0x0002 /* Output is stopped */ 177ab4382d2SGreg Kroah-Hartman #define CH_STOPI 0x0004 /* Input is stopped */ 178ab4382d2SGreg Kroah-Hartman #define CH_CD 0x0008 /* Carrier is present */ 179ab4382d2SGreg Kroah-Hartman #define CH_FCAR 0x0010 /* Carrier forced on */ 180ab4382d2SGreg Kroah-Hartman #define CH_HANGUP 0x0020 /* Hangup received */ 181ab4382d2SGreg Kroah-Hartman 182ab4382d2SGreg Kroah-Hartman #define CH_RECEIVER_OFF 0x0040 /* Receiver is off */ 183ab4382d2SGreg Kroah-Hartman #define CH_OPENING 0x0080 /* Port in fragile open state */ 184ab4382d2SGreg Kroah-Hartman #define CH_CLOSING 0x0100 /* Port in fragile close state */ 185ab4382d2SGreg Kroah-Hartman #define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */ 186ab4382d2SGreg Kroah-Hartman #define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */ 187ab4382d2SGreg Kroah-Hartman #define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */ 188ab4382d2SGreg Kroah-Hartman #define CH_BREAK_SENDING 0x1000 /* Break is being sent */ 189ab4382d2SGreg Kroah-Hartman #define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */ 190ab4382d2SGreg Kroah-Hartman #define CH_BAUD0 0x08000 /* Used for checking B0 transitions */ 191ab4382d2SGreg Kroah-Hartman 192ab4382d2SGreg Kroah-Hartman /* Our Read/Error/Write queue sizes */ 193ab4382d2SGreg Kroah-Hartman #define RQUEUEMASK 0x1FFF /* 8 K - 1 */ 194ab4382d2SGreg Kroah-Hartman #define EQUEUEMASK 0x1FFF /* 8 K - 1 */ 195ab4382d2SGreg Kroah-Hartman #define RQUEUESIZE (RQUEUEMASK + 1) 196ab4382d2SGreg Kroah-Hartman #define EQUEUESIZE RQUEUESIZE 197ab4382d2SGreg Kroah-Hartman 198ab4382d2SGreg Kroah-Hartman 199ab4382d2SGreg Kroah-Hartman /************************************************************************ 200ab4382d2SGreg Kroah-Hartman * Channel information structure. 201ab4382d2SGreg Kroah-Hartman ************************************************************************/ 202ab4382d2SGreg Kroah-Hartman struct jsm_channel { 203ab4382d2SGreg Kroah-Hartman struct uart_port uart_port; 204ab4382d2SGreg Kroah-Hartman struct jsm_board *ch_bd; /* Board structure pointer */ 205ab4382d2SGreg Kroah-Hartman 206ab4382d2SGreg Kroah-Hartman spinlock_t ch_lock; /* provide for serialization */ 207ab4382d2SGreg Kroah-Hartman wait_queue_head_t ch_flags_wait; 208ab4382d2SGreg Kroah-Hartman 209ab4382d2SGreg Kroah-Hartman u32 ch_portnum; /* Port number, 0 offset. */ 210ab4382d2SGreg Kroah-Hartman u32 ch_open_count; /* open count */ 211ab4382d2SGreg Kroah-Hartman u32 ch_flags; /* Channel flags */ 212ab4382d2SGreg Kroah-Hartman 213ab4382d2SGreg Kroah-Hartman u64 ch_close_delay; /* How long we should drop RTS/DTR for */ 214ab4382d2SGreg Kroah-Hartman 215ab4382d2SGreg Kroah-Hartman tcflag_t ch_c_iflag; /* channel iflags */ 216ab4382d2SGreg Kroah-Hartman tcflag_t ch_c_cflag; /* channel cflags */ 217ab4382d2SGreg Kroah-Hartman tcflag_t ch_c_oflag; /* channel oflags */ 218ab4382d2SGreg Kroah-Hartman tcflag_t ch_c_lflag; /* channel lflags */ 219ab4382d2SGreg Kroah-Hartman u8 ch_stopc; /* Stop character */ 220ab4382d2SGreg Kroah-Hartman u8 ch_startc; /* Start character */ 221ab4382d2SGreg Kroah-Hartman 222ab4382d2SGreg Kroah-Hartman u8 ch_mostat; /* FEP output modem status */ 223ab4382d2SGreg Kroah-Hartman u8 ch_mistat; /* FEP input modem status */ 224ab4382d2SGreg Kroah-Hartman 225*d7685ca7SKonrad Zapalowicz /* Pointers to the "mapped" UART structs */ 226*d7685ca7SKonrad Zapalowicz struct neo_uart_struct __iomem *ch_neo_uart; /* NEO card */ 227*d7685ca7SKonrad Zapalowicz struct cls_uart_struct __iomem *ch_cls_uart; /* Classic card */ 228*d7685ca7SKonrad Zapalowicz 229ab4382d2SGreg Kroah-Hartman u8 ch_cached_lsr; /* Cached value of the LSR register */ 230ab4382d2SGreg Kroah-Hartman 231ab4382d2SGreg Kroah-Hartman u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */ 232ab4382d2SGreg Kroah-Hartman u16 ch_r_head; /* Head location of the read queue */ 233ab4382d2SGreg Kroah-Hartman u16 ch_r_tail; /* Tail location of the read queue */ 234ab4382d2SGreg Kroah-Hartman 235ab4382d2SGreg Kroah-Hartman u8 *ch_equeue; /* Our error queue buffer - malloc'ed */ 236ab4382d2SGreg Kroah-Hartman u16 ch_e_head; /* Head location of the error queue */ 237ab4382d2SGreg Kroah-Hartman u16 ch_e_tail; /* Tail location of the error queue */ 238ab4382d2SGreg Kroah-Hartman 239ab4382d2SGreg Kroah-Hartman u64 ch_rxcount; /* total of data received so far */ 240ab4382d2SGreg Kroah-Hartman u64 ch_txcount; /* total of data transmitted so far */ 241ab4382d2SGreg Kroah-Hartman 242ab4382d2SGreg Kroah-Hartman u8 ch_r_tlevel; /* Receive Trigger level */ 243ab4382d2SGreg Kroah-Hartman u8 ch_t_tlevel; /* Transmit Trigger level */ 244ab4382d2SGreg Kroah-Hartman 245ab4382d2SGreg Kroah-Hartman u8 ch_r_watermark; /* Receive Watermark */ 246ab4382d2SGreg Kroah-Hartman 247ab4382d2SGreg Kroah-Hartman 248ab4382d2SGreg Kroah-Hartman u32 ch_stops_sent; /* How many times I have sent a stop character 249ab4382d2SGreg Kroah-Hartman * to try to stop the other guy sending. 250ab4382d2SGreg Kroah-Hartman */ 251ab4382d2SGreg Kroah-Hartman u64 ch_err_parity; /* Count of parity errors on channel */ 252ab4382d2SGreg Kroah-Hartman u64 ch_err_frame; /* Count of framing errors on channel */ 253ab4382d2SGreg Kroah-Hartman u64 ch_err_break; /* Count of breaks on channel */ 254ab4382d2SGreg Kroah-Hartman u64 ch_err_overrun; /* Count of overruns on channel */ 255ab4382d2SGreg Kroah-Hartman 256ab4382d2SGreg Kroah-Hartman u64 ch_xon_sends; /* Count of xons transmitted */ 257ab4382d2SGreg Kroah-Hartman u64 ch_xoff_sends; /* Count of xoffs transmitted */ 258ab4382d2SGreg Kroah-Hartman }; 259ab4382d2SGreg Kroah-Hartman 260*d7685ca7SKonrad Zapalowicz /************************************************************************ 261*d7685ca7SKonrad Zapalowicz * Per channel/port Classic UART structures * 262*d7685ca7SKonrad Zapalowicz ************************************************************************ 263*d7685ca7SKonrad Zapalowicz * Base Structure Entries Usage Meanings to Host * 264*d7685ca7SKonrad Zapalowicz * * 265*d7685ca7SKonrad Zapalowicz * W = read write R = read only * 266*d7685ca7SKonrad Zapalowicz * U = Unused. * 267*d7685ca7SKonrad Zapalowicz ************************************************************************/ 268*d7685ca7SKonrad Zapalowicz 269*d7685ca7SKonrad Zapalowicz struct cls_uart_struct { 270*d7685ca7SKonrad Zapalowicz u8 txrx; /* WR RHR/THR - Holding Reg */ 271*d7685ca7SKonrad Zapalowicz u8 ier; /* WR IER - Interrupt Enable Reg */ 272*d7685ca7SKonrad Zapalowicz u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/ 273*d7685ca7SKonrad Zapalowicz u8 lcr; /* WR LCR - Line Control Reg */ 274*d7685ca7SKonrad Zapalowicz u8 mcr; /* WR MCR - Modem Control Reg */ 275*d7685ca7SKonrad Zapalowicz u8 lsr; /* WR LSR - Line Status Reg */ 276*d7685ca7SKonrad Zapalowicz u8 msr; /* WR MSR - Modem Status Reg */ 277*d7685ca7SKonrad Zapalowicz u8 spr; /* WR SPR - Scratch Pad Reg */ 278*d7685ca7SKonrad Zapalowicz }; 279*d7685ca7SKonrad Zapalowicz 280*d7685ca7SKonrad Zapalowicz /* Where to read the interrupt register (8bits) */ 281*d7685ca7SKonrad Zapalowicz #define UART_CLASSIC_POLL_ADDR_OFFSET 0x40 282*d7685ca7SKonrad Zapalowicz 283*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF 284*d7685ca7SKonrad Zapalowicz 285*d7685ca7SKonrad Zapalowicz #define UART_16654_FCR_TXTRIGGER_8 0x0 286*d7685ca7SKonrad Zapalowicz #define UART_16654_FCR_TXTRIGGER_16 0x10 287*d7685ca7SKonrad Zapalowicz #define UART_16654_FCR_TXTRIGGER_32 0x20 288*d7685ca7SKonrad Zapalowicz #define UART_16654_FCR_TXTRIGGER_56 0x30 289*d7685ca7SKonrad Zapalowicz 290*d7685ca7SKonrad Zapalowicz #define UART_16654_FCR_RXTRIGGER_8 0x0 291*d7685ca7SKonrad Zapalowicz #define UART_16654_FCR_RXTRIGGER_16 0x40 292*d7685ca7SKonrad Zapalowicz #define UART_16654_FCR_RXTRIGGER_56 0x80 293*d7685ca7SKonrad Zapalowicz #define UART_16654_FCR_RXTRIGGER_60 0xC0 294*d7685ca7SKonrad Zapalowicz 295*d7685ca7SKonrad Zapalowicz #define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */ 296*d7685ca7SKonrad Zapalowicz #define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 297*d7685ca7SKonrad Zapalowicz 298*d7685ca7SKonrad Zapalowicz /* 299*d7685ca7SKonrad Zapalowicz * These are the EXTENDED definitions for the Exar 654's Interrupt 300*d7685ca7SKonrad Zapalowicz * Enable Register. 301*d7685ca7SKonrad Zapalowicz */ 302*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */ 303*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 304*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 305*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 306*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 307*d7685ca7SKonrad Zapalowicz 308*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 309*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 310*d7685ca7SKonrad Zapalowicz 311*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 312*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 313*d7685ca7SKonrad Zapalowicz #define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 314ab4382d2SGreg Kroah-Hartman 315ab4382d2SGreg Kroah-Hartman /************************************************************************ 316ab4382d2SGreg Kroah-Hartman * Per channel/port NEO UART structure * 317ab4382d2SGreg Kroah-Hartman ************************************************************************ 318ab4382d2SGreg Kroah-Hartman * Base Structure Entries Usage Meanings to Host * 319ab4382d2SGreg Kroah-Hartman * * 320ab4382d2SGreg Kroah-Hartman * W = read write R = read only * 321ab4382d2SGreg Kroah-Hartman * U = Unused. * 322ab4382d2SGreg Kroah-Hartman ************************************************************************/ 323ab4382d2SGreg Kroah-Hartman 324ab4382d2SGreg Kroah-Hartman struct neo_uart_struct { 325ab4382d2SGreg Kroah-Hartman u8 txrx; /* WR RHR/THR - Holding Reg */ 326ab4382d2SGreg Kroah-Hartman u8 ier; /* WR IER - Interrupt Enable Reg */ 327ab4382d2SGreg Kroah-Hartman u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ 328ab4382d2SGreg Kroah-Hartman u8 lcr; /* WR LCR - Line Control Reg */ 329ab4382d2SGreg Kroah-Hartman u8 mcr; /* WR MCR - Modem Control Reg */ 330ab4382d2SGreg Kroah-Hartman u8 lsr; /* WR LSR - Line Status Reg */ 331ab4382d2SGreg Kroah-Hartman u8 msr; /* WR MSR - Modem Status Reg */ 332ab4382d2SGreg Kroah-Hartman u8 spr; /* WR SPR - Scratch Pad Reg */ 333ab4382d2SGreg Kroah-Hartman u8 fctr; /* WR FCTR - Feature Control Reg */ 334ab4382d2SGreg Kroah-Hartman u8 efr; /* WR EFR - Enhanced Function Reg */ 335ab4382d2SGreg Kroah-Hartman u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */ 33625985edcSLucas De Marchi u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */ 337ab4382d2SGreg Kroah-Hartman u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */ 338ab4382d2SGreg Kroah-Hartman u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */ 339ab4382d2SGreg Kroah-Hartman u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */ 340ab4382d2SGreg Kroah-Hartman u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */ 341ab4382d2SGreg Kroah-Hartman 342ab4382d2SGreg Kroah-Hartman u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */ 343ab4382d2SGreg Kroah-Hartman u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */ 344ab4382d2SGreg Kroah-Hartman u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */ 345ab4382d2SGreg Kroah-Hartman u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */ 346ab4382d2SGreg Kroah-Hartman }; 347ab4382d2SGreg Kroah-Hartman 348ab4382d2SGreg Kroah-Hartman /* Where to read the extended interrupt register (32bits instead of 8bits) */ 349ab4382d2SGreg Kroah-Hartman #define UART_17158_POLL_ADDR_OFFSET 0x80 350ab4382d2SGreg Kroah-Hartman 351ab4382d2SGreg Kroah-Hartman /* 352ab4382d2SGreg Kroah-Hartman * These are the redefinitions for the FCTR on the XR17C158, since 353ab4382d2SGreg Kroah-Hartman * Exar made them different than their earlier design. (XR16C854) 354ab4382d2SGreg Kroah-Hartman */ 355ab4382d2SGreg Kroah-Hartman 356ab4382d2SGreg Kroah-Hartman /* These are only applicable when table D is selected */ 357ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_NODELAY 0x00 358ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_4DELAY 0x01 359ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_6DELAY 0x02 360ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_8DELAY 0x03 361ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_12DELAY 0x12 362ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_16DELAY 0x05 363ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_20DELAY 0x13 364ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_24DELAY 0x06 365ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_28DELAY 0x14 366ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_32DELAY 0x07 367ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_36DELAY 0x16 368ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_40DELAY 0x08 369ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_44DELAY 0x09 370ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_48DELAY 0x10 371ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_52DELAY 0x11 372ab4382d2SGreg Kroah-Hartman 373ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_IRDA 0x10 374ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RS485 0x20 375ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_TRGA 0x00 376ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_TRGB 0x40 377ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_TRGC 0x80 378ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_TRGD 0xC0 379ab4382d2SGreg Kroah-Hartman 380ab4382d2SGreg Kroah-Hartman /* 17158 trigger table selects.. */ 381ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_BIT6 0x40 382ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_BIT7 0x80 383ab4382d2SGreg Kroah-Hartman 384ab4382d2SGreg Kroah-Hartman /* 17158 TX/RX memmapped buffer offsets */ 385ab4382d2SGreg Kroah-Hartman #define UART_17158_RX_FIFOSIZE 64 386ab4382d2SGreg Kroah-Hartman #define UART_17158_TX_FIFOSIZE 64 387ab4382d2SGreg Kroah-Hartman 388ab4382d2SGreg Kroah-Hartman /* 17158 Extended IIR's */ 389ab4382d2SGreg Kroah-Hartman #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 390ab4382d2SGreg Kroah-Hartman #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */ 391ab4382d2SGreg Kroah-Hartman #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */ 392ab4382d2SGreg Kroah-Hartman #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */ 393ab4382d2SGreg Kroah-Hartman 394ab4382d2SGreg Kroah-Hartman /* 395ab4382d2SGreg Kroah-Hartman * These are the extended interrupts that get sent 396ab4382d2SGreg Kroah-Hartman * back to us from the UART's 32bit interrupt register 397ab4382d2SGreg Kroah-Hartman */ 398ab4382d2SGreg Kroah-Hartman #define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */ 399ab4382d2SGreg Kroah-Hartman #define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */ 400ab4382d2SGreg Kroah-Hartman #define UART_17158_TXRDY 0x3 /* TX Ready */ 401ab4382d2SGreg Kroah-Hartman #define UART_17158_MSR 0x4 /* Modem State Change */ 402ab4382d2SGreg Kroah-Hartman #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */ 403ab4382d2SGreg Kroah-Hartman #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */ 404ab4382d2SGreg Kroah-Hartman 405ab4382d2SGreg Kroah-Hartman /* 406ab4382d2SGreg Kroah-Hartman * These are the EXTENDED definitions for the 17C158's Interrupt 407ab4382d2SGreg Kroah-Hartman * Enable Register. 408ab4382d2SGreg Kroah-Hartman */ 409ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */ 410ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 411ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 412ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 413ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 414ab4382d2SGreg Kroah-Hartman 415ab4382d2SGreg Kroah-Hartman #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 416ab4382d2SGreg Kroah-Hartman #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 417ab4382d2SGreg Kroah-Hartman 418ab4382d2SGreg Kroah-Hartman #define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */ 419ab4382d2SGreg Kroah-Hartman #define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 420ab4382d2SGreg Kroah-Hartman #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 421ab4382d2SGreg Kroah-Hartman #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 422ab4382d2SGreg Kroah-Hartman 423ab4382d2SGreg Kroah-Hartman #define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI" 424ab4382d2SGreg Kroah-Hartman #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator" 425ab4382d2SGreg Kroah-Hartman #define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI" 426ab4382d2SGreg Kroah-Hartman #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator" 427ab4382d2SGreg Kroah-Hartman #define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM" 428ab4382d2SGreg Kroah-Hartman 429ab4382d2SGreg Kroah-Hartman /* 430ab4382d2SGreg Kroah-Hartman * Our Global Variables. 431ab4382d2SGreg Kroah-Hartman */ 432ab4382d2SGreg Kroah-Hartman extern struct uart_driver jsm_uart_driver; 433ab4382d2SGreg Kroah-Hartman extern struct board_ops jsm_neo_ops; 434ab4382d2SGreg Kroah-Hartman extern int jsm_debug; 435ab4382d2SGreg Kroah-Hartman 436ab4382d2SGreg Kroah-Hartman /************************************************************************* 437ab4382d2SGreg Kroah-Hartman * 438ab4382d2SGreg Kroah-Hartman * Prototypes for non-static functions used in more than one module 439ab4382d2SGreg Kroah-Hartman * 440ab4382d2SGreg Kroah-Hartman *************************************************************************/ 441ab4382d2SGreg Kroah-Hartman int jsm_tty_init(struct jsm_board *); 442ab4382d2SGreg Kroah-Hartman int jsm_uart_port_init(struct jsm_board *); 443ab4382d2SGreg Kroah-Hartman int jsm_remove_uart_port(struct jsm_board *); 444ab4382d2SGreg Kroah-Hartman void jsm_input(struct jsm_channel *ch); 445ab4382d2SGreg Kroah-Hartman void jsm_check_queue_flow_control(struct jsm_channel *ch); 446ab4382d2SGreg Kroah-Hartman 447ab4382d2SGreg Kroah-Hartman #endif 448