1*ab4382d2SGreg Kroah-Hartman /************************************************************************ 2*ab4382d2SGreg Kroah-Hartman * Copyright 2003 Digi International (www.digi.com) 3*ab4382d2SGreg Kroah-Hartman * 4*ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 IBM Corporation. All rights reserved. 5*ab4382d2SGreg Kroah-Hartman * 6*ab4382d2SGreg Kroah-Hartman * This program is free software; you can redistribute it and/or modify 7*ab4382d2SGreg Kroah-Hartman * it under the terms of the GNU General Public License as published by 8*ab4382d2SGreg Kroah-Hartman * the Free Software Foundation; either version 2, or (at your option) 9*ab4382d2SGreg Kroah-Hartman * any later version. 10*ab4382d2SGreg Kroah-Hartman * 11*ab4382d2SGreg Kroah-Hartman * This program is distributed in the hope that it will be useful, 12*ab4382d2SGreg Kroah-Hartman * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 13*ab4382d2SGreg Kroah-Hartman * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 14*ab4382d2SGreg Kroah-Hartman * PURPOSE. See the GNU General Public License for more details. 15*ab4382d2SGreg Kroah-Hartman * 16*ab4382d2SGreg Kroah-Hartman * You should have received a copy of the GNU General Public License 17*ab4382d2SGreg Kroah-Hartman * along with this program; if not, write to the Free Software 18*ab4382d2SGreg Kroah-Hartman * Foundation, Inc., 59 * Temple Place - Suite 330, Boston, 19*ab4382d2SGreg Kroah-Hartman * MA 02111-1307, USA. 20*ab4382d2SGreg Kroah-Hartman * 21*ab4382d2SGreg Kroah-Hartman * Contact Information: 22*ab4382d2SGreg Kroah-Hartman * Scott H Kilau <Scott_Kilau@digi.com> 23*ab4382d2SGreg Kroah-Hartman * Wendy Xiong <wendyx@us.ibm.com> 24*ab4382d2SGreg Kroah-Hartman * 25*ab4382d2SGreg Kroah-Hartman ***********************************************************************/ 26*ab4382d2SGreg Kroah-Hartman 27*ab4382d2SGreg Kroah-Hartman #ifndef __JSM_DRIVER_H 28*ab4382d2SGreg Kroah-Hartman #define __JSM_DRIVER_H 29*ab4382d2SGreg Kroah-Hartman 30*ab4382d2SGreg Kroah-Hartman #include <linux/kernel.h> 31*ab4382d2SGreg Kroah-Hartman #include <linux/types.h> /* To pick up the varions Linux types */ 32*ab4382d2SGreg Kroah-Hartman #include <linux/tty.h> 33*ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h> 34*ab4382d2SGreg Kroah-Hartman #include <linux/device.h> 35*ab4382d2SGreg Kroah-Hartman 36*ab4382d2SGreg Kroah-Hartman /* 37*ab4382d2SGreg Kroah-Hartman * Debugging levels can be set using debug insmod variable 38*ab4382d2SGreg Kroah-Hartman * They can also be compiled out completely. 39*ab4382d2SGreg Kroah-Hartman */ 40*ab4382d2SGreg Kroah-Hartman enum { 41*ab4382d2SGreg Kroah-Hartman DBG_INIT = 0x01, 42*ab4382d2SGreg Kroah-Hartman DBG_BASIC = 0x02, 43*ab4382d2SGreg Kroah-Hartman DBG_CORE = 0x04, 44*ab4382d2SGreg Kroah-Hartman DBG_OPEN = 0x08, 45*ab4382d2SGreg Kroah-Hartman DBG_CLOSE = 0x10, 46*ab4382d2SGreg Kroah-Hartman DBG_READ = 0x20, 47*ab4382d2SGreg Kroah-Hartman DBG_WRITE = 0x40, 48*ab4382d2SGreg Kroah-Hartman DBG_IOCTL = 0x80, 49*ab4382d2SGreg Kroah-Hartman DBG_PROC = 0x100, 50*ab4382d2SGreg Kroah-Hartman DBG_PARAM = 0x200, 51*ab4382d2SGreg Kroah-Hartman DBG_PSCAN = 0x400, 52*ab4382d2SGreg Kroah-Hartman DBG_EVENT = 0x800, 53*ab4382d2SGreg Kroah-Hartman DBG_DRAIN = 0x1000, 54*ab4382d2SGreg Kroah-Hartman DBG_MSIGS = 0x2000, 55*ab4382d2SGreg Kroah-Hartman DBG_MGMT = 0x4000, 56*ab4382d2SGreg Kroah-Hartman DBG_INTR = 0x8000, 57*ab4382d2SGreg Kroah-Hartman DBG_CARR = 0x10000, 58*ab4382d2SGreg Kroah-Hartman }; 59*ab4382d2SGreg Kroah-Hartman 60*ab4382d2SGreg Kroah-Hartman #define jsm_printk(nlevel, klevel, pdev, fmt, args...) \ 61*ab4382d2SGreg Kroah-Hartman if ((DBG_##nlevel & jsm_debug)) \ 62*ab4382d2SGreg Kroah-Hartman dev_printk(KERN_##klevel, pdev->dev, fmt, ## args) 63*ab4382d2SGreg Kroah-Hartman 64*ab4382d2SGreg Kroah-Hartman #define MAXLINES 256 65*ab4382d2SGreg Kroah-Hartman #define MAXPORTS 8 66*ab4382d2SGreg Kroah-Hartman #define MAX_STOPS_SENT 5 67*ab4382d2SGreg Kroah-Hartman 68*ab4382d2SGreg Kroah-Hartman /* Board type definitions */ 69*ab4382d2SGreg Kroah-Hartman 70*ab4382d2SGreg Kroah-Hartman #define T_NEO 0000 71*ab4382d2SGreg Kroah-Hartman #define T_CLASSIC 0001 72*ab4382d2SGreg Kroah-Hartman #define T_PCIBUS 0400 73*ab4382d2SGreg Kroah-Hartman 74*ab4382d2SGreg Kroah-Hartman /* Board State Definitions */ 75*ab4382d2SGreg Kroah-Hartman 76*ab4382d2SGreg Kroah-Hartman #define BD_RUNNING 0x0 77*ab4382d2SGreg Kroah-Hartman #define BD_REASON 0x7f 78*ab4382d2SGreg Kroah-Hartman #define BD_NOTFOUND 0x1 79*ab4382d2SGreg Kroah-Hartman #define BD_NOIOPORT 0x2 80*ab4382d2SGreg Kroah-Hartman #define BD_NOMEM 0x3 81*ab4382d2SGreg Kroah-Hartman #define BD_NOBIOS 0x4 82*ab4382d2SGreg Kroah-Hartman #define BD_NOFEP 0x5 83*ab4382d2SGreg Kroah-Hartman #define BD_FAILED 0x6 84*ab4382d2SGreg Kroah-Hartman #define BD_ALLOCATED 0x7 85*ab4382d2SGreg Kroah-Hartman #define BD_TRIBOOT 0x8 86*ab4382d2SGreg Kroah-Hartman #define BD_BADKME 0x80 87*ab4382d2SGreg Kroah-Hartman 88*ab4382d2SGreg Kroah-Hartman 89*ab4382d2SGreg Kroah-Hartman /* 4 extra for alignment play space */ 90*ab4382d2SGreg Kroah-Hartman #define WRITEBUFLEN ((4096) + 4) 91*ab4382d2SGreg Kroah-Hartman #define MYFLIPLEN N_TTY_BUF_SIZE 92*ab4382d2SGreg Kroah-Hartman 93*ab4382d2SGreg Kroah-Hartman #define JSM_VERSION "jsm: 1.2-1-INKERNEL" 94*ab4382d2SGreg Kroah-Hartman #define JSM_PARTNUM "40002438_A-INKERNEL" 95*ab4382d2SGreg Kroah-Hartman 96*ab4382d2SGreg Kroah-Hartman struct jsm_board; 97*ab4382d2SGreg Kroah-Hartman struct jsm_channel; 98*ab4382d2SGreg Kroah-Hartman 99*ab4382d2SGreg Kroah-Hartman /************************************************************************ 100*ab4382d2SGreg Kroah-Hartman * Per board operations structure * 101*ab4382d2SGreg Kroah-Hartman ************************************************************************/ 102*ab4382d2SGreg Kroah-Hartman struct board_ops { 103*ab4382d2SGreg Kroah-Hartman irq_handler_t intr; 104*ab4382d2SGreg Kroah-Hartman void (*uart_init) (struct jsm_channel *ch); 105*ab4382d2SGreg Kroah-Hartman void (*uart_off) (struct jsm_channel *ch); 106*ab4382d2SGreg Kroah-Hartman void (*param) (struct jsm_channel *ch); 107*ab4382d2SGreg Kroah-Hartman void (*assert_modem_signals) (struct jsm_channel *ch); 108*ab4382d2SGreg Kroah-Hartman void (*flush_uart_write) (struct jsm_channel *ch); 109*ab4382d2SGreg Kroah-Hartman void (*flush_uart_read) (struct jsm_channel *ch); 110*ab4382d2SGreg Kroah-Hartman void (*disable_receiver) (struct jsm_channel *ch); 111*ab4382d2SGreg Kroah-Hartman void (*enable_receiver) (struct jsm_channel *ch); 112*ab4382d2SGreg Kroah-Hartman void (*send_break) (struct jsm_channel *ch); 113*ab4382d2SGreg Kroah-Hartman void (*clear_break) (struct jsm_channel *ch, int); 114*ab4382d2SGreg Kroah-Hartman void (*send_start_character) (struct jsm_channel *ch); 115*ab4382d2SGreg Kroah-Hartman void (*send_stop_character) (struct jsm_channel *ch); 116*ab4382d2SGreg Kroah-Hartman void (*copy_data_from_queue_to_uart) (struct jsm_channel *ch); 117*ab4382d2SGreg Kroah-Hartman u32 (*get_uart_bytes_left) (struct jsm_channel *ch); 118*ab4382d2SGreg Kroah-Hartman void (*send_immediate_char) (struct jsm_channel *ch, unsigned char); 119*ab4382d2SGreg Kroah-Hartman }; 120*ab4382d2SGreg Kroah-Hartman 121*ab4382d2SGreg Kroah-Hartman 122*ab4382d2SGreg Kroah-Hartman /* 123*ab4382d2SGreg Kroah-Hartman * Per-board information 124*ab4382d2SGreg Kroah-Hartman */ 125*ab4382d2SGreg Kroah-Hartman struct jsm_board 126*ab4382d2SGreg Kroah-Hartman { 127*ab4382d2SGreg Kroah-Hartman int boardnum; /* Board number: 0-32 */ 128*ab4382d2SGreg Kroah-Hartman 129*ab4382d2SGreg Kroah-Hartman int type; /* Type of board */ 130*ab4382d2SGreg Kroah-Hartman u8 rev; /* PCI revision ID */ 131*ab4382d2SGreg Kroah-Hartman struct pci_dev *pci_dev; 132*ab4382d2SGreg Kroah-Hartman u32 maxports; /* MAX ports this board can handle */ 133*ab4382d2SGreg Kroah-Hartman 134*ab4382d2SGreg Kroah-Hartman spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and 135*ab4382d2SGreg Kroah-Hartman * the interrupt routine from each other. 136*ab4382d2SGreg Kroah-Hartman */ 137*ab4382d2SGreg Kroah-Hartman 138*ab4382d2SGreg Kroah-Hartman u32 nasync; /* Number of ports on card */ 139*ab4382d2SGreg Kroah-Hartman 140*ab4382d2SGreg Kroah-Hartman u32 irq; /* Interrupt request number */ 141*ab4382d2SGreg Kroah-Hartman 142*ab4382d2SGreg Kroah-Hartman u64 membase; /* Start of base memory of the card */ 143*ab4382d2SGreg Kroah-Hartman u64 membase_end; /* End of base memory of the card */ 144*ab4382d2SGreg Kroah-Hartman 145*ab4382d2SGreg Kroah-Hartman u8 __iomem *re_map_membase;/* Remapped memory of the card */ 146*ab4382d2SGreg Kroah-Hartman 147*ab4382d2SGreg Kroah-Hartman u64 iobase; /* Start of io base of the card */ 148*ab4382d2SGreg Kroah-Hartman u64 iobase_end; /* End of io base of the card */ 149*ab4382d2SGreg Kroah-Hartman 150*ab4382d2SGreg Kroah-Hartman u32 bd_uart_offset; /* Space between each UART */ 151*ab4382d2SGreg Kroah-Hartman 152*ab4382d2SGreg Kroah-Hartman struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */ 153*ab4382d2SGreg Kroah-Hartman char *flipbuf; /* Our flip buffer, alloced if board is found */ 154*ab4382d2SGreg Kroah-Hartman 155*ab4382d2SGreg Kroah-Hartman u32 bd_dividend; /* Board/UARTs specific dividend */ 156*ab4382d2SGreg Kroah-Hartman 157*ab4382d2SGreg Kroah-Hartman struct board_ops *bd_ops; 158*ab4382d2SGreg Kroah-Hartman 159*ab4382d2SGreg Kroah-Hartman struct list_head jsm_board_entry; 160*ab4382d2SGreg Kroah-Hartman }; 161*ab4382d2SGreg Kroah-Hartman 162*ab4382d2SGreg Kroah-Hartman /************************************************************************ 163*ab4382d2SGreg Kroah-Hartman * Device flag definitions for ch_flags. 164*ab4382d2SGreg Kroah-Hartman ************************************************************************/ 165*ab4382d2SGreg Kroah-Hartman #define CH_PRON 0x0001 /* Printer on string */ 166*ab4382d2SGreg Kroah-Hartman #define CH_STOP 0x0002 /* Output is stopped */ 167*ab4382d2SGreg Kroah-Hartman #define CH_STOPI 0x0004 /* Input is stopped */ 168*ab4382d2SGreg Kroah-Hartman #define CH_CD 0x0008 /* Carrier is present */ 169*ab4382d2SGreg Kroah-Hartman #define CH_FCAR 0x0010 /* Carrier forced on */ 170*ab4382d2SGreg Kroah-Hartman #define CH_HANGUP 0x0020 /* Hangup received */ 171*ab4382d2SGreg Kroah-Hartman 172*ab4382d2SGreg Kroah-Hartman #define CH_RECEIVER_OFF 0x0040 /* Receiver is off */ 173*ab4382d2SGreg Kroah-Hartman #define CH_OPENING 0x0080 /* Port in fragile open state */ 174*ab4382d2SGreg Kroah-Hartman #define CH_CLOSING 0x0100 /* Port in fragile close state */ 175*ab4382d2SGreg Kroah-Hartman #define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */ 176*ab4382d2SGreg Kroah-Hartman #define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */ 177*ab4382d2SGreg Kroah-Hartman #define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */ 178*ab4382d2SGreg Kroah-Hartman #define CH_BREAK_SENDING 0x1000 /* Break is being sent */ 179*ab4382d2SGreg Kroah-Hartman #define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */ 180*ab4382d2SGreg Kroah-Hartman #define CH_FLIPBUF_IN_USE 0x4000 /* Channel's flipbuf is in use */ 181*ab4382d2SGreg Kroah-Hartman #define CH_BAUD0 0x08000 /* Used for checking B0 transitions */ 182*ab4382d2SGreg Kroah-Hartman 183*ab4382d2SGreg Kroah-Hartman /* Our Read/Error/Write queue sizes */ 184*ab4382d2SGreg Kroah-Hartman #define RQUEUEMASK 0x1FFF /* 8 K - 1 */ 185*ab4382d2SGreg Kroah-Hartman #define EQUEUEMASK 0x1FFF /* 8 K - 1 */ 186*ab4382d2SGreg Kroah-Hartman #define WQUEUEMASK 0x0FFF /* 4 K - 1 */ 187*ab4382d2SGreg Kroah-Hartman #define RQUEUESIZE (RQUEUEMASK + 1) 188*ab4382d2SGreg Kroah-Hartman #define EQUEUESIZE RQUEUESIZE 189*ab4382d2SGreg Kroah-Hartman #define WQUEUESIZE (WQUEUEMASK + 1) 190*ab4382d2SGreg Kroah-Hartman 191*ab4382d2SGreg Kroah-Hartman 192*ab4382d2SGreg Kroah-Hartman /************************************************************************ 193*ab4382d2SGreg Kroah-Hartman * Channel information structure. 194*ab4382d2SGreg Kroah-Hartman ************************************************************************/ 195*ab4382d2SGreg Kroah-Hartman struct jsm_channel { 196*ab4382d2SGreg Kroah-Hartman struct uart_port uart_port; 197*ab4382d2SGreg Kroah-Hartman struct jsm_board *ch_bd; /* Board structure pointer */ 198*ab4382d2SGreg Kroah-Hartman 199*ab4382d2SGreg Kroah-Hartman spinlock_t ch_lock; /* provide for serialization */ 200*ab4382d2SGreg Kroah-Hartman wait_queue_head_t ch_flags_wait; 201*ab4382d2SGreg Kroah-Hartman 202*ab4382d2SGreg Kroah-Hartman u32 ch_portnum; /* Port number, 0 offset. */ 203*ab4382d2SGreg Kroah-Hartman u32 ch_open_count; /* open count */ 204*ab4382d2SGreg Kroah-Hartman u32 ch_flags; /* Channel flags */ 205*ab4382d2SGreg Kroah-Hartman 206*ab4382d2SGreg Kroah-Hartman u64 ch_close_delay; /* How long we should drop RTS/DTR for */ 207*ab4382d2SGreg Kroah-Hartman 208*ab4382d2SGreg Kroah-Hartman tcflag_t ch_c_iflag; /* channel iflags */ 209*ab4382d2SGreg Kroah-Hartman tcflag_t ch_c_cflag; /* channel cflags */ 210*ab4382d2SGreg Kroah-Hartman tcflag_t ch_c_oflag; /* channel oflags */ 211*ab4382d2SGreg Kroah-Hartman tcflag_t ch_c_lflag; /* channel lflags */ 212*ab4382d2SGreg Kroah-Hartman u8 ch_stopc; /* Stop character */ 213*ab4382d2SGreg Kroah-Hartman u8 ch_startc; /* Start character */ 214*ab4382d2SGreg Kroah-Hartman 215*ab4382d2SGreg Kroah-Hartman u8 ch_mostat; /* FEP output modem status */ 216*ab4382d2SGreg Kroah-Hartman u8 ch_mistat; /* FEP input modem status */ 217*ab4382d2SGreg Kroah-Hartman 218*ab4382d2SGreg Kroah-Hartman struct neo_uart_struct __iomem *ch_neo_uart; /* Pointer to the "mapped" UART struct */ 219*ab4382d2SGreg Kroah-Hartman u8 ch_cached_lsr; /* Cached value of the LSR register */ 220*ab4382d2SGreg Kroah-Hartman 221*ab4382d2SGreg Kroah-Hartman u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */ 222*ab4382d2SGreg Kroah-Hartman u16 ch_r_head; /* Head location of the read queue */ 223*ab4382d2SGreg Kroah-Hartman u16 ch_r_tail; /* Tail location of the read queue */ 224*ab4382d2SGreg Kroah-Hartman 225*ab4382d2SGreg Kroah-Hartman u8 *ch_equeue; /* Our error queue buffer - malloc'ed */ 226*ab4382d2SGreg Kroah-Hartman u16 ch_e_head; /* Head location of the error queue */ 227*ab4382d2SGreg Kroah-Hartman u16 ch_e_tail; /* Tail location of the error queue */ 228*ab4382d2SGreg Kroah-Hartman 229*ab4382d2SGreg Kroah-Hartman u8 *ch_wqueue; /* Our write queue buffer - malloc'ed */ 230*ab4382d2SGreg Kroah-Hartman u16 ch_w_head; /* Head location of the write queue */ 231*ab4382d2SGreg Kroah-Hartman u16 ch_w_tail; /* Tail location of the write queue */ 232*ab4382d2SGreg Kroah-Hartman 233*ab4382d2SGreg Kroah-Hartman u64 ch_rxcount; /* total of data received so far */ 234*ab4382d2SGreg Kroah-Hartman u64 ch_txcount; /* total of data transmitted so far */ 235*ab4382d2SGreg Kroah-Hartman 236*ab4382d2SGreg Kroah-Hartman u8 ch_r_tlevel; /* Receive Trigger level */ 237*ab4382d2SGreg Kroah-Hartman u8 ch_t_tlevel; /* Transmit Trigger level */ 238*ab4382d2SGreg Kroah-Hartman 239*ab4382d2SGreg Kroah-Hartman u8 ch_r_watermark; /* Receive Watermark */ 240*ab4382d2SGreg Kroah-Hartman 241*ab4382d2SGreg Kroah-Hartman 242*ab4382d2SGreg Kroah-Hartman u32 ch_stops_sent; /* How many times I have sent a stop character 243*ab4382d2SGreg Kroah-Hartman * to try to stop the other guy sending. 244*ab4382d2SGreg Kroah-Hartman */ 245*ab4382d2SGreg Kroah-Hartman u64 ch_err_parity; /* Count of parity errors on channel */ 246*ab4382d2SGreg Kroah-Hartman u64 ch_err_frame; /* Count of framing errors on channel */ 247*ab4382d2SGreg Kroah-Hartman u64 ch_err_break; /* Count of breaks on channel */ 248*ab4382d2SGreg Kroah-Hartman u64 ch_err_overrun; /* Count of overruns on channel */ 249*ab4382d2SGreg Kroah-Hartman 250*ab4382d2SGreg Kroah-Hartman u64 ch_xon_sends; /* Count of xons transmitted */ 251*ab4382d2SGreg Kroah-Hartman u64 ch_xoff_sends; /* Count of xoffs transmitted */ 252*ab4382d2SGreg Kroah-Hartman }; 253*ab4382d2SGreg Kroah-Hartman 254*ab4382d2SGreg Kroah-Hartman 255*ab4382d2SGreg Kroah-Hartman /************************************************************************ 256*ab4382d2SGreg Kroah-Hartman * Per channel/port NEO UART structure * 257*ab4382d2SGreg Kroah-Hartman ************************************************************************ 258*ab4382d2SGreg Kroah-Hartman * Base Structure Entries Usage Meanings to Host * 259*ab4382d2SGreg Kroah-Hartman * * 260*ab4382d2SGreg Kroah-Hartman * W = read write R = read only * 261*ab4382d2SGreg Kroah-Hartman * U = Unused. * 262*ab4382d2SGreg Kroah-Hartman ************************************************************************/ 263*ab4382d2SGreg Kroah-Hartman 264*ab4382d2SGreg Kroah-Hartman struct neo_uart_struct { 265*ab4382d2SGreg Kroah-Hartman u8 txrx; /* WR RHR/THR - Holding Reg */ 266*ab4382d2SGreg Kroah-Hartman u8 ier; /* WR IER - Interrupt Enable Reg */ 267*ab4382d2SGreg Kroah-Hartman u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ 268*ab4382d2SGreg Kroah-Hartman u8 lcr; /* WR LCR - Line Control Reg */ 269*ab4382d2SGreg Kroah-Hartman u8 mcr; /* WR MCR - Modem Control Reg */ 270*ab4382d2SGreg Kroah-Hartman u8 lsr; /* WR LSR - Line Status Reg */ 271*ab4382d2SGreg Kroah-Hartman u8 msr; /* WR MSR - Modem Status Reg */ 272*ab4382d2SGreg Kroah-Hartman u8 spr; /* WR SPR - Scratch Pad Reg */ 273*ab4382d2SGreg Kroah-Hartman u8 fctr; /* WR FCTR - Feature Control Reg */ 274*ab4382d2SGreg Kroah-Hartman u8 efr; /* WR EFR - Enhanced Function Reg */ 275*ab4382d2SGreg Kroah-Hartman u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */ 276*ab4382d2SGreg Kroah-Hartman u8 rfifo; /* WR RXCNT/RXTRG - Recieve FIFO Reg */ 277*ab4382d2SGreg Kroah-Hartman u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */ 278*ab4382d2SGreg Kroah-Hartman u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */ 279*ab4382d2SGreg Kroah-Hartman u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */ 280*ab4382d2SGreg Kroah-Hartman u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */ 281*ab4382d2SGreg Kroah-Hartman 282*ab4382d2SGreg Kroah-Hartman u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */ 283*ab4382d2SGreg Kroah-Hartman u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */ 284*ab4382d2SGreg Kroah-Hartman u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */ 285*ab4382d2SGreg Kroah-Hartman u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */ 286*ab4382d2SGreg Kroah-Hartman }; 287*ab4382d2SGreg Kroah-Hartman 288*ab4382d2SGreg Kroah-Hartman /* Where to read the extended interrupt register (32bits instead of 8bits) */ 289*ab4382d2SGreg Kroah-Hartman #define UART_17158_POLL_ADDR_OFFSET 0x80 290*ab4382d2SGreg Kroah-Hartman 291*ab4382d2SGreg Kroah-Hartman /* 292*ab4382d2SGreg Kroah-Hartman * These are the redefinitions for the FCTR on the XR17C158, since 293*ab4382d2SGreg Kroah-Hartman * Exar made them different than their earlier design. (XR16C854) 294*ab4382d2SGreg Kroah-Hartman */ 295*ab4382d2SGreg Kroah-Hartman 296*ab4382d2SGreg Kroah-Hartman /* These are only applicable when table D is selected */ 297*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_NODELAY 0x00 298*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_4DELAY 0x01 299*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_6DELAY 0x02 300*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_8DELAY 0x03 301*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_12DELAY 0x12 302*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_16DELAY 0x05 303*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_20DELAY 0x13 304*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_24DELAY 0x06 305*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_28DELAY 0x14 306*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_32DELAY 0x07 307*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_36DELAY 0x16 308*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_40DELAY 0x08 309*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_44DELAY 0x09 310*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_48DELAY 0x10 311*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_52DELAY 0x11 312*ab4382d2SGreg Kroah-Hartman 313*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RTS_IRDA 0x10 314*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_RS485 0x20 315*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_TRGA 0x00 316*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_TRGB 0x40 317*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_TRGC 0x80 318*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_TRGD 0xC0 319*ab4382d2SGreg Kroah-Hartman 320*ab4382d2SGreg Kroah-Hartman /* 17158 trigger table selects.. */ 321*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_BIT6 0x40 322*ab4382d2SGreg Kroah-Hartman #define UART_17158_FCTR_BIT7 0x80 323*ab4382d2SGreg Kroah-Hartman 324*ab4382d2SGreg Kroah-Hartman /* 17158 TX/RX memmapped buffer offsets */ 325*ab4382d2SGreg Kroah-Hartman #define UART_17158_RX_FIFOSIZE 64 326*ab4382d2SGreg Kroah-Hartman #define UART_17158_TX_FIFOSIZE 64 327*ab4382d2SGreg Kroah-Hartman 328*ab4382d2SGreg Kroah-Hartman /* 17158 Extended IIR's */ 329*ab4382d2SGreg Kroah-Hartman #define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 330*ab4382d2SGreg Kroah-Hartman #define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */ 331*ab4382d2SGreg Kroah-Hartman #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */ 332*ab4382d2SGreg Kroah-Hartman #define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */ 333*ab4382d2SGreg Kroah-Hartman 334*ab4382d2SGreg Kroah-Hartman /* 335*ab4382d2SGreg Kroah-Hartman * These are the extended interrupts that get sent 336*ab4382d2SGreg Kroah-Hartman * back to us from the UART's 32bit interrupt register 337*ab4382d2SGreg Kroah-Hartman */ 338*ab4382d2SGreg Kroah-Hartman #define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */ 339*ab4382d2SGreg Kroah-Hartman #define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */ 340*ab4382d2SGreg Kroah-Hartman #define UART_17158_TXRDY 0x3 /* TX Ready */ 341*ab4382d2SGreg Kroah-Hartman #define UART_17158_MSR 0x4 /* Modem State Change */ 342*ab4382d2SGreg Kroah-Hartman #define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */ 343*ab4382d2SGreg Kroah-Hartman #define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */ 344*ab4382d2SGreg Kroah-Hartman 345*ab4382d2SGreg Kroah-Hartman /* 346*ab4382d2SGreg Kroah-Hartman * These are the EXTENDED definitions for the 17C158's Interrupt 347*ab4382d2SGreg Kroah-Hartman * Enable Register. 348*ab4382d2SGreg Kroah-Hartman */ 349*ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */ 350*ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 351*ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 352*ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 353*ab4382d2SGreg Kroah-Hartman #define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 354*ab4382d2SGreg Kroah-Hartman 355*ab4382d2SGreg Kroah-Hartman #define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 356*ab4382d2SGreg Kroah-Hartman #define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 357*ab4382d2SGreg Kroah-Hartman 358*ab4382d2SGreg Kroah-Hartman #define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */ 359*ab4382d2SGreg Kroah-Hartman #define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 360*ab4382d2SGreg Kroah-Hartman #define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 361*ab4382d2SGreg Kroah-Hartman #define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 362*ab4382d2SGreg Kroah-Hartman 363*ab4382d2SGreg Kroah-Hartman #define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI" 364*ab4382d2SGreg Kroah-Hartman #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator" 365*ab4382d2SGreg Kroah-Hartman #define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI" 366*ab4382d2SGreg Kroah-Hartman #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator" 367*ab4382d2SGreg Kroah-Hartman #define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM" 368*ab4382d2SGreg Kroah-Hartman 369*ab4382d2SGreg Kroah-Hartman /* 370*ab4382d2SGreg Kroah-Hartman * Our Global Variables. 371*ab4382d2SGreg Kroah-Hartman */ 372*ab4382d2SGreg Kroah-Hartman extern struct uart_driver jsm_uart_driver; 373*ab4382d2SGreg Kroah-Hartman extern struct board_ops jsm_neo_ops; 374*ab4382d2SGreg Kroah-Hartman extern int jsm_debug; 375*ab4382d2SGreg Kroah-Hartman 376*ab4382d2SGreg Kroah-Hartman /************************************************************************* 377*ab4382d2SGreg Kroah-Hartman * 378*ab4382d2SGreg Kroah-Hartman * Prototypes for non-static functions used in more than one module 379*ab4382d2SGreg Kroah-Hartman * 380*ab4382d2SGreg Kroah-Hartman *************************************************************************/ 381*ab4382d2SGreg Kroah-Hartman int jsm_tty_write(struct uart_port *port); 382*ab4382d2SGreg Kroah-Hartman int jsm_tty_init(struct jsm_board *); 383*ab4382d2SGreg Kroah-Hartman int jsm_uart_port_init(struct jsm_board *); 384*ab4382d2SGreg Kroah-Hartman int jsm_remove_uart_port(struct jsm_board *); 385*ab4382d2SGreg Kroah-Hartman void jsm_input(struct jsm_channel *ch); 386*ab4382d2SGreg Kroah-Hartman void jsm_check_queue_flow_control(struct jsm_channel *ch); 387*ab4382d2SGreg Kroah-Hartman 388*ab4382d2SGreg Kroah-Hartman #endif 389