1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Motorola/Freescale IMX serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Author: Sascha Hauer <sascha@saschahauer.de> 8 * Copyright (C) 2004 Pengutronix 9 */ 10 11 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12 #define SUPPORT_SYSRQ 13 #endif 14 15 #include <linux/module.h> 16 #include <linux/ioport.h> 17 #include <linux/init.h> 18 #include <linux/console.h> 19 #include <linux/sysrq.h> 20 #include <linux/platform_device.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/serial.h> 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/rational.h> 29 #include <linux/slab.h> 30 #include <linux/of.h> 31 #include <linux/of_device.h> 32 #include <linux/io.h> 33 #include <linux/dma-mapping.h> 34 35 #include <asm/irq.h> 36 #include <linux/platform_data/serial-imx.h> 37 #include <linux/platform_data/dma-imx.h> 38 39 #include "serial_mctrl_gpio.h" 40 41 /* Register definitions */ 42 #define URXD0 0x0 /* Receiver Register */ 43 #define URTX0 0x40 /* Transmitter Register */ 44 #define UCR1 0x80 /* Control Register 1 */ 45 #define UCR2 0x84 /* Control Register 2 */ 46 #define UCR3 0x88 /* Control Register 3 */ 47 #define UCR4 0x8c /* Control Register 4 */ 48 #define UFCR 0x90 /* FIFO Control Register */ 49 #define USR1 0x94 /* Status Register 1 */ 50 #define USR2 0x98 /* Status Register 2 */ 51 #define UESC 0x9c /* Escape Character Register */ 52 #define UTIM 0xa0 /* Escape Timer Register */ 53 #define UBIR 0xa4 /* BRM Incremental Register */ 54 #define UBMR 0xa8 /* BRM Modulator Register */ 55 #define UBRC 0xac /* Baud Rate Count Register */ 56 #define IMX21_ONEMS 0xb0 /* One Millisecond register */ 57 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ 58 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ 59 60 /* UART Control Register Bit Fields.*/ 61 #define URXD_DUMMY_READ (1<<16) 62 #define URXD_CHARRDY (1<<15) 63 #define URXD_ERR (1<<14) 64 #define URXD_OVRRUN (1<<13) 65 #define URXD_FRMERR (1<<12) 66 #define URXD_BRK (1<<11) 67 #define URXD_PRERR (1<<10) 68 #define URXD_RX_DATA (0xFF<<0) 69 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ 70 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 71 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 72 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 73 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ 74 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 75 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */ 76 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 77 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 78 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 79 #define UCR1_SNDBRK (1<<4) /* Send break */ 80 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */ 81 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ 82 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ 83 #define UCR1_DOZE (1<<1) /* Doze */ 84 #define UCR1_UARTEN (1<<0) /* UART enabled */ 85 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ 86 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ 87 #define UCR2_CTSC (1<<13) /* CTS pin control */ 88 #define UCR2_CTS (1<<12) /* Clear to send */ 89 #define UCR2_ESCEN (1<<11) /* Escape enable */ 90 #define UCR2_PREN (1<<8) /* Parity enable */ 91 #define UCR2_PROE (1<<7) /* Parity odd/even */ 92 #define UCR2_STPB (1<<6) /* Stop */ 93 #define UCR2_WS (1<<5) /* Word size */ 94 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ 95 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ 96 #define UCR2_TXEN (1<<2) /* Transmitter enabled */ 97 #define UCR2_RXEN (1<<1) /* Receiver enabled */ 98 #define UCR2_SRST (1<<0) /* SW reset */ 99 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ 100 #define UCR3_PARERREN (1<<12) /* Parity enable */ 101 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ 102 #define UCR3_DSR (1<<10) /* Data set ready */ 103 #define UCR3_DCD (1<<9) /* Data carrier detect */ 104 #define UCR3_RI (1<<8) /* Ring indicator */ 105 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ 106 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 107 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 108 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 109 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */ 110 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ 111 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 112 #define UCR3_BPEN (1<<0) /* Preset registers enable */ 113 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ 114 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ 115 #define UCR4_INVR (1<<9) /* Inverted infrared reception */ 116 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ 117 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ 118 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ 119 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ 120 #define UCR4_IRSC (1<<5) /* IR special case */ 121 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ 122 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ 123 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ 124 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ 125 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ 126 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ 127 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ 128 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) 129 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ 130 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ 131 #define USR1_RTSS (1<<14) /* RTS pin status */ 132 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ 133 #define USR1_RTSD (1<<12) /* RTS delta */ 134 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ 135 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ 136 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ 137 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */ 138 #define USR1_DTRD (1<<7) /* DTR Delta */ 139 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ 140 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ 141 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ 142 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ 143 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ 144 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ 145 #define USR2_IDLE (1<<12) /* Idle condition */ 146 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ 147 #define USR2_RIIN (1<<9) /* Ring Indicator Input */ 148 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ 149 #define USR2_WAKE (1<<7) /* Wake */ 150 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ 151 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ 152 #define USR2_TXDC (1<<3) /* Transmitter complete */ 153 #define USR2_BRCD (1<<2) /* Break condition */ 154 #define USR2_ORE (1<<1) /* Overrun error */ 155 #define USR2_RDR (1<<0) /* Recv data ready */ 156 #define UTS_FRCPERR (1<<13) /* Force parity error */ 157 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 158 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 159 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 160 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 161 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 162 #define UTS_SOFTRST (1<<0) /* Software reset */ 163 164 /* We've been assigned a range on the "Low-density serial ports" major */ 165 #define SERIAL_IMX_MAJOR 207 166 #define MINOR_START 16 167 #define DEV_NAME "ttymxc" 168 169 /* 170 * This determines how often we check the modem status signals 171 * for any change. They generally aren't connected to an IRQ 172 * so we have to poll them. We also check immediately before 173 * filling the TX fifo incase CTS has been dropped. 174 */ 175 #define MCTRL_TIMEOUT (250*HZ/1000) 176 177 #define DRIVER_NAME "IMX-uart" 178 179 #define UART_NR 8 180 181 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */ 182 enum imx_uart_type { 183 IMX1_UART, 184 IMX21_UART, 185 IMX53_UART, 186 IMX6Q_UART, 187 }; 188 189 /* device type dependent stuff */ 190 struct imx_uart_data { 191 unsigned uts_reg; 192 enum imx_uart_type devtype; 193 }; 194 195 struct imx_port { 196 struct uart_port port; 197 struct timer_list timer; 198 unsigned int old_status; 199 unsigned int have_rtscts:1; 200 unsigned int have_rtsgpio:1; 201 unsigned int dte_mode:1; 202 struct clk *clk_ipg; 203 struct clk *clk_per; 204 const struct imx_uart_data *devdata; 205 206 struct mctrl_gpios *gpios; 207 208 /* shadow registers */ 209 unsigned int ucr1; 210 unsigned int ucr2; 211 unsigned int ucr3; 212 unsigned int ucr4; 213 unsigned int ufcr; 214 215 /* DMA fields */ 216 unsigned int dma_is_enabled:1; 217 unsigned int dma_is_rxing:1; 218 unsigned int dma_is_txing:1; 219 struct dma_chan *dma_chan_rx, *dma_chan_tx; 220 struct scatterlist rx_sgl, tx_sgl[2]; 221 void *rx_buf; 222 struct circ_buf rx_ring; 223 unsigned int rx_periods; 224 dma_cookie_t rx_cookie; 225 unsigned int tx_bytes; 226 unsigned int dma_tx_nents; 227 unsigned int saved_reg[10]; 228 bool context_saved; 229 }; 230 231 struct imx_port_ucrs { 232 unsigned int ucr1; 233 unsigned int ucr2; 234 unsigned int ucr3; 235 }; 236 237 static struct imx_uart_data imx_uart_devdata[] = { 238 [IMX1_UART] = { 239 .uts_reg = IMX1_UTS, 240 .devtype = IMX1_UART, 241 }, 242 [IMX21_UART] = { 243 .uts_reg = IMX21_UTS, 244 .devtype = IMX21_UART, 245 }, 246 [IMX53_UART] = { 247 .uts_reg = IMX21_UTS, 248 .devtype = IMX53_UART, 249 }, 250 [IMX6Q_UART] = { 251 .uts_reg = IMX21_UTS, 252 .devtype = IMX6Q_UART, 253 }, 254 }; 255 256 static const struct platform_device_id imx_uart_devtype[] = { 257 { 258 .name = "imx1-uart", 259 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], 260 }, { 261 .name = "imx21-uart", 262 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], 263 }, { 264 .name = "imx53-uart", 265 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART], 266 }, { 267 .name = "imx6q-uart", 268 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], 269 }, { 270 /* sentinel */ 271 } 272 }; 273 MODULE_DEVICE_TABLE(platform, imx_uart_devtype); 274 275 static const struct of_device_id imx_uart_dt_ids[] = { 276 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 277 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 280 { /* sentinel */ } 281 }; 282 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); 283 284 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) 285 { 286 switch (offset) { 287 case UCR1: 288 sport->ucr1 = val; 289 break; 290 case UCR2: 291 sport->ucr2 = val; 292 break; 293 case UCR3: 294 sport->ucr3 = val; 295 break; 296 case UCR4: 297 sport->ucr4 = val; 298 break; 299 case UFCR: 300 sport->ufcr = val; 301 break; 302 default: 303 break; 304 } 305 writel(val, sport->port.membase + offset); 306 } 307 308 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) 309 { 310 switch (offset) { 311 case UCR1: 312 return sport->ucr1; 313 break; 314 case UCR2: 315 /* 316 * UCR2_SRST is the only bit in the cached registers that might 317 * differ from the value that was last written. As it only 318 * automatically becomes one after being cleared, reread 319 * conditionally. 320 */ 321 if (!(sport->ucr2 & UCR2_SRST)) 322 sport->ucr2 = readl(sport->port.membase + offset); 323 return sport->ucr2; 324 break; 325 case UCR3: 326 return sport->ucr3; 327 break; 328 case UCR4: 329 return sport->ucr4; 330 break; 331 case UFCR: 332 return sport->ufcr; 333 break; 334 default: 335 return readl(sport->port.membase + offset); 336 } 337 } 338 339 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) 340 { 341 return sport->devdata->uts_reg; 342 } 343 344 static inline int imx_uart_is_imx1(struct imx_port *sport) 345 { 346 return sport->devdata->devtype == IMX1_UART; 347 } 348 349 static inline int imx_uart_is_imx21(struct imx_port *sport) 350 { 351 return sport->devdata->devtype == IMX21_UART; 352 } 353 354 static inline int imx_uart_is_imx53(struct imx_port *sport) 355 { 356 return sport->devdata->devtype == IMX53_UART; 357 } 358 359 static inline int imx_uart_is_imx6q(struct imx_port *sport) 360 { 361 return sport->devdata->devtype == IMX6Q_UART; 362 } 363 /* 364 * Save and restore functions for UCR1, UCR2 and UCR3 registers 365 */ 366 #if defined(CONFIG_SERIAL_IMX_CONSOLE) 367 static void imx_uart_ucrs_save(struct imx_port *sport, 368 struct imx_port_ucrs *ucr) 369 { 370 /* save control registers */ 371 ucr->ucr1 = imx_uart_readl(sport, UCR1); 372 ucr->ucr2 = imx_uart_readl(sport, UCR2); 373 ucr->ucr3 = imx_uart_readl(sport, UCR3); 374 } 375 376 static void imx_uart_ucrs_restore(struct imx_port *sport, 377 struct imx_port_ucrs *ucr) 378 { 379 /* restore control registers */ 380 imx_uart_writel(sport, ucr->ucr1, UCR1); 381 imx_uart_writel(sport, ucr->ucr2, UCR2); 382 imx_uart_writel(sport, ucr->ucr3, UCR3); 383 } 384 #endif 385 386 /* called with port.lock taken and irqs caller dependent */ 387 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) 388 { 389 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS); 390 391 sport->port.mctrl |= TIOCM_RTS; 392 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 393 } 394 395 /* called with port.lock taken and irqs caller dependent */ 396 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) 397 { 398 *ucr2 &= ~UCR2_CTSC; 399 *ucr2 |= UCR2_CTS; 400 401 sport->port.mctrl &= ~TIOCM_RTS; 402 mctrl_gpio_set(sport->gpios, sport->port.mctrl); 403 } 404 405 /* called with port.lock taken and irqs off */ 406 static void imx_uart_start_rx(struct uart_port *port) 407 { 408 struct imx_port *sport = (struct imx_port *)port; 409 unsigned int ucr1, ucr2; 410 411 ucr1 = imx_uart_readl(sport, UCR1); 412 ucr2 = imx_uart_readl(sport, UCR2); 413 414 ucr2 |= UCR2_RXEN; 415 416 if (sport->dma_is_enabled) { 417 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN; 418 } else { 419 ucr1 |= UCR1_RRDYEN; 420 ucr2 |= UCR2_ATEN; 421 } 422 423 /* Write UCR2 first as it includes RXEN */ 424 imx_uart_writel(sport, ucr2, UCR2); 425 imx_uart_writel(sport, ucr1, UCR1); 426 } 427 428 /* called with port.lock taken and irqs off */ 429 static void imx_uart_stop_tx(struct uart_port *port) 430 { 431 struct imx_port *sport = (struct imx_port *)port; 432 u32 ucr1; 433 434 /* 435 * We are maybe in the SMP context, so if the DMA TX thread is running 436 * on other cpu, we have to wait for it to finish. 437 */ 438 if (sport->dma_is_txing) 439 return; 440 441 ucr1 = imx_uart_readl(sport, UCR1); 442 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); 443 444 /* in rs485 mode disable transmitter if shifter is empty */ 445 if (port->rs485.flags & SER_RS485_ENABLED && 446 imx_uart_readl(sport, USR2) & USR2_TXDC) { 447 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4; 448 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 449 imx_uart_rts_active(sport, &ucr2); 450 else 451 imx_uart_rts_inactive(sport, &ucr2); 452 imx_uart_writel(sport, ucr2, UCR2); 453 454 imx_uart_start_rx(port); 455 456 ucr4 = imx_uart_readl(sport, UCR4); 457 ucr4 &= ~UCR4_TCEN; 458 imx_uart_writel(sport, ucr4, UCR4); 459 } 460 } 461 462 /* called with port.lock taken and irqs off */ 463 static void imx_uart_stop_rx(struct uart_port *port) 464 { 465 struct imx_port *sport = (struct imx_port *)port; 466 u32 ucr1, ucr2; 467 468 ucr1 = imx_uart_readl(sport, UCR1); 469 ucr2 = imx_uart_readl(sport, UCR2); 470 471 if (sport->dma_is_enabled) { 472 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN); 473 } else { 474 ucr1 &= ~UCR1_RRDYEN; 475 ucr2 &= ~UCR2_ATEN; 476 } 477 imx_uart_writel(sport, ucr1, UCR1); 478 479 ucr2 &= ~UCR2_RXEN; 480 imx_uart_writel(sport, ucr2, UCR2); 481 } 482 483 /* called with port.lock taken and irqs off */ 484 static void imx_uart_enable_ms(struct uart_port *port) 485 { 486 struct imx_port *sport = (struct imx_port *)port; 487 488 mod_timer(&sport->timer, jiffies); 489 490 mctrl_gpio_enable_ms(sport->gpios); 491 } 492 493 static void imx_uart_dma_tx(struct imx_port *sport); 494 495 /* called with port.lock taken and irqs off */ 496 static inline void imx_uart_transmit_buffer(struct imx_port *sport) 497 { 498 struct circ_buf *xmit = &sport->port.state->xmit; 499 500 if (sport->port.x_char) { 501 /* Send next char */ 502 imx_uart_writel(sport, sport->port.x_char, URTX0); 503 sport->port.icount.tx++; 504 sport->port.x_char = 0; 505 return; 506 } 507 508 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 509 imx_uart_stop_tx(&sport->port); 510 return; 511 } 512 513 if (sport->dma_is_enabled) { 514 u32 ucr1; 515 /* 516 * We've just sent a X-char Ensure the TX DMA is enabled 517 * and the TX IRQ is disabled. 518 **/ 519 ucr1 = imx_uart_readl(sport, UCR1); 520 ucr1 &= ~UCR1_TRDYEN; 521 if (sport->dma_is_txing) { 522 ucr1 |= UCR1_TXDMAEN; 523 imx_uart_writel(sport, ucr1, UCR1); 524 } else { 525 imx_uart_writel(sport, ucr1, UCR1); 526 imx_uart_dma_tx(sport); 527 } 528 529 return; 530 } 531 532 while (!uart_circ_empty(xmit) && 533 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { 534 /* send xmit->buf[xmit->tail] 535 * out the port here */ 536 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); 537 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 538 sport->port.icount.tx++; 539 } 540 541 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 542 uart_write_wakeup(&sport->port); 543 544 if (uart_circ_empty(xmit)) 545 imx_uart_stop_tx(&sport->port); 546 } 547 548 static void imx_uart_dma_tx_callback(void *data) 549 { 550 struct imx_port *sport = data; 551 struct scatterlist *sgl = &sport->tx_sgl[0]; 552 struct circ_buf *xmit = &sport->port.state->xmit; 553 unsigned long flags; 554 u32 ucr1; 555 556 spin_lock_irqsave(&sport->port.lock, flags); 557 558 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 559 560 ucr1 = imx_uart_readl(sport, UCR1); 561 ucr1 &= ~UCR1_TXDMAEN; 562 imx_uart_writel(sport, ucr1, UCR1); 563 564 /* update the stat */ 565 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); 566 sport->port.icount.tx += sport->tx_bytes; 567 568 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); 569 570 sport->dma_is_txing = 0; 571 572 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 573 uart_write_wakeup(&sport->port); 574 575 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 576 imx_uart_dma_tx(sport); 577 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { 578 u32 ucr4 = imx_uart_readl(sport, UCR4); 579 ucr4 |= UCR4_TCEN; 580 imx_uart_writel(sport, ucr4, UCR4); 581 } 582 583 spin_unlock_irqrestore(&sport->port.lock, flags); 584 } 585 586 /* called with port.lock taken and irqs off */ 587 static void imx_uart_dma_tx(struct imx_port *sport) 588 { 589 struct circ_buf *xmit = &sport->port.state->xmit; 590 struct scatterlist *sgl = sport->tx_sgl; 591 struct dma_async_tx_descriptor *desc; 592 struct dma_chan *chan = sport->dma_chan_tx; 593 struct device *dev = sport->port.dev; 594 u32 ucr1, ucr4; 595 int ret; 596 597 if (sport->dma_is_txing) 598 return; 599 600 ucr4 = imx_uart_readl(sport, UCR4); 601 ucr4 &= ~UCR4_TCEN; 602 imx_uart_writel(sport, ucr4, UCR4); 603 604 sport->tx_bytes = uart_circ_chars_pending(xmit); 605 606 if (xmit->tail < xmit->head) { 607 sport->dma_tx_nents = 1; 608 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); 609 } else { 610 sport->dma_tx_nents = 2; 611 sg_init_table(sgl, 2); 612 sg_set_buf(sgl, xmit->buf + xmit->tail, 613 UART_XMIT_SIZE - xmit->tail); 614 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 615 } 616 617 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 618 if (ret == 0) { 619 dev_err(dev, "DMA mapping error for TX.\n"); 620 return; 621 } 622 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, 623 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 624 if (!desc) { 625 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, 626 DMA_TO_DEVICE); 627 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); 628 return; 629 } 630 desc->callback = imx_uart_dma_tx_callback; 631 desc->callback_param = sport; 632 633 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", 634 uart_circ_chars_pending(xmit)); 635 636 ucr1 = imx_uart_readl(sport, UCR1); 637 ucr1 |= UCR1_TXDMAEN; 638 imx_uart_writel(sport, ucr1, UCR1); 639 640 /* fire it */ 641 sport->dma_is_txing = 1; 642 dmaengine_submit(desc); 643 dma_async_issue_pending(chan); 644 return; 645 } 646 647 /* called with port.lock taken and irqs off */ 648 static void imx_uart_start_tx(struct uart_port *port) 649 { 650 struct imx_port *sport = (struct imx_port *)port; 651 u32 ucr1; 652 653 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) 654 return; 655 656 if (port->rs485.flags & SER_RS485_ENABLED) { 657 u32 ucr2; 658 659 ucr2 = imx_uart_readl(sport, UCR2); 660 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 661 imx_uart_rts_active(sport, &ucr2); 662 else 663 imx_uart_rts_inactive(sport, &ucr2); 664 imx_uart_writel(sport, ucr2, UCR2); 665 666 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 667 imx_uart_stop_rx(port); 668 669 /* 670 * Enable transmitter and shifter empty irq only if DMA is off. 671 * In the DMA case this is done in the tx-callback. 672 */ 673 if (!sport->dma_is_enabled) { 674 u32 ucr4 = imx_uart_readl(sport, UCR4); 675 ucr4 |= UCR4_TCEN; 676 imx_uart_writel(sport, ucr4, UCR4); 677 } 678 } 679 680 if (!sport->dma_is_enabled) { 681 ucr1 = imx_uart_readl(sport, UCR1); 682 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); 683 } 684 685 if (sport->dma_is_enabled) { 686 if (sport->port.x_char) { 687 /* We have X-char to send, so enable TX IRQ and 688 * disable TX DMA to let TX interrupt to send X-char */ 689 ucr1 = imx_uart_readl(sport, UCR1); 690 ucr1 &= ~UCR1_TXDMAEN; 691 ucr1 |= UCR1_TRDYEN; 692 imx_uart_writel(sport, ucr1, UCR1); 693 return; 694 } 695 696 if (!uart_circ_empty(&port->state->xmit) && 697 !uart_tx_stopped(port)) 698 imx_uart_dma_tx(sport); 699 return; 700 } 701 } 702 703 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id) 704 { 705 struct imx_port *sport = dev_id; 706 u32 usr1; 707 708 spin_lock(&sport->port.lock); 709 710 imx_uart_writel(sport, USR1_RTSD, USR1); 711 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; 712 uart_handle_cts_change(&sport->port, !!usr1); 713 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 714 715 spin_unlock(&sport->port.lock); 716 return IRQ_HANDLED; 717 } 718 719 static irqreturn_t imx_uart_txint(int irq, void *dev_id) 720 { 721 struct imx_port *sport = dev_id; 722 723 spin_lock(&sport->port.lock); 724 imx_uart_transmit_buffer(sport); 725 spin_unlock(&sport->port.lock); 726 return IRQ_HANDLED; 727 } 728 729 static irqreturn_t imx_uart_rxint(int irq, void *dev_id) 730 { 731 struct imx_port *sport = dev_id; 732 unsigned int rx, flg, ignored = 0; 733 struct tty_port *port = &sport->port.state->port; 734 735 spin_lock(&sport->port.lock); 736 737 while (imx_uart_readl(sport, USR2) & USR2_RDR) { 738 u32 usr2; 739 740 flg = TTY_NORMAL; 741 sport->port.icount.rx++; 742 743 rx = imx_uart_readl(sport, URXD0); 744 745 usr2 = imx_uart_readl(sport, USR2); 746 if (usr2 & USR2_BRCD) { 747 imx_uart_writel(sport, USR2_BRCD, USR2); 748 if (uart_handle_break(&sport->port)) 749 continue; 750 } 751 752 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 753 continue; 754 755 if (unlikely(rx & URXD_ERR)) { 756 if (rx & URXD_BRK) 757 sport->port.icount.brk++; 758 else if (rx & URXD_PRERR) 759 sport->port.icount.parity++; 760 else if (rx & URXD_FRMERR) 761 sport->port.icount.frame++; 762 if (rx & URXD_OVRRUN) 763 sport->port.icount.overrun++; 764 765 if (rx & sport->port.ignore_status_mask) { 766 if (++ignored > 100) 767 goto out; 768 continue; 769 } 770 771 rx &= (sport->port.read_status_mask | 0xFF); 772 773 if (rx & URXD_BRK) 774 flg = TTY_BREAK; 775 else if (rx & URXD_PRERR) 776 flg = TTY_PARITY; 777 else if (rx & URXD_FRMERR) 778 flg = TTY_FRAME; 779 if (rx & URXD_OVRRUN) 780 flg = TTY_OVERRUN; 781 782 #ifdef SUPPORT_SYSRQ 783 sport->port.sysrq = 0; 784 #endif 785 } 786 787 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) 788 goto out; 789 790 if (tty_insert_flip_char(port, rx, flg) == 0) 791 sport->port.icount.buf_overrun++; 792 } 793 794 out: 795 spin_unlock(&sport->port.lock); 796 tty_flip_buffer_push(port); 797 return IRQ_HANDLED; 798 } 799 800 static void imx_uart_clear_rx_errors(struct imx_port *sport); 801 802 /* 803 * We have a modem side uart, so the meanings of RTS and CTS are inverted. 804 */ 805 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) 806 { 807 unsigned int tmp = TIOCM_DSR; 808 unsigned usr1 = imx_uart_readl(sport, USR1); 809 unsigned usr2 = imx_uart_readl(sport, USR2); 810 811 if (usr1 & USR1_RTSS) 812 tmp |= TIOCM_CTS; 813 814 /* in DCE mode DCDIN is always 0 */ 815 if (!(usr2 & USR2_DCDIN)) 816 tmp |= TIOCM_CAR; 817 818 if (sport->dte_mode) 819 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) 820 tmp |= TIOCM_RI; 821 822 return tmp; 823 } 824 825 /* 826 * Handle any change of modem status signal since we were last called. 827 */ 828 static void imx_uart_mctrl_check(struct imx_port *sport) 829 { 830 unsigned int status, changed; 831 832 status = imx_uart_get_hwmctrl(sport); 833 changed = status ^ sport->old_status; 834 835 if (changed == 0) 836 return; 837 838 sport->old_status = status; 839 840 if (changed & TIOCM_RI && status & TIOCM_RI) 841 sport->port.icount.rng++; 842 if (changed & TIOCM_DSR) 843 sport->port.icount.dsr++; 844 if (changed & TIOCM_CAR) 845 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); 846 if (changed & TIOCM_CTS) 847 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); 848 849 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); 850 } 851 852 static irqreturn_t imx_uart_int(int irq, void *dev_id) 853 { 854 struct imx_port *sport = dev_id; 855 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 856 irqreturn_t ret = IRQ_NONE; 857 858 usr1 = imx_uart_readl(sport, USR1); 859 usr2 = imx_uart_readl(sport, USR2); 860 ucr1 = imx_uart_readl(sport, UCR1); 861 ucr2 = imx_uart_readl(sport, UCR2); 862 ucr3 = imx_uart_readl(sport, UCR3); 863 ucr4 = imx_uart_readl(sport, UCR4); 864 865 /* 866 * Even if a condition is true that can trigger an irq only handle it if 867 * the respective irq source is enabled. This prevents some undesired 868 * actions, for example if a character that sits in the RX FIFO and that 869 * should be fetched via DMA is tried to be fetched using PIO. Or the 870 * receiver is currently off and so reading from URXD0 results in an 871 * exception. So just mask the (raw) status bits for disabled irqs. 872 */ 873 if ((ucr1 & UCR1_RRDYEN) == 0) 874 usr1 &= ~USR1_RRDY; 875 if ((ucr2 & UCR2_ATEN) == 0) 876 usr1 &= ~USR1_AGTIM; 877 if ((ucr1 & UCR1_TRDYEN) == 0) 878 usr1 &= ~USR1_TRDY; 879 if ((ucr4 & UCR4_TCEN) == 0) 880 usr2 &= ~USR2_TXDC; 881 if ((ucr3 & UCR3_DTRDEN) == 0) 882 usr1 &= ~USR1_DTRD; 883 if ((ucr1 & UCR1_RTSDEN) == 0) 884 usr1 &= ~USR1_RTSD; 885 if ((ucr3 & UCR3_AWAKEN) == 0) 886 usr1 &= ~USR1_AWAKE; 887 if ((ucr4 & UCR4_OREN) == 0) 888 usr2 &= ~USR2_ORE; 889 890 if (usr1 & (USR1_RRDY | USR1_AGTIM)) { 891 imx_uart_rxint(irq, dev_id); 892 ret = IRQ_HANDLED; 893 } 894 895 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) { 896 imx_uart_txint(irq, dev_id); 897 ret = IRQ_HANDLED; 898 } 899 900 if (usr1 & USR1_DTRD) { 901 imx_uart_writel(sport, USR1_DTRD, USR1); 902 903 spin_lock(&sport->port.lock); 904 imx_uart_mctrl_check(sport); 905 spin_unlock(&sport->port.lock); 906 907 ret = IRQ_HANDLED; 908 } 909 910 if (usr1 & USR1_RTSD) { 911 imx_uart_rtsint(irq, dev_id); 912 ret = IRQ_HANDLED; 913 } 914 915 if (usr1 & USR1_AWAKE) { 916 imx_uart_writel(sport, USR1_AWAKE, USR1); 917 ret = IRQ_HANDLED; 918 } 919 920 if (usr2 & USR2_ORE) { 921 sport->port.icount.overrun++; 922 imx_uart_writel(sport, USR2_ORE, USR2); 923 ret = IRQ_HANDLED; 924 } 925 926 return ret; 927 } 928 929 /* 930 * Return TIOCSER_TEMT when transmitter is not busy. 931 */ 932 static unsigned int imx_uart_tx_empty(struct uart_port *port) 933 { 934 struct imx_port *sport = (struct imx_port *)port; 935 unsigned int ret; 936 937 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; 938 939 /* If the TX DMA is working, return 0. */ 940 if (sport->dma_is_txing) 941 ret = 0; 942 943 return ret; 944 } 945 946 /* called with port.lock taken and irqs off */ 947 static unsigned int imx_uart_get_mctrl(struct uart_port *port) 948 { 949 struct imx_port *sport = (struct imx_port *)port; 950 unsigned int ret = imx_uart_get_hwmctrl(sport); 951 952 mctrl_gpio_get(sport->gpios, &ret); 953 954 return ret; 955 } 956 957 /* called with port.lock taken and irqs off */ 958 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 959 { 960 struct imx_port *sport = (struct imx_port *)port; 961 u32 ucr3, uts; 962 963 if (!(port->rs485.flags & SER_RS485_ENABLED)) { 964 u32 ucr2; 965 966 /* 967 * Turn off autoRTS if RTS is lowered and restore autoRTS 968 * setting if RTS is raised. 969 */ 970 ucr2 = imx_uart_readl(sport, UCR2); 971 ucr2 &= ~(UCR2_CTS | UCR2_CTSC); 972 if (mctrl & TIOCM_RTS) { 973 ucr2 |= UCR2_CTS; 974 /* 975 * UCR2_IRTS is unset if and only if the port is 976 * configured for CRTSCTS, so we use inverted UCR2_IRTS 977 * to get the state to restore to. 978 */ 979 if (!(ucr2 & UCR2_IRTS)) 980 ucr2 |= UCR2_CTSC; 981 } 982 imx_uart_writel(sport, ucr2, UCR2); 983 } 984 985 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; 986 if (!(mctrl & TIOCM_DTR)) 987 ucr3 |= UCR3_DSR; 988 imx_uart_writel(sport, ucr3, UCR3); 989 990 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; 991 if (mctrl & TIOCM_LOOP) 992 uts |= UTS_LOOP; 993 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); 994 995 mctrl_gpio_set(sport->gpios, mctrl); 996 } 997 998 /* 999 * Interrupts always disabled. 1000 */ 1001 static void imx_uart_break_ctl(struct uart_port *port, int break_state) 1002 { 1003 struct imx_port *sport = (struct imx_port *)port; 1004 unsigned long flags; 1005 u32 ucr1; 1006 1007 spin_lock_irqsave(&sport->port.lock, flags); 1008 1009 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1010 1011 if (break_state != 0) 1012 ucr1 |= UCR1_SNDBRK; 1013 1014 imx_uart_writel(sport, ucr1, UCR1); 1015 1016 spin_unlock_irqrestore(&sport->port.lock, flags); 1017 } 1018 1019 /* 1020 * This is our per-port timeout handler, for checking the 1021 * modem status signals. 1022 */ 1023 static void imx_uart_timeout(struct timer_list *t) 1024 { 1025 struct imx_port *sport = from_timer(sport, t, timer); 1026 unsigned long flags; 1027 1028 if (sport->port.state) { 1029 spin_lock_irqsave(&sport->port.lock, flags); 1030 imx_uart_mctrl_check(sport); 1031 spin_unlock_irqrestore(&sport->port.lock, flags); 1032 1033 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1034 } 1035 } 1036 1037 #define RX_BUF_SIZE (PAGE_SIZE) 1038 1039 /* 1040 * There are two kinds of RX DMA interrupts(such as in the MX6Q): 1041 * [1] the RX DMA buffer is full. 1042 * [2] the aging timer expires 1043 * 1044 * Condition [2] is triggered when a character has been sitting in the FIFO 1045 * for at least 8 byte durations. 1046 */ 1047 static void imx_uart_dma_rx_callback(void *data) 1048 { 1049 struct imx_port *sport = data; 1050 struct dma_chan *chan = sport->dma_chan_rx; 1051 struct scatterlist *sgl = &sport->rx_sgl; 1052 struct tty_port *port = &sport->port.state->port; 1053 struct dma_tx_state state; 1054 struct circ_buf *rx_ring = &sport->rx_ring; 1055 enum dma_status status; 1056 unsigned int w_bytes = 0; 1057 unsigned int r_bytes; 1058 unsigned int bd_size; 1059 1060 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1061 1062 if (status == DMA_ERROR) { 1063 imx_uart_clear_rx_errors(sport); 1064 return; 1065 } 1066 1067 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1068 1069 /* 1070 * The state-residue variable represents the empty space 1071 * relative to the entire buffer. Taking this in consideration 1072 * the head is always calculated base on the buffer total 1073 * length - DMA transaction residue. The UART script from the 1074 * SDMA firmware will jump to the next buffer descriptor, 1075 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). 1076 * Taking this in consideration the tail is always at the 1077 * beginning of the buffer descriptor that contains the head. 1078 */ 1079 1080 /* Calculate the head */ 1081 rx_ring->head = sg_dma_len(sgl) - state.residue; 1082 1083 /* Calculate the tail. */ 1084 bd_size = sg_dma_len(sgl) / sport->rx_periods; 1085 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; 1086 1087 if (rx_ring->head <= sg_dma_len(sgl) && 1088 rx_ring->head > rx_ring->tail) { 1089 1090 /* Move data from tail to head */ 1091 r_bytes = rx_ring->head - rx_ring->tail; 1092 1093 /* CPU claims ownership of RX DMA buffer */ 1094 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, 1095 DMA_FROM_DEVICE); 1096 1097 w_bytes = tty_insert_flip_string(port, 1098 sport->rx_buf + rx_ring->tail, r_bytes); 1099 1100 /* UART retrieves ownership of RX DMA buffer */ 1101 dma_sync_sg_for_device(sport->port.dev, sgl, 1, 1102 DMA_FROM_DEVICE); 1103 1104 if (w_bytes != r_bytes) 1105 sport->port.icount.buf_overrun++; 1106 1107 sport->port.icount.rx += w_bytes; 1108 } else { 1109 WARN_ON(rx_ring->head > sg_dma_len(sgl)); 1110 WARN_ON(rx_ring->head <= rx_ring->tail); 1111 } 1112 } 1113 1114 if (w_bytes) { 1115 tty_flip_buffer_push(port); 1116 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); 1117 } 1118 } 1119 1120 /* RX DMA buffer periods */ 1121 #define RX_DMA_PERIODS 4 1122 1123 static int imx_uart_start_rx_dma(struct imx_port *sport) 1124 { 1125 struct scatterlist *sgl = &sport->rx_sgl; 1126 struct dma_chan *chan = sport->dma_chan_rx; 1127 struct device *dev = sport->port.dev; 1128 struct dma_async_tx_descriptor *desc; 1129 int ret; 1130 1131 sport->rx_ring.head = 0; 1132 sport->rx_ring.tail = 0; 1133 sport->rx_periods = RX_DMA_PERIODS; 1134 1135 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); 1136 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1137 if (ret == 0) { 1138 dev_err(dev, "DMA mapping error for RX.\n"); 1139 return -EINVAL; 1140 } 1141 1142 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl), 1143 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, 1144 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 1145 1146 if (!desc) { 1147 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); 1148 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); 1149 return -EINVAL; 1150 } 1151 desc->callback = imx_uart_dma_rx_callback; 1152 desc->callback_param = sport; 1153 1154 dev_dbg(dev, "RX: prepare for the DMA.\n"); 1155 sport->dma_is_rxing = 1; 1156 sport->rx_cookie = dmaengine_submit(desc); 1157 dma_async_issue_pending(chan); 1158 return 0; 1159 } 1160 1161 static void imx_uart_clear_rx_errors(struct imx_port *sport) 1162 { 1163 struct tty_port *port = &sport->port.state->port; 1164 u32 usr1, usr2; 1165 1166 usr1 = imx_uart_readl(sport, USR1); 1167 usr2 = imx_uart_readl(sport, USR2); 1168 1169 if (usr2 & USR2_BRCD) { 1170 sport->port.icount.brk++; 1171 imx_uart_writel(sport, USR2_BRCD, USR2); 1172 uart_handle_break(&sport->port); 1173 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0) 1174 sport->port.icount.buf_overrun++; 1175 tty_flip_buffer_push(port); 1176 } else { 1177 if (usr1 & USR1_FRAMERR) { 1178 sport->port.icount.frame++; 1179 imx_uart_writel(sport, USR1_FRAMERR, USR1); 1180 } else if (usr1 & USR1_PARITYERR) { 1181 sport->port.icount.parity++; 1182 imx_uart_writel(sport, USR1_PARITYERR, USR1); 1183 } 1184 } 1185 1186 if (usr2 & USR2_ORE) { 1187 sport->port.icount.overrun++; 1188 imx_uart_writel(sport, USR2_ORE, USR2); 1189 } 1190 1191 } 1192 1193 #define TXTL_DEFAULT 2 /* reset default */ 1194 #define RXTL_DEFAULT 1 /* reset default */ 1195 #define TXTL_DMA 8 /* DMA burst setting */ 1196 #define RXTL_DMA 9 /* DMA burst setting */ 1197 1198 static void imx_uart_setup_ufcr(struct imx_port *sport, 1199 unsigned char txwl, unsigned char rxwl) 1200 { 1201 unsigned int val; 1202 1203 /* set receiver / transmitter trigger level */ 1204 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); 1205 val |= txwl << UFCR_TXTL_SHF | rxwl; 1206 imx_uart_writel(sport, val, UFCR); 1207 } 1208 1209 static void imx_uart_dma_exit(struct imx_port *sport) 1210 { 1211 if (sport->dma_chan_rx) { 1212 dmaengine_terminate_sync(sport->dma_chan_rx); 1213 dma_release_channel(sport->dma_chan_rx); 1214 sport->dma_chan_rx = NULL; 1215 sport->rx_cookie = -EINVAL; 1216 kfree(sport->rx_buf); 1217 sport->rx_buf = NULL; 1218 } 1219 1220 if (sport->dma_chan_tx) { 1221 dmaengine_terminate_sync(sport->dma_chan_tx); 1222 dma_release_channel(sport->dma_chan_tx); 1223 sport->dma_chan_tx = NULL; 1224 } 1225 } 1226 1227 static int imx_uart_dma_init(struct imx_port *sport) 1228 { 1229 struct dma_slave_config slave_config = {}; 1230 struct device *dev = sport->port.dev; 1231 int ret; 1232 1233 /* Prepare for RX : */ 1234 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); 1235 if (!sport->dma_chan_rx) { 1236 dev_dbg(dev, "cannot get the DMA channel.\n"); 1237 ret = -EINVAL; 1238 goto err; 1239 } 1240 1241 slave_config.direction = DMA_DEV_TO_MEM; 1242 slave_config.src_addr = sport->port.mapbase + URXD0; 1243 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1244 /* one byte less than the watermark level to enable the aging timer */ 1245 slave_config.src_maxburst = RXTL_DMA - 1; 1246 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); 1247 if (ret) { 1248 dev_err(dev, "error in RX dma configuration.\n"); 1249 goto err; 1250 } 1251 1252 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); 1253 if (!sport->rx_buf) { 1254 ret = -ENOMEM; 1255 goto err; 1256 } 1257 sport->rx_ring.buf = sport->rx_buf; 1258 1259 /* Prepare for TX : */ 1260 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); 1261 if (!sport->dma_chan_tx) { 1262 dev_err(dev, "cannot get the TX DMA channel!\n"); 1263 ret = -EINVAL; 1264 goto err; 1265 } 1266 1267 slave_config.direction = DMA_MEM_TO_DEV; 1268 slave_config.dst_addr = sport->port.mapbase + URTX0; 1269 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1270 slave_config.dst_maxburst = TXTL_DMA; 1271 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); 1272 if (ret) { 1273 dev_err(dev, "error in TX dma configuration."); 1274 goto err; 1275 } 1276 1277 return 0; 1278 err: 1279 imx_uart_dma_exit(sport); 1280 return ret; 1281 } 1282 1283 static void imx_uart_enable_dma(struct imx_port *sport) 1284 { 1285 u32 ucr1; 1286 1287 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); 1288 1289 /* set UCR1 */ 1290 ucr1 = imx_uart_readl(sport, UCR1); 1291 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN; 1292 imx_uart_writel(sport, ucr1, UCR1); 1293 1294 sport->dma_is_enabled = 1; 1295 } 1296 1297 static void imx_uart_disable_dma(struct imx_port *sport) 1298 { 1299 u32 ucr1; 1300 1301 /* clear UCR1 */ 1302 ucr1 = imx_uart_readl(sport, UCR1); 1303 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN); 1304 imx_uart_writel(sport, ucr1, UCR1); 1305 1306 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1307 1308 sport->dma_is_enabled = 0; 1309 } 1310 1311 /* half the RX buffer size */ 1312 #define CTSTL 16 1313 1314 static int imx_uart_startup(struct uart_port *port) 1315 { 1316 struct imx_port *sport = (struct imx_port *)port; 1317 int retval, i; 1318 unsigned long flags; 1319 int dma_is_inited = 0; 1320 u32 ucr1, ucr2, ucr4; 1321 1322 retval = clk_prepare_enable(sport->clk_per); 1323 if (retval) 1324 return retval; 1325 retval = clk_prepare_enable(sport->clk_ipg); 1326 if (retval) { 1327 clk_disable_unprepare(sport->clk_per); 1328 return retval; 1329 } 1330 1331 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1332 1333 /* disable the DREN bit (Data Ready interrupt enable) before 1334 * requesting IRQs 1335 */ 1336 ucr4 = imx_uart_readl(sport, UCR4); 1337 1338 /* set the trigger level for CTS */ 1339 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); 1340 ucr4 |= CTSTL << UCR4_CTSTL_SHF; 1341 1342 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1343 1344 /* Can we enable the DMA support? */ 1345 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 1346 dma_is_inited = 1; 1347 1348 spin_lock_irqsave(&sport->port.lock, flags); 1349 /* Reset fifo's and state machines */ 1350 i = 100; 1351 1352 ucr2 = imx_uart_readl(sport, UCR2); 1353 ucr2 &= ~UCR2_SRST; 1354 imx_uart_writel(sport, ucr2, UCR2); 1355 1356 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1357 udelay(1); 1358 1359 /* 1360 * Finally, clear and enable interrupts 1361 */ 1362 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); 1363 imx_uart_writel(sport, USR2_ORE, USR2); 1364 1365 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; 1366 ucr1 |= UCR1_UARTEN; 1367 if (sport->have_rtscts) 1368 ucr1 |= UCR1_RTSDEN; 1369 1370 imx_uart_writel(sport, ucr1, UCR1); 1371 1372 ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN; 1373 if (!sport->dma_is_enabled) 1374 ucr4 |= UCR4_OREN; 1375 imx_uart_writel(sport, ucr4, UCR4); 1376 1377 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; 1378 ucr2 |= (UCR2_RXEN | UCR2_TXEN); 1379 if (!sport->have_rtscts) 1380 ucr2 |= UCR2_IRTS; 1381 /* 1382 * make sure the edge sensitive RTS-irq is disabled, 1383 * we're using RTSD instead. 1384 */ 1385 if (!imx_uart_is_imx1(sport)) 1386 ucr2 &= ~UCR2_RTSEN; 1387 imx_uart_writel(sport, ucr2, UCR2); 1388 1389 if (!imx_uart_is_imx1(sport)) { 1390 u32 ucr3; 1391 1392 ucr3 = imx_uart_readl(sport, UCR3); 1393 1394 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD; 1395 1396 if (sport->dte_mode) 1397 /* disable broken interrupts */ 1398 ucr3 &= ~(UCR3_RI | UCR3_DCD); 1399 1400 imx_uart_writel(sport, ucr3, UCR3); 1401 } 1402 1403 /* 1404 * Enable modem status interrupts 1405 */ 1406 imx_uart_enable_ms(&sport->port); 1407 1408 if (dma_is_inited) { 1409 imx_uart_enable_dma(sport); 1410 imx_uart_start_rx_dma(sport); 1411 } else { 1412 ucr1 = imx_uart_readl(sport, UCR1); 1413 ucr1 |= UCR1_RRDYEN; 1414 imx_uart_writel(sport, ucr1, UCR1); 1415 1416 ucr2 = imx_uart_readl(sport, UCR2); 1417 ucr2 |= UCR2_ATEN; 1418 imx_uart_writel(sport, ucr2, UCR2); 1419 } 1420 1421 spin_unlock_irqrestore(&sport->port.lock, flags); 1422 1423 return 0; 1424 } 1425 1426 static void imx_uart_shutdown(struct uart_port *port) 1427 { 1428 struct imx_port *sport = (struct imx_port *)port; 1429 unsigned long flags; 1430 u32 ucr1, ucr2, ucr4; 1431 1432 if (sport->dma_is_enabled) { 1433 dmaengine_terminate_sync(sport->dma_chan_tx); 1434 if (sport->dma_is_txing) { 1435 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 1436 sport->dma_tx_nents, DMA_TO_DEVICE); 1437 sport->dma_is_txing = 0; 1438 } 1439 dmaengine_terminate_sync(sport->dma_chan_rx); 1440 if (sport->dma_is_rxing) { 1441 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1442 1, DMA_FROM_DEVICE); 1443 sport->dma_is_rxing = 0; 1444 } 1445 1446 spin_lock_irqsave(&sport->port.lock, flags); 1447 imx_uart_stop_tx(port); 1448 imx_uart_stop_rx(port); 1449 imx_uart_disable_dma(sport); 1450 spin_unlock_irqrestore(&sport->port.lock, flags); 1451 imx_uart_dma_exit(sport); 1452 } 1453 1454 mctrl_gpio_disable_ms(sport->gpios); 1455 1456 spin_lock_irqsave(&sport->port.lock, flags); 1457 ucr2 = imx_uart_readl(sport, UCR2); 1458 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 1459 imx_uart_writel(sport, ucr2, UCR2); 1460 1461 ucr4 = imx_uart_readl(sport, UCR4); 1462 ucr4 &= ~UCR4_OREN; 1463 imx_uart_writel(sport, ucr4, UCR4); 1464 spin_unlock_irqrestore(&sport->port.lock, flags); 1465 1466 /* 1467 * Stop our timer. 1468 */ 1469 del_timer_sync(&sport->timer); 1470 1471 /* 1472 * Disable all interrupts, port and break condition. 1473 */ 1474 1475 spin_lock_irqsave(&sport->port.lock, flags); 1476 ucr1 = imx_uart_readl(sport, UCR1); 1477 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); 1478 1479 imx_uart_writel(sport, ucr1, UCR1); 1480 spin_unlock_irqrestore(&sport->port.lock, flags); 1481 1482 clk_disable_unprepare(sport->clk_per); 1483 clk_disable_unprepare(sport->clk_ipg); 1484 } 1485 1486 /* called with port.lock taken and irqs off */ 1487 static void imx_uart_flush_buffer(struct uart_port *port) 1488 { 1489 struct imx_port *sport = (struct imx_port *)port; 1490 struct scatterlist *sgl = &sport->tx_sgl[0]; 1491 u32 ucr2; 1492 int i = 100, ubir, ubmr, uts; 1493 1494 if (!sport->dma_chan_tx) 1495 return; 1496 1497 sport->tx_bytes = 0; 1498 dmaengine_terminate_all(sport->dma_chan_tx); 1499 if (sport->dma_is_txing) { 1500 u32 ucr1; 1501 1502 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, 1503 DMA_TO_DEVICE); 1504 ucr1 = imx_uart_readl(sport, UCR1); 1505 ucr1 &= ~UCR1_TXDMAEN; 1506 imx_uart_writel(sport, ucr1, UCR1); 1507 sport->dma_is_txing = 0; 1508 } 1509 1510 /* 1511 * According to the Reference Manual description of the UART SRST bit: 1512 * 1513 * "Reset the transmit and receive state machines, 1514 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD 1515 * and UTS[6-3]". 1516 * 1517 * We don't need to restore the old values from USR1, USR2, URXD and 1518 * UTXD. UBRC is read only, so only save/restore the other three 1519 * registers. 1520 */ 1521 ubir = imx_uart_readl(sport, UBIR); 1522 ubmr = imx_uart_readl(sport, UBMR); 1523 uts = imx_uart_readl(sport, IMX21_UTS); 1524 1525 ucr2 = imx_uart_readl(sport, UCR2); 1526 ucr2 &= ~UCR2_SRST; 1527 imx_uart_writel(sport, ucr2, UCR2); 1528 1529 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) 1530 udelay(1); 1531 1532 /* Restore the registers */ 1533 imx_uart_writel(sport, ubir, UBIR); 1534 imx_uart_writel(sport, ubmr, UBMR); 1535 imx_uart_writel(sport, uts, IMX21_UTS); 1536 } 1537 1538 static void 1539 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1540 struct ktermios *old) 1541 { 1542 struct imx_port *sport = (struct imx_port *)port; 1543 unsigned long flags; 1544 u32 ucr2, old_ucr2, ufcr; 1545 unsigned int baud, quot; 1546 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1547 unsigned long div; 1548 unsigned long num, denom, old_ubir, old_ubmr; 1549 uint64_t tdiv64; 1550 1551 /* 1552 * We only support CS7 and CS8. 1553 */ 1554 while ((termios->c_cflag & CSIZE) != CS7 && 1555 (termios->c_cflag & CSIZE) != CS8) { 1556 termios->c_cflag &= ~CSIZE; 1557 termios->c_cflag |= old_csize; 1558 old_csize = CS8; 1559 } 1560 1561 del_timer_sync(&sport->timer); 1562 1563 /* 1564 * Ask the core to calculate the divisor for us. 1565 */ 1566 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1567 quot = uart_get_divisor(port, baud); 1568 1569 spin_lock_irqsave(&sport->port.lock, flags); 1570 1571 /* 1572 * Read current UCR2 and save it for future use, then clear all the bits 1573 * except those we will or may need to preserve. 1574 */ 1575 old_ucr2 = imx_uart_readl(sport, UCR2); 1576 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS); 1577 1578 ucr2 |= UCR2_SRST | UCR2_IRTS; 1579 if ((termios->c_cflag & CSIZE) == CS8) 1580 ucr2 |= UCR2_WS; 1581 1582 if (!sport->have_rtscts) 1583 termios->c_cflag &= ~CRTSCTS; 1584 1585 if (port->rs485.flags & SER_RS485_ENABLED) { 1586 /* 1587 * RTS is mandatory for rs485 operation, so keep 1588 * it under manual control and keep transmitter 1589 * disabled. 1590 */ 1591 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1592 imx_uart_rts_active(sport, &ucr2); 1593 else 1594 imx_uart_rts_inactive(sport, &ucr2); 1595 1596 } else if (termios->c_cflag & CRTSCTS) { 1597 /* 1598 * Only let receiver control RTS output if we were not requested 1599 * to have RTS inactive (which then should take precedence). 1600 */ 1601 if (ucr2 & UCR2_CTS) 1602 ucr2 |= UCR2_CTSC; 1603 } 1604 1605 if (termios->c_cflag & CRTSCTS) 1606 ucr2 &= ~UCR2_IRTS; 1607 1608 if (termios->c_cflag & CSTOPB) 1609 ucr2 |= UCR2_STPB; 1610 if (termios->c_cflag & PARENB) { 1611 ucr2 |= UCR2_PREN; 1612 if (termios->c_cflag & PARODD) 1613 ucr2 |= UCR2_PROE; 1614 } 1615 1616 sport->port.read_status_mask = 0; 1617 if (termios->c_iflag & INPCK) 1618 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); 1619 if (termios->c_iflag & (BRKINT | PARMRK)) 1620 sport->port.read_status_mask |= URXD_BRK; 1621 1622 /* 1623 * Characters to ignore 1624 */ 1625 sport->port.ignore_status_mask = 0; 1626 if (termios->c_iflag & IGNPAR) 1627 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; 1628 if (termios->c_iflag & IGNBRK) { 1629 sport->port.ignore_status_mask |= URXD_BRK; 1630 /* 1631 * If we're ignoring parity and break indicators, 1632 * ignore overruns too (for real raw support). 1633 */ 1634 if (termios->c_iflag & IGNPAR) 1635 sport->port.ignore_status_mask |= URXD_OVRRUN; 1636 } 1637 1638 if ((termios->c_cflag & CREAD) == 0) 1639 sport->port.ignore_status_mask |= URXD_DUMMY_READ; 1640 1641 /* 1642 * Update the per-port timeout. 1643 */ 1644 uart_update_timeout(port, termios->c_cflag, baud); 1645 1646 /* custom-baudrate handling */ 1647 div = sport->port.uartclk / (baud * 16); 1648 if (baud == 38400 && quot != div) 1649 baud = sport->port.uartclk / (quot * 16); 1650 1651 div = sport->port.uartclk / (baud * 16); 1652 if (div > 7) 1653 div = 7; 1654 if (!div) 1655 div = 1; 1656 1657 rational_best_approximation(16 * div * baud, sport->port.uartclk, 1658 1 << 16, 1 << 16, &num, &denom); 1659 1660 tdiv64 = sport->port.uartclk; 1661 tdiv64 *= num; 1662 do_div(tdiv64, denom * 16 * div); 1663 tty_termios_encode_baud_rate(termios, 1664 (speed_t)tdiv64, (speed_t)tdiv64); 1665 1666 num -= 1; 1667 denom -= 1; 1668 1669 ufcr = imx_uart_readl(sport, UFCR); 1670 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); 1671 imx_uart_writel(sport, ufcr, UFCR); 1672 1673 /* 1674 * Two registers below should always be written both and in this 1675 * particular order. One consequence is that we need to check if any of 1676 * them changes and then update both. We do need the check for change 1677 * as even writing the same values seem to "restart" 1678 * transmission/receiving logic in the hardware, that leads to data 1679 * breakage even when rate doesn't in fact change. E.g., user switches 1680 * RTS/CTS handshake and suddenly gets broken bytes. 1681 */ 1682 old_ubir = imx_uart_readl(sport, UBIR); 1683 old_ubmr = imx_uart_readl(sport, UBMR); 1684 if (old_ubir != num || old_ubmr != denom) { 1685 imx_uart_writel(sport, num, UBIR); 1686 imx_uart_writel(sport, denom, UBMR); 1687 } 1688 1689 if (!imx_uart_is_imx1(sport)) 1690 imx_uart_writel(sport, sport->port.uartclk / div / 1000, 1691 IMX21_ONEMS); 1692 1693 imx_uart_writel(sport, ucr2, UCR2); 1694 1695 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1696 imx_uart_enable_ms(&sport->port); 1697 1698 spin_unlock_irqrestore(&sport->port.lock, flags); 1699 } 1700 1701 static const char *imx_uart_type(struct uart_port *port) 1702 { 1703 struct imx_port *sport = (struct imx_port *)port; 1704 1705 return sport->port.type == PORT_IMX ? "IMX" : NULL; 1706 } 1707 1708 /* 1709 * Configure/autoconfigure the port. 1710 */ 1711 static void imx_uart_config_port(struct uart_port *port, int flags) 1712 { 1713 struct imx_port *sport = (struct imx_port *)port; 1714 1715 if (flags & UART_CONFIG_TYPE) 1716 sport->port.type = PORT_IMX; 1717 } 1718 1719 /* 1720 * Verify the new serial_struct (for TIOCSSERIAL). 1721 * The only change we allow are to the flags and type, and 1722 * even then only between PORT_IMX and PORT_UNKNOWN 1723 */ 1724 static int 1725 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) 1726 { 1727 struct imx_port *sport = (struct imx_port *)port; 1728 int ret = 0; 1729 1730 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) 1731 ret = -EINVAL; 1732 if (sport->port.irq != ser->irq) 1733 ret = -EINVAL; 1734 if (ser->io_type != UPIO_MEM) 1735 ret = -EINVAL; 1736 if (sport->port.uartclk / 16 != ser->baud_base) 1737 ret = -EINVAL; 1738 if (sport->port.mapbase != (unsigned long)ser->iomem_base) 1739 ret = -EINVAL; 1740 if (sport->port.iobase != ser->port) 1741 ret = -EINVAL; 1742 if (ser->hub6 != 0) 1743 ret = -EINVAL; 1744 return ret; 1745 } 1746 1747 #if defined(CONFIG_CONSOLE_POLL) 1748 1749 static int imx_uart_poll_init(struct uart_port *port) 1750 { 1751 struct imx_port *sport = (struct imx_port *)port; 1752 unsigned long flags; 1753 u32 ucr1, ucr2; 1754 int retval; 1755 1756 retval = clk_prepare_enable(sport->clk_ipg); 1757 if (retval) 1758 return retval; 1759 retval = clk_prepare_enable(sport->clk_per); 1760 if (retval) 1761 clk_disable_unprepare(sport->clk_ipg); 1762 1763 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1764 1765 spin_lock_irqsave(&sport->port.lock, flags); 1766 1767 /* 1768 * Be careful about the order of enabling bits here. First enable the 1769 * receiver (UARTEN + RXEN) and only then the corresponding irqs. 1770 * This prevents that a character that already sits in the RX fifo is 1771 * triggering an irq but the try to fetch it from there results in an 1772 * exception because UARTEN or RXEN is still off. 1773 */ 1774 ucr1 = imx_uart_readl(sport, UCR1); 1775 ucr2 = imx_uart_readl(sport, UCR2); 1776 1777 if (imx_uart_is_imx1(sport)) 1778 ucr1 |= IMX1_UCR1_UARTCLKEN; 1779 1780 ucr1 |= UCR1_UARTEN; 1781 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); 1782 1783 ucr2 |= UCR2_RXEN; 1784 ucr2 &= ~UCR2_ATEN; 1785 1786 imx_uart_writel(sport, ucr1, UCR1); 1787 imx_uart_writel(sport, ucr2, UCR2); 1788 1789 /* now enable irqs */ 1790 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 1791 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 1792 1793 spin_unlock_irqrestore(&sport->port.lock, flags); 1794 1795 return 0; 1796 } 1797 1798 static int imx_uart_poll_get_char(struct uart_port *port) 1799 { 1800 struct imx_port *sport = (struct imx_port *)port; 1801 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) 1802 return NO_POLL_CHAR; 1803 1804 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; 1805 } 1806 1807 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c) 1808 { 1809 struct imx_port *sport = (struct imx_port *)port; 1810 unsigned int status; 1811 1812 /* drain */ 1813 do { 1814 status = imx_uart_readl(sport, USR1); 1815 } while (~status & USR1_TRDY); 1816 1817 /* write */ 1818 imx_uart_writel(sport, c, URTX0); 1819 1820 /* flush */ 1821 do { 1822 status = imx_uart_readl(sport, USR2); 1823 } while (~status & USR2_TXDC); 1824 } 1825 #endif 1826 1827 /* called with port.lock taken and irqs off or from .probe without locking */ 1828 static int imx_uart_rs485_config(struct uart_port *port, 1829 struct serial_rs485 *rs485conf) 1830 { 1831 struct imx_port *sport = (struct imx_port *)port; 1832 u32 ucr2; 1833 1834 /* unimplemented */ 1835 rs485conf->delay_rts_before_send = 0; 1836 rs485conf->delay_rts_after_send = 0; 1837 1838 /* RTS is required to control the transmitter */ 1839 if (!sport->have_rtscts && !sport->have_rtsgpio) 1840 rs485conf->flags &= ~SER_RS485_ENABLED; 1841 1842 if (rs485conf->flags & SER_RS485_ENABLED) { 1843 /* Enable receiver if low-active RTS signal is requested */ 1844 if (sport->have_rtscts && !sport->have_rtsgpio && 1845 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) 1846 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1847 1848 /* disable transmitter */ 1849 ucr2 = imx_uart_readl(sport, UCR2); 1850 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) 1851 imx_uart_rts_active(sport, &ucr2); 1852 else 1853 imx_uart_rts_inactive(sport, &ucr2); 1854 imx_uart_writel(sport, ucr2, UCR2); 1855 } 1856 1857 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ 1858 if (!(rs485conf->flags & SER_RS485_ENABLED) || 1859 rs485conf->flags & SER_RS485_RX_DURING_TX) 1860 imx_uart_start_rx(port); 1861 1862 port->rs485 = *rs485conf; 1863 1864 return 0; 1865 } 1866 1867 static const struct uart_ops imx_uart_pops = { 1868 .tx_empty = imx_uart_tx_empty, 1869 .set_mctrl = imx_uart_set_mctrl, 1870 .get_mctrl = imx_uart_get_mctrl, 1871 .stop_tx = imx_uart_stop_tx, 1872 .start_tx = imx_uart_start_tx, 1873 .stop_rx = imx_uart_stop_rx, 1874 .enable_ms = imx_uart_enable_ms, 1875 .break_ctl = imx_uart_break_ctl, 1876 .startup = imx_uart_startup, 1877 .shutdown = imx_uart_shutdown, 1878 .flush_buffer = imx_uart_flush_buffer, 1879 .set_termios = imx_uart_set_termios, 1880 .type = imx_uart_type, 1881 .config_port = imx_uart_config_port, 1882 .verify_port = imx_uart_verify_port, 1883 #if defined(CONFIG_CONSOLE_POLL) 1884 .poll_init = imx_uart_poll_init, 1885 .poll_get_char = imx_uart_poll_get_char, 1886 .poll_put_char = imx_uart_poll_put_char, 1887 #endif 1888 }; 1889 1890 static struct imx_port *imx_uart_ports[UART_NR]; 1891 1892 #ifdef CONFIG_SERIAL_IMX_CONSOLE 1893 static void imx_uart_console_putchar(struct uart_port *port, int ch) 1894 { 1895 struct imx_port *sport = (struct imx_port *)port; 1896 1897 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) 1898 barrier(); 1899 1900 imx_uart_writel(sport, ch, URTX0); 1901 } 1902 1903 /* 1904 * Interrupts are disabled on entering 1905 */ 1906 static void 1907 imx_uart_console_write(struct console *co, const char *s, unsigned int count) 1908 { 1909 struct imx_port *sport = imx_uart_ports[co->index]; 1910 struct imx_port_ucrs old_ucr; 1911 unsigned int ucr1; 1912 unsigned long flags = 0; 1913 int locked = 1; 1914 int retval; 1915 1916 retval = clk_enable(sport->clk_per); 1917 if (retval) 1918 return; 1919 retval = clk_enable(sport->clk_ipg); 1920 if (retval) { 1921 clk_disable(sport->clk_per); 1922 return; 1923 } 1924 1925 if (sport->port.sysrq) 1926 locked = 0; 1927 else if (oops_in_progress) 1928 locked = spin_trylock_irqsave(&sport->port.lock, flags); 1929 else 1930 spin_lock_irqsave(&sport->port.lock, flags); 1931 1932 /* 1933 * First, save UCR1/2/3 and then disable interrupts 1934 */ 1935 imx_uart_ucrs_save(sport, &old_ucr); 1936 ucr1 = old_ucr.ucr1; 1937 1938 if (imx_uart_is_imx1(sport)) 1939 ucr1 |= IMX1_UCR1_UARTCLKEN; 1940 ucr1 |= UCR1_UARTEN; 1941 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); 1942 1943 imx_uart_writel(sport, ucr1, UCR1); 1944 1945 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); 1946 1947 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); 1948 1949 /* 1950 * Finally, wait for transmitter to become empty 1951 * and restore UCR1/2/3 1952 */ 1953 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); 1954 1955 imx_uart_ucrs_restore(sport, &old_ucr); 1956 1957 if (locked) 1958 spin_unlock_irqrestore(&sport->port.lock, flags); 1959 1960 clk_disable(sport->clk_ipg); 1961 clk_disable(sport->clk_per); 1962 } 1963 1964 /* 1965 * If the port was already initialised (eg, by a boot loader), 1966 * try to determine the current setup. 1967 */ 1968 static void __init 1969 imx_uart_console_get_options(struct imx_port *sport, int *baud, 1970 int *parity, int *bits) 1971 { 1972 1973 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { 1974 /* ok, the port was enabled */ 1975 unsigned int ucr2, ubir, ubmr, uartclk; 1976 unsigned int baud_raw; 1977 unsigned int ucfr_rfdiv; 1978 1979 ucr2 = imx_uart_readl(sport, UCR2); 1980 1981 *parity = 'n'; 1982 if (ucr2 & UCR2_PREN) { 1983 if (ucr2 & UCR2_PROE) 1984 *parity = 'o'; 1985 else 1986 *parity = 'e'; 1987 } 1988 1989 if (ucr2 & UCR2_WS) 1990 *bits = 8; 1991 else 1992 *bits = 7; 1993 1994 ubir = imx_uart_readl(sport, UBIR) & 0xffff; 1995 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; 1996 1997 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; 1998 if (ucfr_rfdiv == 6) 1999 ucfr_rfdiv = 7; 2000 else 2001 ucfr_rfdiv = 6 - ucfr_rfdiv; 2002 2003 uartclk = clk_get_rate(sport->clk_per); 2004 uartclk /= ucfr_rfdiv; 2005 2006 { /* 2007 * The next code provides exact computation of 2008 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) 2009 * without need of float support or long long division, 2010 * which would be required to prevent 32bit arithmetic overflow 2011 */ 2012 unsigned int mul = ubir + 1; 2013 unsigned int div = 16 * (ubmr + 1); 2014 unsigned int rem = uartclk % div; 2015 2016 baud_raw = (uartclk / div) * mul; 2017 baud_raw += (rem * mul + div / 2) / div; 2018 *baud = (baud_raw + 50) / 100 * 100; 2019 } 2020 2021 if (*baud != baud_raw) 2022 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", 2023 baud_raw, *baud); 2024 } 2025 } 2026 2027 static int __init 2028 imx_uart_console_setup(struct console *co, char *options) 2029 { 2030 struct imx_port *sport; 2031 int baud = 9600; 2032 int bits = 8; 2033 int parity = 'n'; 2034 int flow = 'n'; 2035 int retval; 2036 2037 /* 2038 * Check whether an invalid uart number has been specified, and 2039 * if so, search for the first available port that does have 2040 * console support. 2041 */ 2042 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) 2043 co->index = 0; 2044 sport = imx_uart_ports[co->index]; 2045 if (sport == NULL) 2046 return -ENODEV; 2047 2048 /* For setting the registers, we only need to enable the ipg clock. */ 2049 retval = clk_prepare_enable(sport->clk_ipg); 2050 if (retval) 2051 goto error_console; 2052 2053 if (options) 2054 uart_parse_options(options, &baud, &parity, &bits, &flow); 2055 else 2056 imx_uart_console_get_options(sport, &baud, &parity, &bits); 2057 2058 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 2059 2060 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); 2061 2062 clk_disable(sport->clk_ipg); 2063 if (retval) { 2064 clk_unprepare(sport->clk_ipg); 2065 goto error_console; 2066 } 2067 2068 retval = clk_prepare(sport->clk_per); 2069 if (retval) 2070 clk_unprepare(sport->clk_ipg); 2071 2072 error_console: 2073 return retval; 2074 } 2075 2076 static struct uart_driver imx_uart_uart_driver; 2077 static struct console imx_uart_console = { 2078 .name = DEV_NAME, 2079 .write = imx_uart_console_write, 2080 .device = uart_console_device, 2081 .setup = imx_uart_console_setup, 2082 .flags = CON_PRINTBUFFER, 2083 .index = -1, 2084 .data = &imx_uart_uart_driver, 2085 }; 2086 2087 #define IMX_CONSOLE &imx_uart_console 2088 2089 #ifdef CONFIG_OF 2090 static void imx_uart_console_early_putchar(struct uart_port *port, int ch) 2091 { 2092 struct imx_port *sport = (struct imx_port *)port; 2093 2094 while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL) 2095 cpu_relax(); 2096 2097 imx_uart_writel(sport, ch, URTX0); 2098 } 2099 2100 static void imx_uart_console_early_write(struct console *con, const char *s, 2101 unsigned count) 2102 { 2103 struct earlycon_device *dev = con->data; 2104 2105 uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar); 2106 } 2107 2108 static int __init 2109 imx_console_early_setup(struct earlycon_device *dev, const char *opt) 2110 { 2111 if (!dev->port.membase) 2112 return -ENODEV; 2113 2114 dev->con->write = imx_uart_console_early_write; 2115 2116 return 0; 2117 } 2118 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup); 2119 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup); 2120 #endif 2121 2122 #else 2123 #define IMX_CONSOLE NULL 2124 #endif 2125 2126 static struct uart_driver imx_uart_uart_driver = { 2127 .owner = THIS_MODULE, 2128 .driver_name = DRIVER_NAME, 2129 .dev_name = DEV_NAME, 2130 .major = SERIAL_IMX_MAJOR, 2131 .minor = MINOR_START, 2132 .nr = ARRAY_SIZE(imx_uart_ports), 2133 .cons = IMX_CONSOLE, 2134 }; 2135 2136 #ifdef CONFIG_OF 2137 /* 2138 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it 2139 * could successfully get all information from dt or a negative errno. 2140 */ 2141 static int imx_uart_probe_dt(struct imx_port *sport, 2142 struct platform_device *pdev) 2143 { 2144 struct device_node *np = pdev->dev.of_node; 2145 int ret; 2146 2147 sport->devdata = of_device_get_match_data(&pdev->dev); 2148 if (!sport->devdata) 2149 /* no device tree device */ 2150 return 1; 2151 2152 ret = of_alias_get_id(np, "serial"); 2153 if (ret < 0) { 2154 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2155 return ret; 2156 } 2157 sport->port.line = ret; 2158 2159 if (of_get_property(np, "uart-has-rtscts", NULL) || 2160 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 2161 sport->have_rtscts = 1; 2162 2163 if (of_get_property(np, "fsl,dte-mode", NULL)) 2164 sport->dte_mode = 1; 2165 2166 if (of_get_property(np, "rts-gpios", NULL)) 2167 sport->have_rtsgpio = 1; 2168 2169 return 0; 2170 } 2171 #else 2172 static inline int imx_uart_probe_dt(struct imx_port *sport, 2173 struct platform_device *pdev) 2174 { 2175 return 1; 2176 } 2177 #endif 2178 2179 static void imx_uart_probe_pdata(struct imx_port *sport, 2180 struct platform_device *pdev) 2181 { 2182 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); 2183 2184 sport->port.line = pdev->id; 2185 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; 2186 2187 if (!pdata) 2188 return; 2189 2190 if (pdata->flags & IMXUART_HAVE_RTSCTS) 2191 sport->have_rtscts = 1; 2192 } 2193 2194 static int imx_uart_probe(struct platform_device *pdev) 2195 { 2196 struct imx_port *sport; 2197 void __iomem *base; 2198 int ret = 0; 2199 u32 ucr1; 2200 struct resource *res; 2201 int txirq, rxirq, rtsirq; 2202 2203 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2204 if (!sport) 2205 return -ENOMEM; 2206 2207 ret = imx_uart_probe_dt(sport, pdev); 2208 if (ret > 0) 2209 imx_uart_probe_pdata(sport, pdev); 2210 else if (ret < 0) 2211 return ret; 2212 2213 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { 2214 dev_err(&pdev->dev, "serial%d out of range\n", 2215 sport->port.line); 2216 return -EINVAL; 2217 } 2218 2219 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2220 base = devm_ioremap_resource(&pdev->dev, res); 2221 if (IS_ERR(base)) 2222 return PTR_ERR(base); 2223 2224 rxirq = platform_get_irq(pdev, 0); 2225 txirq = platform_get_irq(pdev, 1); 2226 rtsirq = platform_get_irq(pdev, 2); 2227 2228 sport->port.dev = &pdev->dev; 2229 sport->port.mapbase = res->start; 2230 sport->port.membase = base; 2231 sport->port.type = PORT_IMX, 2232 sport->port.iotype = UPIO_MEM; 2233 sport->port.irq = rxirq; 2234 sport->port.fifosize = 32; 2235 sport->port.ops = &imx_uart_pops; 2236 sport->port.rs485_config = imx_uart_rs485_config; 2237 sport->port.flags = UPF_BOOT_AUTOCONF; 2238 timer_setup(&sport->timer, imx_uart_timeout, 0); 2239 2240 sport->gpios = mctrl_gpio_init(&sport->port, 0); 2241 if (IS_ERR(sport->gpios)) 2242 return PTR_ERR(sport->gpios); 2243 2244 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2245 if (IS_ERR(sport->clk_ipg)) { 2246 ret = PTR_ERR(sport->clk_ipg); 2247 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); 2248 return ret; 2249 } 2250 2251 sport->clk_per = devm_clk_get(&pdev->dev, "per"); 2252 if (IS_ERR(sport->clk_per)) { 2253 ret = PTR_ERR(sport->clk_per); 2254 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); 2255 return ret; 2256 } 2257 2258 sport->port.uartclk = clk_get_rate(sport->clk_per); 2259 2260 /* For register access, we only need to enable the ipg clock. */ 2261 ret = clk_prepare_enable(sport->clk_ipg); 2262 if (ret) { 2263 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); 2264 return ret; 2265 } 2266 2267 /* initialize shadow register values */ 2268 sport->ucr1 = readl(sport->port.membase + UCR1); 2269 sport->ucr2 = readl(sport->port.membase + UCR2); 2270 sport->ucr3 = readl(sport->port.membase + UCR3); 2271 sport->ucr4 = readl(sport->port.membase + UCR4); 2272 sport->ufcr = readl(sport->port.membase + UFCR); 2273 2274 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485); 2275 2276 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2277 (!sport->have_rtscts && !sport->have_rtsgpio)) 2278 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); 2279 2280 /* 2281 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B) 2282 * signal cannot be set low during transmission in case the 2283 * receiver is off (limitation of the i.MX UART IP). 2284 */ 2285 if (sport->port.rs485.flags & SER_RS485_ENABLED && 2286 sport->have_rtscts && !sport->have_rtsgpio && 2287 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && 2288 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) 2289 dev_err(&pdev->dev, 2290 "low-active RTS not possible when receiver is off, enabling receiver\n"); 2291 2292 imx_uart_rs485_config(&sport->port, &sport->port.rs485); 2293 2294 /* Disable interrupts before requesting them */ 2295 ucr1 = imx_uart_readl(sport, UCR1); 2296 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | 2297 UCR1_TRDYEN | UCR1_RTSDEN); 2298 imx_uart_writel(sport, ucr1, UCR1); 2299 2300 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { 2301 /* 2302 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI 2303 * and influences if UCR3_RI and UCR3_DCD changes the level of RI 2304 * and DCD (when they are outputs) or enables the respective 2305 * irqs. So set this bit early, i.e. before requesting irqs. 2306 */ 2307 u32 ufcr = imx_uart_readl(sport, UFCR); 2308 if (!(ufcr & UFCR_DCEDTE)) 2309 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); 2310 2311 /* 2312 * Disable UCR3_RI and UCR3_DCD irqs. They are also not 2313 * enabled later because they cannot be cleared 2314 * (confirmed on i.MX25) which makes them unusable. 2315 */ 2316 imx_uart_writel(sport, 2317 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR, 2318 UCR3); 2319 2320 } else { 2321 u32 ucr3 = UCR3_DSR; 2322 u32 ufcr = imx_uart_readl(sport, UFCR); 2323 if (ufcr & UFCR_DCEDTE) 2324 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); 2325 2326 if (!imx_uart_is_imx1(sport)) 2327 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; 2328 imx_uart_writel(sport, ucr3, UCR3); 2329 } 2330 2331 clk_disable_unprepare(sport->clk_ipg); 2332 2333 /* 2334 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later 2335 * chips only have one interrupt. 2336 */ 2337 if (txirq > 0) { 2338 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, 2339 dev_name(&pdev->dev), sport); 2340 if (ret) { 2341 dev_err(&pdev->dev, "failed to request rx irq: %d\n", 2342 ret); 2343 return ret; 2344 } 2345 2346 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, 2347 dev_name(&pdev->dev), sport); 2348 if (ret) { 2349 dev_err(&pdev->dev, "failed to request tx irq: %d\n", 2350 ret); 2351 return ret; 2352 } 2353 2354 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, 2355 dev_name(&pdev->dev), sport); 2356 if (ret) { 2357 dev_err(&pdev->dev, "failed to request rts irq: %d\n", 2358 ret); 2359 return ret; 2360 } 2361 } else { 2362 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, 2363 dev_name(&pdev->dev), sport); 2364 if (ret) { 2365 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); 2366 return ret; 2367 } 2368 } 2369 2370 imx_uart_ports[sport->port.line] = sport; 2371 2372 platform_set_drvdata(pdev, sport); 2373 2374 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); 2375 } 2376 2377 static int imx_uart_remove(struct platform_device *pdev) 2378 { 2379 struct imx_port *sport = platform_get_drvdata(pdev); 2380 2381 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); 2382 } 2383 2384 static void imx_uart_restore_context(struct imx_port *sport) 2385 { 2386 unsigned long flags; 2387 2388 spin_lock_irqsave(&sport->port.lock, flags); 2389 if (!sport->context_saved) { 2390 spin_unlock_irqrestore(&sport->port.lock, flags); 2391 return; 2392 } 2393 2394 imx_uart_writel(sport, sport->saved_reg[4], UFCR); 2395 imx_uart_writel(sport, sport->saved_reg[5], UESC); 2396 imx_uart_writel(sport, sport->saved_reg[6], UTIM); 2397 imx_uart_writel(sport, sport->saved_reg[7], UBIR); 2398 imx_uart_writel(sport, sport->saved_reg[8], UBMR); 2399 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); 2400 imx_uart_writel(sport, sport->saved_reg[0], UCR1); 2401 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); 2402 imx_uart_writel(sport, sport->saved_reg[2], UCR3); 2403 imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2404 sport->context_saved = false; 2405 spin_unlock_irqrestore(&sport->port.lock, flags); 2406 } 2407 2408 static void imx_uart_save_context(struct imx_port *sport) 2409 { 2410 unsigned long flags; 2411 2412 /* Save necessary regs */ 2413 spin_lock_irqsave(&sport->port.lock, flags); 2414 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 2415 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 2416 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); 2417 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); 2418 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); 2419 sport->saved_reg[5] = imx_uart_readl(sport, UESC); 2420 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); 2421 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); 2422 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 2423 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2424 sport->context_saved = true; 2425 spin_unlock_irqrestore(&sport->port.lock, flags); 2426 } 2427 2428 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) 2429 { 2430 u32 ucr3; 2431 2432 ucr3 = imx_uart_readl(sport, UCR3); 2433 if (on) { 2434 imx_uart_writel(sport, USR1_AWAKE, USR1); 2435 ucr3 |= UCR3_AWAKEN; 2436 } else { 2437 ucr3 &= ~UCR3_AWAKEN; 2438 } 2439 imx_uart_writel(sport, ucr3, UCR3); 2440 2441 if (sport->have_rtscts) { 2442 u32 ucr1 = imx_uart_readl(sport, UCR1); 2443 if (on) 2444 ucr1 |= UCR1_RTSDEN; 2445 else 2446 ucr1 &= ~UCR1_RTSDEN; 2447 imx_uart_writel(sport, ucr1, UCR1); 2448 } 2449 } 2450 2451 static int imx_uart_suspend_noirq(struct device *dev) 2452 { 2453 struct imx_port *sport = dev_get_drvdata(dev); 2454 2455 imx_uart_save_context(sport); 2456 2457 clk_disable(sport->clk_ipg); 2458 2459 pinctrl_pm_select_sleep_state(dev); 2460 2461 return 0; 2462 } 2463 2464 static int imx_uart_resume_noirq(struct device *dev) 2465 { 2466 struct imx_port *sport = dev_get_drvdata(dev); 2467 int ret; 2468 2469 pinctrl_pm_select_default_state(dev); 2470 2471 ret = clk_enable(sport->clk_ipg); 2472 if (ret) 2473 return ret; 2474 2475 imx_uart_restore_context(sport); 2476 2477 return 0; 2478 } 2479 2480 static int imx_uart_suspend(struct device *dev) 2481 { 2482 struct imx_port *sport = dev_get_drvdata(dev); 2483 int ret; 2484 2485 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2486 disable_irq(sport->port.irq); 2487 2488 ret = clk_prepare_enable(sport->clk_ipg); 2489 if (ret) 2490 return ret; 2491 2492 /* enable wakeup from i.MX UART */ 2493 imx_uart_enable_wakeup(sport, true); 2494 2495 return 0; 2496 } 2497 2498 static int imx_uart_resume(struct device *dev) 2499 { 2500 struct imx_port *sport = dev_get_drvdata(dev); 2501 2502 /* disable wakeup from i.MX UART */ 2503 imx_uart_enable_wakeup(sport, false); 2504 2505 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2506 enable_irq(sport->port.irq); 2507 2508 clk_disable_unprepare(sport->clk_ipg); 2509 2510 return 0; 2511 } 2512 2513 static int imx_uart_freeze(struct device *dev) 2514 { 2515 struct imx_port *sport = dev_get_drvdata(dev); 2516 2517 uart_suspend_port(&imx_uart_uart_driver, &sport->port); 2518 2519 return clk_prepare_enable(sport->clk_ipg); 2520 } 2521 2522 static int imx_uart_thaw(struct device *dev) 2523 { 2524 struct imx_port *sport = dev_get_drvdata(dev); 2525 2526 uart_resume_port(&imx_uart_uart_driver, &sport->port); 2527 2528 clk_disable_unprepare(sport->clk_ipg); 2529 2530 return 0; 2531 } 2532 2533 static const struct dev_pm_ops imx_uart_pm_ops = { 2534 .suspend_noirq = imx_uart_suspend_noirq, 2535 .resume_noirq = imx_uart_resume_noirq, 2536 .freeze_noirq = imx_uart_suspend_noirq, 2537 .restore_noirq = imx_uart_resume_noirq, 2538 .suspend = imx_uart_suspend, 2539 .resume = imx_uart_resume, 2540 .freeze = imx_uart_freeze, 2541 .thaw = imx_uart_thaw, 2542 .restore = imx_uart_thaw, 2543 }; 2544 2545 static struct platform_driver imx_uart_platform_driver = { 2546 .probe = imx_uart_probe, 2547 .remove = imx_uart_remove, 2548 2549 .id_table = imx_uart_devtype, 2550 .driver = { 2551 .name = "imx-uart", 2552 .of_match_table = imx_uart_dt_ids, 2553 .pm = &imx_uart_pm_ops, 2554 }, 2555 }; 2556 2557 static int __init imx_uart_init(void) 2558 { 2559 int ret = uart_register_driver(&imx_uart_uart_driver); 2560 2561 if (ret) 2562 return ret; 2563 2564 ret = platform_driver_register(&imx_uart_platform_driver); 2565 if (ret != 0) 2566 uart_unregister_driver(&imx_uart_uart_driver); 2567 2568 return ret; 2569 } 2570 2571 static void __exit imx_uart_exit(void) 2572 { 2573 platform_driver_unregister(&imx_uart_platform_driver); 2574 uart_unregister_driver(&imx_uart_uart_driver); 2575 } 2576 2577 module_init(imx_uart_init); 2578 module_exit(imx_uart_exit); 2579 2580 MODULE_AUTHOR("Sascha Hauer"); 2581 MODULE_DESCRIPTION("IMX generic serial port driver"); 2582 MODULE_LICENSE("GPL"); 2583 MODULE_ALIAS("platform:imx-uart"); 2584