xref: /linux/drivers/tty/serial/imx.c (revision 0d456bad36d42d16022be045c8a53ddbb59ee478) 
1 /*
2  *  Driver for Motorola IMX serial ports
3  *
4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5  *
6  *  Author: Sascha Hauer <sascha@saschahauer.de>
7  *  Copyright (C) 2004 Pengutronix
8  *
9  *  Copyright (C) 2009 emlix GmbH
10  *  Author: Fabian Godehardt (added IrDA support for iMX)
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This program is distributed in the hope that it will be useful,
18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  * GNU General Public License for more details.
21  *
22  * You should have received a copy of the GNU General Public License
23  * along with this program; if not, write to the Free Software
24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
25  *
26  * [29-Mar-2005] Mike Lee
27  * Added hardware handshake
28  */
29 
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33 
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/pinctrl/consumer.h>
51 
52 #include <asm/io.h>
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55 
56 /* Register definitions */
57 #define URXD0 0x0  /* Receiver Register */
58 #define URTX0 0x40 /* Transmitter Register */
59 #define UCR1  0x80 /* Control Register 1 */
60 #define UCR2  0x84 /* Control Register 2 */
61 #define UCR3  0x88 /* Control Register 3 */
62 #define UCR4  0x8c /* Control Register 4 */
63 #define UFCR  0x90 /* FIFO Control Register */
64 #define USR1  0x94 /* Status Register 1 */
65 #define USR2  0x98 /* Status Register 2 */
66 #define UESC  0x9c /* Escape Character Register */
67 #define UTIM  0xa0 /* Escape Timer Register */
68 #define UBIR  0xa4 /* BRM Incremental Register */
69 #define UBMR  0xa8 /* BRM Modulator Register */
70 #define UBRC  0xac /* Baud Rate Count Register */
71 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
72 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
73 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
74 
75 /* UART Control Register Bit Fields.*/
76 #define  URXD_CHARRDY    (1<<15)
77 #define  URXD_ERR        (1<<14)
78 #define  URXD_OVRRUN     (1<<13)
79 #define  URXD_FRMERR     (1<<12)
80 #define  URXD_BRK        (1<<11)
81 #define  URXD_PRERR      (1<<10)
82 #define  UCR1_ADEN       (1<<15) /* Auto detect interrupt */
83 #define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
84 #define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
85 #define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
86 #define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
87 #define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
88 #define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
89 #define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
90 #define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
91 #define  UCR1_SNDBRK     (1<<4)	 /* Send break */
92 #define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
93 #define  IMX1_UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled, i.mx1 only */
94 #define  UCR1_DOZE       (1<<1)	 /* Doze */
95 #define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
96 #define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
97 #define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
98 #define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
99 #define  UCR2_CTS        (1<<12) /* Clear to send */
100 #define  UCR2_ESCEN      (1<<11) /* Escape enable */
101 #define  UCR2_PREN       (1<<8)  /* Parity enable */
102 #define  UCR2_PROE       (1<<7)  /* Parity odd/even */
103 #define  UCR2_STPB       (1<<6)	 /* Stop */
104 #define  UCR2_WS         (1<<5)	 /* Word size */
105 #define  UCR2_RTSEN      (1<<4)	 /* Request to send interrupt enable */
106 #define  UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
107 #define  UCR2_TXEN       (1<<2)	 /* Transmitter enabled */
108 #define  UCR2_RXEN       (1<<1)	 /* Receiver enabled */
109 #define  UCR2_SRST 	 (1<<0)	 /* SW reset */
110 #define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
111 #define  UCR3_PARERREN   (1<<12) /* Parity enable */
112 #define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
113 #define  UCR3_DSR        (1<<10) /* Data set ready */
114 #define  UCR3_DCD        (1<<9)  /* Data carrier detect */
115 #define  UCR3_RI         (1<<8)  /* Ring indicator */
116 #define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
117 #define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
118 #define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
119 #define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
120 #define  IMX21_UCR3_RXDMUXSEL	 (1<<2)  /* RXD Muxed Input Select */
121 #define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
122 #define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
123 #define  UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
124 #define  UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
125 #define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
126 #define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
127 #define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
128 #define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
129 #define  UCR4_IRSC  	 (1<<5)  /* IR special case */
130 #define  UCR4_TCEN  	 (1<<3)  /* Transmit complete interrupt enable */
131 #define  UCR4_BKEN  	 (1<<2)  /* Break condition interrupt enable */
132 #define  UCR4_OREN  	 (1<<1)  /* Receiver overrun interrupt enable */
133 #define  UCR4_DREN  	 (1<<0)  /* Recv data ready interrupt enable */
134 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
135 #define  UFCR_DCEDTE	 (1<<6)  /* DCE/DTE mode select */
136 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
137 #define  UFCR_RFDIV_REG(x)	(((x) < 7 ? 6 - (x) : 6) << 7)
138 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
139 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
140 #define  USR1_RTSS  	 (1<<14) /* RTS pin status */
141 #define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
142 #define  USR1_RTSD  	 (1<<12) /* RTS delta */
143 #define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
144 #define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
145 #define  USR1_RRDY       (1<<9)	 /* Receiver ready interrupt/dma flag */
146 #define  USR1_TIMEOUT    (1<<7)	 /* Receive timeout interrupt status */
147 #define  USR1_RXDS  	 (1<<6)	 /* Receiver idle interrupt flag */
148 #define  USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
149 #define  USR1_AWAKE 	 (1<<4)	 /* Aysnc wake interrupt flag */
150 #define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
151 #define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
152 #define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
153 #define  USR2_IDLE  	 (1<<12) /* Idle condition */
154 #define  USR2_IRINT 	 (1<<8)	 /* Serial infrared interrupt flag */
155 #define  USR2_WAKE  	 (1<<7)	 /* Wake */
156 #define  USR2_RTSF  	 (1<<4)	 /* RTS edge interrupt flag */
157 #define  USR2_TXDC  	 (1<<3)	 /* Transmitter complete */
158 #define  USR2_BRCD  	 (1<<2)	 /* Break condition */
159 #define  USR2_ORE        (1<<1)	 /* Overrun error */
160 #define  USR2_RDR        (1<<0)	 /* Recv data ready */
161 #define  UTS_FRCPERR	 (1<<13) /* Force parity error */
162 #define  UTS_LOOP        (1<<12) /* Loop tx and rx */
163 #define  UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
164 #define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
165 #define  UTS_TXFULL 	 (1<<4)	 /* TxFIFO full */
166 #define  UTS_RXFULL 	 (1<<3)	 /* RxFIFO full */
167 #define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
168 
169 /* We've been assigned a range on the "Low-density serial ports" major */
170 #define SERIAL_IMX_MAJOR        207
171 #define MINOR_START	        16
172 #define DEV_NAME		"ttymxc"
173 
174 /*
175  * This determines how often we check the modem status signals
176  * for any change.  They generally aren't connected to an IRQ
177  * so we have to poll them.  We also check immediately before
178  * filling the TX fifo incase CTS has been dropped.
179  */
180 #define MCTRL_TIMEOUT	(250*HZ/1000)
181 
182 #define DRIVER_NAME "IMX-uart"
183 
184 #define UART_NR 8
185 
186 /* i.mx21 type uart runs on all i.mx except i.mx1 */
187 enum imx_uart_type {
188 	IMX1_UART,
189 	IMX21_UART,
190 };
191 
192 /* device type dependent stuff */
193 struct imx_uart_data {
194 	unsigned uts_reg;
195 	enum imx_uart_type devtype;
196 };
197 
198 struct imx_port {
199 	struct uart_port	port;
200 	struct timer_list	timer;
201 	unsigned int		old_status;
202 	int			txirq,rxirq,rtsirq;
203 	unsigned int		have_rtscts:1;
204 	unsigned int		use_irda:1;
205 	unsigned int		irda_inv_rx:1;
206 	unsigned int		irda_inv_tx:1;
207 	unsigned short		trcv_delay; /* transceiver delay */
208 	struct clk		*clk_ipg;
209 	struct clk		*clk_per;
210 	const struct imx_uart_data *devdata;
211 };
212 
213 struct imx_port_ucrs {
214 	unsigned int	ucr1;
215 	unsigned int	ucr2;
216 	unsigned int	ucr3;
217 };
218 
219 #ifdef CONFIG_IRDA
220 #define USE_IRDA(sport)	((sport)->use_irda)
221 #else
222 #define USE_IRDA(sport)	(0)
223 #endif
224 
225 static struct imx_uart_data imx_uart_devdata[] = {
226 	[IMX1_UART] = {
227 		.uts_reg = IMX1_UTS,
228 		.devtype = IMX1_UART,
229 	},
230 	[IMX21_UART] = {
231 		.uts_reg = IMX21_UTS,
232 		.devtype = IMX21_UART,
233 	},
234 };
235 
236 static struct platform_device_id imx_uart_devtype[] = {
237 	{
238 		.name = "imx1-uart",
239 		.driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
240 	}, {
241 		.name = "imx21-uart",
242 		.driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
243 	}, {
244 		/* sentinel */
245 	}
246 };
247 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
248 
249 static struct of_device_id imx_uart_dt_ids[] = {
250 	{ .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
251 	{ .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
252 	{ /* sentinel */ }
253 };
254 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
255 
256 static inline unsigned uts_reg(struct imx_port *sport)
257 {
258 	return sport->devdata->uts_reg;
259 }
260 
261 static inline int is_imx1_uart(struct imx_port *sport)
262 {
263 	return sport->devdata->devtype == IMX1_UART;
264 }
265 
266 static inline int is_imx21_uart(struct imx_port *sport)
267 {
268 	return sport->devdata->devtype == IMX21_UART;
269 }
270 
271 /*
272  * Save and restore functions for UCR1, UCR2 and UCR3 registers
273  */
274 static void imx_port_ucrs_save(struct uart_port *port,
275 			       struct imx_port_ucrs *ucr)
276 {
277 	/* save control registers */
278 	ucr->ucr1 = readl(port->membase + UCR1);
279 	ucr->ucr2 = readl(port->membase + UCR2);
280 	ucr->ucr3 = readl(port->membase + UCR3);
281 }
282 
283 static void imx_port_ucrs_restore(struct uart_port *port,
284 				  struct imx_port_ucrs *ucr)
285 {
286 	/* restore control registers */
287 	writel(ucr->ucr1, port->membase + UCR1);
288 	writel(ucr->ucr2, port->membase + UCR2);
289 	writel(ucr->ucr3, port->membase + UCR3);
290 }
291 
292 /*
293  * Handle any change of modem status signal since we were last called.
294  */
295 static void imx_mctrl_check(struct imx_port *sport)
296 {
297 	unsigned int status, changed;
298 
299 	status = sport->port.ops->get_mctrl(&sport->port);
300 	changed = status ^ sport->old_status;
301 
302 	if (changed == 0)
303 		return;
304 
305 	sport->old_status = status;
306 
307 	if (changed & TIOCM_RI)
308 		sport->port.icount.rng++;
309 	if (changed & TIOCM_DSR)
310 		sport->port.icount.dsr++;
311 	if (changed & TIOCM_CAR)
312 		uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
313 	if (changed & TIOCM_CTS)
314 		uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
315 
316 	wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
317 }
318 
319 /*
320  * This is our per-port timeout handler, for checking the
321  * modem status signals.
322  */
323 static void imx_timeout(unsigned long data)
324 {
325 	struct imx_port *sport = (struct imx_port *)data;
326 	unsigned long flags;
327 
328 	if (sport->port.state) {
329 		spin_lock_irqsave(&sport->port.lock, flags);
330 		imx_mctrl_check(sport);
331 		spin_unlock_irqrestore(&sport->port.lock, flags);
332 
333 		mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
334 	}
335 }
336 
337 /*
338  * interrupts disabled on entry
339  */
340 static void imx_stop_tx(struct uart_port *port)
341 {
342 	struct imx_port *sport = (struct imx_port *)port;
343 	unsigned long temp;
344 
345 	if (USE_IRDA(sport)) {
346 		/* half duplex - wait for end of transmission */
347 		int n = 256;
348 		while ((--n > 0) &&
349 		      !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
350 			udelay(5);
351 			barrier();
352 		}
353 		/*
354 		 * irda transceiver - wait a bit more to avoid
355 		 * cutoff, hardware dependent
356 		 */
357 		udelay(sport->trcv_delay);
358 
359 		/*
360 		 * half duplex - reactivate receive mode,
361 		 * flush receive pipe echo crap
362 		 */
363 		if (readl(sport->port.membase + USR2) & USR2_TXDC) {
364 			temp = readl(sport->port.membase + UCR1);
365 			temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
366 			writel(temp, sport->port.membase + UCR1);
367 
368 			temp = readl(sport->port.membase + UCR4);
369 			temp &= ~(UCR4_TCEN);
370 			writel(temp, sport->port.membase + UCR4);
371 
372 			while (readl(sport->port.membase + URXD0) &
373 			       URXD_CHARRDY)
374 				barrier();
375 
376 			temp = readl(sport->port.membase + UCR1);
377 			temp |= UCR1_RRDYEN;
378 			writel(temp, sport->port.membase + UCR1);
379 
380 			temp = readl(sport->port.membase + UCR4);
381 			temp |= UCR4_DREN;
382 			writel(temp, sport->port.membase + UCR4);
383 		}
384 		return;
385 	}
386 
387 	temp = readl(sport->port.membase + UCR1);
388 	writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
389 }
390 
391 /*
392  * interrupts disabled on entry
393  */
394 static void imx_stop_rx(struct uart_port *port)
395 {
396 	struct imx_port *sport = (struct imx_port *)port;
397 	unsigned long temp;
398 
399 	temp = readl(sport->port.membase + UCR2);
400 	writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
401 }
402 
403 /*
404  * Set the modem control timer to fire immediately.
405  */
406 static void imx_enable_ms(struct uart_port *port)
407 {
408 	struct imx_port *sport = (struct imx_port *)port;
409 
410 	mod_timer(&sport->timer, jiffies);
411 }
412 
413 static inline void imx_transmit_buffer(struct imx_port *sport)
414 {
415 	struct circ_buf *xmit = &sport->port.state->xmit;
416 
417 	while (!uart_circ_empty(xmit) &&
418 			!(readl(sport->port.membase + uts_reg(sport))
419 				& UTS_TXFULL)) {
420 		/* send xmit->buf[xmit->tail]
421 		 * out the port here */
422 		writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
423 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
424 		sport->port.icount.tx++;
425 	}
426 
427 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
428 		uart_write_wakeup(&sport->port);
429 
430 	if (uart_circ_empty(xmit))
431 		imx_stop_tx(&sport->port);
432 }
433 
434 /*
435  * interrupts disabled on entry
436  */
437 static void imx_start_tx(struct uart_port *port)
438 {
439 	struct imx_port *sport = (struct imx_port *)port;
440 	unsigned long temp;
441 
442 	if (USE_IRDA(sport)) {
443 		/* half duplex in IrDA mode; have to disable receive mode */
444 		temp = readl(sport->port.membase + UCR4);
445 		temp &= ~(UCR4_DREN);
446 		writel(temp, sport->port.membase + UCR4);
447 
448 		temp = readl(sport->port.membase + UCR1);
449 		temp &= ~(UCR1_RRDYEN);
450 		writel(temp, sport->port.membase + UCR1);
451 	}
452 
453 	temp = readl(sport->port.membase + UCR1);
454 	writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
455 
456 	if (USE_IRDA(sport)) {
457 		temp = readl(sport->port.membase + UCR1);
458 		temp |= UCR1_TRDYEN;
459 		writel(temp, sport->port.membase + UCR1);
460 
461 		temp = readl(sport->port.membase + UCR4);
462 		temp |= UCR4_TCEN;
463 		writel(temp, sport->port.membase + UCR4);
464 	}
465 
466 	if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
467 		imx_transmit_buffer(sport);
468 }
469 
470 static irqreturn_t imx_rtsint(int irq, void *dev_id)
471 {
472 	struct imx_port *sport = dev_id;
473 	unsigned int val;
474 	unsigned long flags;
475 
476 	spin_lock_irqsave(&sport->port.lock, flags);
477 
478 	writel(USR1_RTSD, sport->port.membase + USR1);
479 	val = readl(sport->port.membase + USR1) & USR1_RTSS;
480 	uart_handle_cts_change(&sport->port, !!val);
481 	wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
482 
483 	spin_unlock_irqrestore(&sport->port.lock, flags);
484 	return IRQ_HANDLED;
485 }
486 
487 static irqreturn_t imx_txint(int irq, void *dev_id)
488 {
489 	struct imx_port *sport = dev_id;
490 	struct circ_buf *xmit = &sport->port.state->xmit;
491 	unsigned long flags;
492 
493 	spin_lock_irqsave(&sport->port.lock,flags);
494 	if (sport->port.x_char)
495 	{
496 		/* Send next char */
497 		writel(sport->port.x_char, sport->port.membase + URTX0);
498 		goto out;
499 	}
500 
501 	if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
502 		imx_stop_tx(&sport->port);
503 		goto out;
504 	}
505 
506 	imx_transmit_buffer(sport);
507 
508 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
509 		uart_write_wakeup(&sport->port);
510 
511 out:
512 	spin_unlock_irqrestore(&sport->port.lock,flags);
513 	return IRQ_HANDLED;
514 }
515 
516 static irqreturn_t imx_rxint(int irq, void *dev_id)
517 {
518 	struct imx_port *sport = dev_id;
519 	unsigned int rx,flg,ignored = 0;
520 	struct tty_struct *tty = sport->port.state->port.tty;
521 	unsigned long flags, temp;
522 
523 	spin_lock_irqsave(&sport->port.lock,flags);
524 
525 	while (readl(sport->port.membase + USR2) & USR2_RDR) {
526 		flg = TTY_NORMAL;
527 		sport->port.icount.rx++;
528 
529 		rx = readl(sport->port.membase + URXD0);
530 
531 		temp = readl(sport->port.membase + USR2);
532 		if (temp & USR2_BRCD) {
533 			writel(USR2_BRCD, sport->port.membase + USR2);
534 			if (uart_handle_break(&sport->port))
535 				continue;
536 		}
537 
538 		if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
539 			continue;
540 
541 		if (unlikely(rx & URXD_ERR)) {
542 			if (rx & URXD_BRK)
543 				sport->port.icount.brk++;
544 			else if (rx & URXD_PRERR)
545 				sport->port.icount.parity++;
546 			else if (rx & URXD_FRMERR)
547 				sport->port.icount.frame++;
548 			if (rx & URXD_OVRRUN)
549 				sport->port.icount.overrun++;
550 
551 			if (rx & sport->port.ignore_status_mask) {
552 				if (++ignored > 100)
553 					goto out;
554 				continue;
555 			}
556 
557 			rx &= sport->port.read_status_mask;
558 
559 			if (rx & URXD_BRK)
560 				flg = TTY_BREAK;
561 			else if (rx & URXD_PRERR)
562 				flg = TTY_PARITY;
563 			else if (rx & URXD_FRMERR)
564 				flg = TTY_FRAME;
565 			if (rx & URXD_OVRRUN)
566 				flg = TTY_OVERRUN;
567 
568 #ifdef SUPPORT_SYSRQ
569 			sport->port.sysrq = 0;
570 #endif
571 		}
572 
573 		tty_insert_flip_char(tty, rx, flg);
574 	}
575 
576 out:
577 	spin_unlock_irqrestore(&sport->port.lock,flags);
578 	tty_flip_buffer_push(tty);
579 	return IRQ_HANDLED;
580 }
581 
582 static irqreturn_t imx_int(int irq, void *dev_id)
583 {
584 	struct imx_port *sport = dev_id;
585 	unsigned int sts;
586 
587 	sts = readl(sport->port.membase + USR1);
588 
589 	if (sts & USR1_RRDY)
590 		imx_rxint(irq, dev_id);
591 
592 	if (sts & USR1_TRDY &&
593 			readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
594 		imx_txint(irq, dev_id);
595 
596 	if (sts & USR1_RTSD)
597 		imx_rtsint(irq, dev_id);
598 
599 	if (sts & USR1_AWAKE)
600 		writel(USR1_AWAKE, sport->port.membase + USR1);
601 
602 	return IRQ_HANDLED;
603 }
604 
605 /*
606  * Return TIOCSER_TEMT when transmitter is not busy.
607  */
608 static unsigned int imx_tx_empty(struct uart_port *port)
609 {
610 	struct imx_port *sport = (struct imx_port *)port;
611 
612 	return (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
613 }
614 
615 /*
616  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
617  */
618 static unsigned int imx_get_mctrl(struct uart_port *port)
619 {
620 	struct imx_port *sport = (struct imx_port *)port;
621 	unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
622 
623 	if (readl(sport->port.membase + USR1) & USR1_RTSS)
624 		tmp |= TIOCM_CTS;
625 
626 	if (readl(sport->port.membase + UCR2) & UCR2_CTS)
627 		tmp |= TIOCM_RTS;
628 
629 	return tmp;
630 }
631 
632 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
633 {
634 	struct imx_port *sport = (struct imx_port *)port;
635 	unsigned long temp;
636 
637 	temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
638 
639 	if (mctrl & TIOCM_RTS)
640 		temp |= UCR2_CTS;
641 
642 	writel(temp, sport->port.membase + UCR2);
643 }
644 
645 /*
646  * Interrupts always disabled.
647  */
648 static void imx_break_ctl(struct uart_port *port, int break_state)
649 {
650 	struct imx_port *sport = (struct imx_port *)port;
651 	unsigned long flags, temp;
652 
653 	spin_lock_irqsave(&sport->port.lock, flags);
654 
655 	temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
656 
657 	if ( break_state != 0 )
658 		temp |= UCR1_SNDBRK;
659 
660 	writel(temp, sport->port.membase + UCR1);
661 
662 	spin_unlock_irqrestore(&sport->port.lock, flags);
663 }
664 
665 #define TXTL 2 /* reset default */
666 #define RXTL 1 /* reset default */
667 
668 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
669 {
670 	unsigned int val;
671 
672 	/* set receiver / transmitter trigger level */
673 	val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
674 	val |= TXTL << UFCR_TXTL_SHF | RXTL;
675 	writel(val, sport->port.membase + UFCR);
676 	return 0;
677 }
678 
679 /* half the RX buffer size */
680 #define CTSTL 16
681 
682 static int imx_startup(struct uart_port *port)
683 {
684 	struct imx_port *sport = (struct imx_port *)port;
685 	int retval;
686 	unsigned long flags, temp;
687 
688 	imx_setup_ufcr(sport, 0);
689 
690 	/* disable the DREN bit (Data Ready interrupt enable) before
691 	 * requesting IRQs
692 	 */
693 	temp = readl(sport->port.membase + UCR4);
694 
695 	if (USE_IRDA(sport))
696 		temp |= UCR4_IRSC;
697 
698 	/* set the trigger level for CTS */
699 	temp &= ~(UCR4_CTSTL_MASK<<  UCR4_CTSTL_SHF);
700 	temp |= CTSTL<<  UCR4_CTSTL_SHF;
701 
702 	writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
703 
704 	if (USE_IRDA(sport)) {
705 		/* reset fifo's and state machines */
706 		int i = 100;
707 		temp = readl(sport->port.membase + UCR2);
708 		temp &= ~UCR2_SRST;
709 		writel(temp, sport->port.membase + UCR2);
710 		while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
711 		    (--i > 0)) {
712 			udelay(1);
713 		}
714 	}
715 
716 	/*
717 	 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
718 	 * chips only have one interrupt.
719 	 */
720 	if (sport->txirq > 0) {
721 		retval = request_irq(sport->rxirq, imx_rxint, 0,
722 				DRIVER_NAME, sport);
723 		if (retval)
724 			goto error_out1;
725 
726 		retval = request_irq(sport->txirq, imx_txint, 0,
727 				DRIVER_NAME, sport);
728 		if (retval)
729 			goto error_out2;
730 
731 		/* do not use RTS IRQ on IrDA */
732 		if (!USE_IRDA(sport)) {
733 			retval = request_irq(sport->rtsirq, imx_rtsint, 0,
734 					DRIVER_NAME, sport);
735 			if (retval)
736 				goto error_out3;
737 		}
738 	} else {
739 		retval = request_irq(sport->port.irq, imx_int, 0,
740 				DRIVER_NAME, sport);
741 		if (retval) {
742 			free_irq(sport->port.irq, sport);
743 			goto error_out1;
744 		}
745 	}
746 
747 	spin_lock_irqsave(&sport->port.lock, flags);
748 	/*
749 	 * Finally, clear and enable interrupts
750 	 */
751 	writel(USR1_RTSD, sport->port.membase + USR1);
752 
753 	temp = readl(sport->port.membase + UCR1);
754 	temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
755 
756 	if (USE_IRDA(sport)) {
757 		temp |= UCR1_IREN;
758 		temp &= ~(UCR1_RTSDEN);
759 	}
760 
761 	writel(temp, sport->port.membase + UCR1);
762 
763 	temp = readl(sport->port.membase + UCR2);
764 	temp |= (UCR2_RXEN | UCR2_TXEN);
765 	writel(temp, sport->port.membase + UCR2);
766 
767 	if (USE_IRDA(sport)) {
768 		/* clear RX-FIFO */
769 		int i = 64;
770 		while ((--i > 0) &&
771 			(readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
772 			barrier();
773 		}
774 	}
775 
776 	if (is_imx21_uart(sport)) {
777 		temp = readl(sport->port.membase + UCR3);
778 		temp |= IMX21_UCR3_RXDMUXSEL;
779 		writel(temp, sport->port.membase + UCR3);
780 	}
781 
782 	if (USE_IRDA(sport)) {
783 		temp = readl(sport->port.membase + UCR4);
784 		if (sport->irda_inv_rx)
785 			temp |= UCR4_INVR;
786 		else
787 			temp &= ~(UCR4_INVR);
788 		writel(temp | UCR4_DREN, sport->port.membase + UCR4);
789 
790 		temp = readl(sport->port.membase + UCR3);
791 		if (sport->irda_inv_tx)
792 			temp |= UCR3_INVT;
793 		else
794 			temp &= ~(UCR3_INVT);
795 		writel(temp, sport->port.membase + UCR3);
796 	}
797 
798 	/*
799 	 * Enable modem status interrupts
800 	 */
801 	imx_enable_ms(&sport->port);
802 	spin_unlock_irqrestore(&sport->port.lock,flags);
803 
804 	if (USE_IRDA(sport)) {
805 		struct imxuart_platform_data *pdata;
806 		pdata = sport->port.dev->platform_data;
807 		sport->irda_inv_rx = pdata->irda_inv_rx;
808 		sport->irda_inv_tx = pdata->irda_inv_tx;
809 		sport->trcv_delay = pdata->transceiver_delay;
810 		if (pdata->irda_enable)
811 			pdata->irda_enable(1);
812 	}
813 
814 	return 0;
815 
816 error_out3:
817 	if (sport->txirq)
818 		free_irq(sport->txirq, sport);
819 error_out2:
820 	if (sport->rxirq)
821 		free_irq(sport->rxirq, sport);
822 error_out1:
823 	return retval;
824 }
825 
826 static void imx_shutdown(struct uart_port *port)
827 {
828 	struct imx_port *sport = (struct imx_port *)port;
829 	unsigned long temp;
830 	unsigned long flags;
831 
832 	spin_lock_irqsave(&sport->port.lock, flags);
833 	temp = readl(sport->port.membase + UCR2);
834 	temp &= ~(UCR2_TXEN);
835 	writel(temp, sport->port.membase + UCR2);
836 	spin_unlock_irqrestore(&sport->port.lock, flags);
837 
838 	if (USE_IRDA(sport)) {
839 		struct imxuart_platform_data *pdata;
840 		pdata = sport->port.dev->platform_data;
841 		if (pdata->irda_enable)
842 			pdata->irda_enable(0);
843 	}
844 
845 	/*
846 	 * Stop our timer.
847 	 */
848 	del_timer_sync(&sport->timer);
849 
850 	/*
851 	 * Free the interrupts
852 	 */
853 	if (sport->txirq > 0) {
854 		if (!USE_IRDA(sport))
855 			free_irq(sport->rtsirq, sport);
856 		free_irq(sport->txirq, sport);
857 		free_irq(sport->rxirq, sport);
858 	} else
859 		free_irq(sport->port.irq, sport);
860 
861 	/*
862 	 * Disable all interrupts, port and break condition.
863 	 */
864 
865 	spin_lock_irqsave(&sport->port.lock, flags);
866 	temp = readl(sport->port.membase + UCR1);
867 	temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
868 	if (USE_IRDA(sport))
869 		temp &= ~(UCR1_IREN);
870 
871 	writel(temp, sport->port.membase + UCR1);
872 	spin_unlock_irqrestore(&sport->port.lock, flags);
873 }
874 
875 static void
876 imx_set_termios(struct uart_port *port, struct ktermios *termios,
877 		   struct ktermios *old)
878 {
879 	struct imx_port *sport = (struct imx_port *)port;
880 	unsigned long flags;
881 	unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
882 	unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
883 	unsigned int div, ufcr;
884 	unsigned long num, denom;
885 	uint64_t tdiv64;
886 
887 	/*
888 	 * If we don't support modem control lines, don't allow
889 	 * these to be set.
890 	 */
891 	if (0) {
892 		termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
893 		termios->c_cflag |= CLOCAL;
894 	}
895 
896 	/*
897 	 * We only support CS7 and CS8.
898 	 */
899 	while ((termios->c_cflag & CSIZE) != CS7 &&
900 	       (termios->c_cflag & CSIZE) != CS8) {
901 		termios->c_cflag &= ~CSIZE;
902 		termios->c_cflag |= old_csize;
903 		old_csize = CS8;
904 	}
905 
906 	if ((termios->c_cflag & CSIZE) == CS8)
907 		ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
908 	else
909 		ucr2 = UCR2_SRST | UCR2_IRTS;
910 
911 	if (termios->c_cflag & CRTSCTS) {
912 		if( sport->have_rtscts ) {
913 			ucr2 &= ~UCR2_IRTS;
914 			ucr2 |= UCR2_CTSC;
915 		} else {
916 			termios->c_cflag &= ~CRTSCTS;
917 		}
918 	}
919 
920 	if (termios->c_cflag & CSTOPB)
921 		ucr2 |= UCR2_STPB;
922 	if (termios->c_cflag & PARENB) {
923 		ucr2 |= UCR2_PREN;
924 		if (termios->c_cflag & PARODD)
925 			ucr2 |= UCR2_PROE;
926 	}
927 
928 	del_timer_sync(&sport->timer);
929 
930 	/*
931 	 * Ask the core to calculate the divisor for us.
932 	 */
933 	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
934 	quot = uart_get_divisor(port, baud);
935 
936 	spin_lock_irqsave(&sport->port.lock, flags);
937 
938 	sport->port.read_status_mask = 0;
939 	if (termios->c_iflag & INPCK)
940 		sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
941 	if (termios->c_iflag & (BRKINT | PARMRK))
942 		sport->port.read_status_mask |= URXD_BRK;
943 
944 	/*
945 	 * Characters to ignore
946 	 */
947 	sport->port.ignore_status_mask = 0;
948 	if (termios->c_iflag & IGNPAR)
949 		sport->port.ignore_status_mask |= URXD_PRERR;
950 	if (termios->c_iflag & IGNBRK) {
951 		sport->port.ignore_status_mask |= URXD_BRK;
952 		/*
953 		 * If we're ignoring parity and break indicators,
954 		 * ignore overruns too (for real raw support).
955 		 */
956 		if (termios->c_iflag & IGNPAR)
957 			sport->port.ignore_status_mask |= URXD_OVRRUN;
958 	}
959 
960 	/*
961 	 * Update the per-port timeout.
962 	 */
963 	uart_update_timeout(port, termios->c_cflag, baud);
964 
965 	/*
966 	 * disable interrupts and drain transmitter
967 	 */
968 	old_ucr1 = readl(sport->port.membase + UCR1);
969 	writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
970 			sport->port.membase + UCR1);
971 
972 	while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
973 		barrier();
974 
975 	/* then, disable everything */
976 	old_txrxen = readl(sport->port.membase + UCR2);
977 	writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
978 			sport->port.membase + UCR2);
979 	old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
980 
981 	if (USE_IRDA(sport)) {
982 		/*
983 		 * use maximum available submodule frequency to
984 		 * avoid missing short pulses due to low sampling rate
985 		 */
986 		div = 1;
987 	} else {
988 		div = sport->port.uartclk / (baud * 16);
989 		if (div > 7)
990 			div = 7;
991 		if (!div)
992 			div = 1;
993 	}
994 
995 	rational_best_approximation(16 * div * baud, sport->port.uartclk,
996 		1 << 16, 1 << 16, &num, &denom);
997 
998 	tdiv64 = sport->port.uartclk;
999 	tdiv64 *= num;
1000 	do_div(tdiv64, denom * 16 * div);
1001 	tty_termios_encode_baud_rate(termios,
1002 				(speed_t)tdiv64, (speed_t)tdiv64);
1003 
1004 	num -= 1;
1005 	denom -= 1;
1006 
1007 	ufcr = readl(sport->port.membase + UFCR);
1008 	ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1009 	writel(ufcr, sport->port.membase + UFCR);
1010 
1011 	writel(num, sport->port.membase + UBIR);
1012 	writel(denom, sport->port.membase + UBMR);
1013 
1014 	if (is_imx21_uart(sport))
1015 		writel(sport->port.uartclk / div / 1000,
1016 				sport->port.membase + IMX21_ONEMS);
1017 
1018 	writel(old_ucr1, sport->port.membase + UCR1);
1019 
1020 	/* set the parity, stop bits and data size */
1021 	writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1022 
1023 	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1024 		imx_enable_ms(&sport->port);
1025 
1026 	spin_unlock_irqrestore(&sport->port.lock, flags);
1027 }
1028 
1029 static const char *imx_type(struct uart_port *port)
1030 {
1031 	struct imx_port *sport = (struct imx_port *)port;
1032 
1033 	return sport->port.type == PORT_IMX ? "IMX" : NULL;
1034 }
1035 
1036 /*
1037  * Release the memory region(s) being used by 'port'.
1038  */
1039 static void imx_release_port(struct uart_port *port)
1040 {
1041 	struct platform_device *pdev = to_platform_device(port->dev);
1042 	struct resource *mmres;
1043 
1044 	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1045 	release_mem_region(mmres->start, resource_size(mmres));
1046 }
1047 
1048 /*
1049  * Request the memory region(s) being used by 'port'.
1050  */
1051 static int imx_request_port(struct uart_port *port)
1052 {
1053 	struct platform_device *pdev = to_platform_device(port->dev);
1054 	struct resource *mmres;
1055 	void *ret;
1056 
1057 	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1058 	if (!mmres)
1059 		return -ENODEV;
1060 
1061 	ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1062 
1063 	return  ret ? 0 : -EBUSY;
1064 }
1065 
1066 /*
1067  * Configure/autoconfigure the port.
1068  */
1069 static void imx_config_port(struct uart_port *port, int flags)
1070 {
1071 	struct imx_port *sport = (struct imx_port *)port;
1072 
1073 	if (flags & UART_CONFIG_TYPE &&
1074 	    imx_request_port(&sport->port) == 0)
1075 		sport->port.type = PORT_IMX;
1076 }
1077 
1078 /*
1079  * Verify the new serial_struct (for TIOCSSERIAL).
1080  * The only change we allow are to the flags and type, and
1081  * even then only between PORT_IMX and PORT_UNKNOWN
1082  */
1083 static int
1084 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1085 {
1086 	struct imx_port *sport = (struct imx_port *)port;
1087 	int ret = 0;
1088 
1089 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1090 		ret = -EINVAL;
1091 	if (sport->port.irq != ser->irq)
1092 		ret = -EINVAL;
1093 	if (ser->io_type != UPIO_MEM)
1094 		ret = -EINVAL;
1095 	if (sport->port.uartclk / 16 != ser->baud_base)
1096 		ret = -EINVAL;
1097 	if ((void *)sport->port.mapbase != ser->iomem_base)
1098 		ret = -EINVAL;
1099 	if (sport->port.iobase != ser->port)
1100 		ret = -EINVAL;
1101 	if (ser->hub6 != 0)
1102 		ret = -EINVAL;
1103 	return ret;
1104 }
1105 
1106 #if defined(CONFIG_CONSOLE_POLL)
1107 static int imx_poll_get_char(struct uart_port *port)
1108 {
1109 	struct imx_port_ucrs old_ucr;
1110 	unsigned int status;
1111 	unsigned char c;
1112 
1113 	/* save control registers */
1114 	imx_port_ucrs_save(port, &old_ucr);
1115 
1116 	/* disable interrupts */
1117 	writel(UCR1_UARTEN, port->membase + UCR1);
1118 	writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1119 	       port->membase + UCR2);
1120 	writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1121 	       port->membase + UCR3);
1122 
1123 	/* poll */
1124 	do {
1125 		status = readl(port->membase + USR2);
1126 	} while (~status & USR2_RDR);
1127 
1128 	/* read */
1129 	c = readl(port->membase + URXD0);
1130 
1131 	/* restore control registers */
1132 	imx_port_ucrs_restore(port, &old_ucr);
1133 
1134 	return c;
1135 }
1136 
1137 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1138 {
1139 	struct imx_port_ucrs old_ucr;
1140 	unsigned int status;
1141 
1142 	/* save control registers */
1143 	imx_port_ucrs_save(port, &old_ucr);
1144 
1145 	/* disable interrupts */
1146 	writel(UCR1_UARTEN, port->membase + UCR1);
1147 	writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1148 	       port->membase + UCR2);
1149 	writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1150 	       port->membase + UCR3);
1151 
1152 	/* drain */
1153 	do {
1154 		status = readl(port->membase + USR1);
1155 	} while (~status & USR1_TRDY);
1156 
1157 	/* write */
1158 	writel(c, port->membase + URTX0);
1159 
1160 	/* flush */
1161 	do {
1162 		status = readl(port->membase + USR2);
1163 	} while (~status & USR2_TXDC);
1164 
1165 	/* restore control registers */
1166 	imx_port_ucrs_restore(port, &old_ucr);
1167 }
1168 #endif
1169 
1170 static struct uart_ops imx_pops = {
1171 	.tx_empty	= imx_tx_empty,
1172 	.set_mctrl	= imx_set_mctrl,
1173 	.get_mctrl	= imx_get_mctrl,
1174 	.stop_tx	= imx_stop_tx,
1175 	.start_tx	= imx_start_tx,
1176 	.stop_rx	= imx_stop_rx,
1177 	.enable_ms	= imx_enable_ms,
1178 	.break_ctl	= imx_break_ctl,
1179 	.startup	= imx_startup,
1180 	.shutdown	= imx_shutdown,
1181 	.set_termios	= imx_set_termios,
1182 	.type		= imx_type,
1183 	.release_port	= imx_release_port,
1184 	.request_port	= imx_request_port,
1185 	.config_port	= imx_config_port,
1186 	.verify_port	= imx_verify_port,
1187 #if defined(CONFIG_CONSOLE_POLL)
1188 	.poll_get_char  = imx_poll_get_char,
1189 	.poll_put_char  = imx_poll_put_char,
1190 #endif
1191 };
1192 
1193 static struct imx_port *imx_ports[UART_NR];
1194 
1195 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1196 static void imx_console_putchar(struct uart_port *port, int ch)
1197 {
1198 	struct imx_port *sport = (struct imx_port *)port;
1199 
1200 	while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1201 		barrier();
1202 
1203 	writel(ch, sport->port.membase + URTX0);
1204 }
1205 
1206 /*
1207  * Interrupts are disabled on entering
1208  */
1209 static void
1210 imx_console_write(struct console *co, const char *s, unsigned int count)
1211 {
1212 	struct imx_port *sport = imx_ports[co->index];
1213 	struct imx_port_ucrs old_ucr;
1214 	unsigned int ucr1;
1215 	unsigned long flags;
1216 
1217 	spin_lock_irqsave(&sport->port.lock, flags);
1218 
1219 	/*
1220 	 *	First, save UCR1/2/3 and then disable interrupts
1221 	 */
1222 	imx_port_ucrs_save(&sport->port, &old_ucr);
1223 	ucr1 = old_ucr.ucr1;
1224 
1225 	if (is_imx1_uart(sport))
1226 		ucr1 |= IMX1_UCR1_UARTCLKEN;
1227 	ucr1 |= UCR1_UARTEN;
1228 	ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1229 
1230 	writel(ucr1, sport->port.membase + UCR1);
1231 
1232 	writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1233 
1234 	uart_console_write(&sport->port, s, count, imx_console_putchar);
1235 
1236 	/*
1237 	 *	Finally, wait for transmitter to become empty
1238 	 *	and restore UCR1/2/3
1239 	 */
1240 	while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1241 
1242 	imx_port_ucrs_restore(&sport->port, &old_ucr);
1243 
1244 	spin_unlock_irqrestore(&sport->port.lock, flags);
1245 }
1246 
1247 /*
1248  * If the port was already initialised (eg, by a boot loader),
1249  * try to determine the current setup.
1250  */
1251 static void __init
1252 imx_console_get_options(struct imx_port *sport, int *baud,
1253 			   int *parity, int *bits)
1254 {
1255 
1256 	if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1257 		/* ok, the port was enabled */
1258 		unsigned int ucr2, ubir,ubmr, uartclk;
1259 		unsigned int baud_raw;
1260 		unsigned int ucfr_rfdiv;
1261 
1262 		ucr2 = readl(sport->port.membase + UCR2);
1263 
1264 		*parity = 'n';
1265 		if (ucr2 & UCR2_PREN) {
1266 			if (ucr2 & UCR2_PROE)
1267 				*parity = 'o';
1268 			else
1269 				*parity = 'e';
1270 		}
1271 
1272 		if (ucr2 & UCR2_WS)
1273 			*bits = 8;
1274 		else
1275 			*bits = 7;
1276 
1277 		ubir = readl(sport->port.membase + UBIR) & 0xffff;
1278 		ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1279 
1280 		ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1281 		if (ucfr_rfdiv == 6)
1282 			ucfr_rfdiv = 7;
1283 		else
1284 			ucfr_rfdiv = 6 - ucfr_rfdiv;
1285 
1286 		uartclk = clk_get_rate(sport->clk_per);
1287 		uartclk /= ucfr_rfdiv;
1288 
1289 		{	/*
1290 			 * The next code provides exact computation of
1291 			 *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1292 			 * without need of float support or long long division,
1293 			 * which would be required to prevent 32bit arithmetic overflow
1294 			 */
1295 			unsigned int mul = ubir + 1;
1296 			unsigned int div = 16 * (ubmr + 1);
1297 			unsigned int rem = uartclk % div;
1298 
1299 			baud_raw = (uartclk / div) * mul;
1300 			baud_raw += (rem * mul + div / 2) / div;
1301 			*baud = (baud_raw + 50) / 100 * 100;
1302 		}
1303 
1304 		if(*baud != baud_raw)
1305 			printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1306 				baud_raw, *baud);
1307 	}
1308 }
1309 
1310 static int __init
1311 imx_console_setup(struct console *co, char *options)
1312 {
1313 	struct imx_port *sport;
1314 	int baud = 9600;
1315 	int bits = 8;
1316 	int parity = 'n';
1317 	int flow = 'n';
1318 
1319 	/*
1320 	 * Check whether an invalid uart number has been specified, and
1321 	 * if so, search for the first available port that does have
1322 	 * console support.
1323 	 */
1324 	if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1325 		co->index = 0;
1326 	sport = imx_ports[co->index];
1327 	if(sport == NULL)
1328 		return -ENODEV;
1329 
1330 	if (options)
1331 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1332 	else
1333 		imx_console_get_options(sport, &baud, &parity, &bits);
1334 
1335 	imx_setup_ufcr(sport, 0);
1336 
1337 	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1338 }
1339 
1340 static struct uart_driver imx_reg;
1341 static struct console imx_console = {
1342 	.name		= DEV_NAME,
1343 	.write		= imx_console_write,
1344 	.device		= uart_console_device,
1345 	.setup		= imx_console_setup,
1346 	.flags		= CON_PRINTBUFFER,
1347 	.index		= -1,
1348 	.data		= &imx_reg,
1349 };
1350 
1351 #define IMX_CONSOLE	&imx_console
1352 #else
1353 #define IMX_CONSOLE	NULL
1354 #endif
1355 
1356 static struct uart_driver imx_reg = {
1357 	.owner          = THIS_MODULE,
1358 	.driver_name    = DRIVER_NAME,
1359 	.dev_name       = DEV_NAME,
1360 	.major          = SERIAL_IMX_MAJOR,
1361 	.minor          = MINOR_START,
1362 	.nr             = ARRAY_SIZE(imx_ports),
1363 	.cons           = IMX_CONSOLE,
1364 };
1365 
1366 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1367 {
1368 	struct imx_port *sport = platform_get_drvdata(dev);
1369 	unsigned int val;
1370 
1371 	/* enable wakeup from i.MX UART */
1372 	val = readl(sport->port.membase + UCR3);
1373 	val |= UCR3_AWAKEN;
1374 	writel(val, sport->port.membase + UCR3);
1375 
1376 	uart_suspend_port(&imx_reg, &sport->port);
1377 
1378 	return 0;
1379 }
1380 
1381 static int serial_imx_resume(struct platform_device *dev)
1382 {
1383 	struct imx_port *sport = platform_get_drvdata(dev);
1384 	unsigned int val;
1385 
1386 	/* disable wakeup from i.MX UART */
1387 	val = readl(sport->port.membase + UCR3);
1388 	val &= ~UCR3_AWAKEN;
1389 	writel(val, sport->port.membase + UCR3);
1390 
1391 	uart_resume_port(&imx_reg, &sport->port);
1392 
1393 	return 0;
1394 }
1395 
1396 #ifdef CONFIG_OF
1397 /*
1398  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1399  * could successfully get all information from dt or a negative errno.
1400  */
1401 static int serial_imx_probe_dt(struct imx_port *sport,
1402 		struct platform_device *pdev)
1403 {
1404 	struct device_node *np = pdev->dev.of_node;
1405 	const struct of_device_id *of_id =
1406 			of_match_device(imx_uart_dt_ids, &pdev->dev);
1407 	int ret;
1408 
1409 	if (!np)
1410 		/* no device tree device */
1411 		return 1;
1412 
1413 	ret = of_alias_get_id(np, "serial");
1414 	if (ret < 0) {
1415 		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1416 		return ret;
1417 	}
1418 	sport->port.line = ret;
1419 
1420 	if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1421 		sport->have_rtscts = 1;
1422 
1423 	if (of_get_property(np, "fsl,irda-mode", NULL))
1424 		sport->use_irda = 1;
1425 
1426 	sport->devdata = of_id->data;
1427 
1428 	return 0;
1429 }
1430 #else
1431 static inline int serial_imx_probe_dt(struct imx_port *sport,
1432 		struct platform_device *pdev)
1433 {
1434 	return 1;
1435 }
1436 #endif
1437 
1438 static void serial_imx_probe_pdata(struct imx_port *sport,
1439 		struct platform_device *pdev)
1440 {
1441 	struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1442 
1443 	sport->port.line = pdev->id;
1444 	sport->devdata = (struct imx_uart_data	*) pdev->id_entry->driver_data;
1445 
1446 	if (!pdata)
1447 		return;
1448 
1449 	if (pdata->flags & IMXUART_HAVE_RTSCTS)
1450 		sport->have_rtscts = 1;
1451 
1452 	if (pdata->flags & IMXUART_IRDA)
1453 		sport->use_irda = 1;
1454 }
1455 
1456 static int serial_imx_probe(struct platform_device *pdev)
1457 {
1458 	struct imx_port *sport;
1459 	struct imxuart_platform_data *pdata;
1460 	void __iomem *base;
1461 	int ret = 0;
1462 	struct resource *res;
1463 	struct pinctrl *pinctrl;
1464 
1465 	sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1466 	if (!sport)
1467 		return -ENOMEM;
1468 
1469 	ret = serial_imx_probe_dt(sport, pdev);
1470 	if (ret > 0)
1471 		serial_imx_probe_pdata(sport, pdev);
1472 	else if (ret < 0)
1473 		goto free;
1474 
1475 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1476 	if (!res) {
1477 		ret = -ENODEV;
1478 		goto free;
1479 	}
1480 
1481 	base = ioremap(res->start, PAGE_SIZE);
1482 	if (!base) {
1483 		ret = -ENOMEM;
1484 		goto free;
1485 	}
1486 
1487 	sport->port.dev = &pdev->dev;
1488 	sport->port.mapbase = res->start;
1489 	sport->port.membase = base;
1490 	sport->port.type = PORT_IMX,
1491 	sport->port.iotype = UPIO_MEM;
1492 	sport->port.irq = platform_get_irq(pdev, 0);
1493 	sport->rxirq = platform_get_irq(pdev, 0);
1494 	sport->txirq = platform_get_irq(pdev, 1);
1495 	sport->rtsirq = platform_get_irq(pdev, 2);
1496 	sport->port.fifosize = 32;
1497 	sport->port.ops = &imx_pops;
1498 	sport->port.flags = UPF_BOOT_AUTOCONF;
1499 	init_timer(&sport->timer);
1500 	sport->timer.function = imx_timeout;
1501 	sport->timer.data     = (unsigned long)sport;
1502 
1503 	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1504 	if (IS_ERR(pinctrl)) {
1505 		ret = PTR_ERR(pinctrl);
1506 		dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
1507 		goto unmap;
1508 	}
1509 
1510 	sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1511 	if (IS_ERR(sport->clk_ipg)) {
1512 		ret = PTR_ERR(sport->clk_ipg);
1513 		dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1514 		goto unmap;
1515 	}
1516 
1517 	sport->clk_per = devm_clk_get(&pdev->dev, "per");
1518 	if (IS_ERR(sport->clk_per)) {
1519 		ret = PTR_ERR(sport->clk_per);
1520 		dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1521 		goto unmap;
1522 	}
1523 
1524 	clk_prepare_enable(sport->clk_per);
1525 	clk_prepare_enable(sport->clk_ipg);
1526 
1527 	sport->port.uartclk = clk_get_rate(sport->clk_per);
1528 
1529 	imx_ports[sport->port.line] = sport;
1530 
1531 	pdata = pdev->dev.platform_data;
1532 	if (pdata && pdata->init) {
1533 		ret = pdata->init(pdev);
1534 		if (ret)
1535 			goto clkput;
1536 	}
1537 
1538 	ret = uart_add_one_port(&imx_reg, &sport->port);
1539 	if (ret)
1540 		goto deinit;
1541 	platform_set_drvdata(pdev, sport);
1542 
1543 	return 0;
1544 deinit:
1545 	if (pdata && pdata->exit)
1546 		pdata->exit(pdev);
1547 clkput:
1548 	clk_disable_unprepare(sport->clk_per);
1549 	clk_disable_unprepare(sport->clk_ipg);
1550 unmap:
1551 	iounmap(sport->port.membase);
1552 free:
1553 	kfree(sport);
1554 
1555 	return ret;
1556 }
1557 
1558 static int serial_imx_remove(struct platform_device *pdev)
1559 {
1560 	struct imxuart_platform_data *pdata;
1561 	struct imx_port *sport = platform_get_drvdata(pdev);
1562 
1563 	pdata = pdev->dev.platform_data;
1564 
1565 	platform_set_drvdata(pdev, NULL);
1566 
1567 	uart_remove_one_port(&imx_reg, &sport->port);
1568 
1569 	clk_disable_unprepare(sport->clk_per);
1570 	clk_disable_unprepare(sport->clk_ipg);
1571 
1572 	if (pdata && pdata->exit)
1573 		pdata->exit(pdev);
1574 
1575 	iounmap(sport->port.membase);
1576 	kfree(sport);
1577 
1578 	return 0;
1579 }
1580 
1581 static struct platform_driver serial_imx_driver = {
1582 	.probe		= serial_imx_probe,
1583 	.remove		= serial_imx_remove,
1584 
1585 	.suspend	= serial_imx_suspend,
1586 	.resume		= serial_imx_resume,
1587 	.id_table	= imx_uart_devtype,
1588 	.driver		= {
1589 		.name	= "imx-uart",
1590 		.owner	= THIS_MODULE,
1591 		.of_match_table = imx_uart_dt_ids,
1592 	},
1593 };
1594 
1595 static int __init imx_serial_init(void)
1596 {
1597 	int ret;
1598 
1599 	printk(KERN_INFO "Serial: IMX driver\n");
1600 
1601 	ret = uart_register_driver(&imx_reg);
1602 	if (ret)
1603 		return ret;
1604 
1605 	ret = platform_driver_register(&serial_imx_driver);
1606 	if (ret != 0)
1607 		uart_unregister_driver(&imx_reg);
1608 
1609 	return ret;
1610 }
1611 
1612 static void __exit imx_serial_exit(void)
1613 {
1614 	platform_driver_unregister(&serial_imx_driver);
1615 	uart_unregister_driver(&imx_reg);
1616 }
1617 
1618 module_init(imx_serial_init);
1619 module_exit(imx_serial_exit);
1620 
1621 MODULE_AUTHOR("Sascha Hauer");
1622 MODULE_DESCRIPTION("IMX generic serial port driver");
1623 MODULE_LICENSE("GPL");
1624 MODULE_ALIAS("platform:imx-uart");
1625