1 /* 2 * Freescale lpuart serial port driver 3 * 4 * Copyright 2012-2014 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 13 #define SUPPORT_SYSRQ 14 #endif 15 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/dmaengine.h> 20 #include <linux/dmapool.h> 21 #include <linux/io.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/of_dma.h> 27 #include <linux/serial_core.h> 28 #include <linux/slab.h> 29 #include <linux/tty_flip.h> 30 31 /* All registers are 8-bit width */ 32 #define UARTBDH 0x00 33 #define UARTBDL 0x01 34 #define UARTCR1 0x02 35 #define UARTCR2 0x03 36 #define UARTSR1 0x04 37 #define UARTCR3 0x06 38 #define UARTDR 0x07 39 #define UARTCR4 0x0a 40 #define UARTCR5 0x0b 41 #define UARTMODEM 0x0d 42 #define UARTPFIFO 0x10 43 #define UARTCFIFO 0x11 44 #define UARTSFIFO 0x12 45 #define UARTTWFIFO 0x13 46 #define UARTTCFIFO 0x14 47 #define UARTRWFIFO 0x15 48 49 #define UARTBDH_LBKDIE 0x80 50 #define UARTBDH_RXEDGIE 0x40 51 #define UARTBDH_SBR_MASK 0x1f 52 53 #define UARTCR1_LOOPS 0x80 54 #define UARTCR1_RSRC 0x20 55 #define UARTCR1_M 0x10 56 #define UARTCR1_WAKE 0x08 57 #define UARTCR1_ILT 0x04 58 #define UARTCR1_PE 0x02 59 #define UARTCR1_PT 0x01 60 61 #define UARTCR2_TIE 0x80 62 #define UARTCR2_TCIE 0x40 63 #define UARTCR2_RIE 0x20 64 #define UARTCR2_ILIE 0x10 65 #define UARTCR2_TE 0x08 66 #define UARTCR2_RE 0x04 67 #define UARTCR2_RWU 0x02 68 #define UARTCR2_SBK 0x01 69 70 #define UARTSR1_TDRE 0x80 71 #define UARTSR1_TC 0x40 72 #define UARTSR1_RDRF 0x20 73 #define UARTSR1_IDLE 0x10 74 #define UARTSR1_OR 0x08 75 #define UARTSR1_NF 0x04 76 #define UARTSR1_FE 0x02 77 #define UARTSR1_PE 0x01 78 79 #define UARTCR3_R8 0x80 80 #define UARTCR3_T8 0x40 81 #define UARTCR3_TXDIR 0x20 82 #define UARTCR3_TXINV 0x10 83 #define UARTCR3_ORIE 0x08 84 #define UARTCR3_NEIE 0x04 85 #define UARTCR3_FEIE 0x02 86 #define UARTCR3_PEIE 0x01 87 88 #define UARTCR4_MAEN1 0x80 89 #define UARTCR4_MAEN2 0x40 90 #define UARTCR4_M10 0x20 91 #define UARTCR4_BRFA_MASK 0x1f 92 #define UARTCR4_BRFA_OFF 0 93 94 #define UARTCR5_TDMAS 0x80 95 #define UARTCR5_RDMAS 0x20 96 97 #define UARTMODEM_RXRTSE 0x08 98 #define UARTMODEM_TXRTSPOL 0x04 99 #define UARTMODEM_TXRTSE 0x02 100 #define UARTMODEM_TXCTSE 0x01 101 102 #define UARTPFIFO_TXFE 0x80 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7 104 #define UARTPFIFO_TXSIZE_OFF 4 105 #define UARTPFIFO_RXFE 0x08 106 #define UARTPFIFO_RXSIZE_OFF 0 107 108 #define UARTCFIFO_TXFLUSH 0x80 109 #define UARTCFIFO_RXFLUSH 0x40 110 #define UARTCFIFO_RXOFE 0x04 111 #define UARTCFIFO_TXOFE 0x02 112 #define UARTCFIFO_RXUFE 0x01 113 114 #define UARTSFIFO_TXEMPT 0x80 115 #define UARTSFIFO_RXEMPT 0x40 116 #define UARTSFIFO_RXOF 0x04 117 #define UARTSFIFO_TXOF 0x02 118 #define UARTSFIFO_RXUF 0x01 119 120 /* 32-bit register defination */ 121 #define UARTBAUD 0x00 122 #define UARTSTAT 0x04 123 #define UARTCTRL 0x08 124 #define UARTDATA 0x0C 125 #define UARTMATCH 0x10 126 #define UARTMODIR 0x14 127 #define UARTFIFO 0x18 128 #define UARTWATER 0x1c 129 130 #define UARTBAUD_MAEN1 0x80000000 131 #define UARTBAUD_MAEN2 0x40000000 132 #define UARTBAUD_M10 0x20000000 133 #define UARTBAUD_TDMAE 0x00800000 134 #define UARTBAUD_RDMAE 0x00200000 135 #define UARTBAUD_MATCFG 0x00400000 136 #define UARTBAUD_BOTHEDGE 0x00020000 137 #define UARTBAUD_RESYNCDIS 0x00010000 138 #define UARTBAUD_LBKDIE 0x00008000 139 #define UARTBAUD_RXEDGIE 0x00004000 140 #define UARTBAUD_SBNS 0x00002000 141 #define UARTBAUD_SBR 0x00000000 142 #define UARTBAUD_SBR_MASK 0x1fff 143 144 #define UARTSTAT_LBKDIF 0x80000000 145 #define UARTSTAT_RXEDGIF 0x40000000 146 #define UARTSTAT_MSBF 0x20000000 147 #define UARTSTAT_RXINV 0x10000000 148 #define UARTSTAT_RWUID 0x08000000 149 #define UARTSTAT_BRK13 0x04000000 150 #define UARTSTAT_LBKDE 0x02000000 151 #define UARTSTAT_RAF 0x01000000 152 #define UARTSTAT_TDRE 0x00800000 153 #define UARTSTAT_TC 0x00400000 154 #define UARTSTAT_RDRF 0x00200000 155 #define UARTSTAT_IDLE 0x00100000 156 #define UARTSTAT_OR 0x00080000 157 #define UARTSTAT_NF 0x00040000 158 #define UARTSTAT_FE 0x00020000 159 #define UARTSTAT_PE 0x00010000 160 #define UARTSTAT_MA1F 0x00008000 161 #define UARTSTAT_M21F 0x00004000 162 163 #define UARTCTRL_R8T9 0x80000000 164 #define UARTCTRL_R9T8 0x40000000 165 #define UARTCTRL_TXDIR 0x20000000 166 #define UARTCTRL_TXINV 0x10000000 167 #define UARTCTRL_ORIE 0x08000000 168 #define UARTCTRL_NEIE 0x04000000 169 #define UARTCTRL_FEIE 0x02000000 170 #define UARTCTRL_PEIE 0x01000000 171 #define UARTCTRL_TIE 0x00800000 172 #define UARTCTRL_TCIE 0x00400000 173 #define UARTCTRL_RIE 0x00200000 174 #define UARTCTRL_ILIE 0x00100000 175 #define UARTCTRL_TE 0x00080000 176 #define UARTCTRL_RE 0x00040000 177 #define UARTCTRL_RWU 0x00020000 178 #define UARTCTRL_SBK 0x00010000 179 #define UARTCTRL_MA1IE 0x00008000 180 #define UARTCTRL_MA2IE 0x00004000 181 #define UARTCTRL_IDLECFG 0x00000100 182 #define UARTCTRL_LOOPS 0x00000080 183 #define UARTCTRL_DOZEEN 0x00000040 184 #define UARTCTRL_RSRC 0x00000020 185 #define UARTCTRL_M 0x00000010 186 #define UARTCTRL_WAKE 0x00000008 187 #define UARTCTRL_ILT 0x00000004 188 #define UARTCTRL_PE 0x00000002 189 #define UARTCTRL_PT 0x00000001 190 191 #define UARTDATA_NOISY 0x00008000 192 #define UARTDATA_PARITYE 0x00004000 193 #define UARTDATA_FRETSC 0x00002000 194 #define UARTDATA_RXEMPT 0x00001000 195 #define UARTDATA_IDLINE 0x00000800 196 #define UARTDATA_MASK 0x3ff 197 198 #define UARTMODIR_IREN 0x00020000 199 #define UARTMODIR_TXCTSSRC 0x00000020 200 #define UARTMODIR_TXCTSC 0x00000010 201 #define UARTMODIR_RXRTSE 0x00000008 202 #define UARTMODIR_TXRTSPOL 0x00000004 203 #define UARTMODIR_TXRTSE 0x00000002 204 #define UARTMODIR_TXCTSE 0x00000001 205 206 #define UARTFIFO_TXEMPT 0x00800000 207 #define UARTFIFO_RXEMPT 0x00400000 208 #define UARTFIFO_TXOF 0x00020000 209 #define UARTFIFO_RXUF 0x00010000 210 #define UARTFIFO_TXFLUSH 0x00008000 211 #define UARTFIFO_RXFLUSH 0x00004000 212 #define UARTFIFO_TXOFE 0x00000200 213 #define UARTFIFO_RXUFE 0x00000100 214 #define UARTFIFO_TXFE 0x00000080 215 #define UARTFIFO_FIFOSIZE_MASK 0x7 216 #define UARTFIFO_TXSIZE_OFF 4 217 #define UARTFIFO_RXFE 0x00000008 218 #define UARTFIFO_RXSIZE_OFF 0 219 220 #define UARTWATER_COUNT_MASK 0xff 221 #define UARTWATER_TXCNT_OFF 8 222 #define UARTWATER_RXCNT_OFF 24 223 #define UARTWATER_WATER_MASK 0xff 224 #define UARTWATER_TXWATER_OFF 0 225 #define UARTWATER_RXWATER_OFF 16 226 227 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 228 #define DMA_RX_TIMEOUT (10) 229 230 #define DRIVER_NAME "fsl-lpuart" 231 #define DEV_NAME "ttyLP" 232 #define UART_NR 6 233 234 struct lpuart_port { 235 struct uart_port port; 236 struct clk *clk; 237 unsigned int txfifo_size; 238 unsigned int rxfifo_size; 239 bool lpuart32; 240 241 bool lpuart_dma_tx_use; 242 bool lpuart_dma_rx_use; 243 struct dma_chan *dma_tx_chan; 244 struct dma_chan *dma_rx_chan; 245 struct dma_async_tx_descriptor *dma_tx_desc; 246 struct dma_async_tx_descriptor *dma_rx_desc; 247 dma_cookie_t dma_tx_cookie; 248 dma_cookie_t dma_rx_cookie; 249 unsigned int dma_tx_bytes; 250 unsigned int dma_rx_bytes; 251 bool dma_tx_in_progress; 252 unsigned int dma_rx_timeout; 253 struct timer_list lpuart_timer; 254 struct scatterlist rx_sgl, tx_sgl[2]; 255 struct circ_buf rx_ring; 256 int rx_dma_rng_buf_len; 257 unsigned int dma_tx_nents; 258 wait_queue_head_t dma_wait; 259 }; 260 261 static const struct of_device_id lpuart_dt_ids[] = { 262 { 263 .compatible = "fsl,vf610-lpuart", 264 }, 265 { 266 .compatible = "fsl,ls1021a-lpuart", 267 }, 268 { /* sentinel */ } 269 }; 270 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 271 272 /* Forward declare this for the dma callbacks*/ 273 static void lpuart_dma_tx_complete(void *arg); 274 275 static u32 lpuart32_read(void __iomem *addr) 276 { 277 return ioread32be(addr); 278 } 279 280 static void lpuart32_write(u32 val, void __iomem *addr) 281 { 282 iowrite32be(val, addr); 283 } 284 285 static void lpuart_stop_tx(struct uart_port *port) 286 { 287 unsigned char temp; 288 289 temp = readb(port->membase + UARTCR2); 290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 291 writeb(temp, port->membase + UARTCR2); 292 } 293 294 static void lpuart32_stop_tx(struct uart_port *port) 295 { 296 unsigned long temp; 297 298 temp = lpuart32_read(port->membase + UARTCTRL); 299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 300 lpuart32_write(temp, port->membase + UARTCTRL); 301 } 302 303 static void lpuart_stop_rx(struct uart_port *port) 304 { 305 unsigned char temp; 306 307 temp = readb(port->membase + UARTCR2); 308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 309 } 310 311 static void lpuart32_stop_rx(struct uart_port *port) 312 { 313 unsigned long temp; 314 315 temp = lpuart32_read(port->membase + UARTCTRL); 316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL); 317 } 318 319 static void lpuart_dma_tx(struct lpuart_port *sport) 320 { 321 struct circ_buf *xmit = &sport->port.state->xmit; 322 struct scatterlist *sgl = sport->tx_sgl; 323 struct device *dev = sport->port.dev; 324 int ret; 325 326 if (sport->dma_tx_in_progress) 327 return; 328 329 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 330 331 if (xmit->tail < xmit->head || xmit->head == 0) { 332 sport->dma_tx_nents = 1; 333 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 334 } else { 335 sport->dma_tx_nents = 2; 336 sg_init_table(sgl, 2); 337 sg_set_buf(sgl, xmit->buf + xmit->tail, 338 UART_XMIT_SIZE - xmit->tail); 339 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 340 } 341 342 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 343 if (!ret) { 344 dev_err(dev, "DMA mapping error for TX.\n"); 345 return; 346 } 347 348 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, 349 sport->dma_tx_nents, 350 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 351 if (!sport->dma_tx_desc) { 352 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 353 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 354 return; 355 } 356 357 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 358 sport->dma_tx_desc->callback_param = sport; 359 sport->dma_tx_in_progress = true; 360 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 361 dma_async_issue_pending(sport->dma_tx_chan); 362 } 363 364 static void lpuart_dma_tx_complete(void *arg) 365 { 366 struct lpuart_port *sport = arg; 367 struct scatterlist *sgl = &sport->tx_sgl[0]; 368 struct circ_buf *xmit = &sport->port.state->xmit; 369 unsigned long flags; 370 371 spin_lock_irqsave(&sport->port.lock, flags); 372 373 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 374 375 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 376 377 sport->port.icount.tx += sport->dma_tx_bytes; 378 sport->dma_tx_in_progress = false; 379 spin_unlock_irqrestore(&sport->port.lock, flags); 380 381 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 382 uart_write_wakeup(&sport->port); 383 384 if (waitqueue_active(&sport->dma_wait)) { 385 wake_up(&sport->dma_wait); 386 return; 387 } 388 389 spin_lock_irqsave(&sport->port.lock, flags); 390 391 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) 392 lpuart_dma_tx(sport); 393 394 spin_unlock_irqrestore(&sport->port.lock, flags); 395 } 396 397 static int lpuart_dma_tx_request(struct uart_port *port) 398 { 399 struct lpuart_port *sport = container_of(port, 400 struct lpuart_port, port); 401 struct dma_slave_config dma_tx_sconfig = {}; 402 int ret; 403 404 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; 405 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 406 dma_tx_sconfig.dst_maxburst = 1; 407 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 408 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 409 410 if (ret) { 411 dev_err(sport->port.dev, 412 "DMA slave config failed, err = %d\n", ret); 413 return ret; 414 } 415 416 return 0; 417 } 418 419 static void lpuart_flush_buffer(struct uart_port *port) 420 { 421 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 422 423 if (sport->lpuart_dma_tx_use) { 424 if (sport->dma_tx_in_progress) { 425 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], 426 sport->dma_tx_nents, DMA_TO_DEVICE); 427 sport->dma_tx_in_progress = false; 428 } 429 dmaengine_terminate_all(sport->dma_tx_chan); 430 } 431 } 432 433 #if defined(CONFIG_CONSOLE_POLL) 434 435 static int lpuart_poll_init(struct uart_port *port) 436 { 437 struct lpuart_port *sport = container_of(port, 438 struct lpuart_port, port); 439 unsigned long flags; 440 unsigned char temp; 441 442 sport->port.fifosize = 0; 443 444 spin_lock_irqsave(&sport->port.lock, flags); 445 /* Disable Rx & Tx */ 446 writeb(0, sport->port.membase + UARTCR2); 447 448 temp = readb(sport->port.membase + UARTPFIFO); 449 /* Enable Rx and Tx FIFO */ 450 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 451 sport->port.membase + UARTPFIFO); 452 453 /* flush Tx and Rx FIFO */ 454 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 455 sport->port.membase + UARTCFIFO); 456 457 /* explicitly clear RDRF */ 458 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 459 readb(sport->port.membase + UARTDR); 460 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 461 } 462 463 writeb(0, sport->port.membase + UARTTWFIFO); 464 writeb(1, sport->port.membase + UARTRWFIFO); 465 466 /* Enable Rx and Tx */ 467 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 468 spin_unlock_irqrestore(&sport->port.lock, flags); 469 470 return 0; 471 } 472 473 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 474 { 475 /* drain */ 476 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 477 barrier(); 478 479 writeb(c, port->membase + UARTDR); 480 } 481 482 static int lpuart_poll_get_char(struct uart_port *port) 483 { 484 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 485 return NO_POLL_CHAR; 486 487 return readb(port->membase + UARTDR); 488 } 489 490 #endif 491 492 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 493 { 494 struct circ_buf *xmit = &sport->port.state->xmit; 495 496 while (!uart_circ_empty(xmit) && 497 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 498 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 499 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 500 sport->port.icount.tx++; 501 } 502 503 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 504 uart_write_wakeup(&sport->port); 505 506 if (uart_circ_empty(xmit)) 507 lpuart_stop_tx(&sport->port); 508 } 509 510 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 511 { 512 struct circ_buf *xmit = &sport->port.state->xmit; 513 unsigned long txcnt; 514 515 txcnt = lpuart32_read(sport->port.membase + UARTWATER); 516 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 517 txcnt &= UARTWATER_COUNT_MASK; 518 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 519 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA); 520 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 521 sport->port.icount.tx++; 522 txcnt = lpuart32_read(sport->port.membase + UARTWATER); 523 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 524 txcnt &= UARTWATER_COUNT_MASK; 525 } 526 527 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 528 uart_write_wakeup(&sport->port); 529 530 if (uart_circ_empty(xmit)) 531 lpuart32_stop_tx(&sport->port); 532 } 533 534 static void lpuart_start_tx(struct uart_port *port) 535 { 536 struct lpuart_port *sport = container_of(port, 537 struct lpuart_port, port); 538 struct circ_buf *xmit = &sport->port.state->xmit; 539 unsigned char temp; 540 541 temp = readb(port->membase + UARTCR2); 542 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 543 544 if (sport->lpuart_dma_tx_use) { 545 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) 546 lpuart_dma_tx(sport); 547 } else { 548 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 549 lpuart_transmit_buffer(sport); 550 } 551 } 552 553 static void lpuart32_start_tx(struct uart_port *port) 554 { 555 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 556 unsigned long temp; 557 558 temp = lpuart32_read(port->membase + UARTCTRL); 559 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL); 560 561 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE) 562 lpuart32_transmit_buffer(sport); 563 } 564 565 /* return TIOCSER_TEMT when transmitter is not busy */ 566 static unsigned int lpuart_tx_empty(struct uart_port *port) 567 { 568 struct lpuart_port *sport = container_of(port, 569 struct lpuart_port, port); 570 unsigned char sr1 = readb(port->membase + UARTSR1); 571 unsigned char sfifo = readb(port->membase + UARTSFIFO); 572 573 if (sport->dma_tx_in_progress) 574 return 0; 575 576 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 577 return TIOCSER_TEMT; 578 579 return 0; 580 } 581 582 static unsigned int lpuart32_tx_empty(struct uart_port *port) 583 { 584 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ? 585 TIOCSER_TEMT : 0; 586 } 587 588 static irqreturn_t lpuart_txint(int irq, void *dev_id) 589 { 590 struct lpuart_port *sport = dev_id; 591 struct circ_buf *xmit = &sport->port.state->xmit; 592 unsigned long flags; 593 594 spin_lock_irqsave(&sport->port.lock, flags); 595 if (sport->port.x_char) { 596 if (sport->lpuart32) 597 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA); 598 else 599 writeb(sport->port.x_char, sport->port.membase + UARTDR); 600 goto out; 601 } 602 603 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { 604 if (sport->lpuart32) 605 lpuart32_stop_tx(&sport->port); 606 else 607 lpuart_stop_tx(&sport->port); 608 goto out; 609 } 610 611 if (sport->lpuart32) 612 lpuart32_transmit_buffer(sport); 613 else 614 lpuart_transmit_buffer(sport); 615 616 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 617 uart_write_wakeup(&sport->port); 618 619 out: 620 spin_unlock_irqrestore(&sport->port.lock, flags); 621 return IRQ_HANDLED; 622 } 623 624 static irqreturn_t lpuart_rxint(int irq, void *dev_id) 625 { 626 struct lpuart_port *sport = dev_id; 627 unsigned int flg, ignored = 0; 628 struct tty_port *port = &sport->port.state->port; 629 unsigned long flags; 630 unsigned char rx, sr; 631 632 spin_lock_irqsave(&sport->port.lock, flags); 633 634 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 635 flg = TTY_NORMAL; 636 sport->port.icount.rx++; 637 /* 638 * to clear the FE, OR, NF, FE, PE flags, 639 * read SR1 then read DR 640 */ 641 sr = readb(sport->port.membase + UARTSR1); 642 rx = readb(sport->port.membase + UARTDR); 643 644 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 645 continue; 646 647 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 648 if (sr & UARTSR1_PE) 649 sport->port.icount.parity++; 650 else if (sr & UARTSR1_FE) 651 sport->port.icount.frame++; 652 653 if (sr & UARTSR1_OR) 654 sport->port.icount.overrun++; 655 656 if (sr & sport->port.ignore_status_mask) { 657 if (++ignored > 100) 658 goto out; 659 continue; 660 } 661 662 sr &= sport->port.read_status_mask; 663 664 if (sr & UARTSR1_PE) 665 flg = TTY_PARITY; 666 else if (sr & UARTSR1_FE) 667 flg = TTY_FRAME; 668 669 if (sr & UARTSR1_OR) 670 flg = TTY_OVERRUN; 671 672 #ifdef SUPPORT_SYSRQ 673 sport->port.sysrq = 0; 674 #endif 675 } 676 677 tty_insert_flip_char(port, rx, flg); 678 } 679 680 out: 681 spin_unlock_irqrestore(&sport->port.lock, flags); 682 683 tty_flip_buffer_push(port); 684 return IRQ_HANDLED; 685 } 686 687 static irqreturn_t lpuart32_rxint(int irq, void *dev_id) 688 { 689 struct lpuart_port *sport = dev_id; 690 unsigned int flg, ignored = 0; 691 struct tty_port *port = &sport->port.state->port; 692 unsigned long flags; 693 unsigned long rx, sr; 694 695 spin_lock_irqsave(&sport->port.lock, flags); 696 697 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) { 698 flg = TTY_NORMAL; 699 sport->port.icount.rx++; 700 /* 701 * to clear the FE, OR, NF, FE, PE flags, 702 * read STAT then read DATA reg 703 */ 704 sr = lpuart32_read(sport->port.membase + UARTSTAT); 705 rx = lpuart32_read(sport->port.membase + UARTDATA); 706 rx &= 0x3ff; 707 708 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 709 continue; 710 711 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 712 if (sr & UARTSTAT_PE) 713 sport->port.icount.parity++; 714 else if (sr & UARTSTAT_FE) 715 sport->port.icount.frame++; 716 717 if (sr & UARTSTAT_OR) 718 sport->port.icount.overrun++; 719 720 if (sr & sport->port.ignore_status_mask) { 721 if (++ignored > 100) 722 goto out; 723 continue; 724 } 725 726 sr &= sport->port.read_status_mask; 727 728 if (sr & UARTSTAT_PE) 729 flg = TTY_PARITY; 730 else if (sr & UARTSTAT_FE) 731 flg = TTY_FRAME; 732 733 if (sr & UARTSTAT_OR) 734 flg = TTY_OVERRUN; 735 736 #ifdef SUPPORT_SYSRQ 737 sport->port.sysrq = 0; 738 #endif 739 } 740 741 tty_insert_flip_char(port, rx, flg); 742 } 743 744 out: 745 spin_unlock_irqrestore(&sport->port.lock, flags); 746 747 tty_flip_buffer_push(port); 748 return IRQ_HANDLED; 749 } 750 751 static irqreturn_t lpuart_int(int irq, void *dev_id) 752 { 753 struct lpuart_port *sport = dev_id; 754 unsigned char sts; 755 756 sts = readb(sport->port.membase + UARTSR1); 757 758 if (sts & UARTSR1_RDRF) 759 lpuart_rxint(irq, dev_id); 760 761 if (sts & UARTSR1_TDRE) 762 lpuart_txint(irq, dev_id); 763 764 return IRQ_HANDLED; 765 } 766 767 static irqreturn_t lpuart32_int(int irq, void *dev_id) 768 { 769 struct lpuart_port *sport = dev_id; 770 unsigned long sts, rxcount; 771 772 sts = lpuart32_read(sport->port.membase + UARTSTAT); 773 rxcount = lpuart32_read(sport->port.membase + UARTWATER); 774 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 775 776 if (sts & UARTSTAT_RDRF || rxcount > 0) 777 lpuart32_rxint(irq, dev_id); 778 779 if ((sts & UARTSTAT_TDRE) && 780 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE)) 781 lpuart_txint(irq, dev_id); 782 783 lpuart32_write(sts, sport->port.membase + UARTSTAT); 784 return IRQ_HANDLED; 785 } 786 787 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 788 { 789 struct tty_port *port = &sport->port.state->port; 790 struct dma_tx_state state; 791 enum dma_status dmastat; 792 struct circ_buf *ring = &sport->rx_ring; 793 unsigned long flags; 794 int count = 0; 795 unsigned char sr; 796 797 sr = readb(sport->port.membase + UARTSR1); 798 799 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 800 /* Read DR to clear the error flags */ 801 readb(sport->port.membase + UARTDR); 802 803 if (sr & UARTSR1_PE) 804 sport->port.icount.parity++; 805 else if (sr & UARTSR1_FE) 806 sport->port.icount.frame++; 807 } 808 809 async_tx_ack(sport->dma_rx_desc); 810 811 spin_lock_irqsave(&sport->port.lock, flags); 812 813 dmastat = dmaengine_tx_status(sport->dma_rx_chan, 814 sport->dma_rx_cookie, 815 &state); 816 817 if (dmastat == DMA_ERROR) { 818 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 819 spin_unlock_irqrestore(&sport->port.lock, flags); 820 return; 821 } 822 823 /* CPU claims ownership of RX DMA buffer */ 824 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 825 826 /* 827 * ring->head points to the end of data already written by the DMA. 828 * ring->tail points to the beginning of data to be read by the 829 * framework. 830 * The current transfer size should not be larger than the dma buffer 831 * length. 832 */ 833 ring->head = sport->rx_sgl.length - state.residue; 834 BUG_ON(ring->head > sport->rx_sgl.length); 835 /* 836 * At this point ring->head may point to the first byte right after the 837 * last byte of the dma buffer: 838 * 0 <= ring->head <= sport->rx_sgl.length 839 * 840 * However ring->tail must always points inside the dma buffer: 841 * 0 <= ring->tail <= sport->rx_sgl.length - 1 842 * 843 * Since we use a ring buffer, we have to handle the case 844 * where head is lower than tail. In such a case, we first read from 845 * tail to the end of the buffer then reset tail. 846 */ 847 if (ring->head < ring->tail) { 848 count = sport->rx_sgl.length - ring->tail; 849 850 tty_insert_flip_string(port, ring->buf + ring->tail, count); 851 ring->tail = 0; 852 sport->port.icount.rx += count; 853 } 854 855 /* Finally we read data from tail to head */ 856 if (ring->tail < ring->head) { 857 count = ring->head - ring->tail; 858 tty_insert_flip_string(port, ring->buf + ring->tail, count); 859 /* Wrap ring->head if needed */ 860 if (ring->head >= sport->rx_sgl.length) 861 ring->head = 0; 862 ring->tail = ring->head; 863 sport->port.icount.rx += count; 864 } 865 866 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, 867 DMA_FROM_DEVICE); 868 869 spin_unlock_irqrestore(&sport->port.lock, flags); 870 871 tty_flip_buffer_push(port); 872 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 873 } 874 875 static void lpuart_dma_rx_complete(void *arg) 876 { 877 struct lpuart_port *sport = arg; 878 879 lpuart_copy_rx_to_tty(sport); 880 } 881 882 static void lpuart_timer_func(unsigned long data) 883 { 884 struct lpuart_port *sport = (struct lpuart_port *)data; 885 886 lpuart_copy_rx_to_tty(sport); 887 } 888 889 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 890 { 891 struct dma_slave_config dma_rx_sconfig = {}; 892 struct circ_buf *ring = &sport->rx_ring; 893 int ret, nent; 894 int bits, baud; 895 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port); 896 struct ktermios *termios = &tty->termios; 897 898 baud = tty_get_baud_rate(tty); 899 900 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 901 if (termios->c_cflag & PARENB) 902 bits++; 903 904 /* 905 * Calculate length of one DMA buffer size to keep latency below 906 * 10ms at any baud rate. 907 */ 908 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 909 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 910 if (sport->rx_dma_rng_buf_len < 16) 911 sport->rx_dma_rng_buf_len = 16; 912 913 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 914 if (!ring->buf) { 915 dev_err(sport->port.dev, "Ring buf alloc failed\n"); 916 return -ENOMEM; 917 } 918 919 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 920 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 921 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 922 923 if (!nent) { 924 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 925 return -EINVAL; 926 } 927 928 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; 929 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 930 dma_rx_sconfig.src_maxburst = 1; 931 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 932 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); 933 934 if (ret < 0) { 935 dev_err(sport->port.dev, 936 "DMA Rx slave config failed, err = %d\n", ret); 937 return ret; 938 } 939 940 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, 941 sg_dma_address(&sport->rx_sgl), 942 sport->rx_sgl.length, 943 sport->rx_sgl.length / 2, 944 DMA_DEV_TO_MEM, 945 DMA_PREP_INTERRUPT); 946 if (!sport->dma_rx_desc) { 947 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 948 return -EFAULT; 949 } 950 951 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 952 sport->dma_rx_desc->callback_param = sport; 953 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 954 dma_async_issue_pending(sport->dma_rx_chan); 955 956 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 957 sport->port.membase + UARTCR5); 958 959 return 0; 960 } 961 962 static void lpuart_dma_rx_free(struct uart_port *port) 963 { 964 struct lpuart_port *sport = container_of(port, 965 struct lpuart_port, port); 966 967 if (sport->dma_rx_chan) 968 dmaengine_terminate_all(sport->dma_rx_chan); 969 970 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 971 kfree(sport->rx_ring.buf); 972 sport->rx_ring.tail = 0; 973 sport->rx_ring.head = 0; 974 sport->dma_rx_desc = NULL; 975 sport->dma_rx_cookie = -EINVAL; 976 } 977 978 static int lpuart_config_rs485(struct uart_port *port, 979 struct serial_rs485 *rs485) 980 { 981 struct lpuart_port *sport = container_of(port, 982 struct lpuart_port, port); 983 984 u8 modem = readb(sport->port.membase + UARTMODEM) & 985 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 986 writeb(modem, sport->port.membase + UARTMODEM); 987 988 if (rs485->flags & SER_RS485_ENABLED) { 989 /* Enable auto RS-485 RTS mode */ 990 modem |= UARTMODEM_TXRTSE; 991 992 /* 993 * RTS needs to be logic HIGH either during transer _or_ after 994 * transfer, other variants are not supported by the hardware. 995 */ 996 997 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 998 SER_RS485_RTS_AFTER_SEND))) 999 rs485->flags |= SER_RS485_RTS_ON_SEND; 1000 1001 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1002 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1003 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1004 1005 /* 1006 * The hardware defaults to RTS logic HIGH while transfer. 1007 * Switch polarity in case RTS shall be logic HIGH 1008 * after transfer. 1009 * Note: UART is assumed to be active high. 1010 */ 1011 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1012 modem &= ~UARTMODEM_TXRTSPOL; 1013 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1014 modem |= UARTMODEM_TXRTSPOL; 1015 } 1016 1017 /* Store the new configuration */ 1018 sport->port.rs485 = *rs485; 1019 1020 writeb(modem, sport->port.membase + UARTMODEM); 1021 return 0; 1022 } 1023 1024 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1025 { 1026 unsigned int temp = 0; 1027 unsigned char reg; 1028 1029 reg = readb(port->membase + UARTMODEM); 1030 if (reg & UARTMODEM_TXCTSE) 1031 temp |= TIOCM_CTS; 1032 1033 if (reg & UARTMODEM_RXRTSE) 1034 temp |= TIOCM_RTS; 1035 1036 return temp; 1037 } 1038 1039 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1040 { 1041 unsigned int temp = 0; 1042 unsigned long reg; 1043 1044 reg = lpuart32_read(port->membase + UARTMODIR); 1045 if (reg & UARTMODIR_TXCTSE) 1046 temp |= TIOCM_CTS; 1047 1048 if (reg & UARTMODIR_RXRTSE) 1049 temp |= TIOCM_RTS; 1050 1051 return temp; 1052 } 1053 1054 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1055 { 1056 unsigned char temp; 1057 struct lpuart_port *sport = container_of(port, 1058 struct lpuart_port, port); 1059 1060 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1061 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1062 temp = readb(sport->port.membase + UARTMODEM) & 1063 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1064 1065 if (mctrl & TIOCM_RTS) 1066 temp |= UARTMODEM_RXRTSE; 1067 1068 if (mctrl & TIOCM_CTS) 1069 temp |= UARTMODEM_TXCTSE; 1070 1071 writeb(temp, port->membase + UARTMODEM); 1072 } 1073 } 1074 1075 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1076 { 1077 unsigned long temp; 1078 1079 temp = lpuart32_read(port->membase + UARTMODIR) & 1080 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 1081 1082 if (mctrl & TIOCM_RTS) 1083 temp |= UARTMODIR_RXRTSE; 1084 1085 if (mctrl & TIOCM_CTS) 1086 temp |= UARTMODIR_TXCTSE; 1087 1088 lpuart32_write(temp, port->membase + UARTMODIR); 1089 } 1090 1091 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1092 { 1093 unsigned char temp; 1094 1095 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1096 1097 if (break_state != 0) 1098 temp |= UARTCR2_SBK; 1099 1100 writeb(temp, port->membase + UARTCR2); 1101 } 1102 1103 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1104 { 1105 unsigned long temp; 1106 1107 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK; 1108 1109 if (break_state != 0) 1110 temp |= UARTCTRL_SBK; 1111 1112 lpuart32_write(temp, port->membase + UARTCTRL); 1113 } 1114 1115 static void lpuart_setup_watermark(struct lpuart_port *sport) 1116 { 1117 unsigned char val, cr2; 1118 unsigned char cr2_saved; 1119 1120 cr2 = readb(sport->port.membase + UARTCR2); 1121 cr2_saved = cr2; 1122 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1123 UARTCR2_RIE | UARTCR2_RE); 1124 writeb(cr2, sport->port.membase + UARTCR2); 1125 1126 val = readb(sport->port.membase + UARTPFIFO); 1127 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1128 sport->port.membase + UARTPFIFO); 1129 1130 /* flush Tx and Rx FIFO */ 1131 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1132 sport->port.membase + UARTCFIFO); 1133 1134 /* explicitly clear RDRF */ 1135 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1136 readb(sport->port.membase + UARTDR); 1137 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1138 } 1139 1140 writeb(0, sport->port.membase + UARTTWFIFO); 1141 writeb(1, sport->port.membase + UARTRWFIFO); 1142 1143 /* Restore cr2 */ 1144 writeb(cr2_saved, sport->port.membase + UARTCR2); 1145 } 1146 1147 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1148 { 1149 unsigned long val, ctrl; 1150 unsigned long ctrl_saved; 1151 1152 ctrl = lpuart32_read(sport->port.membase + UARTCTRL); 1153 ctrl_saved = ctrl; 1154 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1155 UARTCTRL_RIE | UARTCTRL_RE); 1156 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); 1157 1158 /* enable FIFO mode */ 1159 val = lpuart32_read(sport->port.membase + UARTFIFO); 1160 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1161 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1162 lpuart32_write(val, sport->port.membase + UARTFIFO); 1163 1164 /* set the watermark */ 1165 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1166 lpuart32_write(val, sport->port.membase + UARTWATER); 1167 1168 /* Restore cr2 */ 1169 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL); 1170 } 1171 1172 static void rx_dma_timer_init(struct lpuart_port *sport) 1173 { 1174 setup_timer(&sport->lpuart_timer, lpuart_timer_func, 1175 (unsigned long)sport); 1176 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1177 add_timer(&sport->lpuart_timer); 1178 } 1179 1180 static int lpuart_startup(struct uart_port *port) 1181 { 1182 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1183 int ret; 1184 unsigned long flags; 1185 unsigned char temp; 1186 1187 /* determine FIFO size and enable FIFO mode */ 1188 temp = readb(sport->port.membase + UARTPFIFO); 1189 1190 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & 1191 UARTPFIFO_FIFOSIZE_MASK) + 1); 1192 1193 sport->port.fifosize = sport->txfifo_size; 1194 1195 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & 1196 UARTPFIFO_FIFOSIZE_MASK) + 1); 1197 1198 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0, 1199 DRIVER_NAME, sport); 1200 if (ret) 1201 return ret; 1202 1203 spin_lock_irqsave(&sport->port.lock, flags); 1204 1205 lpuart_setup_watermark(sport); 1206 1207 temp = readb(sport->port.membase + UARTCR2); 1208 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 1209 writeb(temp, sport->port.membase + UARTCR2); 1210 1211 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { 1212 /* set Rx DMA timeout */ 1213 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1214 if (!sport->dma_rx_timeout) 1215 sport->dma_rx_timeout = 1; 1216 1217 sport->lpuart_dma_rx_use = true; 1218 rx_dma_timer_init(sport); 1219 } else { 1220 sport->lpuart_dma_rx_use = false; 1221 } 1222 1223 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { 1224 init_waitqueue_head(&sport->dma_wait); 1225 sport->lpuart_dma_tx_use = true; 1226 temp = readb(port->membase + UARTCR5); 1227 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); 1228 } else { 1229 sport->lpuart_dma_tx_use = false; 1230 } 1231 1232 spin_unlock_irqrestore(&sport->port.lock, flags); 1233 1234 return 0; 1235 } 1236 1237 static int lpuart32_startup(struct uart_port *port) 1238 { 1239 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1240 int ret; 1241 unsigned long flags; 1242 unsigned long temp; 1243 1244 /* determine FIFO size */ 1245 temp = lpuart32_read(sport->port.membase + UARTFIFO); 1246 1247 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & 1248 UARTFIFO_FIFOSIZE_MASK) - 1); 1249 1250 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & 1251 UARTFIFO_FIFOSIZE_MASK) - 1); 1252 1253 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0, 1254 DRIVER_NAME, sport); 1255 if (ret) 1256 return ret; 1257 1258 spin_lock_irqsave(&sport->port.lock, flags); 1259 1260 lpuart32_setup_watermark(sport); 1261 1262 temp = lpuart32_read(sport->port.membase + UARTCTRL); 1263 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); 1264 temp |= UARTCTRL_ILIE; 1265 lpuart32_write(temp, sport->port.membase + UARTCTRL); 1266 1267 spin_unlock_irqrestore(&sport->port.lock, flags); 1268 return 0; 1269 } 1270 1271 static void lpuart_shutdown(struct uart_port *port) 1272 { 1273 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1274 unsigned char temp; 1275 unsigned long flags; 1276 1277 spin_lock_irqsave(&port->lock, flags); 1278 1279 /* disable Rx/Tx and interrupts */ 1280 temp = readb(port->membase + UARTCR2); 1281 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1282 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1283 writeb(temp, port->membase + UARTCR2); 1284 1285 spin_unlock_irqrestore(&port->lock, flags); 1286 1287 devm_free_irq(port->dev, port->irq, sport); 1288 1289 if (sport->lpuart_dma_rx_use) { 1290 del_timer_sync(&sport->lpuart_timer); 1291 lpuart_dma_rx_free(&sport->port); 1292 } 1293 1294 if (sport->lpuart_dma_tx_use) { 1295 if (wait_event_interruptible(sport->dma_wait, 1296 !sport->dma_tx_in_progress) != false) { 1297 sport->dma_tx_in_progress = false; 1298 dmaengine_terminate_all(sport->dma_tx_chan); 1299 } 1300 1301 lpuart_stop_tx(port); 1302 } 1303 } 1304 1305 static void lpuart32_shutdown(struct uart_port *port) 1306 { 1307 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1308 unsigned long temp; 1309 unsigned long flags; 1310 1311 spin_lock_irqsave(&port->lock, flags); 1312 1313 /* disable Rx/Tx and interrupts */ 1314 temp = lpuart32_read(port->membase + UARTCTRL); 1315 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1316 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1317 lpuart32_write(temp, port->membase + UARTCTRL); 1318 1319 spin_unlock_irqrestore(&port->lock, flags); 1320 1321 devm_free_irq(port->dev, port->irq, sport); 1322 } 1323 1324 static void 1325 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1326 struct ktermios *old) 1327 { 1328 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1329 unsigned long flags; 1330 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1331 unsigned int baud; 1332 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1333 unsigned int sbr, brfa; 1334 1335 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1336 old_cr2 = readb(sport->port.membase + UARTCR2); 1337 cr3 = readb(sport->port.membase + UARTCR3); 1338 cr4 = readb(sport->port.membase + UARTCR4); 1339 bdh = readb(sport->port.membase + UARTBDH); 1340 modem = readb(sport->port.membase + UARTMODEM); 1341 /* 1342 * only support CS8 and CS7, and for CS7 must enable PE. 1343 * supported mode: 1344 * - (7,e/o,1) 1345 * - (8,n,1) 1346 * - (8,m/s,1) 1347 * - (8,e/o,1) 1348 */ 1349 while ((termios->c_cflag & CSIZE) != CS8 && 1350 (termios->c_cflag & CSIZE) != CS7) { 1351 termios->c_cflag &= ~CSIZE; 1352 termios->c_cflag |= old_csize; 1353 old_csize = CS8; 1354 } 1355 1356 if ((termios->c_cflag & CSIZE) == CS8 || 1357 (termios->c_cflag & CSIZE) == CS7) 1358 cr1 = old_cr1 & ~UARTCR1_M; 1359 1360 if (termios->c_cflag & CMSPAR) { 1361 if ((termios->c_cflag & CSIZE) != CS8) { 1362 termios->c_cflag &= ~CSIZE; 1363 termios->c_cflag |= CS8; 1364 } 1365 cr1 |= UARTCR1_M; 1366 } 1367 1368 /* 1369 * When auto RS-485 RTS mode is enabled, 1370 * hardware flow control need to be disabled. 1371 */ 1372 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1373 termios->c_cflag &= ~CRTSCTS; 1374 1375 if (termios->c_cflag & CRTSCTS) { 1376 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1377 } else { 1378 termios->c_cflag &= ~CRTSCTS; 1379 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1380 } 1381 1382 if (termios->c_cflag & CSTOPB) 1383 termios->c_cflag &= ~CSTOPB; 1384 1385 /* parity must be enabled when CS7 to match 8-bits format */ 1386 if ((termios->c_cflag & CSIZE) == CS7) 1387 termios->c_cflag |= PARENB; 1388 1389 if ((termios->c_cflag & PARENB)) { 1390 if (termios->c_cflag & CMSPAR) { 1391 cr1 &= ~UARTCR1_PE; 1392 if (termios->c_cflag & PARODD) 1393 cr3 |= UARTCR3_T8; 1394 else 1395 cr3 &= ~UARTCR3_T8; 1396 } else { 1397 cr1 |= UARTCR1_PE; 1398 if ((termios->c_cflag & CSIZE) == CS8) 1399 cr1 |= UARTCR1_M; 1400 if (termios->c_cflag & PARODD) 1401 cr1 |= UARTCR1_PT; 1402 else 1403 cr1 &= ~UARTCR1_PT; 1404 } 1405 } 1406 1407 /* ask the core to calculate the divisor */ 1408 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1409 1410 /* 1411 * Need to update the Ring buffer length according to the selected 1412 * baud rate and restart Rx DMA path. 1413 * 1414 * Since timer function acqures sport->port.lock, need to stop before 1415 * acquring same lock because otherwise del_timer_sync() can deadlock. 1416 */ 1417 if (old && sport->lpuart_dma_rx_use) { 1418 del_timer_sync(&sport->lpuart_timer); 1419 lpuart_dma_rx_free(&sport->port); 1420 } 1421 1422 spin_lock_irqsave(&sport->port.lock, flags); 1423 1424 sport->port.read_status_mask = 0; 1425 if (termios->c_iflag & INPCK) 1426 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); 1427 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1428 sport->port.read_status_mask |= UARTSR1_FE; 1429 1430 /* characters to ignore */ 1431 sport->port.ignore_status_mask = 0; 1432 if (termios->c_iflag & IGNPAR) 1433 sport->port.ignore_status_mask |= UARTSR1_PE; 1434 if (termios->c_iflag & IGNBRK) { 1435 sport->port.ignore_status_mask |= UARTSR1_FE; 1436 /* 1437 * if we're ignoring parity and break indicators, 1438 * ignore overruns too (for real raw support). 1439 */ 1440 if (termios->c_iflag & IGNPAR) 1441 sport->port.ignore_status_mask |= UARTSR1_OR; 1442 } 1443 1444 /* update the per-port timeout */ 1445 uart_update_timeout(port, termios->c_cflag, baud); 1446 1447 /* wait transmit engin complete */ 1448 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1449 barrier(); 1450 1451 /* disable transmit and receive */ 1452 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1453 sport->port.membase + UARTCR2); 1454 1455 sbr = sport->port.uartclk / (16 * baud); 1456 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1457 bdh &= ~UARTBDH_SBR_MASK; 1458 bdh |= (sbr >> 8) & 0x1F; 1459 cr4 &= ~UARTCR4_BRFA_MASK; 1460 brfa &= UARTCR4_BRFA_MASK; 1461 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1462 writeb(bdh, sport->port.membase + UARTBDH); 1463 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1464 writeb(cr3, sport->port.membase + UARTCR3); 1465 writeb(cr1, sport->port.membase + UARTCR1); 1466 writeb(modem, sport->port.membase + UARTMODEM); 1467 1468 /* restore control register */ 1469 writeb(old_cr2, sport->port.membase + UARTCR2); 1470 1471 if (old && sport->lpuart_dma_rx_use) { 1472 if (!lpuart_start_rx_dma(sport)) 1473 rx_dma_timer_init(sport); 1474 else 1475 sport->lpuart_dma_rx_use = false; 1476 } 1477 1478 spin_unlock_irqrestore(&sport->port.lock, flags); 1479 } 1480 1481 static void 1482 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1483 struct ktermios *old) 1484 { 1485 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1486 unsigned long flags; 1487 unsigned long ctrl, old_ctrl, bd, modem; 1488 unsigned int baud; 1489 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1490 unsigned int sbr; 1491 1492 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL); 1493 bd = lpuart32_read(sport->port.membase + UARTBAUD); 1494 modem = lpuart32_read(sport->port.membase + UARTMODIR); 1495 /* 1496 * only support CS8 and CS7, and for CS7 must enable PE. 1497 * supported mode: 1498 * - (7,e/o,1) 1499 * - (8,n,1) 1500 * - (8,m/s,1) 1501 * - (8,e/o,1) 1502 */ 1503 while ((termios->c_cflag & CSIZE) != CS8 && 1504 (termios->c_cflag & CSIZE) != CS7) { 1505 termios->c_cflag &= ~CSIZE; 1506 termios->c_cflag |= old_csize; 1507 old_csize = CS8; 1508 } 1509 1510 if ((termios->c_cflag & CSIZE) == CS8 || 1511 (termios->c_cflag & CSIZE) == CS7) 1512 ctrl = old_ctrl & ~UARTCTRL_M; 1513 1514 if (termios->c_cflag & CMSPAR) { 1515 if ((termios->c_cflag & CSIZE) != CS8) { 1516 termios->c_cflag &= ~CSIZE; 1517 termios->c_cflag |= CS8; 1518 } 1519 ctrl |= UARTCTRL_M; 1520 } 1521 1522 if (termios->c_cflag & CRTSCTS) { 1523 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1524 } else { 1525 termios->c_cflag &= ~CRTSCTS; 1526 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1527 } 1528 1529 if (termios->c_cflag & CSTOPB) 1530 termios->c_cflag &= ~CSTOPB; 1531 1532 /* parity must be enabled when CS7 to match 8-bits format */ 1533 if ((termios->c_cflag & CSIZE) == CS7) 1534 termios->c_cflag |= PARENB; 1535 1536 if ((termios->c_cflag & PARENB)) { 1537 if (termios->c_cflag & CMSPAR) { 1538 ctrl &= ~UARTCTRL_PE; 1539 ctrl |= UARTCTRL_M; 1540 } else { 1541 ctrl |= UARTCR1_PE; 1542 if ((termios->c_cflag & CSIZE) == CS8) 1543 ctrl |= UARTCTRL_M; 1544 if (termios->c_cflag & PARODD) 1545 ctrl |= UARTCTRL_PT; 1546 else 1547 ctrl &= ~UARTCTRL_PT; 1548 } 1549 } 1550 1551 /* ask the core to calculate the divisor */ 1552 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1553 1554 spin_lock_irqsave(&sport->port.lock, flags); 1555 1556 sport->port.read_status_mask = 0; 1557 if (termios->c_iflag & INPCK) 1558 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); 1559 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1560 sport->port.read_status_mask |= UARTSTAT_FE; 1561 1562 /* characters to ignore */ 1563 sport->port.ignore_status_mask = 0; 1564 if (termios->c_iflag & IGNPAR) 1565 sport->port.ignore_status_mask |= UARTSTAT_PE; 1566 if (termios->c_iflag & IGNBRK) { 1567 sport->port.ignore_status_mask |= UARTSTAT_FE; 1568 /* 1569 * if we're ignoring parity and break indicators, 1570 * ignore overruns too (for real raw support). 1571 */ 1572 if (termios->c_iflag & IGNPAR) 1573 sport->port.ignore_status_mask |= UARTSTAT_OR; 1574 } 1575 1576 /* update the per-port timeout */ 1577 uart_update_timeout(port, termios->c_cflag, baud); 1578 1579 /* wait transmit engin complete */ 1580 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) 1581 barrier(); 1582 1583 /* disable transmit and receive */ 1584 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 1585 sport->port.membase + UARTCTRL); 1586 1587 sbr = sport->port.uartclk / (16 * baud); 1588 bd &= ~UARTBAUD_SBR_MASK; 1589 bd |= sbr & UARTBAUD_SBR_MASK; 1590 bd |= UARTBAUD_BOTHEDGE; 1591 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1592 lpuart32_write(bd, sport->port.membase + UARTBAUD); 1593 lpuart32_write(modem, sport->port.membase + UARTMODIR); 1594 lpuart32_write(ctrl, sport->port.membase + UARTCTRL); 1595 /* restore control register */ 1596 1597 spin_unlock_irqrestore(&sport->port.lock, flags); 1598 } 1599 1600 static const char *lpuart_type(struct uart_port *port) 1601 { 1602 return "FSL_LPUART"; 1603 } 1604 1605 static void lpuart_release_port(struct uart_port *port) 1606 { 1607 /* nothing to do */ 1608 } 1609 1610 static int lpuart_request_port(struct uart_port *port) 1611 { 1612 return 0; 1613 } 1614 1615 /* configure/autoconfigure the port */ 1616 static void lpuart_config_port(struct uart_port *port, int flags) 1617 { 1618 if (flags & UART_CONFIG_TYPE) 1619 port->type = PORT_LPUART; 1620 } 1621 1622 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 1623 { 1624 int ret = 0; 1625 1626 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 1627 ret = -EINVAL; 1628 if (port->irq != ser->irq) 1629 ret = -EINVAL; 1630 if (ser->io_type != UPIO_MEM) 1631 ret = -EINVAL; 1632 if (port->uartclk / 16 != ser->baud_base) 1633 ret = -EINVAL; 1634 if (port->iobase != ser->port) 1635 ret = -EINVAL; 1636 if (ser->hub6 != 0) 1637 ret = -EINVAL; 1638 return ret; 1639 } 1640 1641 static const struct uart_ops lpuart_pops = { 1642 .tx_empty = lpuart_tx_empty, 1643 .set_mctrl = lpuart_set_mctrl, 1644 .get_mctrl = lpuart_get_mctrl, 1645 .stop_tx = lpuart_stop_tx, 1646 .start_tx = lpuart_start_tx, 1647 .stop_rx = lpuart_stop_rx, 1648 .break_ctl = lpuart_break_ctl, 1649 .startup = lpuart_startup, 1650 .shutdown = lpuart_shutdown, 1651 .set_termios = lpuart_set_termios, 1652 .type = lpuart_type, 1653 .request_port = lpuart_request_port, 1654 .release_port = lpuart_release_port, 1655 .config_port = lpuart_config_port, 1656 .verify_port = lpuart_verify_port, 1657 .flush_buffer = lpuart_flush_buffer, 1658 #if defined(CONFIG_CONSOLE_POLL) 1659 .poll_init = lpuart_poll_init, 1660 .poll_get_char = lpuart_poll_get_char, 1661 .poll_put_char = lpuart_poll_put_char, 1662 #endif 1663 }; 1664 1665 static const struct uart_ops lpuart32_pops = { 1666 .tx_empty = lpuart32_tx_empty, 1667 .set_mctrl = lpuart32_set_mctrl, 1668 .get_mctrl = lpuart32_get_mctrl, 1669 .stop_tx = lpuart32_stop_tx, 1670 .start_tx = lpuart32_start_tx, 1671 .stop_rx = lpuart32_stop_rx, 1672 .break_ctl = lpuart32_break_ctl, 1673 .startup = lpuart32_startup, 1674 .shutdown = lpuart32_shutdown, 1675 .set_termios = lpuart32_set_termios, 1676 .type = lpuart_type, 1677 .request_port = lpuart_request_port, 1678 .release_port = lpuart_release_port, 1679 .config_port = lpuart_config_port, 1680 .verify_port = lpuart_verify_port, 1681 .flush_buffer = lpuart_flush_buffer, 1682 }; 1683 1684 static struct lpuart_port *lpuart_ports[UART_NR]; 1685 1686 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 1687 static void lpuart_console_putchar(struct uart_port *port, int ch) 1688 { 1689 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) 1690 barrier(); 1691 1692 writeb(ch, port->membase + UARTDR); 1693 } 1694 1695 static void lpuart32_console_putchar(struct uart_port *port, int ch) 1696 { 1697 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)) 1698 barrier(); 1699 1700 lpuart32_write(ch, port->membase + UARTDATA); 1701 } 1702 1703 static void 1704 lpuart_console_write(struct console *co, const char *s, unsigned int count) 1705 { 1706 struct lpuart_port *sport = lpuart_ports[co->index]; 1707 unsigned char old_cr2, cr2; 1708 1709 /* first save CR2 and then disable interrupts */ 1710 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 1711 cr2 |= (UARTCR2_TE | UARTCR2_RE); 1712 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1713 writeb(cr2, sport->port.membase + UARTCR2); 1714 1715 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 1716 1717 /* wait for transmitter finish complete and restore CR2 */ 1718 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) 1719 barrier(); 1720 1721 writeb(old_cr2, sport->port.membase + UARTCR2); 1722 } 1723 1724 static void 1725 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 1726 { 1727 struct lpuart_port *sport = lpuart_ports[co->index]; 1728 unsigned long old_cr, cr; 1729 1730 /* first save CR2 and then disable interrupts */ 1731 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL); 1732 cr |= (UARTCTRL_TE | UARTCTRL_RE); 1733 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1734 lpuart32_write(cr, sport->port.membase + UARTCTRL); 1735 1736 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 1737 1738 /* wait for transmitter finish complete and restore CR2 */ 1739 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC)) 1740 barrier(); 1741 1742 lpuart32_write(old_cr, sport->port.membase + UARTCTRL); 1743 } 1744 1745 /* 1746 * if the port was already initialised (eg, by a boot loader), 1747 * try to determine the current setup. 1748 */ 1749 static void __init 1750 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 1751 int *parity, int *bits) 1752 { 1753 unsigned char cr, bdh, bdl, brfa; 1754 unsigned int sbr, uartclk, baud_raw; 1755 1756 cr = readb(sport->port.membase + UARTCR2); 1757 cr &= UARTCR2_TE | UARTCR2_RE; 1758 if (!cr) 1759 return; 1760 1761 /* ok, the port was enabled */ 1762 1763 cr = readb(sport->port.membase + UARTCR1); 1764 1765 *parity = 'n'; 1766 if (cr & UARTCR1_PE) { 1767 if (cr & UARTCR1_PT) 1768 *parity = 'o'; 1769 else 1770 *parity = 'e'; 1771 } 1772 1773 if (cr & UARTCR1_M) 1774 *bits = 9; 1775 else 1776 *bits = 8; 1777 1778 bdh = readb(sport->port.membase + UARTBDH); 1779 bdh &= UARTBDH_SBR_MASK; 1780 bdl = readb(sport->port.membase + UARTBDL); 1781 sbr = bdh; 1782 sbr <<= 8; 1783 sbr |= bdl; 1784 brfa = readb(sport->port.membase + UARTCR4); 1785 brfa &= UARTCR4_BRFA_MASK; 1786 1787 uartclk = clk_get_rate(sport->clk); 1788 /* 1789 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1790 */ 1791 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 1792 1793 if (*baud != baud_raw) 1794 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1795 "from %d to %d\n", baud_raw, *baud); 1796 } 1797 1798 static void __init 1799 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 1800 int *parity, int *bits) 1801 { 1802 unsigned long cr, bd; 1803 unsigned int sbr, uartclk, baud_raw; 1804 1805 cr = lpuart32_read(sport->port.membase + UARTCTRL); 1806 cr &= UARTCTRL_TE | UARTCTRL_RE; 1807 if (!cr) 1808 return; 1809 1810 /* ok, the port was enabled */ 1811 1812 cr = lpuart32_read(sport->port.membase + UARTCTRL); 1813 1814 *parity = 'n'; 1815 if (cr & UARTCTRL_PE) { 1816 if (cr & UARTCTRL_PT) 1817 *parity = 'o'; 1818 else 1819 *parity = 'e'; 1820 } 1821 1822 if (cr & UARTCTRL_M) 1823 *bits = 9; 1824 else 1825 *bits = 8; 1826 1827 bd = lpuart32_read(sport->port.membase + UARTBAUD); 1828 bd &= UARTBAUD_SBR_MASK; 1829 sbr = bd; 1830 uartclk = clk_get_rate(sport->clk); 1831 /* 1832 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 1833 */ 1834 baud_raw = uartclk / (16 * sbr); 1835 1836 if (*baud != baud_raw) 1837 printk(KERN_INFO "Serial: Console lpuart rounded baud rate" 1838 "from %d to %d\n", baud_raw, *baud); 1839 } 1840 1841 static int __init lpuart_console_setup(struct console *co, char *options) 1842 { 1843 struct lpuart_port *sport; 1844 int baud = 115200; 1845 int bits = 8; 1846 int parity = 'n'; 1847 int flow = 'n'; 1848 1849 /* 1850 * check whether an invalid uart number has been specified, and 1851 * if so, search for the first available port that does have 1852 * console support. 1853 */ 1854 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 1855 co->index = 0; 1856 1857 sport = lpuart_ports[co->index]; 1858 if (sport == NULL) 1859 return -ENODEV; 1860 1861 if (options) 1862 uart_parse_options(options, &baud, &parity, &bits, &flow); 1863 else 1864 if (sport->lpuart32) 1865 lpuart32_console_get_options(sport, &baud, &parity, &bits); 1866 else 1867 lpuart_console_get_options(sport, &baud, &parity, &bits); 1868 1869 if (sport->lpuart32) 1870 lpuart32_setup_watermark(sport); 1871 else 1872 lpuart_setup_watermark(sport); 1873 1874 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 1875 } 1876 1877 static struct uart_driver lpuart_reg; 1878 static struct console lpuart_console = { 1879 .name = DEV_NAME, 1880 .write = lpuart_console_write, 1881 .device = uart_console_device, 1882 .setup = lpuart_console_setup, 1883 .flags = CON_PRINTBUFFER, 1884 .index = -1, 1885 .data = &lpuart_reg, 1886 }; 1887 1888 static struct console lpuart32_console = { 1889 .name = DEV_NAME, 1890 .write = lpuart32_console_write, 1891 .device = uart_console_device, 1892 .setup = lpuart_console_setup, 1893 .flags = CON_PRINTBUFFER, 1894 .index = -1, 1895 .data = &lpuart_reg, 1896 }; 1897 1898 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 1899 { 1900 struct earlycon_device *dev = con->data; 1901 1902 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 1903 } 1904 1905 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 1906 { 1907 struct earlycon_device *dev = con->data; 1908 1909 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 1910 } 1911 1912 static int __init lpuart_early_console_setup(struct earlycon_device *device, 1913 const char *opt) 1914 { 1915 if (!device->port.membase) 1916 return -ENODEV; 1917 1918 device->con->write = lpuart_early_write; 1919 return 0; 1920 } 1921 1922 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 1923 const char *opt) 1924 { 1925 if (!device->port.membase) 1926 return -ENODEV; 1927 1928 device->con->write = lpuart32_early_write; 1929 return 0; 1930 } 1931 1932 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 1933 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 1934 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 1935 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 1936 1937 #define LPUART_CONSOLE (&lpuart_console) 1938 #define LPUART32_CONSOLE (&lpuart32_console) 1939 #else 1940 #define LPUART_CONSOLE NULL 1941 #define LPUART32_CONSOLE NULL 1942 #endif 1943 1944 static struct uart_driver lpuart_reg = { 1945 .owner = THIS_MODULE, 1946 .driver_name = DRIVER_NAME, 1947 .dev_name = DEV_NAME, 1948 .nr = ARRAY_SIZE(lpuart_ports), 1949 .cons = LPUART_CONSOLE, 1950 }; 1951 1952 static int lpuart_probe(struct platform_device *pdev) 1953 { 1954 struct device_node *np = pdev->dev.of_node; 1955 struct lpuart_port *sport; 1956 struct resource *res; 1957 int ret; 1958 1959 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 1960 if (!sport) 1961 return -ENOMEM; 1962 1963 pdev->dev.coherent_dma_mask = 0; 1964 1965 ret = of_alias_get_id(np, "serial"); 1966 if (ret < 0) { 1967 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 1968 return ret; 1969 } 1970 sport->port.line = ret; 1971 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart"); 1972 1973 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1974 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 1975 if (IS_ERR(sport->port.membase)) 1976 return PTR_ERR(sport->port.membase); 1977 1978 sport->port.mapbase = res->start; 1979 sport->port.dev = &pdev->dev; 1980 sport->port.type = PORT_LPUART; 1981 sport->port.iotype = UPIO_MEM; 1982 ret = platform_get_irq(pdev, 0); 1983 if (ret < 0) { 1984 dev_err(&pdev->dev, "cannot obtain irq\n"); 1985 return ret; 1986 } 1987 sport->port.irq = ret; 1988 1989 if (sport->lpuart32) 1990 sport->port.ops = &lpuart32_pops; 1991 else 1992 sport->port.ops = &lpuart_pops; 1993 sport->port.flags = UPF_BOOT_AUTOCONF; 1994 1995 sport->port.rs485_config = lpuart_config_rs485; 1996 1997 sport->clk = devm_clk_get(&pdev->dev, "ipg"); 1998 if (IS_ERR(sport->clk)) { 1999 ret = PTR_ERR(sport->clk); 2000 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); 2001 return ret; 2002 } 2003 2004 ret = clk_prepare_enable(sport->clk); 2005 if (ret) { 2006 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); 2007 return ret; 2008 } 2009 2010 sport->port.uartclk = clk_get_rate(sport->clk); 2011 2012 lpuart_ports[sport->port.line] = sport; 2013 2014 platform_set_drvdata(pdev, &sport->port); 2015 2016 if (sport->lpuart32) 2017 lpuart_reg.cons = LPUART32_CONSOLE; 2018 else 2019 lpuart_reg.cons = LPUART_CONSOLE; 2020 2021 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2022 if (ret) { 2023 clk_disable_unprepare(sport->clk); 2024 return ret; 2025 } 2026 2027 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); 2028 if (!sport->dma_tx_chan) 2029 dev_info(sport->port.dev, "DMA tx channel request failed, " 2030 "operating without tx DMA\n"); 2031 2032 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); 2033 if (!sport->dma_rx_chan) 2034 dev_info(sport->port.dev, "DMA rx channel request failed, " 2035 "operating without rx DMA\n"); 2036 2037 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) { 2038 sport->port.rs485.flags |= SER_RS485_ENABLED; 2039 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND; 2040 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM); 2041 } 2042 2043 return 0; 2044 } 2045 2046 static int lpuart_remove(struct platform_device *pdev) 2047 { 2048 struct lpuart_port *sport = platform_get_drvdata(pdev); 2049 2050 uart_remove_one_port(&lpuart_reg, &sport->port); 2051 2052 clk_disable_unprepare(sport->clk); 2053 2054 if (sport->dma_tx_chan) 2055 dma_release_channel(sport->dma_tx_chan); 2056 2057 if (sport->dma_rx_chan) 2058 dma_release_channel(sport->dma_rx_chan); 2059 2060 return 0; 2061 } 2062 2063 #ifdef CONFIG_PM_SLEEP 2064 static int lpuart_suspend(struct device *dev) 2065 { 2066 struct lpuart_port *sport = dev_get_drvdata(dev); 2067 unsigned long temp; 2068 2069 if (sport->lpuart32) { 2070 /* disable Rx/Tx and interrupts */ 2071 temp = lpuart32_read(sport->port.membase + UARTCTRL); 2072 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2073 lpuart32_write(temp, sport->port.membase + UARTCTRL); 2074 } else { 2075 /* disable Rx/Tx and interrupts */ 2076 temp = readb(sport->port.membase + UARTCR2); 2077 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2078 writeb(temp, sport->port.membase + UARTCR2); 2079 } 2080 2081 uart_suspend_port(&lpuart_reg, &sport->port); 2082 2083 if (sport->lpuart_dma_rx_use) { 2084 /* 2085 * EDMA driver during suspend will forcefully release any 2086 * non-idle DMA channels. If port wakeup is enabled or if port 2087 * is console port or 'no_console_suspend' is set the Rx DMA 2088 * cannot resume as as expected, hence gracefully release the 2089 * Rx DMA path before suspend and start Rx DMA path on resume. 2090 */ 2091 if (sport->port.irq_wake) { 2092 del_timer_sync(&sport->lpuart_timer); 2093 lpuart_dma_rx_free(&sport->port); 2094 } 2095 2096 /* Disable Rx DMA to use UART port as wakeup source */ 2097 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, 2098 sport->port.membase + UARTCR5); 2099 } 2100 2101 if (sport->lpuart_dma_tx_use) { 2102 sport->dma_tx_in_progress = false; 2103 dmaengine_terminate_all(sport->dma_tx_chan); 2104 } 2105 2106 if (sport->port.suspended && !sport->port.irq_wake) 2107 clk_disable_unprepare(sport->clk); 2108 2109 return 0; 2110 } 2111 2112 static int lpuart_resume(struct device *dev) 2113 { 2114 struct lpuart_port *sport = dev_get_drvdata(dev); 2115 unsigned long temp; 2116 2117 if (sport->port.suspended && !sport->port.irq_wake) 2118 clk_prepare_enable(sport->clk); 2119 2120 if (sport->lpuart32) { 2121 lpuart32_setup_watermark(sport); 2122 temp = lpuart32_read(sport->port.membase + UARTCTRL); 2123 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | 2124 UARTCTRL_TE | UARTCTRL_ILIE); 2125 lpuart32_write(temp, sport->port.membase + UARTCTRL); 2126 } else { 2127 lpuart_setup_watermark(sport); 2128 temp = readb(sport->port.membase + UARTCR2); 2129 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); 2130 writeb(temp, sport->port.membase + UARTCR2); 2131 } 2132 2133 if (sport->lpuart_dma_rx_use) { 2134 if (sport->port.irq_wake) { 2135 if (!lpuart_start_rx_dma(sport)) 2136 rx_dma_timer_init(sport); 2137 else 2138 sport->lpuart_dma_rx_use = false; 2139 } 2140 } 2141 2142 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { 2143 init_waitqueue_head(&sport->dma_wait); 2144 sport->lpuart_dma_tx_use = true; 2145 writeb(readb(sport->port.membase + UARTCR5) | 2146 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 2147 } else { 2148 sport->lpuart_dma_tx_use = false; 2149 } 2150 2151 uart_resume_port(&lpuart_reg, &sport->port); 2152 2153 return 0; 2154 } 2155 #endif 2156 2157 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2158 2159 static struct platform_driver lpuart_driver = { 2160 .probe = lpuart_probe, 2161 .remove = lpuart_remove, 2162 .driver = { 2163 .name = "fsl-lpuart", 2164 .of_match_table = lpuart_dt_ids, 2165 .pm = &lpuart_pm_ops, 2166 }, 2167 }; 2168 2169 static int __init lpuart_serial_init(void) 2170 { 2171 int ret = uart_register_driver(&lpuart_reg); 2172 2173 if (ret) 2174 return ret; 2175 2176 ret = platform_driver_register(&lpuart_driver); 2177 if (ret) 2178 uart_unregister_driver(&lpuart_reg); 2179 2180 return ret; 2181 } 2182 2183 static void __exit lpuart_serial_exit(void) 2184 { 2185 platform_driver_unregister(&lpuart_driver); 2186 uart_unregister_driver(&lpuart_reg); 2187 } 2188 2189 module_init(lpuart_serial_init); 2190 module_exit(lpuart_serial_exit); 2191 2192 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2193 MODULE_LICENSE("GPL v2"); 2194