1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/circ_buf.h> 11 #include <linux/clk.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_dma.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/serial_core.h> 27 #include <linux/slab.h> 28 #include <linux/tty_flip.h> 29 30 /* All registers are 8-bit width */ 31 #define UARTBDH 0x00 32 #define UARTBDL 0x01 33 #define UARTCR1 0x02 34 #define UARTCR2 0x03 35 #define UARTSR1 0x04 36 #define UARTCR3 0x06 37 #define UARTDR 0x07 38 #define UARTCR4 0x0a 39 #define UARTCR5 0x0b 40 #define UARTMODEM 0x0d 41 #define UARTPFIFO 0x10 42 #define UARTCFIFO 0x11 43 #define UARTSFIFO 0x12 44 #define UARTTWFIFO 0x13 45 #define UARTTCFIFO 0x14 46 #define UARTRWFIFO 0x15 47 48 #define UARTBDH_LBKDIE 0x80 49 #define UARTBDH_RXEDGIE 0x40 50 #define UARTBDH_SBR_MASK 0x1f 51 52 #define UARTCR1_LOOPS 0x80 53 #define UARTCR1_RSRC 0x20 54 #define UARTCR1_M 0x10 55 #define UARTCR1_WAKE 0x08 56 #define UARTCR1_ILT 0x04 57 #define UARTCR1_PE 0x02 58 #define UARTCR1_PT 0x01 59 60 #define UARTCR2_TIE 0x80 61 #define UARTCR2_TCIE 0x40 62 #define UARTCR2_RIE 0x20 63 #define UARTCR2_ILIE 0x10 64 #define UARTCR2_TE 0x08 65 #define UARTCR2_RE 0x04 66 #define UARTCR2_RWU 0x02 67 #define UARTCR2_SBK 0x01 68 69 #define UARTSR1_TDRE 0x80 70 #define UARTSR1_TC 0x40 71 #define UARTSR1_RDRF 0x20 72 #define UARTSR1_IDLE 0x10 73 #define UARTSR1_OR 0x08 74 #define UARTSR1_NF 0x04 75 #define UARTSR1_FE 0x02 76 #define UARTSR1_PE 0x01 77 78 #define UARTCR3_R8 0x80 79 #define UARTCR3_T8 0x40 80 #define UARTCR3_TXDIR 0x20 81 #define UARTCR3_TXINV 0x10 82 #define UARTCR3_ORIE 0x08 83 #define UARTCR3_NEIE 0x04 84 #define UARTCR3_FEIE 0x02 85 #define UARTCR3_PEIE 0x01 86 87 #define UARTCR4_MAEN1 0x80 88 #define UARTCR4_MAEN2 0x40 89 #define UARTCR4_M10 0x20 90 #define UARTCR4_BRFA_MASK 0x1f 91 #define UARTCR4_BRFA_OFF 0 92 93 #define UARTCR5_TDMAS 0x80 94 #define UARTCR5_RDMAS 0x20 95 96 #define UARTMODEM_RXRTSE 0x08 97 #define UARTMODEM_TXRTSPOL 0x04 98 #define UARTMODEM_TXRTSE 0x02 99 #define UARTMODEM_TXCTSE 0x01 100 101 #define UARTPFIFO_TXFE 0x80 102 #define UARTPFIFO_FIFOSIZE_MASK 0x7 103 #define UARTPFIFO_TXSIZE_OFF 4 104 #define UARTPFIFO_RXFE 0x08 105 #define UARTPFIFO_RXSIZE_OFF 0 106 107 #define UARTCFIFO_TXFLUSH 0x80 108 #define UARTCFIFO_RXFLUSH 0x40 109 #define UARTCFIFO_RXOFE 0x04 110 #define UARTCFIFO_TXOFE 0x02 111 #define UARTCFIFO_RXUFE 0x01 112 113 #define UARTSFIFO_TXEMPT 0x80 114 #define UARTSFIFO_RXEMPT 0x40 115 #define UARTSFIFO_RXOF 0x04 116 #define UARTSFIFO_TXOF 0x02 117 #define UARTSFIFO_RXUF 0x01 118 119 /* 32-bit global registers only for i.MX7ULP/i.MX8x 120 * Used to reset all internal logic and registers, except the Global Register. 121 */ 122 #define UART_GLOBAL 0x8 123 124 /* 32-bit register definition */ 125 #define UARTBAUD 0x00 126 #define UARTSTAT 0x04 127 #define UARTCTRL 0x08 128 #define UARTDATA 0x0C 129 #define UARTMATCH 0x10 130 #define UARTMODIR 0x14 131 #define UARTFIFO 0x18 132 #define UARTWATER 0x1c 133 134 #define UARTBAUD_MAEN1 0x80000000 135 #define UARTBAUD_MAEN2 0x40000000 136 #define UARTBAUD_M10 0x20000000 137 #define UARTBAUD_TDMAE 0x00800000 138 #define UARTBAUD_RDMAE 0x00200000 139 #define UARTBAUD_MATCFG 0x00400000 140 #define UARTBAUD_BOTHEDGE 0x00020000 141 #define UARTBAUD_RESYNCDIS 0x00010000 142 #define UARTBAUD_LBKDIE 0x00008000 143 #define UARTBAUD_RXEDGIE 0x00004000 144 #define UARTBAUD_SBNS 0x00002000 145 #define UARTBAUD_SBR 0x00000000 146 #define UARTBAUD_SBR_MASK 0x1fff 147 #define UARTBAUD_OSR_MASK 0x1f 148 #define UARTBAUD_OSR_SHIFT 24 149 150 #define UARTSTAT_LBKDIF 0x80000000 151 #define UARTSTAT_RXEDGIF 0x40000000 152 #define UARTSTAT_MSBF 0x20000000 153 #define UARTSTAT_RXINV 0x10000000 154 #define UARTSTAT_RWUID 0x08000000 155 #define UARTSTAT_BRK13 0x04000000 156 #define UARTSTAT_LBKDE 0x02000000 157 #define UARTSTAT_RAF 0x01000000 158 #define UARTSTAT_TDRE 0x00800000 159 #define UARTSTAT_TC 0x00400000 160 #define UARTSTAT_RDRF 0x00200000 161 #define UARTSTAT_IDLE 0x00100000 162 #define UARTSTAT_OR 0x00080000 163 #define UARTSTAT_NF 0x00040000 164 #define UARTSTAT_FE 0x00020000 165 #define UARTSTAT_PE 0x00010000 166 #define UARTSTAT_MA1F 0x00008000 167 #define UARTSTAT_M21F 0x00004000 168 169 #define UARTCTRL_R8T9 0x80000000 170 #define UARTCTRL_R9T8 0x40000000 171 #define UARTCTRL_TXDIR 0x20000000 172 #define UARTCTRL_TXINV 0x10000000 173 #define UARTCTRL_ORIE 0x08000000 174 #define UARTCTRL_NEIE 0x04000000 175 #define UARTCTRL_FEIE 0x02000000 176 #define UARTCTRL_PEIE 0x01000000 177 #define UARTCTRL_TIE 0x00800000 178 #define UARTCTRL_TCIE 0x00400000 179 #define UARTCTRL_RIE 0x00200000 180 #define UARTCTRL_ILIE 0x00100000 181 #define UARTCTRL_TE 0x00080000 182 #define UARTCTRL_RE 0x00040000 183 #define UARTCTRL_RWU 0x00020000 184 #define UARTCTRL_SBK 0x00010000 185 #define UARTCTRL_MA1IE 0x00008000 186 #define UARTCTRL_MA2IE 0x00004000 187 #define UARTCTRL_M7 0x00000800 188 #define UARTCTRL_IDLECFG GENMASK(10, 8) 189 #define UARTCTRL_LOOPS 0x00000080 190 #define UARTCTRL_DOZEEN 0x00000040 191 #define UARTCTRL_RSRC 0x00000020 192 #define UARTCTRL_M 0x00000010 193 #define UARTCTRL_WAKE 0x00000008 194 #define UARTCTRL_ILT 0x00000004 195 #define UARTCTRL_PE 0x00000002 196 #define UARTCTRL_PT 0x00000001 197 198 #define UARTDATA_NOISY 0x00008000 199 #define UARTDATA_PARITYE 0x00004000 200 #define UARTDATA_FRETSC 0x00002000 201 #define UARTDATA_RXEMPT 0x00001000 202 #define UARTDATA_IDLINE 0x00000800 203 #define UARTDATA_MASK 0x3ff 204 205 #define UARTMODIR_IREN 0x00020000 206 #define UARTMODIR_RTSWATER GENMASK(10, 8) 207 #define UARTMODIR_TXCTSSRC 0x00000020 208 #define UARTMODIR_TXCTSC 0x00000010 209 #define UARTMODIR_RXRTSE 0x00000008 210 #define UARTMODIR_TXRTSPOL 0x00000004 211 #define UARTMODIR_TXRTSE 0x00000002 212 #define UARTMODIR_TXCTSE 0x00000001 213 214 #define UARTFIFO_TXEMPT 0x00800000 215 #define UARTFIFO_RXEMPT 0x00400000 216 #define UARTFIFO_TXOF 0x00020000 217 #define UARTFIFO_RXUF 0x00010000 218 #define UARTFIFO_TXFLUSH 0x00008000 219 #define UARTFIFO_RXFLUSH 0x00004000 220 #define UARTFIFO_RXIDEN GENMASK(12, 10) 221 #define UARTFIFO_TXOFE 0x00000200 222 #define UARTFIFO_RXUFE 0x00000100 223 #define UARTFIFO_TXFE 0x00000080 224 #define UARTFIFO_FIFOSIZE_MASK 0x7 225 #define UARTFIFO_TXSIZE_OFF 4 226 #define UARTFIFO_RXFE 0x00000008 227 #define UARTFIFO_RXSIZE_OFF 0 228 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 229 230 #define UARTWATER_COUNT_MASK 0xff 231 #define UARTWATER_TXCNT_OFF 8 232 #define UARTWATER_RXCNT_OFF 24 233 #define UARTWATER_WATER_MASK 0xff 234 #define UARTWATER_TXWATER_OFF 0 235 #define UARTWATER_RXWATER_OFF 16 236 237 #define UART_GLOBAL_RST 0x2 238 #define GLOBAL_RST_MIN_US 20 239 #define GLOBAL_RST_MAX_US 40 240 241 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 242 #define DMA_RX_TIMEOUT (10) 243 #define DMA_RX_IDLE_CHARS 8 244 #define UART_AUTOSUSPEND_TIMEOUT 3000 245 246 #define DRIVER_NAME "fsl-lpuart" 247 #define DEV_NAME "ttyLP" 248 #define UART_NR 8 249 250 /* IMX lpuart has four extra unused regs located at the beginning */ 251 #define IMX_REG_OFF 0x10 252 253 enum lpuart_type { 254 VF610_LPUART, 255 LS1021A_LPUART, 256 LS1028A_LPUART, 257 IMX7ULP_LPUART, 258 IMX8ULP_LPUART, 259 IMX8QXP_LPUART, 260 IMXRT1050_LPUART, 261 }; 262 263 struct lpuart_port { 264 struct uart_port port; 265 enum lpuart_type devtype; 266 struct clk *ipg_clk; 267 struct clk *baud_clk; 268 unsigned int txfifo_size; 269 unsigned int rxfifo_size; 270 271 u8 rx_watermark; 272 bool lpuart_dma_tx_use; 273 bool lpuart_dma_rx_use; 274 struct dma_chan *dma_tx_chan; 275 struct dma_chan *dma_rx_chan; 276 struct dma_async_tx_descriptor *dma_tx_desc; 277 struct dma_async_tx_descriptor *dma_rx_desc; 278 dma_cookie_t dma_tx_cookie; 279 dma_cookie_t dma_rx_cookie; 280 unsigned int dma_tx_bytes; 281 unsigned int dma_rx_bytes; 282 bool dma_tx_in_progress; 283 unsigned int dma_rx_timeout; 284 struct timer_list lpuart_timer; 285 struct scatterlist rx_sgl, tx_sgl[2]; 286 struct circ_buf rx_ring; 287 int rx_dma_rng_buf_len; 288 int last_residue; 289 unsigned int dma_tx_nents; 290 wait_queue_head_t dma_wait; 291 bool is_cs7; /* Set to true when character size is 7 */ 292 /* and the parity is enabled */ 293 bool dma_idle_int; 294 }; 295 296 struct lpuart_soc_data { 297 enum lpuart_type devtype; 298 char iotype; 299 u8 reg_off; 300 u8 rx_watermark; 301 }; 302 303 static const struct lpuart_soc_data vf_data = { 304 .devtype = VF610_LPUART, 305 .iotype = UPIO_MEM, 306 .rx_watermark = 1, 307 }; 308 309 static const struct lpuart_soc_data ls1021a_data = { 310 .devtype = LS1021A_LPUART, 311 .iotype = UPIO_MEM32BE, 312 .rx_watermark = 1, 313 }; 314 315 static const struct lpuart_soc_data ls1028a_data = { 316 .devtype = LS1028A_LPUART, 317 .iotype = UPIO_MEM32, 318 .rx_watermark = 0, 319 }; 320 321 static struct lpuart_soc_data imx7ulp_data = { 322 .devtype = IMX7ULP_LPUART, 323 .iotype = UPIO_MEM32, 324 .reg_off = IMX_REG_OFF, 325 .rx_watermark = 1, 326 }; 327 328 static struct lpuart_soc_data imx8ulp_data = { 329 .devtype = IMX8ULP_LPUART, 330 .iotype = UPIO_MEM32, 331 .reg_off = IMX_REG_OFF, 332 .rx_watermark = 3, 333 }; 334 335 static struct lpuart_soc_data imx8qxp_data = { 336 .devtype = IMX8QXP_LPUART, 337 .iotype = UPIO_MEM32, 338 .reg_off = IMX_REG_OFF, 339 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */ 340 }; 341 static struct lpuart_soc_data imxrt1050_data = { 342 .devtype = IMXRT1050_LPUART, 343 .iotype = UPIO_MEM32, 344 .reg_off = IMX_REG_OFF, 345 .rx_watermark = 1, 346 }; 347 348 static const struct of_device_id lpuart_dt_ids[] = { 349 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 350 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 351 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 352 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 353 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, }, 354 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 355 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, 356 { /* sentinel */ } 357 }; 358 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 359 360 /* Forward declare this for the dma callbacks*/ 361 static void lpuart_dma_tx_complete(void *arg); 362 363 static inline bool is_layerscape_lpuart(struct lpuart_port *sport) 364 { 365 return (sport->devtype == LS1021A_LPUART || 366 sport->devtype == LS1028A_LPUART); 367 } 368 369 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) 370 { 371 return sport->devtype == IMX7ULP_LPUART; 372 } 373 374 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport) 375 { 376 return sport->devtype == IMX8ULP_LPUART; 377 } 378 379 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 380 { 381 return sport->devtype == IMX8QXP_LPUART; 382 } 383 384 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 385 { 386 switch (port->iotype) { 387 case UPIO_MEM32: 388 return readl(port->membase + off); 389 case UPIO_MEM32BE: 390 return ioread32be(port->membase + off); 391 default: 392 return 0; 393 } 394 } 395 396 static inline void lpuart32_write(struct uart_port *port, u32 val, 397 u32 off) 398 { 399 switch (port->iotype) { 400 case UPIO_MEM32: 401 writel(val, port->membase + off); 402 break; 403 case UPIO_MEM32BE: 404 iowrite32be(val, port->membase + off); 405 break; 406 } 407 } 408 409 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 410 { 411 int ret = 0; 412 413 if (is_en) { 414 ret = clk_prepare_enable(sport->ipg_clk); 415 if (ret) 416 return ret; 417 418 ret = clk_prepare_enable(sport->baud_clk); 419 if (ret) { 420 clk_disable_unprepare(sport->ipg_clk); 421 return ret; 422 } 423 } else { 424 clk_disable_unprepare(sport->baud_clk); 425 clk_disable_unprepare(sport->ipg_clk); 426 } 427 428 return 0; 429 } 430 431 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 432 { 433 if (is_imx8qxp_lpuart(sport)) 434 return clk_get_rate(sport->baud_clk); 435 436 return clk_get_rate(sport->ipg_clk); 437 } 438 439 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 440 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 441 442 static void lpuart_stop_tx(struct uart_port *port) 443 { 444 unsigned char temp; 445 446 temp = readb(port->membase + UARTCR2); 447 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 448 writeb(temp, port->membase + UARTCR2); 449 } 450 451 static void lpuart32_stop_tx(struct uart_port *port) 452 { 453 unsigned long temp; 454 455 temp = lpuart32_read(port, UARTCTRL); 456 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 457 lpuart32_write(port, temp, UARTCTRL); 458 } 459 460 static void lpuart_stop_rx(struct uart_port *port) 461 { 462 unsigned char temp; 463 464 temp = readb(port->membase + UARTCR2); 465 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 466 } 467 468 static void lpuart32_stop_rx(struct uart_port *port) 469 { 470 unsigned long temp; 471 472 temp = lpuart32_read(port, UARTCTRL); 473 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 474 } 475 476 static void lpuart_dma_tx(struct lpuart_port *sport) 477 { 478 struct tty_port *tport = &sport->port.state->port; 479 struct scatterlist *sgl = sport->tx_sgl; 480 struct device *dev = sport->port.dev; 481 struct dma_chan *chan = sport->dma_tx_chan; 482 int ret; 483 484 if (sport->dma_tx_in_progress) 485 return; 486 487 sg_init_table(sgl, ARRAY_SIZE(sport->tx_sgl)); 488 sport->dma_tx_bytes = kfifo_len(&tport->xmit_fifo); 489 sport->dma_tx_nents = kfifo_dma_out_prepare(&tport->xmit_fifo, sgl, 490 ARRAY_SIZE(sport->tx_sgl), sport->dma_tx_bytes); 491 492 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 493 DMA_TO_DEVICE); 494 if (!ret) { 495 dev_err(dev, "DMA mapping error for TX.\n"); 496 return; 497 } 498 499 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 500 ret, DMA_MEM_TO_DEV, 501 DMA_PREP_INTERRUPT); 502 if (!sport->dma_tx_desc) { 503 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 504 DMA_TO_DEVICE); 505 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 506 return; 507 } 508 509 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 510 sport->dma_tx_desc->callback_param = sport; 511 sport->dma_tx_in_progress = true; 512 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 513 dma_async_issue_pending(chan); 514 } 515 516 static bool lpuart_stopped_or_empty(struct uart_port *port) 517 { 518 return kfifo_is_empty(&port->state->port.xmit_fifo) || 519 uart_tx_stopped(port); 520 } 521 522 static void lpuart_dma_tx_complete(void *arg) 523 { 524 struct lpuart_port *sport = arg; 525 struct scatterlist *sgl = &sport->tx_sgl[0]; 526 struct tty_port *tport = &sport->port.state->port; 527 struct dma_chan *chan = sport->dma_tx_chan; 528 unsigned long flags; 529 530 uart_port_lock_irqsave(&sport->port, &flags); 531 if (!sport->dma_tx_in_progress) { 532 uart_port_unlock_irqrestore(&sport->port, flags); 533 return; 534 } 535 536 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 537 DMA_TO_DEVICE); 538 539 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); 540 sport->dma_tx_in_progress = false; 541 uart_port_unlock_irqrestore(&sport->port, flags); 542 543 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 544 uart_write_wakeup(&sport->port); 545 546 if (waitqueue_active(&sport->dma_wait)) { 547 wake_up(&sport->dma_wait); 548 return; 549 } 550 551 uart_port_lock_irqsave(&sport->port, &flags); 552 553 if (!lpuart_stopped_or_empty(&sport->port)) 554 lpuart_dma_tx(sport); 555 556 uart_port_unlock_irqrestore(&sport->port, flags); 557 } 558 559 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 560 { 561 switch (sport->port.iotype) { 562 case UPIO_MEM32: 563 return sport->port.mapbase + UARTDATA; 564 case UPIO_MEM32BE: 565 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 566 } 567 return sport->port.mapbase + UARTDR; 568 } 569 570 static int lpuart_dma_tx_request(struct uart_port *port) 571 { 572 struct lpuart_port *sport = container_of(port, 573 struct lpuart_port, port); 574 struct dma_slave_config dma_tx_sconfig = {}; 575 int ret; 576 577 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 578 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 579 dma_tx_sconfig.dst_maxburst = 1; 580 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 581 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 582 583 if (ret) { 584 dev_err(sport->port.dev, 585 "DMA slave config failed, err = %d\n", ret); 586 return ret; 587 } 588 589 return 0; 590 } 591 592 static bool lpuart_is_32(struct lpuart_port *sport) 593 { 594 return sport->port.iotype == UPIO_MEM32 || 595 sport->port.iotype == UPIO_MEM32BE; 596 } 597 598 static void lpuart_flush_buffer(struct uart_port *port) 599 { 600 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 601 struct dma_chan *chan = sport->dma_tx_chan; 602 u32 val; 603 604 if (sport->lpuart_dma_tx_use) { 605 if (sport->dma_tx_in_progress) { 606 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 607 sport->dma_tx_nents, DMA_TO_DEVICE); 608 sport->dma_tx_in_progress = false; 609 } 610 dmaengine_terminate_async(chan); 611 } 612 613 if (lpuart_is_32(sport)) { 614 val = lpuart32_read(&sport->port, UARTFIFO); 615 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 616 lpuart32_write(&sport->port, val, UARTFIFO); 617 } else { 618 val = readb(sport->port.membase + UARTCFIFO); 619 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 620 writeb(val, sport->port.membase + UARTCFIFO); 621 } 622 } 623 624 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 625 u8 bit) 626 { 627 while (!(readb(port->membase + offset) & bit)) 628 cpu_relax(); 629 } 630 631 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 632 u32 bit) 633 { 634 while (!(lpuart32_read(port, offset) & bit)) 635 cpu_relax(); 636 } 637 638 #if defined(CONFIG_CONSOLE_POLL) 639 640 static int lpuart_poll_init(struct uart_port *port) 641 { 642 struct lpuart_port *sport = container_of(port, 643 struct lpuart_port, port); 644 unsigned long flags; 645 unsigned char temp; 646 647 sport->port.fifosize = 0; 648 649 uart_port_lock_irqsave(&sport->port, &flags); 650 /* Disable Rx & Tx */ 651 writeb(0, sport->port.membase + UARTCR2); 652 653 temp = readb(sport->port.membase + UARTPFIFO); 654 /* Enable Rx and Tx FIFO */ 655 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 656 sport->port.membase + UARTPFIFO); 657 658 /* flush Tx and Rx FIFO */ 659 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 660 sport->port.membase + UARTCFIFO); 661 662 /* explicitly clear RDRF */ 663 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 664 readb(sport->port.membase + UARTDR); 665 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 666 } 667 668 writeb(0, sport->port.membase + UARTTWFIFO); 669 writeb(1, sport->port.membase + UARTRWFIFO); 670 671 /* Enable Rx and Tx */ 672 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 673 uart_port_unlock_irqrestore(&sport->port, flags); 674 675 return 0; 676 } 677 678 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 679 { 680 /* drain */ 681 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 682 writeb(c, port->membase + UARTDR); 683 } 684 685 static int lpuart_poll_get_char(struct uart_port *port) 686 { 687 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 688 return NO_POLL_CHAR; 689 690 return readb(port->membase + UARTDR); 691 } 692 693 static int lpuart32_poll_init(struct uart_port *port) 694 { 695 unsigned long flags; 696 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 697 u32 temp; 698 699 sport->port.fifosize = 0; 700 701 uart_port_lock_irqsave(&sport->port, &flags); 702 703 /* Disable Rx & Tx */ 704 lpuart32_write(&sport->port, 0, UARTCTRL); 705 706 temp = lpuart32_read(&sport->port, UARTFIFO); 707 708 /* Enable Rx and Tx FIFO */ 709 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); 710 711 /* flush Tx and Rx FIFO */ 712 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); 713 714 /* explicitly clear RDRF */ 715 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 716 lpuart32_read(&sport->port, UARTDATA); 717 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); 718 } 719 720 /* Enable Rx and Tx */ 721 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 722 uart_port_unlock_irqrestore(&sport->port, flags); 723 724 return 0; 725 } 726 727 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 728 { 729 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 730 lpuart32_write(port, c, UARTDATA); 731 } 732 733 static int lpuart32_poll_get_char(struct uart_port *port) 734 { 735 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF)) 736 return NO_POLL_CHAR; 737 738 return lpuart32_read(port, UARTDATA); 739 } 740 #endif 741 742 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 743 { 744 struct uart_port *port = &sport->port; 745 u8 ch; 746 747 uart_port_tx(port, ch, 748 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, 749 writeb(ch, port->membase + UARTDR)); 750 } 751 752 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 753 { 754 struct tty_port *tport = &sport->port.state->port; 755 unsigned long txcnt; 756 unsigned char c; 757 758 if (sport->port.x_char) { 759 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 760 sport->port.icount.tx++; 761 sport->port.x_char = 0; 762 return; 763 } 764 765 if (lpuart_stopped_or_empty(&sport->port)) { 766 lpuart32_stop_tx(&sport->port); 767 return; 768 } 769 770 txcnt = lpuart32_read(&sport->port, UARTWATER); 771 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 772 txcnt &= UARTWATER_COUNT_MASK; 773 while (txcnt < sport->txfifo_size && 774 uart_fifo_get(&sport->port, &c)) { 775 lpuart32_write(&sport->port, c, UARTDATA); 776 txcnt = lpuart32_read(&sport->port, UARTWATER); 777 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 778 txcnt &= UARTWATER_COUNT_MASK; 779 } 780 781 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 782 uart_write_wakeup(&sport->port); 783 784 if (kfifo_is_empty(&tport->xmit_fifo)) 785 lpuart32_stop_tx(&sport->port); 786 } 787 788 static void lpuart_start_tx(struct uart_port *port) 789 { 790 struct lpuart_port *sport = container_of(port, 791 struct lpuart_port, port); 792 unsigned char temp; 793 794 temp = readb(port->membase + UARTCR2); 795 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 796 797 if (sport->lpuart_dma_tx_use) { 798 if (!lpuart_stopped_or_empty(port)) 799 lpuart_dma_tx(sport); 800 } else { 801 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 802 lpuart_transmit_buffer(sport); 803 } 804 } 805 806 static void lpuart32_start_tx(struct uart_port *port) 807 { 808 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 809 unsigned long temp; 810 811 if (sport->lpuart_dma_tx_use) { 812 if (!lpuart_stopped_or_empty(port)) 813 lpuart_dma_tx(sport); 814 } else { 815 temp = lpuart32_read(port, UARTCTRL); 816 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 817 818 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 819 lpuart32_transmit_buffer(sport); 820 } 821 } 822 823 static void 824 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) 825 { 826 switch (state) { 827 case UART_PM_STATE_OFF: 828 pm_runtime_mark_last_busy(port->dev); 829 pm_runtime_put_autosuspend(port->dev); 830 break; 831 default: 832 pm_runtime_get_sync(port->dev); 833 break; 834 } 835 } 836 837 /* return TIOCSER_TEMT when transmitter is not busy */ 838 static unsigned int lpuart_tx_empty(struct uart_port *port) 839 { 840 struct lpuart_port *sport = container_of(port, 841 struct lpuart_port, port); 842 unsigned char sr1 = readb(port->membase + UARTSR1); 843 unsigned char sfifo = readb(port->membase + UARTSFIFO); 844 845 if (sport->dma_tx_in_progress) 846 return 0; 847 848 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 849 return TIOCSER_TEMT; 850 851 return 0; 852 } 853 854 static unsigned int lpuart32_tx_empty(struct uart_port *port) 855 { 856 struct lpuart_port *sport = container_of(port, 857 struct lpuart_port, port); 858 unsigned long stat = lpuart32_read(port, UARTSTAT); 859 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 860 unsigned long ctrl = lpuart32_read(port, UARTCTRL); 861 862 if (sport->dma_tx_in_progress) 863 return 0; 864 865 /* 866 * LPUART Transmission Complete Flag may never be set while queuing a break 867 * character, so avoid checking for transmission complete when UARTCTRL_SBK 868 * is asserted. 869 */ 870 if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK) 871 return TIOCSER_TEMT; 872 873 return 0; 874 } 875 876 static void lpuart_txint(struct lpuart_port *sport) 877 { 878 uart_port_lock(&sport->port); 879 lpuart_transmit_buffer(sport); 880 uart_port_unlock(&sport->port); 881 } 882 883 static void lpuart_rxint(struct lpuart_port *sport) 884 { 885 unsigned int flg, ignored = 0, overrun = 0; 886 struct tty_port *port = &sport->port.state->port; 887 unsigned char rx, sr; 888 889 uart_port_lock(&sport->port); 890 891 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 892 flg = TTY_NORMAL; 893 sport->port.icount.rx++; 894 /* 895 * to clear the FE, OR, NF, FE, PE flags, 896 * read SR1 then read DR 897 */ 898 sr = readb(sport->port.membase + UARTSR1); 899 rx = readb(sport->port.membase + UARTDR); 900 901 if (uart_prepare_sysrq_char(&sport->port, rx)) 902 continue; 903 904 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 905 if (sr & UARTSR1_PE) 906 sport->port.icount.parity++; 907 else if (sr & UARTSR1_FE) 908 sport->port.icount.frame++; 909 910 if (sr & UARTSR1_OR) 911 overrun++; 912 913 if (sr & sport->port.ignore_status_mask) { 914 if (++ignored > 100) 915 goto out; 916 continue; 917 } 918 919 sr &= sport->port.read_status_mask; 920 921 if (sr & UARTSR1_PE) 922 flg = TTY_PARITY; 923 else if (sr & UARTSR1_FE) 924 flg = TTY_FRAME; 925 926 if (sr & UARTSR1_OR) 927 flg = TTY_OVERRUN; 928 929 sport->port.sysrq = 0; 930 } 931 932 if (tty_insert_flip_char(port, rx, flg) == 0) 933 sport->port.icount.buf_overrun++; 934 } 935 936 out: 937 if (overrun) { 938 sport->port.icount.overrun += overrun; 939 940 /* 941 * Overruns cause FIFO pointers to become missaligned. 942 * Flushing the receive FIFO reinitializes the pointers. 943 */ 944 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 945 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 946 } 947 948 uart_unlock_and_check_sysrq(&sport->port); 949 950 tty_flip_buffer_push(port); 951 } 952 953 static void lpuart32_txint(struct lpuart_port *sport) 954 { 955 uart_port_lock(&sport->port); 956 lpuart32_transmit_buffer(sport); 957 uart_port_unlock(&sport->port); 958 } 959 960 static void lpuart32_rxint(struct lpuart_port *sport) 961 { 962 unsigned int flg, ignored = 0; 963 struct tty_port *port = &sport->port.state->port; 964 unsigned long rx, sr; 965 bool is_break; 966 967 uart_port_lock(&sport->port); 968 969 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 970 flg = TTY_NORMAL; 971 sport->port.icount.rx++; 972 /* 973 * to clear the FE, OR, NF, FE, PE flags, 974 * read STAT then read DATA reg 975 */ 976 sr = lpuart32_read(&sport->port, UARTSTAT); 977 rx = lpuart32_read(&sport->port, UARTDATA); 978 rx &= UARTDATA_MASK; 979 980 /* 981 * The LPUART can't distinguish between a break and a framing error, 982 * thus we assume it is a break if the received data is zero. 983 */ 984 is_break = (sr & UARTSTAT_FE) && !rx; 985 986 if (is_break && uart_handle_break(&sport->port)) 987 continue; 988 989 if (uart_prepare_sysrq_char(&sport->port, rx)) 990 continue; 991 992 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 993 if (sr & UARTSTAT_PE) { 994 sport->port.icount.parity++; 995 } else if (sr & UARTSTAT_FE) { 996 if (is_break) 997 sport->port.icount.brk++; 998 else 999 sport->port.icount.frame++; 1000 } 1001 1002 if (sr & UARTSTAT_OR) 1003 sport->port.icount.overrun++; 1004 1005 if (sr & sport->port.ignore_status_mask) { 1006 if (++ignored > 100) 1007 goto out; 1008 continue; 1009 } 1010 1011 sr &= sport->port.read_status_mask; 1012 1013 if (sr & UARTSTAT_PE) { 1014 flg = TTY_PARITY; 1015 } else if (sr & UARTSTAT_FE) { 1016 if (is_break) 1017 flg = TTY_BREAK; 1018 else 1019 flg = TTY_FRAME; 1020 } 1021 1022 if (sr & UARTSTAT_OR) 1023 flg = TTY_OVERRUN; 1024 } 1025 1026 if (sport->is_cs7) 1027 rx &= 0x7F; 1028 1029 if (tty_insert_flip_char(port, rx, flg) == 0) 1030 sport->port.icount.buf_overrun++; 1031 } 1032 1033 out: 1034 uart_unlock_and_check_sysrq(&sport->port); 1035 1036 tty_flip_buffer_push(port); 1037 } 1038 1039 static irqreturn_t lpuart_int(int irq, void *dev_id) 1040 { 1041 struct lpuart_port *sport = dev_id; 1042 unsigned char sts; 1043 1044 sts = readb(sport->port.membase + UARTSR1); 1045 1046 /* SysRq, using dma, check for linebreak by framing err. */ 1047 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { 1048 readb(sport->port.membase + UARTDR); 1049 uart_handle_break(&sport->port); 1050 /* linebreak produces some garbage, removing it */ 1051 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 1052 return IRQ_HANDLED; 1053 } 1054 1055 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 1056 lpuart_rxint(sport); 1057 1058 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 1059 lpuart_txint(sport); 1060 1061 return IRQ_HANDLED; 1062 } 1063 1064 static inline void lpuart_handle_sysrq_chars(struct uart_port *port, 1065 unsigned char *p, int count) 1066 { 1067 while (count--) { 1068 if (*p && uart_handle_sysrq_char(port, *p)) 1069 return; 1070 p++; 1071 } 1072 } 1073 1074 static void lpuart_handle_sysrq(struct lpuart_port *sport) 1075 { 1076 struct circ_buf *ring = &sport->rx_ring; 1077 int count; 1078 1079 if (ring->head < ring->tail) { 1080 count = sport->rx_sgl.length - ring->tail; 1081 lpuart_handle_sysrq_chars(&sport->port, 1082 ring->buf + ring->tail, count); 1083 ring->tail = 0; 1084 } 1085 1086 if (ring->head > ring->tail) { 1087 count = ring->head - ring->tail; 1088 lpuart_handle_sysrq_chars(&sport->port, 1089 ring->buf + ring->tail, count); 1090 ring->tail = ring->head; 1091 } 1092 } 1093 1094 static int lpuart_tty_insert_flip_string(struct tty_port *port, 1095 unsigned char *chars, size_t size, bool is_cs7) 1096 { 1097 int i; 1098 1099 if (is_cs7) 1100 for (i = 0; i < size; i++) 1101 chars[i] &= 0x7F; 1102 return tty_insert_flip_string(port, chars, size); 1103 } 1104 1105 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1106 { 1107 struct tty_port *port = &sport->port.state->port; 1108 struct dma_tx_state state; 1109 enum dma_status dmastat; 1110 struct dma_chan *chan = sport->dma_rx_chan; 1111 struct circ_buf *ring = &sport->rx_ring; 1112 unsigned long flags; 1113 int count, copied; 1114 1115 if (lpuart_is_32(sport)) { 1116 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1117 1118 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1119 /* Clear the error flags */ 1120 lpuart32_write(&sport->port, sr, UARTSTAT); 1121 1122 if (sr & UARTSTAT_PE) 1123 sport->port.icount.parity++; 1124 else if (sr & UARTSTAT_FE) 1125 sport->port.icount.frame++; 1126 } 1127 } else { 1128 unsigned char sr = readb(sport->port.membase + UARTSR1); 1129 1130 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1131 unsigned char cr2; 1132 1133 /* Disable receiver during this operation... */ 1134 cr2 = readb(sport->port.membase + UARTCR2); 1135 cr2 &= ~UARTCR2_RE; 1136 writeb(cr2, sport->port.membase + UARTCR2); 1137 1138 /* Read DR to clear the error flags */ 1139 readb(sport->port.membase + UARTDR); 1140 1141 if (sr & UARTSR1_PE) 1142 sport->port.icount.parity++; 1143 else if (sr & UARTSR1_FE) 1144 sport->port.icount.frame++; 1145 /* 1146 * At this point parity/framing error is 1147 * cleared However, since the DMA already read 1148 * the data register and we had to read it 1149 * again after reading the status register to 1150 * properly clear the flags, the FIFO actually 1151 * underflowed... This requires a clearing of 1152 * the FIFO... 1153 */ 1154 if (readb(sport->port.membase + UARTSFIFO) & 1155 UARTSFIFO_RXUF) { 1156 writeb(UARTSFIFO_RXUF, 1157 sport->port.membase + UARTSFIFO); 1158 writeb(UARTCFIFO_RXFLUSH, 1159 sport->port.membase + UARTCFIFO); 1160 } 1161 1162 cr2 |= UARTCR2_RE; 1163 writeb(cr2, sport->port.membase + UARTCR2); 1164 } 1165 } 1166 1167 async_tx_ack(sport->dma_rx_desc); 1168 1169 uart_port_lock_irqsave(&sport->port, &flags); 1170 1171 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1172 if (dmastat == DMA_ERROR) { 1173 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1174 uart_port_unlock_irqrestore(&sport->port, flags); 1175 return; 1176 } 1177 1178 /* CPU claims ownership of RX DMA buffer */ 1179 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1180 DMA_FROM_DEVICE); 1181 1182 /* 1183 * ring->head points to the end of data already written by the DMA. 1184 * ring->tail points to the beginning of data to be read by the 1185 * framework. 1186 * The current transfer size should not be larger than the dma buffer 1187 * length. 1188 */ 1189 ring->head = sport->rx_sgl.length - state.residue; 1190 BUG_ON(ring->head > sport->rx_sgl.length); 1191 1192 /* 1193 * Silent handling of keys pressed in the sysrq timeframe 1194 */ 1195 if (sport->port.sysrq) { 1196 lpuart_handle_sysrq(sport); 1197 goto exit; 1198 } 1199 1200 /* 1201 * At this point ring->head may point to the first byte right after the 1202 * last byte of the dma buffer: 1203 * 0 <= ring->head <= sport->rx_sgl.length 1204 * 1205 * However ring->tail must always points inside the dma buffer: 1206 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1207 * 1208 * Since we use a ring buffer, we have to handle the case 1209 * where head is lower than tail. In such a case, we first read from 1210 * tail to the end of the buffer then reset tail. 1211 */ 1212 if (ring->head < ring->tail) { 1213 count = sport->rx_sgl.length - ring->tail; 1214 1215 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1216 count, sport->is_cs7); 1217 if (copied != count) 1218 sport->port.icount.buf_overrun++; 1219 ring->tail = 0; 1220 sport->port.icount.rx += copied; 1221 } 1222 1223 /* Finally we read data from tail to head */ 1224 if (ring->tail < ring->head) { 1225 count = ring->head - ring->tail; 1226 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, 1227 count, sport->is_cs7); 1228 if (copied != count) 1229 sport->port.icount.buf_overrun++; 1230 /* Wrap ring->head if needed */ 1231 if (ring->head >= sport->rx_sgl.length) 1232 ring->head = 0; 1233 ring->tail = ring->head; 1234 sport->port.icount.rx += copied; 1235 } 1236 1237 sport->last_residue = state.residue; 1238 1239 exit: 1240 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1241 DMA_FROM_DEVICE); 1242 1243 uart_port_unlock_irqrestore(&sport->port, flags); 1244 1245 tty_flip_buffer_push(port); 1246 if (!sport->dma_idle_int) 1247 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1248 } 1249 1250 static void lpuart_dma_rx_complete(void *arg) 1251 { 1252 struct lpuart_port *sport = arg; 1253 1254 lpuart_copy_rx_to_tty(sport); 1255 } 1256 1257 static void lpuart32_dma_idleint(struct lpuart_port *sport) 1258 { 1259 enum dma_status dmastat; 1260 struct dma_chan *chan = sport->dma_rx_chan; 1261 struct circ_buf *ring = &sport->rx_ring; 1262 struct dma_tx_state state; 1263 int count = 0; 1264 1265 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1266 if (dmastat == DMA_ERROR) { 1267 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1268 return; 1269 } 1270 1271 ring->head = sport->rx_sgl.length - state.residue; 1272 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); 1273 1274 /* Check if new data received before copying */ 1275 if (count) 1276 lpuart_copy_rx_to_tty(sport); 1277 } 1278 1279 static irqreturn_t lpuart32_int(int irq, void *dev_id) 1280 { 1281 struct lpuart_port *sport = dev_id; 1282 unsigned long sts, rxcount; 1283 1284 sts = lpuart32_read(&sport->port, UARTSTAT); 1285 rxcount = lpuart32_read(&sport->port, UARTWATER); 1286 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 1287 1288 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1289 lpuart32_rxint(sport); 1290 1291 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1292 lpuart32_txint(sport); 1293 1294 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) 1295 lpuart32_dma_idleint(sport); 1296 1297 lpuart32_write(&sport->port, sts, UARTSTAT); 1298 return IRQ_HANDLED; 1299 } 1300 1301 /* 1302 * Timer function to simulate the hardware EOP (End Of Package) event. 1303 * The timer callback is to check for new RX data and copy to TTY buffer. 1304 * If no new data are received since last interval, the EOP condition is 1305 * met, complete the DMA transfer by copying the data. Otherwise, just 1306 * restart timer. 1307 */ 1308 static void lpuart_timer_func(struct timer_list *t) 1309 { 1310 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1311 enum dma_status dmastat; 1312 struct dma_chan *chan = sport->dma_rx_chan; 1313 struct circ_buf *ring = &sport->rx_ring; 1314 struct dma_tx_state state; 1315 unsigned long flags; 1316 int count; 1317 1318 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1319 if (dmastat == DMA_ERROR) { 1320 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1321 return; 1322 } 1323 1324 ring->head = sport->rx_sgl.length - state.residue; 1325 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); 1326 1327 /* Check if new data received before copying */ 1328 if ((count != 0) && (sport->last_residue == state.residue)) 1329 lpuart_copy_rx_to_tty(sport); 1330 else 1331 mod_timer(&sport->lpuart_timer, 1332 jiffies + sport->dma_rx_timeout); 1333 1334 if (uart_port_trylock_irqsave(&sport->port, &flags)) { 1335 sport->last_residue = state.residue; 1336 uart_port_unlock_irqrestore(&sport->port, flags); 1337 } 1338 } 1339 1340 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1341 { 1342 struct dma_slave_config dma_rx_sconfig = {}; 1343 struct circ_buf *ring = &sport->rx_ring; 1344 int ret, nent; 1345 struct tty_port *port = &sport->port.state->port; 1346 struct tty_struct *tty = port->tty; 1347 struct ktermios *termios = &tty->termios; 1348 struct dma_chan *chan = sport->dma_rx_chan; 1349 unsigned int bits = tty_get_frame_size(termios->c_cflag); 1350 unsigned int baud = tty_get_baud_rate(tty); 1351 1352 /* 1353 * Calculate length of one DMA buffer size to keep latency below 1354 * 10ms at any baud rate. 1355 */ 1356 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1357 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); 1358 sport->rx_dma_rng_buf_len = max_t(int, 1359 sport->rxfifo_size * 2, 1360 sport->rx_dma_rng_buf_len); 1361 /* 1362 * Keep this condition check in case rxfifo_size is unavailable 1363 * for some SoCs. 1364 */ 1365 if (sport->rx_dma_rng_buf_len < 16) 1366 sport->rx_dma_rng_buf_len = 16; 1367 1368 sport->last_residue = 0; 1369 sport->dma_rx_timeout = max(nsecs_to_jiffies( 1370 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); 1371 1372 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1373 if (!ring->buf) 1374 return -ENOMEM; 1375 1376 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1377 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1378 DMA_FROM_DEVICE); 1379 1380 if (!nent) { 1381 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1382 return -EINVAL; 1383 } 1384 1385 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1386 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1387 dma_rx_sconfig.src_maxburst = 1; 1388 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1389 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1390 1391 if (ret < 0) { 1392 dev_err(sport->port.dev, 1393 "DMA Rx slave config failed, err = %d\n", ret); 1394 return ret; 1395 } 1396 1397 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1398 sg_dma_address(&sport->rx_sgl), 1399 sport->rx_sgl.length, 1400 sport->rx_sgl.length / 2, 1401 DMA_DEV_TO_MEM, 1402 DMA_PREP_INTERRUPT); 1403 if (!sport->dma_rx_desc) { 1404 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1405 return -EFAULT; 1406 } 1407 1408 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1409 sport->dma_rx_desc->callback_param = sport; 1410 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1411 dma_async_issue_pending(chan); 1412 1413 if (lpuart_is_32(sport)) { 1414 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1415 1416 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1417 1418 if (sport->dma_idle_int) { 1419 unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL); 1420 1421 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); 1422 } 1423 } else { 1424 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1425 sport->port.membase + UARTCR5); 1426 } 1427 1428 return 0; 1429 } 1430 1431 static void lpuart_dma_rx_free(struct uart_port *port) 1432 { 1433 struct lpuart_port *sport = container_of(port, 1434 struct lpuart_port, port); 1435 struct dma_chan *chan = sport->dma_rx_chan; 1436 1437 dmaengine_terminate_sync(chan); 1438 if (!sport->dma_idle_int) 1439 del_timer_sync(&sport->lpuart_timer); 1440 1441 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1442 kfree(sport->rx_ring.buf); 1443 sport->rx_ring.tail = 0; 1444 sport->rx_ring.head = 0; 1445 sport->dma_rx_desc = NULL; 1446 sport->dma_rx_cookie = -EINVAL; 1447 } 1448 1449 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios, 1450 struct serial_rs485 *rs485) 1451 { 1452 struct lpuart_port *sport = container_of(port, 1453 struct lpuart_port, port); 1454 1455 u8 modem = readb(sport->port.membase + UARTMODEM) & 1456 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1457 writeb(modem, sport->port.membase + UARTMODEM); 1458 1459 if (rs485->flags & SER_RS485_ENABLED) { 1460 /* Enable auto RS-485 RTS mode */ 1461 modem |= UARTMODEM_TXRTSE; 1462 1463 /* 1464 * The hardware defaults to RTS logic HIGH while transfer. 1465 * Switch polarity in case RTS shall be logic HIGH 1466 * after transfer. 1467 * Note: UART is assumed to be active high. 1468 */ 1469 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1470 modem |= UARTMODEM_TXRTSPOL; 1471 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1472 modem &= ~UARTMODEM_TXRTSPOL; 1473 } 1474 1475 writeb(modem, sport->port.membase + UARTMODEM); 1476 return 0; 1477 } 1478 1479 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios, 1480 struct serial_rs485 *rs485) 1481 { 1482 struct lpuart_port *sport = container_of(port, 1483 struct lpuart_port, port); 1484 1485 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1486 & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE); 1487 lpuart32_write(&sport->port, modem, UARTMODIR); 1488 1489 if (rs485->flags & SER_RS485_ENABLED) { 1490 /* Enable auto RS-485 RTS mode */ 1491 modem |= UARTMODIR_TXRTSE; 1492 1493 /* 1494 * The hardware defaults to RTS logic HIGH while transfer. 1495 * Switch polarity in case RTS shall be logic HIGH 1496 * after transfer. 1497 * Note: UART is assumed to be active high. 1498 */ 1499 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1500 modem |= UARTMODIR_TXRTSPOL; 1501 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1502 modem &= ~UARTMODIR_TXRTSPOL; 1503 } 1504 1505 lpuart32_write(&sport->port, modem, UARTMODIR); 1506 return 0; 1507 } 1508 1509 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1510 { 1511 unsigned int mctrl = 0; 1512 u8 reg; 1513 1514 reg = readb(port->membase + UARTCR1); 1515 if (reg & UARTCR1_LOOPS) 1516 mctrl |= TIOCM_LOOP; 1517 1518 return mctrl; 1519 } 1520 1521 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1522 { 1523 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 1524 u32 reg; 1525 1526 reg = lpuart32_read(port, UARTCTRL); 1527 if (reg & UARTCTRL_LOOPS) 1528 mctrl |= TIOCM_LOOP; 1529 1530 return mctrl; 1531 } 1532 1533 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1534 { 1535 u8 reg; 1536 1537 reg = readb(port->membase + UARTCR1); 1538 1539 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1540 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC); 1541 if (mctrl & TIOCM_LOOP) 1542 reg |= UARTCR1_LOOPS; 1543 1544 writeb(reg, port->membase + UARTCR1); 1545 } 1546 1547 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1548 { 1549 u32 reg; 1550 1551 reg = lpuart32_read(port, UARTCTRL); 1552 1553 /* for internal loopback we need LOOPS=1 and RSRC=0 */ 1554 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC); 1555 if (mctrl & TIOCM_LOOP) 1556 reg |= UARTCTRL_LOOPS; 1557 1558 lpuart32_write(port, reg, UARTCTRL); 1559 } 1560 1561 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1562 { 1563 unsigned char temp; 1564 1565 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1566 1567 if (break_state != 0) 1568 temp |= UARTCR2_SBK; 1569 1570 writeb(temp, port->membase + UARTCR2); 1571 } 1572 1573 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1574 { 1575 unsigned long temp; 1576 1577 temp = lpuart32_read(port, UARTCTRL); 1578 1579 /* 1580 * LPUART IP now has two known bugs, one is CTS has higher priority than the 1581 * break signal, which causes the break signal sending through UARTCTRL_SBK 1582 * may impacted by the CTS input if the HW flow control is enabled. It 1583 * exists on all platforms we support in this driver. 1584 * Another bug is i.MX8QM LPUART may have an additional break character 1585 * being sent after SBK was cleared. 1586 * To avoid above two bugs, we use Transmit Data Inversion function to send 1587 * the break signal instead of UARTCTRL_SBK. 1588 */ 1589 if (break_state != 0) { 1590 /* 1591 * Disable the transmitter to prevent any data from being sent out 1592 * during break, then invert the TX line to send break. 1593 */ 1594 temp &= ~UARTCTRL_TE; 1595 lpuart32_write(port, temp, UARTCTRL); 1596 temp |= UARTCTRL_TXINV; 1597 lpuart32_write(port, temp, UARTCTRL); 1598 } else { 1599 /* Disable the TXINV to turn off break and re-enable transmitter. */ 1600 temp &= ~UARTCTRL_TXINV; 1601 lpuart32_write(port, temp, UARTCTRL); 1602 temp |= UARTCTRL_TE; 1603 lpuart32_write(port, temp, UARTCTRL); 1604 } 1605 } 1606 1607 static void lpuart_setup_watermark(struct lpuart_port *sport) 1608 { 1609 unsigned char val, cr2; 1610 unsigned char cr2_saved; 1611 1612 cr2 = readb(sport->port.membase + UARTCR2); 1613 cr2_saved = cr2; 1614 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1615 UARTCR2_RIE | UARTCR2_RE); 1616 writeb(cr2, sport->port.membase + UARTCR2); 1617 1618 val = readb(sport->port.membase + UARTPFIFO); 1619 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1620 sport->port.membase + UARTPFIFO); 1621 1622 /* flush Tx and Rx FIFO */ 1623 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1624 sport->port.membase + UARTCFIFO); 1625 1626 /* explicitly clear RDRF */ 1627 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1628 readb(sport->port.membase + UARTDR); 1629 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1630 } 1631 1632 if (uart_console(&sport->port)) 1633 sport->rx_watermark = 1; 1634 writeb(0, sport->port.membase + UARTTWFIFO); 1635 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); 1636 1637 /* Restore cr2 */ 1638 writeb(cr2_saved, sport->port.membase + UARTCR2); 1639 } 1640 1641 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1642 { 1643 unsigned char cr2; 1644 1645 lpuart_setup_watermark(sport); 1646 1647 cr2 = readb(sport->port.membase + UARTCR2); 1648 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1649 writeb(cr2, sport->port.membase + UARTCR2); 1650 } 1651 1652 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1653 { 1654 unsigned long val, ctrl; 1655 unsigned long ctrl_saved; 1656 1657 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1658 ctrl_saved = ctrl; 1659 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1660 UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE); 1661 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1662 1663 /* enable FIFO mode */ 1664 val = lpuart32_read(&sport->port, UARTFIFO); 1665 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1666 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1667 val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3); 1668 lpuart32_write(&sport->port, val, UARTFIFO); 1669 1670 /* set the watermark */ 1671 if (uart_console(&sport->port)) 1672 sport->rx_watermark = 1; 1673 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | 1674 (0x0 << UARTWATER_TXWATER_OFF); 1675 lpuart32_write(&sport->port, val, UARTWATER); 1676 1677 /* set RTS watermark */ 1678 if (!uart_console(&sport->port)) { 1679 val = lpuart32_read(&sport->port, UARTMODIR); 1680 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); 1681 lpuart32_write(&sport->port, val, UARTMODIR); 1682 } 1683 1684 /* Restore cr2 */ 1685 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1686 } 1687 1688 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1689 { 1690 u32 temp; 1691 1692 lpuart32_setup_watermark(sport); 1693 1694 temp = lpuart32_read(&sport->port, UARTCTRL); 1695 temp |= UARTCTRL_RE | UARTCTRL_TE; 1696 temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7); 1697 lpuart32_write(&sport->port, temp, UARTCTRL); 1698 } 1699 1700 static void rx_dma_timer_init(struct lpuart_port *sport) 1701 { 1702 if (sport->dma_idle_int) 1703 return; 1704 1705 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1706 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1707 add_timer(&sport->lpuart_timer); 1708 } 1709 1710 static void lpuart_request_dma(struct lpuart_port *sport) 1711 { 1712 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1713 if (IS_ERR(sport->dma_tx_chan)) { 1714 dev_dbg_once(sport->port.dev, 1715 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1716 PTR_ERR(sport->dma_tx_chan)); 1717 sport->dma_tx_chan = NULL; 1718 } 1719 1720 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1721 if (IS_ERR(sport->dma_rx_chan)) { 1722 dev_dbg_once(sport->port.dev, 1723 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1724 PTR_ERR(sport->dma_rx_chan)); 1725 sport->dma_rx_chan = NULL; 1726 } 1727 } 1728 1729 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1730 { 1731 u32 uartbaud; 1732 int ret; 1733 1734 if (uart_console(&sport->port)) 1735 goto err; 1736 1737 if (!sport->dma_tx_chan) 1738 goto err; 1739 1740 ret = lpuart_dma_tx_request(&sport->port); 1741 if (ret) 1742 goto err; 1743 1744 init_waitqueue_head(&sport->dma_wait); 1745 sport->lpuart_dma_tx_use = true; 1746 if (lpuart_is_32(sport)) { 1747 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1748 lpuart32_write(&sport->port, 1749 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1750 } else { 1751 writeb(readb(sport->port.membase + UARTCR5) | 1752 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1753 } 1754 1755 return; 1756 1757 err: 1758 sport->lpuart_dma_tx_use = false; 1759 } 1760 1761 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1762 { 1763 int ret; 1764 unsigned char cr3; 1765 1766 if (uart_console(&sport->port)) 1767 goto err; 1768 1769 if (!sport->dma_rx_chan) 1770 goto err; 1771 1772 /* set default Rx DMA timeout */ 1773 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1774 1775 ret = lpuart_start_rx_dma(sport); 1776 if (ret) 1777 goto err; 1778 1779 if (!sport->dma_rx_timeout) 1780 sport->dma_rx_timeout = 1; 1781 1782 sport->lpuart_dma_rx_use = true; 1783 rx_dma_timer_init(sport); 1784 1785 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { 1786 cr3 = readb(sport->port.membase + UARTCR3); 1787 cr3 |= UARTCR3_FEIE; 1788 writeb(cr3, sport->port.membase + UARTCR3); 1789 } 1790 1791 return; 1792 1793 err: 1794 sport->lpuart_dma_rx_use = false; 1795 } 1796 1797 static void lpuart_hw_setup(struct lpuart_port *sport) 1798 { 1799 unsigned long flags; 1800 1801 uart_port_lock_irqsave(&sport->port, &flags); 1802 1803 lpuart_setup_watermark_enable(sport); 1804 1805 lpuart_rx_dma_startup(sport); 1806 lpuart_tx_dma_startup(sport); 1807 1808 uart_port_unlock_irqrestore(&sport->port, flags); 1809 } 1810 1811 static int lpuart_startup(struct uart_port *port) 1812 { 1813 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1814 unsigned char temp; 1815 1816 /* determine FIFO size and enable FIFO mode */ 1817 temp = readb(sport->port.membase + UARTPFIFO); 1818 1819 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1820 UARTPFIFO_FIFOSIZE_MASK); 1821 sport->port.fifosize = sport->txfifo_size; 1822 1823 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1824 UARTPFIFO_FIFOSIZE_MASK); 1825 1826 lpuart_request_dma(sport); 1827 lpuart_hw_setup(sport); 1828 1829 return 0; 1830 } 1831 1832 static void lpuart32_hw_disable(struct lpuart_port *sport) 1833 { 1834 unsigned long temp; 1835 1836 temp = lpuart32_read(&sport->port, UARTCTRL); 1837 temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | 1838 UARTCTRL_TIE | UARTCTRL_TE); 1839 lpuart32_write(&sport->port, temp, UARTCTRL); 1840 } 1841 1842 static void lpuart32_configure(struct lpuart_port *sport) 1843 { 1844 unsigned long temp; 1845 1846 temp = lpuart32_read(&sport->port, UARTCTRL); 1847 if (!sport->lpuart_dma_rx_use) 1848 temp |= UARTCTRL_RIE | UARTCTRL_ILIE; 1849 if (!sport->lpuart_dma_tx_use) 1850 temp |= UARTCTRL_TIE; 1851 lpuart32_write(&sport->port, temp, UARTCTRL); 1852 } 1853 1854 static void lpuart32_hw_setup(struct lpuart_port *sport) 1855 { 1856 unsigned long flags; 1857 1858 uart_port_lock_irqsave(&sport->port, &flags); 1859 1860 lpuart32_hw_disable(sport); 1861 1862 lpuart_rx_dma_startup(sport); 1863 lpuart_tx_dma_startup(sport); 1864 1865 lpuart32_setup_watermark_enable(sport); 1866 lpuart32_configure(sport); 1867 1868 uart_port_unlock_irqrestore(&sport->port, flags); 1869 } 1870 1871 static int lpuart32_startup(struct uart_port *port) 1872 { 1873 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1874 unsigned long temp; 1875 1876 /* determine FIFO size */ 1877 temp = lpuart32_read(&sport->port, UARTFIFO); 1878 1879 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1880 UARTFIFO_FIFOSIZE_MASK); 1881 sport->port.fifosize = sport->txfifo_size; 1882 1883 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1884 UARTFIFO_FIFOSIZE_MASK); 1885 1886 /* 1887 * The LS1021A and LS1028A have a fixed FIFO depth of 16 words. 1888 * Although they support the RX/TXSIZE fields, their encoding is 1889 * different. Eg the reference manual states 0b101 is 16 words. 1890 */ 1891 if (is_layerscape_lpuart(sport)) { 1892 sport->rxfifo_size = 16; 1893 sport->txfifo_size = 16; 1894 sport->port.fifosize = sport->txfifo_size; 1895 } 1896 1897 lpuart_request_dma(sport); 1898 lpuart32_hw_setup(sport); 1899 1900 return 0; 1901 } 1902 1903 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1904 { 1905 if (sport->lpuart_dma_rx_use) { 1906 lpuart_dma_rx_free(&sport->port); 1907 sport->lpuart_dma_rx_use = false; 1908 } 1909 1910 if (sport->lpuart_dma_tx_use) { 1911 if (wait_event_interruptible_timeout(sport->dma_wait, 1912 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { 1913 sport->dma_tx_in_progress = false; 1914 dmaengine_terminate_sync(sport->dma_tx_chan); 1915 } 1916 sport->lpuart_dma_tx_use = false; 1917 } 1918 1919 if (sport->dma_tx_chan) 1920 dma_release_channel(sport->dma_tx_chan); 1921 if (sport->dma_rx_chan) 1922 dma_release_channel(sport->dma_rx_chan); 1923 } 1924 1925 static void lpuart_shutdown(struct uart_port *port) 1926 { 1927 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1928 unsigned char temp; 1929 unsigned long flags; 1930 1931 uart_port_lock_irqsave(port, &flags); 1932 1933 /* disable Rx/Tx and interrupts */ 1934 temp = readb(port->membase + UARTCR2); 1935 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1936 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1937 writeb(temp, port->membase + UARTCR2); 1938 1939 uart_port_unlock_irqrestore(port, flags); 1940 1941 lpuart_dma_shutdown(sport); 1942 } 1943 1944 static void lpuart32_shutdown(struct uart_port *port) 1945 { 1946 struct lpuart_port *sport = 1947 container_of(port, struct lpuart_port, port); 1948 unsigned long temp; 1949 unsigned long flags; 1950 1951 uart_port_lock_irqsave(port, &flags); 1952 1953 /* clear status */ 1954 temp = lpuart32_read(&sport->port, UARTSTAT); 1955 lpuart32_write(&sport->port, temp, UARTSTAT); 1956 1957 /* disable Rx/Tx DMA */ 1958 temp = lpuart32_read(port, UARTBAUD); 1959 temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); 1960 lpuart32_write(port, temp, UARTBAUD); 1961 1962 /* disable Rx/Tx and interrupts and break condition */ 1963 temp = lpuart32_read(port, UARTCTRL); 1964 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE | 1965 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK); 1966 lpuart32_write(port, temp, UARTCTRL); 1967 1968 uart_port_unlock_irqrestore(port, flags); 1969 1970 lpuart_dma_shutdown(sport); 1971 } 1972 1973 static void 1974 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1975 const struct ktermios *old) 1976 { 1977 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1978 unsigned long flags; 1979 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1980 unsigned int baud; 1981 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1982 unsigned int sbr, brfa; 1983 1984 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1985 old_cr2 = readb(sport->port.membase + UARTCR2); 1986 cr3 = readb(sport->port.membase + UARTCR3); 1987 cr4 = readb(sport->port.membase + UARTCR4); 1988 bdh = readb(sport->port.membase + UARTBDH); 1989 modem = readb(sport->port.membase + UARTMODEM); 1990 /* 1991 * only support CS8 and CS7, and for CS7 must enable PE. 1992 * supported mode: 1993 * - (7,e/o,1) 1994 * - (8,n,1) 1995 * - (8,m/s,1) 1996 * - (8,e/o,1) 1997 */ 1998 while ((termios->c_cflag & CSIZE) != CS8 && 1999 (termios->c_cflag & CSIZE) != CS7) { 2000 termios->c_cflag &= ~CSIZE; 2001 termios->c_cflag |= old_csize; 2002 old_csize = CS8; 2003 } 2004 2005 if ((termios->c_cflag & CSIZE) == CS8 || 2006 (termios->c_cflag & CSIZE) == CS7) 2007 cr1 = old_cr1 & ~UARTCR1_M; 2008 2009 if (termios->c_cflag & CMSPAR) { 2010 if ((termios->c_cflag & CSIZE) != CS8) { 2011 termios->c_cflag &= ~CSIZE; 2012 termios->c_cflag |= CS8; 2013 } 2014 cr1 |= UARTCR1_M; 2015 } 2016 2017 /* 2018 * When auto RS-485 RTS mode is enabled, 2019 * hardware flow control need to be disabled. 2020 */ 2021 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2022 termios->c_cflag &= ~CRTSCTS; 2023 2024 if (termios->c_cflag & CRTSCTS) 2025 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 2026 else 2027 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 2028 2029 termios->c_cflag &= ~CSTOPB; 2030 2031 /* parity must be enabled when CS7 to match 8-bits format */ 2032 if ((termios->c_cflag & CSIZE) == CS7) 2033 termios->c_cflag |= PARENB; 2034 2035 if (termios->c_cflag & PARENB) { 2036 if (termios->c_cflag & CMSPAR) { 2037 cr1 &= ~UARTCR1_PE; 2038 if (termios->c_cflag & PARODD) 2039 cr3 |= UARTCR3_T8; 2040 else 2041 cr3 &= ~UARTCR3_T8; 2042 } else { 2043 cr1 |= UARTCR1_PE; 2044 if ((termios->c_cflag & CSIZE) == CS8) 2045 cr1 |= UARTCR1_M; 2046 if (termios->c_cflag & PARODD) 2047 cr1 |= UARTCR1_PT; 2048 else 2049 cr1 &= ~UARTCR1_PT; 2050 } 2051 } else { 2052 cr1 &= ~UARTCR1_PE; 2053 } 2054 2055 /* ask the core to calculate the divisor */ 2056 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 2057 2058 /* 2059 * Need to update the Ring buffer length according to the selected 2060 * baud rate and restart Rx DMA path. 2061 * 2062 * Since timer function acqures sport->port.lock, need to stop before 2063 * acquring same lock because otherwise del_timer_sync() can deadlock. 2064 */ 2065 if (old && sport->lpuart_dma_rx_use) 2066 lpuart_dma_rx_free(&sport->port); 2067 2068 uart_port_lock_irqsave(&sport->port, &flags); 2069 2070 sport->port.read_status_mask = 0; 2071 if (termios->c_iflag & INPCK) 2072 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 2073 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2074 sport->port.read_status_mask |= UARTSR1_FE; 2075 2076 /* characters to ignore */ 2077 sport->port.ignore_status_mask = 0; 2078 if (termios->c_iflag & IGNPAR) 2079 sport->port.ignore_status_mask |= UARTSR1_PE; 2080 if (termios->c_iflag & IGNBRK) { 2081 sport->port.ignore_status_mask |= UARTSR1_FE; 2082 /* 2083 * if we're ignoring parity and break indicators, 2084 * ignore overruns too (for real raw support). 2085 */ 2086 if (termios->c_iflag & IGNPAR) 2087 sport->port.ignore_status_mask |= UARTSR1_OR; 2088 } 2089 2090 /* update the per-port timeout */ 2091 uart_update_timeout(port, termios->c_cflag, baud); 2092 2093 /* wait transmit engin complete */ 2094 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2095 2096 /* disable transmit and receive */ 2097 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 2098 sport->port.membase + UARTCR2); 2099 2100 sbr = sport->port.uartclk / (16 * baud); 2101 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 2102 bdh &= ~UARTBDH_SBR_MASK; 2103 bdh |= (sbr >> 8) & 0x1F; 2104 cr4 &= ~UARTCR4_BRFA_MASK; 2105 brfa &= UARTCR4_BRFA_MASK; 2106 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 2107 writeb(bdh, sport->port.membase + UARTBDH); 2108 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 2109 writeb(cr3, sport->port.membase + UARTCR3); 2110 writeb(cr1, sport->port.membase + UARTCR1); 2111 writeb(modem, sport->port.membase + UARTMODEM); 2112 2113 /* restore control register */ 2114 writeb(old_cr2, sport->port.membase + UARTCR2); 2115 2116 if (old && sport->lpuart_dma_rx_use) { 2117 if (!lpuart_start_rx_dma(sport)) 2118 rx_dma_timer_init(sport); 2119 else 2120 sport->lpuart_dma_rx_use = false; 2121 } 2122 2123 uart_port_unlock_irqrestore(&sport->port, flags); 2124 } 2125 2126 static void __lpuart32_serial_setbrg(struct uart_port *port, 2127 unsigned int baudrate, bool use_rx_dma, 2128 bool use_tx_dma) 2129 { 2130 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 2131 u32 clk = port->uartclk; 2132 2133 /* 2134 * The idea is to use the best OSR (over-sampling rate) possible. 2135 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 2136 * Loop to find the best OSR value possible, one that generates minimum 2137 * baud_diff iterate through the rest of the supported values of OSR. 2138 * 2139 * Calculation Formula: 2140 * Baud Rate = baud clock / ((OSR+1) × SBR) 2141 */ 2142 baud_diff = baudrate; 2143 osr = 0; 2144 sbr = 0; 2145 2146 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 2147 /* calculate the temporary sbr value */ 2148 tmp_sbr = (clk / (baudrate * tmp_osr)); 2149 if (tmp_sbr == 0) 2150 tmp_sbr = 1; 2151 2152 /* 2153 * calculate the baud rate difference based on the temporary 2154 * osr and sbr values 2155 */ 2156 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 2157 2158 /* select best values between sbr and sbr+1 */ 2159 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 2160 if (tmp_diff > (baudrate - tmp)) { 2161 tmp_diff = baudrate - tmp; 2162 tmp_sbr++; 2163 } 2164 2165 if (tmp_sbr > UARTBAUD_SBR_MASK) 2166 continue; 2167 2168 if (tmp_diff <= baud_diff) { 2169 baud_diff = tmp_diff; 2170 osr = tmp_osr; 2171 sbr = tmp_sbr; 2172 2173 if (!baud_diff) 2174 break; 2175 } 2176 } 2177 2178 /* handle buadrate outside acceptable rate */ 2179 if (baud_diff > ((baudrate / 100) * 3)) 2180 dev_warn(port->dev, 2181 "unacceptable baud rate difference of more than 3%%\n"); 2182 2183 tmp = lpuart32_read(port, UARTBAUD); 2184 2185 if ((osr > 3) && (osr < 8)) 2186 tmp |= UARTBAUD_BOTHEDGE; 2187 2188 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 2189 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 2190 2191 tmp &= ~UARTBAUD_SBR_MASK; 2192 tmp |= sbr & UARTBAUD_SBR_MASK; 2193 2194 if (!use_rx_dma) 2195 tmp &= ~UARTBAUD_RDMAE; 2196 if (!use_tx_dma) 2197 tmp &= ~UARTBAUD_TDMAE; 2198 2199 lpuart32_write(port, tmp, UARTBAUD); 2200 } 2201 2202 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 2203 unsigned int baudrate) 2204 { 2205 __lpuart32_serial_setbrg(&sport->port, baudrate, 2206 sport->lpuart_dma_rx_use, 2207 sport->lpuart_dma_tx_use); 2208 } 2209 2210 2211 static void 2212 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 2213 const struct ktermios *old) 2214 { 2215 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 2216 unsigned long flags; 2217 unsigned long ctrl, old_ctrl, bd, modem; 2218 unsigned int baud; 2219 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 2220 2221 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 2222 bd = lpuart32_read(&sport->port, UARTBAUD); 2223 modem = lpuart32_read(&sport->port, UARTMODIR); 2224 sport->is_cs7 = false; 2225 /* 2226 * only support CS8 and CS7 2227 * supported mode: 2228 * - (7,n,1) (imx only) 2229 * - (7,e/o,1) 2230 * - (8,n,1) 2231 * - (8,m/s,1) 2232 * - (8,e/o,1) 2233 */ 2234 while ((termios->c_cflag & CSIZE) != CS8 && 2235 (termios->c_cflag & CSIZE) != CS7) { 2236 termios->c_cflag &= ~CSIZE; 2237 termios->c_cflag |= old_csize; 2238 old_csize = CS8; 2239 } 2240 2241 if ((termios->c_cflag & CSIZE) == CS8 || 2242 (termios->c_cflag & CSIZE) == CS7) 2243 ctrl = old_ctrl & ~(UARTCTRL_M | UARTCTRL_M7); 2244 2245 if (termios->c_cflag & CMSPAR) { 2246 if ((termios->c_cflag & CSIZE) != CS8) { 2247 termios->c_cflag &= ~CSIZE; 2248 termios->c_cflag |= CS8; 2249 } 2250 ctrl |= UARTCTRL_M; 2251 } 2252 2253 /* 2254 * When auto RS-485 RTS mode is enabled, 2255 * hardware flow control need to be disabled. 2256 */ 2257 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2258 termios->c_cflag &= ~CRTSCTS; 2259 2260 if (termios->c_cflag & CRTSCTS) 2261 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE; 2262 else 2263 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2264 2265 if (termios->c_cflag & CSTOPB) 2266 bd |= UARTBAUD_SBNS; 2267 else 2268 bd &= ~UARTBAUD_SBNS; 2269 2270 /* 2271 * imx support 7-bits format, no limitation on parity when CS7 2272 * for layerscape, parity must be enabled when CS7 to match 8-bits format 2273 */ 2274 if ((termios->c_cflag & CSIZE) == CS7 && !(termios->c_cflag & PARENB)) { 2275 if (is_imx7ulp_lpuart(sport) || 2276 is_imx8ulp_lpuart(sport) || 2277 is_imx8qxp_lpuart(sport)) 2278 ctrl |= UARTCTRL_M7; 2279 else 2280 termios->c_cflag |= PARENB; 2281 } 2282 2283 if ((termios->c_cflag & PARENB)) { 2284 if (termios->c_cflag & CMSPAR) { 2285 ctrl &= ~UARTCTRL_PE; 2286 ctrl |= UARTCTRL_M; 2287 } else { 2288 ctrl |= UARTCTRL_PE; 2289 if ((termios->c_cflag & CSIZE) == CS8) 2290 ctrl |= UARTCTRL_M; 2291 if (termios->c_cflag & PARODD) 2292 ctrl |= UARTCTRL_PT; 2293 else 2294 ctrl &= ~UARTCTRL_PT; 2295 } 2296 } else { 2297 ctrl &= ~UARTCTRL_PE; 2298 } 2299 2300 /* ask the core to calculate the divisor */ 2301 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2302 2303 /* 2304 * Need to update the Ring buffer length according to the selected 2305 * baud rate and restart Rx DMA path. 2306 * 2307 * Since timer function acqures sport->port.lock, need to stop before 2308 * acquring same lock because otherwise del_timer_sync() can deadlock. 2309 */ 2310 if (old && sport->lpuart_dma_rx_use) 2311 lpuart_dma_rx_free(&sport->port); 2312 2313 uart_port_lock_irqsave(&sport->port, &flags); 2314 2315 sport->port.read_status_mask = 0; 2316 if (termios->c_iflag & INPCK) 2317 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2318 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2319 sport->port.read_status_mask |= UARTSTAT_FE; 2320 2321 /* characters to ignore */ 2322 sport->port.ignore_status_mask = 0; 2323 if (termios->c_iflag & IGNPAR) 2324 sport->port.ignore_status_mask |= UARTSTAT_PE; 2325 if (termios->c_iflag & IGNBRK) { 2326 sport->port.ignore_status_mask |= UARTSTAT_FE; 2327 /* 2328 * if we're ignoring parity and break indicators, 2329 * ignore overruns too (for real raw support). 2330 */ 2331 if (termios->c_iflag & IGNPAR) 2332 sport->port.ignore_status_mask |= UARTSTAT_OR; 2333 } 2334 2335 /* update the per-port timeout */ 2336 uart_update_timeout(port, termios->c_cflag, baud); 2337 2338 /* 2339 * LPUART Transmission Complete Flag may never be set while queuing a break 2340 * character, so skip waiting for transmission complete when UARTCTRL_SBK is 2341 * asserted. 2342 */ 2343 if (!(old_ctrl & UARTCTRL_SBK)) { 2344 lpuart32_write(&sport->port, 0, UARTMODIR); 2345 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2346 } 2347 2348 /* disable transmit and receive */ 2349 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2350 UARTCTRL); 2351 2352 lpuart32_write(&sport->port, bd, UARTBAUD); 2353 lpuart32_serial_setbrg(sport, baud); 2354 /* disable CTS before enabling UARTCTRL_TE to avoid pending idle preamble */ 2355 lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); 2356 /* restore control register */ 2357 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2358 /* re-enable the CTS if needed */ 2359 lpuart32_write(&sport->port, modem, UARTMODIR); 2360 2361 if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE) 2362 sport->is_cs7 = true; 2363 2364 if (old && sport->lpuart_dma_rx_use) { 2365 if (!lpuart_start_rx_dma(sport)) 2366 rx_dma_timer_init(sport); 2367 else 2368 sport->lpuart_dma_rx_use = false; 2369 } 2370 2371 uart_port_unlock_irqrestore(&sport->port, flags); 2372 } 2373 2374 static const char *lpuart_type(struct uart_port *port) 2375 { 2376 return "FSL_LPUART"; 2377 } 2378 2379 static void lpuart_release_port(struct uart_port *port) 2380 { 2381 /* nothing to do */ 2382 } 2383 2384 static int lpuart_request_port(struct uart_port *port) 2385 { 2386 return 0; 2387 } 2388 2389 /* configure/autoconfigure the port */ 2390 static void lpuart_config_port(struct uart_port *port, int flags) 2391 { 2392 if (flags & UART_CONFIG_TYPE) 2393 port->type = PORT_LPUART; 2394 } 2395 2396 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2397 { 2398 int ret = 0; 2399 2400 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2401 ret = -EINVAL; 2402 if (port->irq != ser->irq) 2403 ret = -EINVAL; 2404 if (ser->io_type != UPIO_MEM) 2405 ret = -EINVAL; 2406 if (port->uartclk / 16 != ser->baud_base) 2407 ret = -EINVAL; 2408 if (port->iobase != ser->port) 2409 ret = -EINVAL; 2410 if (ser->hub6 != 0) 2411 ret = -EINVAL; 2412 return ret; 2413 } 2414 2415 static const struct uart_ops lpuart_pops = { 2416 .tx_empty = lpuart_tx_empty, 2417 .set_mctrl = lpuart_set_mctrl, 2418 .get_mctrl = lpuart_get_mctrl, 2419 .stop_tx = lpuart_stop_tx, 2420 .start_tx = lpuart_start_tx, 2421 .stop_rx = lpuart_stop_rx, 2422 .break_ctl = lpuart_break_ctl, 2423 .startup = lpuart_startup, 2424 .shutdown = lpuart_shutdown, 2425 .set_termios = lpuart_set_termios, 2426 .pm = lpuart_uart_pm, 2427 .type = lpuart_type, 2428 .request_port = lpuart_request_port, 2429 .release_port = lpuart_release_port, 2430 .config_port = lpuart_config_port, 2431 .verify_port = lpuart_verify_port, 2432 .flush_buffer = lpuart_flush_buffer, 2433 #if defined(CONFIG_CONSOLE_POLL) 2434 .poll_init = lpuart_poll_init, 2435 .poll_get_char = lpuart_poll_get_char, 2436 .poll_put_char = lpuart_poll_put_char, 2437 #endif 2438 }; 2439 2440 static const struct uart_ops lpuart32_pops = { 2441 .tx_empty = lpuart32_tx_empty, 2442 .set_mctrl = lpuart32_set_mctrl, 2443 .get_mctrl = lpuart32_get_mctrl, 2444 .stop_tx = lpuart32_stop_tx, 2445 .start_tx = lpuart32_start_tx, 2446 .stop_rx = lpuart32_stop_rx, 2447 .break_ctl = lpuart32_break_ctl, 2448 .startup = lpuart32_startup, 2449 .shutdown = lpuart32_shutdown, 2450 .set_termios = lpuart32_set_termios, 2451 .pm = lpuart_uart_pm, 2452 .type = lpuart_type, 2453 .request_port = lpuart_request_port, 2454 .release_port = lpuart_release_port, 2455 .config_port = lpuart_config_port, 2456 .verify_port = lpuart_verify_port, 2457 .flush_buffer = lpuart_flush_buffer, 2458 #if defined(CONFIG_CONSOLE_POLL) 2459 .poll_init = lpuart32_poll_init, 2460 .poll_get_char = lpuart32_poll_get_char, 2461 .poll_put_char = lpuart32_poll_put_char, 2462 #endif 2463 }; 2464 2465 static struct lpuart_port *lpuart_ports[UART_NR]; 2466 2467 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2468 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch) 2469 { 2470 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2471 writeb(ch, port->membase + UARTDR); 2472 } 2473 2474 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch) 2475 { 2476 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2477 lpuart32_write(port, ch, UARTDATA); 2478 } 2479 2480 static void 2481 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2482 { 2483 struct lpuart_port *sport = lpuart_ports[co->index]; 2484 unsigned char old_cr2, cr2; 2485 unsigned long flags; 2486 int locked = 1; 2487 2488 if (oops_in_progress) 2489 locked = uart_port_trylock_irqsave(&sport->port, &flags); 2490 else 2491 uart_port_lock_irqsave(&sport->port, &flags); 2492 2493 /* first save CR2 and then disable interrupts */ 2494 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2495 cr2 |= UARTCR2_TE | UARTCR2_RE; 2496 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2497 writeb(cr2, sport->port.membase + UARTCR2); 2498 2499 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2500 2501 /* wait for transmitter finish complete and restore CR2 */ 2502 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2503 2504 writeb(old_cr2, sport->port.membase + UARTCR2); 2505 2506 if (locked) 2507 uart_port_unlock_irqrestore(&sport->port, flags); 2508 } 2509 2510 static void 2511 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2512 { 2513 struct lpuart_port *sport = lpuart_ports[co->index]; 2514 unsigned long old_cr, cr; 2515 unsigned long flags; 2516 int locked = 1; 2517 2518 if (oops_in_progress) 2519 locked = uart_port_trylock_irqsave(&sport->port, &flags); 2520 else 2521 uart_port_lock_irqsave(&sport->port, &flags); 2522 2523 /* first save CR2 and then disable interrupts */ 2524 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2525 cr |= UARTCTRL_TE | UARTCTRL_RE; 2526 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2527 lpuart32_write(&sport->port, cr, UARTCTRL); 2528 2529 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2530 2531 /* wait for transmitter finish complete and restore CR2 */ 2532 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2533 2534 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2535 2536 if (locked) 2537 uart_port_unlock_irqrestore(&sport->port, flags); 2538 } 2539 2540 /* 2541 * if the port was already initialised (eg, by a boot loader), 2542 * try to determine the current setup. 2543 */ 2544 static void __init 2545 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2546 int *parity, int *bits) 2547 { 2548 unsigned char cr, bdh, bdl, brfa; 2549 unsigned int sbr, uartclk, baud_raw; 2550 2551 cr = readb(sport->port.membase + UARTCR2); 2552 cr &= UARTCR2_TE | UARTCR2_RE; 2553 if (!cr) 2554 return; 2555 2556 /* ok, the port was enabled */ 2557 2558 cr = readb(sport->port.membase + UARTCR1); 2559 2560 *parity = 'n'; 2561 if (cr & UARTCR1_PE) { 2562 if (cr & UARTCR1_PT) 2563 *parity = 'o'; 2564 else 2565 *parity = 'e'; 2566 } 2567 2568 if (cr & UARTCR1_M) 2569 *bits = 9; 2570 else 2571 *bits = 8; 2572 2573 bdh = readb(sport->port.membase + UARTBDH); 2574 bdh &= UARTBDH_SBR_MASK; 2575 bdl = readb(sport->port.membase + UARTBDL); 2576 sbr = bdh; 2577 sbr <<= 8; 2578 sbr |= bdl; 2579 brfa = readb(sport->port.membase + UARTCR4); 2580 brfa &= UARTCR4_BRFA_MASK; 2581 2582 uartclk = lpuart_get_baud_clk_rate(sport); 2583 /* 2584 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2585 */ 2586 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2587 2588 if (*baud != baud_raw) 2589 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2590 "from %d to %d\n", baud_raw, *baud); 2591 } 2592 2593 static void __init 2594 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2595 int *parity, int *bits) 2596 { 2597 unsigned long cr, bd; 2598 unsigned int sbr, uartclk, baud_raw; 2599 2600 cr = lpuart32_read(&sport->port, UARTCTRL); 2601 cr &= UARTCTRL_TE | UARTCTRL_RE; 2602 if (!cr) 2603 return; 2604 2605 /* ok, the port was enabled */ 2606 2607 cr = lpuart32_read(&sport->port, UARTCTRL); 2608 2609 *parity = 'n'; 2610 if (cr & UARTCTRL_PE) { 2611 if (cr & UARTCTRL_PT) 2612 *parity = 'o'; 2613 else 2614 *parity = 'e'; 2615 } 2616 2617 if (cr & UARTCTRL_M) 2618 *bits = 9; 2619 else 2620 *bits = 8; 2621 2622 bd = lpuart32_read(&sport->port, UARTBAUD); 2623 bd &= UARTBAUD_SBR_MASK; 2624 if (!bd) 2625 return; 2626 2627 sbr = bd; 2628 uartclk = lpuart_get_baud_clk_rate(sport); 2629 /* 2630 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2631 */ 2632 baud_raw = uartclk / (16 * sbr); 2633 2634 if (*baud != baud_raw) 2635 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2636 "from %d to %d\n", baud_raw, *baud); 2637 } 2638 2639 static int __init lpuart_console_setup(struct console *co, char *options) 2640 { 2641 struct lpuart_port *sport; 2642 int baud = 115200; 2643 int bits = 8; 2644 int parity = 'n'; 2645 int flow = 'n'; 2646 2647 /* 2648 * check whether an invalid uart number has been specified, and 2649 * if so, search for the first available port that does have 2650 * console support. 2651 */ 2652 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2653 co->index = 0; 2654 2655 sport = lpuart_ports[co->index]; 2656 if (sport == NULL) 2657 return -ENODEV; 2658 2659 if (options) 2660 uart_parse_options(options, &baud, &parity, &bits, &flow); 2661 else 2662 if (lpuart_is_32(sport)) 2663 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2664 else 2665 lpuart_console_get_options(sport, &baud, &parity, &bits); 2666 2667 if (lpuart_is_32(sport)) 2668 lpuart32_setup_watermark(sport); 2669 else 2670 lpuart_setup_watermark(sport); 2671 2672 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2673 } 2674 2675 static struct uart_driver lpuart_reg; 2676 static struct console lpuart_console = { 2677 .name = DEV_NAME, 2678 .write = lpuart_console_write, 2679 .device = uart_console_device, 2680 .setup = lpuart_console_setup, 2681 .flags = CON_PRINTBUFFER, 2682 .index = -1, 2683 .data = &lpuart_reg, 2684 }; 2685 2686 static struct console lpuart32_console = { 2687 .name = DEV_NAME, 2688 .write = lpuart32_console_write, 2689 .device = uart_console_device, 2690 .setup = lpuart_console_setup, 2691 .flags = CON_PRINTBUFFER, 2692 .index = -1, 2693 .data = &lpuart_reg, 2694 }; 2695 2696 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2697 { 2698 struct earlycon_device *dev = con->data; 2699 2700 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2701 } 2702 2703 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2704 { 2705 struct earlycon_device *dev = con->data; 2706 2707 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2708 } 2709 2710 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2711 const char *opt) 2712 { 2713 if (!device->port.membase) 2714 return -ENODEV; 2715 2716 device->con->write = lpuart_early_write; 2717 return 0; 2718 } 2719 2720 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2721 const char *opt) 2722 { 2723 if (!device->port.membase) 2724 return -ENODEV; 2725 2726 if (device->port.iotype != UPIO_MEM32) 2727 device->port.iotype = UPIO_MEM32BE; 2728 2729 device->con->write = lpuart32_early_write; 2730 return 0; 2731 } 2732 2733 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2734 const char *opt) 2735 { 2736 u32 cr; 2737 2738 if (!device->port.membase) 2739 return -ENODEV; 2740 2741 device->port.iotype = UPIO_MEM32; 2742 device->con->write = lpuart32_early_write; 2743 2744 /* set the baudrate */ 2745 if (device->port.uartclk && device->baud) 2746 __lpuart32_serial_setbrg(&device->port, device->baud, 2747 false, false); 2748 2749 /* enable transmitter */ 2750 cr = lpuart32_read(&device->port, UARTCTRL); 2751 cr |= UARTCTRL_TE; 2752 lpuart32_write(&device->port, cr, UARTCTRL); 2753 2754 return 0; 2755 } 2756 2757 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2758 const char *opt) 2759 { 2760 if (!device->port.membase) 2761 return -ENODEV; 2762 2763 device->port.iotype = UPIO_MEM32; 2764 device->port.membase += IMX_REG_OFF; 2765 device->con->write = lpuart32_early_write; 2766 2767 return 0; 2768 } 2769 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2770 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2771 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2772 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2773 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup); 2774 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); 2775 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup); 2776 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2777 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2778 2779 #define LPUART_CONSOLE (&lpuart_console) 2780 #define LPUART32_CONSOLE (&lpuart32_console) 2781 #else 2782 #define LPUART_CONSOLE NULL 2783 #define LPUART32_CONSOLE NULL 2784 #endif 2785 2786 static struct uart_driver lpuart_reg = { 2787 .owner = THIS_MODULE, 2788 .driver_name = DRIVER_NAME, 2789 .dev_name = DEV_NAME, 2790 .nr = ARRAY_SIZE(lpuart_ports), 2791 .cons = LPUART_CONSOLE, 2792 }; 2793 2794 static const struct serial_rs485 lpuart_rs485_supported = { 2795 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 2796 /* delay_rts_* and RX_DURING_TX are not supported */ 2797 }; 2798 2799 static int lpuart_global_reset(struct lpuart_port *sport) 2800 { 2801 struct uart_port *port = &sport->port; 2802 void __iomem *global_addr; 2803 unsigned long ctrl, bd; 2804 unsigned int val = 0; 2805 int ret; 2806 2807 ret = clk_prepare_enable(sport->ipg_clk); 2808 if (ret) { 2809 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); 2810 return ret; 2811 } 2812 2813 if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { 2814 /* 2815 * If the transmitter is used by earlycon, wait for transmit engine to 2816 * complete and then reset. 2817 */ 2818 ctrl = lpuart32_read(port, UARTCTRL); 2819 if (ctrl & UARTCTRL_TE) { 2820 bd = lpuart32_read(&sport->port, UARTBAUD); 2821 if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false, 2822 port)) { 2823 dev_warn(sport->port.dev, 2824 "timeout waiting for transmit engine to complete\n"); 2825 clk_disable_unprepare(sport->ipg_clk); 2826 return 0; 2827 } 2828 } 2829 2830 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; 2831 writel(UART_GLOBAL_RST, global_addr); 2832 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2833 writel(0, global_addr); 2834 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US); 2835 2836 /* Recover the transmitter for earlycon. */ 2837 if (ctrl & UARTCTRL_TE) { 2838 lpuart32_write(port, bd, UARTBAUD); 2839 lpuart32_write(port, ctrl, UARTCTRL); 2840 } 2841 } 2842 2843 clk_disable_unprepare(sport->ipg_clk); 2844 return 0; 2845 } 2846 2847 static int lpuart_probe(struct platform_device *pdev) 2848 { 2849 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); 2850 struct device_node *np = pdev->dev.of_node; 2851 struct lpuart_port *sport; 2852 struct resource *res; 2853 irq_handler_t handler; 2854 int ret; 2855 2856 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2857 if (!sport) 2858 return -ENOMEM; 2859 2860 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2861 if (IS_ERR(sport->port.membase)) 2862 return PTR_ERR(sport->port.membase); 2863 2864 sport->port.membase += sdata->reg_off; 2865 sport->port.mapbase = res->start + sdata->reg_off; 2866 sport->port.dev = &pdev->dev; 2867 sport->port.type = PORT_LPUART; 2868 sport->devtype = sdata->devtype; 2869 sport->rx_watermark = sdata->rx_watermark; 2870 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || 2871 is_imx8qxp_lpuart(sport); 2872 ret = platform_get_irq(pdev, 0); 2873 if (ret < 0) 2874 return ret; 2875 sport->port.irq = ret; 2876 sport->port.iotype = sdata->iotype; 2877 if (lpuart_is_32(sport)) 2878 sport->port.ops = &lpuart32_pops; 2879 else 2880 sport->port.ops = &lpuart_pops; 2881 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2882 sport->port.flags = UPF_BOOT_AUTOCONF; 2883 2884 if (lpuart_is_32(sport)) 2885 sport->port.rs485_config = lpuart32_config_rs485; 2886 else 2887 sport->port.rs485_config = lpuart_config_rs485; 2888 sport->port.rs485_supported = lpuart_rs485_supported; 2889 2890 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2891 if (IS_ERR(sport->ipg_clk)) { 2892 ret = PTR_ERR(sport->ipg_clk); 2893 return dev_err_probe(&pdev->dev, ret, "failed to get uart ipg clk\n"); 2894 } 2895 2896 sport->baud_clk = NULL; 2897 if (is_imx8qxp_lpuart(sport)) { 2898 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2899 if (IS_ERR(sport->baud_clk)) { 2900 ret = PTR_ERR(sport->baud_clk); 2901 return dev_err_probe(&pdev->dev, ret, "failed to get uart baud clk\n"); 2902 } 2903 } 2904 2905 ret = of_alias_get_id(np, "serial"); 2906 if (ret < 0) { 2907 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 2908 return ret; 2909 } 2910 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2911 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2912 return -EINVAL; 2913 } 2914 sport->port.line = ret; 2915 2916 ret = lpuart_enable_clks(sport); 2917 if (ret) 2918 return ret; 2919 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2920 2921 lpuart_ports[sport->port.line] = sport; 2922 2923 platform_set_drvdata(pdev, &sport->port); 2924 2925 if (lpuart_is_32(sport)) { 2926 lpuart_reg.cons = LPUART32_CONSOLE; 2927 handler = lpuart32_int; 2928 } else { 2929 lpuart_reg.cons = LPUART_CONSOLE; 2930 handler = lpuart_int; 2931 } 2932 2933 pm_runtime_use_autosuspend(&pdev->dev); 2934 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); 2935 pm_runtime_set_active(&pdev->dev); 2936 pm_runtime_enable(&pdev->dev); 2937 pm_runtime_mark_last_busy(&pdev->dev); 2938 2939 ret = lpuart_global_reset(sport); 2940 if (ret) 2941 goto failed_reset; 2942 2943 ret = uart_get_rs485_mode(&sport->port); 2944 if (ret) 2945 goto failed_get_rs485; 2946 2947 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2948 if (ret) 2949 goto failed_attach_port; 2950 2951 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, 2952 DRIVER_NAME, sport); 2953 if (ret) 2954 goto failed_irq_request; 2955 2956 return 0; 2957 2958 failed_irq_request: 2959 uart_remove_one_port(&lpuart_reg, &sport->port); 2960 failed_attach_port: 2961 failed_get_rs485: 2962 failed_reset: 2963 pm_runtime_disable(&pdev->dev); 2964 pm_runtime_set_suspended(&pdev->dev); 2965 pm_runtime_dont_use_autosuspend(&pdev->dev); 2966 lpuart_disable_clks(sport); 2967 return ret; 2968 } 2969 2970 static void lpuart_remove(struct platform_device *pdev) 2971 { 2972 struct lpuart_port *sport = platform_get_drvdata(pdev); 2973 2974 uart_remove_one_port(&lpuart_reg, &sport->port); 2975 2976 lpuart_disable_clks(sport); 2977 2978 if (sport->dma_tx_chan) 2979 dma_release_channel(sport->dma_tx_chan); 2980 2981 if (sport->dma_rx_chan) 2982 dma_release_channel(sport->dma_rx_chan); 2983 2984 pm_runtime_disable(&pdev->dev); 2985 pm_runtime_set_suspended(&pdev->dev); 2986 pm_runtime_dont_use_autosuspend(&pdev->dev); 2987 } 2988 2989 static int lpuart_runtime_suspend(struct device *dev) 2990 { 2991 struct platform_device *pdev = to_platform_device(dev); 2992 struct lpuart_port *sport = platform_get_drvdata(pdev); 2993 2994 lpuart_disable_clks(sport); 2995 2996 return 0; 2997 }; 2998 2999 static int lpuart_runtime_resume(struct device *dev) 3000 { 3001 struct platform_device *pdev = to_platform_device(dev); 3002 struct lpuart_port *sport = platform_get_drvdata(pdev); 3003 3004 return lpuart_enable_clks(sport); 3005 }; 3006 3007 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on) 3008 { 3009 unsigned int val, baud; 3010 3011 if (lpuart_is_32(sport)) { 3012 val = lpuart32_read(&sport->port, UARTCTRL); 3013 baud = lpuart32_read(&sport->port, UARTBAUD); 3014 if (on) { 3015 /* set rx_watermark to 0 in wakeup source mode */ 3016 lpuart32_write(&sport->port, 0, UARTWATER); 3017 val |= UARTCTRL_RIE; 3018 /* clear RXEDGIF flag before enable RXEDGIE interrupt */ 3019 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); 3020 baud |= UARTBAUD_RXEDGIE; 3021 } else { 3022 val &= ~UARTCTRL_RIE; 3023 baud &= ~UARTBAUD_RXEDGIE; 3024 } 3025 lpuart32_write(&sport->port, val, UARTCTRL); 3026 lpuart32_write(&sport->port, baud, UARTBAUD); 3027 } else { 3028 val = readb(sport->port.membase + UARTCR2); 3029 if (on) 3030 val |= UARTCR2_RIE; 3031 else 3032 val &= ~UARTCR2_RIE; 3033 writeb(val, sport->port.membase + UARTCR2); 3034 } 3035 } 3036 3037 static bool lpuart_uport_is_active(struct lpuart_port *sport) 3038 { 3039 struct tty_port *port = &sport->port.state->port; 3040 struct tty_struct *tty; 3041 struct device *tty_dev; 3042 int may_wake = 0; 3043 3044 tty = tty_port_tty_get(port); 3045 if (tty) { 3046 tty_dev = tty->dev; 3047 may_wake = tty_dev && device_may_wakeup(tty_dev); 3048 tty_kref_put(tty); 3049 } 3050 3051 if ((tty_port_initialized(port) && may_wake) || 3052 (!console_suspend_enabled && uart_console(&sport->port))) 3053 return true; 3054 3055 return false; 3056 } 3057 3058 static int lpuart_suspend_noirq(struct device *dev) 3059 { 3060 struct lpuart_port *sport = dev_get_drvdata(dev); 3061 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 3062 3063 if (lpuart_uport_is_active(sport)) 3064 serial_lpuart_enable_wakeup(sport, !!irq_wake); 3065 3066 pinctrl_pm_select_sleep_state(dev); 3067 3068 return 0; 3069 } 3070 3071 static int lpuart_resume_noirq(struct device *dev) 3072 { 3073 struct lpuart_port *sport = dev_get_drvdata(dev); 3074 unsigned int val; 3075 3076 pinctrl_pm_select_default_state(dev); 3077 3078 if (lpuart_uport_is_active(sport)) { 3079 serial_lpuart_enable_wakeup(sport, false); 3080 3081 /* clear the wakeup flags */ 3082 if (lpuart_is_32(sport)) { 3083 val = lpuart32_read(&sport->port, UARTSTAT); 3084 lpuart32_write(&sport->port, val, UARTSTAT); 3085 } 3086 } 3087 3088 return 0; 3089 } 3090 3091 static int lpuart_suspend(struct device *dev) 3092 { 3093 struct lpuart_port *sport = dev_get_drvdata(dev); 3094 unsigned long temp, flags; 3095 3096 uart_suspend_port(&lpuart_reg, &sport->port); 3097 3098 if (lpuart_uport_is_active(sport)) { 3099 uart_port_lock_irqsave(&sport->port, &flags); 3100 if (lpuart_is_32(sport)) { 3101 /* disable Rx/Tx and interrupts */ 3102 temp = lpuart32_read(&sport->port, UARTCTRL); 3103 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 3104 lpuart32_write(&sport->port, temp, UARTCTRL); 3105 } else { 3106 /* disable Rx/Tx and interrupts */ 3107 temp = readb(sport->port.membase + UARTCR2); 3108 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 3109 writeb(temp, sport->port.membase + UARTCR2); 3110 } 3111 uart_port_unlock_irqrestore(&sport->port, flags); 3112 3113 if (sport->lpuart_dma_rx_use) { 3114 /* 3115 * EDMA driver during suspend will forcefully release any 3116 * non-idle DMA channels. If port wakeup is enabled or if port 3117 * is console port or 'no_console_suspend' is set the Rx DMA 3118 * cannot resume as expected, hence gracefully release the 3119 * Rx DMA path before suspend and start Rx DMA path on resume. 3120 */ 3121 lpuart_dma_rx_free(&sport->port); 3122 3123 /* Disable Rx DMA to use UART port as wakeup source */ 3124 uart_port_lock_irqsave(&sport->port, &flags); 3125 if (lpuart_is_32(sport)) { 3126 temp = lpuart32_read(&sport->port, UARTBAUD); 3127 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 3128 UARTBAUD); 3129 } else { 3130 writeb(readb(sport->port.membase + UARTCR5) & 3131 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 3132 } 3133 uart_port_unlock_irqrestore(&sport->port, flags); 3134 } 3135 3136 if (sport->lpuart_dma_tx_use) { 3137 uart_port_lock_irqsave(&sport->port, &flags); 3138 if (lpuart_is_32(sport)) { 3139 temp = lpuart32_read(&sport->port, UARTBAUD); 3140 temp &= ~UARTBAUD_TDMAE; 3141 lpuart32_write(&sport->port, temp, UARTBAUD); 3142 } else { 3143 temp = readb(sport->port.membase + UARTCR5); 3144 temp &= ~UARTCR5_TDMAS; 3145 writeb(temp, sport->port.membase + UARTCR5); 3146 } 3147 uart_port_unlock_irqrestore(&sport->port, flags); 3148 sport->dma_tx_in_progress = false; 3149 dmaengine_terminate_sync(sport->dma_tx_chan); 3150 } 3151 } else if (pm_runtime_active(sport->port.dev)) { 3152 lpuart_disable_clks(sport); 3153 pm_runtime_disable(sport->port.dev); 3154 pm_runtime_set_suspended(sport->port.dev); 3155 } 3156 3157 return 0; 3158 } 3159 3160 static void lpuart_console_fixup(struct lpuart_port *sport) 3161 { 3162 struct tty_port *port = &sport->port.state->port; 3163 struct uart_port *uport = &sport->port; 3164 struct ktermios termios; 3165 3166 /* i.MX7ULP enter VLLS mode that lpuart module power off and registers 3167 * all lost no matter the port is wakeup source. 3168 * For console port, console baud rate setting lost and print messy 3169 * log when enable the console port as wakeup source. To avoid the 3170 * issue happen, user should not enable uart port as wakeup source 3171 * in VLLS mode, or restore console setting here. 3172 */ 3173 if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) && 3174 console_suspend_enabled && uart_console(&sport->port)) { 3175 3176 mutex_lock(&port->mutex); 3177 memset(&termios, 0, sizeof(struct ktermios)); 3178 termios.c_cflag = uport->cons->cflag; 3179 if (port->tty && termios.c_cflag == 0) 3180 termios = port->tty->termios; 3181 uport->ops->set_termios(uport, &termios, NULL); 3182 mutex_unlock(&port->mutex); 3183 } 3184 } 3185 3186 static int lpuart_resume(struct device *dev) 3187 { 3188 struct lpuart_port *sport = dev_get_drvdata(dev); 3189 int ret; 3190 3191 if (lpuart_uport_is_active(sport)) { 3192 if (lpuart_is_32(sport)) 3193 lpuart32_hw_setup(sport); 3194 else 3195 lpuart_hw_setup(sport); 3196 } else if (pm_runtime_active(sport->port.dev)) { 3197 ret = lpuart_enable_clks(sport); 3198 if (ret) 3199 return ret; 3200 pm_runtime_set_active(sport->port.dev); 3201 pm_runtime_enable(sport->port.dev); 3202 } 3203 3204 lpuart_console_fixup(sport); 3205 uart_resume_port(&lpuart_reg, &sport->port); 3206 3207 return 0; 3208 } 3209 3210 static const struct dev_pm_ops lpuart_pm_ops = { 3211 RUNTIME_PM_OPS(lpuart_runtime_suspend, 3212 lpuart_runtime_resume, NULL) 3213 NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq, 3214 lpuart_resume_noirq) 3215 SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume) 3216 }; 3217 3218 static struct platform_driver lpuart_driver = { 3219 .probe = lpuart_probe, 3220 .remove = lpuart_remove, 3221 .driver = { 3222 .name = "fsl-lpuart", 3223 .of_match_table = lpuart_dt_ids, 3224 .pm = pm_ptr(&lpuart_pm_ops), 3225 }, 3226 }; 3227 3228 static int __init lpuart_serial_init(void) 3229 { 3230 int ret = uart_register_driver(&lpuart_reg); 3231 3232 if (ret) 3233 return ret; 3234 3235 ret = platform_driver_register(&lpuart_driver); 3236 if (ret) 3237 uart_unregister_driver(&lpuart_reg); 3238 3239 return ret; 3240 } 3241 3242 static void __exit lpuart_serial_exit(void) 3243 { 3244 platform_driver_unregister(&lpuart_driver); 3245 uart_unregister_driver(&lpuart_reg); 3246 } 3247 3248 module_init(lpuart_serial_init); 3249 module_exit(lpuart_serial_exit); 3250 3251 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 3252 MODULE_LICENSE("GPL v2"); 3253