1 // SPDX-License-Identifier: GPL-2.0-or-later 2 3 #include <linux/bitfield.h> 4 #include <linux/bits.h> 5 #include <linux/clk.h> 6 #include <linux/console.h> 7 #include <linux/delay.h> 8 #include <linux/io.h> 9 #include <linux/irq.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/serial_core.h> 14 #include <linux/slab.h> 15 #include <linux/tty_flip.h> 16 #include <asm/serial.h> 17 18 #define DRIVER_NAME "esp32-uart" 19 #define DEV_NAME "ttyS" 20 #define UART_NR 3 21 22 #define ESP32_UART_TX_FIFO_SIZE 127 23 #define ESP32_UART_RX_FIFO_SIZE 127 24 25 #define UART_FIFO_REG 0x00 26 #define UART_INT_RAW_REG 0x04 27 #define UART_INT_ST_REG 0x08 28 #define UART_INT_ENA_REG 0x0c 29 #define UART_INT_CLR_REG 0x10 30 #define UART_RXFIFO_FULL_INT BIT(0) 31 #define UART_TXFIFO_EMPTY_INT BIT(1) 32 #define UART_BRK_DET_INT BIT(7) 33 #define UART_CLKDIV_REG 0x14 34 #define ESP32_UART_CLKDIV GENMASK(19, 0) 35 #define ESP32S3_UART_CLKDIV GENMASK(11, 0) 36 #define UART_CLKDIV_SHIFT 0 37 #define UART_CLKDIV_FRAG GENMASK(23, 20) 38 #define UART_STATUS_REG 0x1c 39 #define ESP32_UART_RXFIFO_CNT GENMASK(7, 0) 40 #define ESP32S3_UART_RXFIFO_CNT GENMASK(9, 0) 41 #define UART_RXFIFO_CNT_SHIFT 0 42 #define UART_DSRN BIT(13) 43 #define UART_CTSN BIT(14) 44 #define ESP32_UART_TXFIFO_CNT GENMASK(23, 16) 45 #define ESP32S3_UART_TXFIFO_CNT GENMASK(25, 16) 46 #define UART_TXFIFO_CNT_SHIFT 16 47 #define UART_CONF0_REG 0x20 48 #define UART_PARITY BIT(0) 49 #define UART_PARITY_EN BIT(1) 50 #define UART_BIT_NUM GENMASK(3, 2) 51 #define UART_BIT_NUM_5 0 52 #define UART_BIT_NUM_6 1 53 #define UART_BIT_NUM_7 2 54 #define UART_BIT_NUM_8 3 55 #define UART_STOP_BIT_NUM GENMASK(5, 4) 56 #define UART_STOP_BIT_NUM_1 1 57 #define UART_STOP_BIT_NUM_2 3 58 #define UART_SW_RTS BIT(6) 59 #define UART_SW_DTR BIT(7) 60 #define UART_LOOPBACK BIT(14) 61 #define UART_TX_FLOW_EN BIT(15) 62 #define UART_RTS_INV BIT(23) 63 #define UART_DTR_INV BIT(24) 64 #define UART_CONF1_REG 0x24 65 #define UART_RXFIFO_FULL_THRHD_SHIFT 0 66 #define ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT 8 67 #define ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT 10 68 #define ESP32_UART_RX_FLOW_EN BIT(23) 69 #define ESP32S3_UART_RX_FLOW_EN BIT(22) 70 #define ESP32S3_UART_CLK_CONF_REG 0x78 71 #define ESP32S3_UART_SCLK_DIV_B GENMASK(5, 0) 72 #define ESP32S3_UART_SCLK_DIV_A GENMASK(11, 6) 73 #define ESP32S3_UART_SCLK_DIV_NUM GENMASK(19, 12) 74 #define ESP32S3_UART_SCLK_SEL GENMASK(21, 20) 75 #define APB_CLK 1 76 #define RC_FAST_CLK 2 77 #define XTAL_CLK 3 78 #define ESP32S3_UART_SCLK_EN BIT(22) 79 #define ESP32S3_UART_RST_CORE BIT(23) 80 #define ESP32S3_UART_TX_SCLK_EN BIT(24) 81 #define ESP32S3_UART_RX_SCLK_EN BIT(25) 82 #define ESP32S3_UART_TX_RST_CORE BIT(26) 83 #define ESP32S3_UART_RX_RST_CORE BIT(27) 84 85 #define ESP32S3_UART_CLK_CONF_DEFAULT \ 86 (ESP32S3_UART_RX_SCLK_EN | \ 87 ESP32S3_UART_TX_SCLK_EN | \ 88 ESP32S3_UART_SCLK_EN | \ 89 FIELD_PREP(ESP32S3_UART_SCLK_SEL, XTAL_CLK)) 90 91 struct esp32_port { 92 struct uart_port port; 93 struct clk *clk; 94 }; 95 96 struct esp32_uart_variant { 97 u32 clkdiv_mask; 98 u32 rxfifo_cnt_mask; 99 u32 txfifo_cnt_mask; 100 u32 txfifo_empty_thrhd_shift; 101 u32 rx_flow_en; 102 const char *type; 103 bool has_clkconf; 104 }; 105 106 static const struct esp32_uart_variant esp32_variant = { 107 .clkdiv_mask = ESP32_UART_CLKDIV, 108 .rxfifo_cnt_mask = ESP32_UART_RXFIFO_CNT, 109 .txfifo_cnt_mask = ESP32_UART_TXFIFO_CNT, 110 .txfifo_empty_thrhd_shift = ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT, 111 .rx_flow_en = ESP32_UART_RX_FLOW_EN, 112 .type = "ESP32 UART", 113 }; 114 115 static const struct esp32_uart_variant esp32s3_variant = { 116 .clkdiv_mask = ESP32S3_UART_CLKDIV, 117 .rxfifo_cnt_mask = ESP32S3_UART_RXFIFO_CNT, 118 .txfifo_cnt_mask = ESP32S3_UART_TXFIFO_CNT, 119 .txfifo_empty_thrhd_shift = ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT, 120 .rx_flow_en = ESP32S3_UART_RX_FLOW_EN, 121 .type = "ESP32S3 UART", 122 .has_clkconf = true, 123 }; 124 125 static const struct of_device_id esp32_uart_dt_ids[] = { 126 { 127 .compatible = "esp,esp32-uart", 128 .data = &esp32_variant, 129 }, { 130 .compatible = "esp,esp32s3-uart", 131 .data = &esp32s3_variant, 132 }, { /* sentinel */ } 133 }; 134 MODULE_DEVICE_TABLE(of, esp32_uart_dt_ids); 135 136 static struct esp32_port *esp32_uart_ports[UART_NR]; 137 138 static const struct esp32_uart_variant *port_variant(struct uart_port *port) 139 { 140 return port->private_data; 141 } 142 143 static void esp32_uart_write(struct uart_port *port, unsigned long reg, u32 v) 144 { 145 writel(v, port->membase + reg); 146 } 147 148 static u32 esp32_uart_read(struct uart_port *port, unsigned long reg) 149 { 150 return readl(port->membase + reg); 151 } 152 153 static u32 esp32_uart_tx_fifo_cnt(struct uart_port *port) 154 { 155 u32 status = esp32_uart_read(port, UART_STATUS_REG); 156 157 return (status & port_variant(port)->txfifo_cnt_mask) >> UART_TXFIFO_CNT_SHIFT; 158 } 159 160 static u32 esp32_uart_rx_fifo_cnt(struct uart_port *port) 161 { 162 u32 status = esp32_uart_read(port, UART_STATUS_REG); 163 164 return (status & port_variant(port)->rxfifo_cnt_mask) >> UART_RXFIFO_CNT_SHIFT; 165 } 166 167 /* return TIOCSER_TEMT when transmitter is not busy */ 168 static unsigned int esp32_uart_tx_empty(struct uart_port *port) 169 { 170 return esp32_uart_tx_fifo_cnt(port) ? 0 : TIOCSER_TEMT; 171 } 172 173 static void esp32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 174 { 175 u32 conf0 = esp32_uart_read(port, UART_CONF0_REG); 176 177 conf0 &= ~(UART_LOOPBACK | 178 UART_SW_RTS | UART_RTS_INV | 179 UART_SW_DTR | UART_DTR_INV); 180 181 if (mctrl & TIOCM_RTS) 182 conf0 |= UART_SW_RTS; 183 if (mctrl & TIOCM_DTR) 184 conf0 |= UART_SW_DTR; 185 if (mctrl & TIOCM_LOOP) 186 conf0 |= UART_LOOPBACK; 187 188 esp32_uart_write(port, UART_CONF0_REG, conf0); 189 } 190 191 static unsigned int esp32_uart_get_mctrl(struct uart_port *port) 192 { 193 u32 status = esp32_uart_read(port, UART_STATUS_REG); 194 unsigned int ret = TIOCM_CAR; 195 196 if (status & UART_DSRN) 197 ret |= TIOCM_DSR; 198 if (status & UART_CTSN) 199 ret |= TIOCM_CTS; 200 201 return ret; 202 } 203 204 static void esp32_uart_stop_tx(struct uart_port *port) 205 { 206 u32 int_ena; 207 208 int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 209 int_ena &= ~UART_TXFIFO_EMPTY_INT; 210 esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 211 } 212 213 static void esp32_uart_rxint(struct uart_port *port) 214 { 215 struct tty_port *tty_port = &port->state->port; 216 u32 rx_fifo_cnt = esp32_uart_rx_fifo_cnt(port); 217 unsigned long flags; 218 u32 i; 219 220 if (!rx_fifo_cnt) 221 return; 222 223 spin_lock_irqsave(&port->lock, flags); 224 225 for (i = 0; i < rx_fifo_cnt; ++i) { 226 u32 rx = esp32_uart_read(port, UART_FIFO_REG); 227 228 if (!rx && 229 (esp32_uart_read(port, UART_INT_ST_REG) & UART_BRK_DET_INT)) { 230 esp32_uart_write(port, UART_INT_CLR_REG, UART_BRK_DET_INT); 231 ++port->icount.brk; 232 uart_handle_break(port); 233 } else { 234 if (uart_handle_sysrq_char(port, (unsigned char)rx)) 235 continue; 236 tty_insert_flip_char(tty_port, rx, TTY_NORMAL); 237 ++port->icount.rx; 238 } 239 } 240 spin_unlock_irqrestore(&port->lock, flags); 241 242 tty_flip_buffer_push(tty_port); 243 } 244 245 static void esp32_uart_put_char(struct uart_port *port, u8 c) 246 { 247 esp32_uart_write(port, UART_FIFO_REG, c); 248 } 249 250 static void esp32_uart_put_char_sync(struct uart_port *port, u8 c) 251 { 252 unsigned long timeout = jiffies + HZ; 253 254 while (esp32_uart_tx_fifo_cnt(port) >= ESP32_UART_TX_FIFO_SIZE) { 255 if (time_after(jiffies, timeout)) { 256 dev_warn(port->dev, "timeout waiting for TX FIFO\n"); 257 return; 258 } 259 cpu_relax(); 260 } 261 esp32_uart_put_char(port, c); 262 } 263 264 static void esp32_uart_transmit_buffer(struct uart_port *port) 265 { 266 u32 tx_fifo_used = esp32_uart_tx_fifo_cnt(port); 267 unsigned int pending; 268 u8 ch; 269 270 if (tx_fifo_used >= ESP32_UART_TX_FIFO_SIZE) 271 return; 272 273 pending = uart_port_tx_limited(port, ch, 274 ESP32_UART_TX_FIFO_SIZE - tx_fifo_used, 275 true, esp32_uart_put_char(port, ch), 276 ({})); 277 if (pending) { 278 u32 int_ena; 279 280 int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 281 int_ena |= UART_TXFIFO_EMPTY_INT; 282 esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 283 } 284 } 285 286 static void esp32_uart_txint(struct uart_port *port) 287 { 288 esp32_uart_transmit_buffer(port); 289 } 290 291 static irqreturn_t esp32_uart_int(int irq, void *dev_id) 292 { 293 struct uart_port *port = dev_id; 294 u32 status; 295 296 status = esp32_uart_read(port, UART_INT_ST_REG); 297 298 if (status & (UART_RXFIFO_FULL_INT | UART_BRK_DET_INT)) 299 esp32_uart_rxint(port); 300 if (status & UART_TXFIFO_EMPTY_INT) 301 esp32_uart_txint(port); 302 303 esp32_uart_write(port, UART_INT_CLR_REG, status); 304 305 return IRQ_RETVAL(status); 306 } 307 308 static void esp32_uart_start_tx(struct uart_port *port) 309 { 310 esp32_uart_transmit_buffer(port); 311 } 312 313 static void esp32_uart_stop_rx(struct uart_port *port) 314 { 315 u32 int_ena; 316 317 int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 318 int_ena &= ~UART_RXFIFO_FULL_INT; 319 esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 320 } 321 322 static int esp32_uart_startup(struct uart_port *port) 323 { 324 int ret = 0; 325 unsigned long flags; 326 struct esp32_port *sport = container_of(port, struct esp32_port, port); 327 328 ret = clk_prepare_enable(sport->clk); 329 if (ret) 330 return ret; 331 332 ret = request_irq(port->irq, esp32_uart_int, 0, DRIVER_NAME, port); 333 if (ret) { 334 clk_disable_unprepare(sport->clk); 335 return ret; 336 } 337 338 spin_lock_irqsave(&port->lock, flags); 339 if (port_variant(port)->has_clkconf) 340 esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG, 341 ESP32S3_UART_CLK_CONF_DEFAULT); 342 esp32_uart_write(port, UART_CONF1_REG, 343 (1 << UART_RXFIFO_FULL_THRHD_SHIFT) | 344 (1 << port_variant(port)->txfifo_empty_thrhd_shift)); 345 esp32_uart_write(port, UART_INT_CLR_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); 346 esp32_uart_write(port, UART_INT_ENA_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); 347 spin_unlock_irqrestore(&port->lock, flags); 348 349 return ret; 350 } 351 352 static void esp32_uart_shutdown(struct uart_port *port) 353 { 354 struct esp32_port *sport = container_of(port, struct esp32_port, port); 355 356 esp32_uart_write(port, UART_INT_ENA_REG, 0); 357 free_irq(port->irq, port); 358 clk_disable_unprepare(sport->clk); 359 } 360 361 static bool esp32_uart_set_baud(struct uart_port *port, u32 baud) 362 { 363 u32 sclk = port->uartclk; 364 u32 div = sclk / baud; 365 366 if (port_variant(port)->has_clkconf) { 367 u32 sclk_div = div / port_variant(port)->clkdiv_mask; 368 369 if (div > port_variant(port)->clkdiv_mask) { 370 sclk /= (sclk_div + 1); 371 div = sclk / baud; 372 } 373 esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG, 374 FIELD_PREP(ESP32S3_UART_SCLK_DIV_NUM, sclk_div) | 375 ESP32S3_UART_CLK_CONF_DEFAULT); 376 } 377 378 if (div <= port_variant(port)->clkdiv_mask) { 379 u32 frag = (sclk * 16) / baud - div * 16; 380 381 esp32_uart_write(port, UART_CLKDIV_REG, 382 div | FIELD_PREP(UART_CLKDIV_FRAG, frag)); 383 return true; 384 } 385 386 return false; 387 } 388 389 static void esp32_uart_set_termios(struct uart_port *port, 390 struct ktermios *termios, 391 const struct ktermios *old) 392 { 393 unsigned long flags; 394 u32 conf0, conf1; 395 u32 baud; 396 const u32 rx_flow_en = port_variant(port)->rx_flow_en; 397 u32 max_div = port_variant(port)->clkdiv_mask; 398 399 termios->c_cflag &= ~CMSPAR; 400 401 if (port_variant(port)->has_clkconf) 402 max_div *= FIELD_MAX(ESP32S3_UART_SCLK_DIV_NUM); 403 404 baud = uart_get_baud_rate(port, termios, old, 405 port->uartclk / max_div, 406 port->uartclk / 16); 407 408 spin_lock_irqsave(&port->lock, flags); 409 410 conf0 = esp32_uart_read(port, UART_CONF0_REG); 411 conf0 &= ~(UART_PARITY_EN | UART_PARITY | UART_BIT_NUM | UART_STOP_BIT_NUM); 412 413 conf1 = esp32_uart_read(port, UART_CONF1_REG); 414 conf1 &= ~rx_flow_en; 415 416 if (termios->c_cflag & PARENB) { 417 conf0 |= UART_PARITY_EN; 418 if (termios->c_cflag & PARODD) 419 conf0 |= UART_PARITY; 420 } 421 422 switch (termios->c_cflag & CSIZE) { 423 case CS5: 424 conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_5); 425 break; 426 case CS6: 427 conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_6); 428 break; 429 case CS7: 430 conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_7); 431 break; 432 case CS8: 433 conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_8); 434 break; 435 } 436 437 if (termios->c_cflag & CSTOPB) 438 conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_2); 439 else 440 conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_1); 441 442 if (termios->c_cflag & CRTSCTS) 443 conf1 |= rx_flow_en; 444 445 esp32_uart_write(port, UART_CONF0_REG, conf0); 446 esp32_uart_write(port, UART_CONF1_REG, conf1); 447 448 if (baud) { 449 esp32_uart_set_baud(port, baud); 450 uart_update_timeout(port, termios->c_cflag, baud); 451 } else { 452 if (esp32_uart_set_baud(port, 115200)) { 453 baud = 115200; 454 tty_termios_encode_baud_rate(termios, baud, baud); 455 uart_update_timeout(port, termios->c_cflag, baud); 456 } else { 457 dev_warn(port->dev, 458 "unable to set speed to %d baud or the default 115200\n", 459 baud); 460 } 461 } 462 spin_unlock_irqrestore(&port->lock, flags); 463 } 464 465 static const char *esp32_uart_type(struct uart_port *port) 466 { 467 return port_variant(port)->type; 468 } 469 470 /* configure/auto-configure the port */ 471 static void esp32_uart_config_port(struct uart_port *port, int flags) 472 { 473 if (flags & UART_CONFIG_TYPE) 474 port->type = PORT_GENERIC; 475 } 476 477 #ifdef CONFIG_CONSOLE_POLL 478 static int esp32_uart_poll_init(struct uart_port *port) 479 { 480 struct esp32_port *sport = container_of(port, struct esp32_port, port); 481 482 return clk_prepare_enable(sport->clk); 483 } 484 485 static void esp32_uart_poll_put_char(struct uart_port *port, unsigned char c) 486 { 487 esp32_uart_put_char_sync(port, c); 488 } 489 490 static int esp32_uart_poll_get_char(struct uart_port *port) 491 { 492 if (esp32_uart_rx_fifo_cnt(port)) 493 return esp32_uart_read(port, UART_FIFO_REG); 494 else 495 return NO_POLL_CHAR; 496 497 } 498 #endif 499 500 static const struct uart_ops esp32_uart_pops = { 501 .tx_empty = esp32_uart_tx_empty, 502 .set_mctrl = esp32_uart_set_mctrl, 503 .get_mctrl = esp32_uart_get_mctrl, 504 .stop_tx = esp32_uart_stop_tx, 505 .start_tx = esp32_uart_start_tx, 506 .stop_rx = esp32_uart_stop_rx, 507 .startup = esp32_uart_startup, 508 .shutdown = esp32_uart_shutdown, 509 .set_termios = esp32_uart_set_termios, 510 .type = esp32_uart_type, 511 .config_port = esp32_uart_config_port, 512 #ifdef CONFIG_CONSOLE_POLL 513 .poll_init = esp32_uart_poll_init, 514 .poll_put_char = esp32_uart_poll_put_char, 515 .poll_get_char = esp32_uart_poll_get_char, 516 #endif 517 }; 518 519 static void esp32_uart_console_putchar(struct uart_port *port, u8 c) 520 { 521 esp32_uart_put_char_sync(port, c); 522 } 523 524 static void esp32_uart_string_write(struct uart_port *port, const char *s, 525 unsigned int count) 526 { 527 uart_console_write(port, s, count, esp32_uart_console_putchar); 528 } 529 530 static void 531 esp32_uart_console_write(struct console *co, const char *s, unsigned int count) 532 { 533 struct esp32_port *sport = esp32_uart_ports[co->index]; 534 struct uart_port *port = &sport->port; 535 unsigned long flags; 536 bool locked = true; 537 538 if (port->sysrq) 539 locked = false; 540 else if (oops_in_progress) 541 locked = spin_trylock_irqsave(&port->lock, flags); 542 else 543 spin_lock_irqsave(&port->lock, flags); 544 545 esp32_uart_string_write(port, s, count); 546 547 if (locked) 548 spin_unlock_irqrestore(&port->lock, flags); 549 } 550 551 static int __init esp32_uart_console_setup(struct console *co, char *options) 552 { 553 struct esp32_port *sport; 554 int baud = 115200; 555 int bits = 8; 556 int parity = 'n'; 557 int flow = 'n'; 558 int ret; 559 560 /* 561 * check whether an invalid uart number has been specified, and 562 * if so, search for the first available port that does have 563 * console support. 564 */ 565 if (co->index == -1 || co->index >= ARRAY_SIZE(esp32_uart_ports)) 566 co->index = 0; 567 568 sport = esp32_uart_ports[co->index]; 569 if (!sport) 570 return -ENODEV; 571 572 ret = clk_prepare_enable(sport->clk); 573 if (ret) 574 return ret; 575 576 if (options) 577 uart_parse_options(options, &baud, &parity, &bits, &flow); 578 579 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 580 } 581 582 static int esp32_uart_console_exit(struct console *co) 583 { 584 struct esp32_port *sport = esp32_uart_ports[co->index]; 585 586 clk_disable_unprepare(sport->clk); 587 return 0; 588 } 589 590 static struct uart_driver esp32_uart_reg; 591 static struct console esp32_uart_console = { 592 .name = DEV_NAME, 593 .write = esp32_uart_console_write, 594 .device = uart_console_device, 595 .setup = esp32_uart_console_setup, 596 .exit = esp32_uart_console_exit, 597 .flags = CON_PRINTBUFFER, 598 .index = -1, 599 .data = &esp32_uart_reg, 600 }; 601 602 static void esp32_uart_earlycon_putchar(struct uart_port *port, u8 c) 603 { 604 esp32_uart_put_char_sync(port, c); 605 } 606 607 static void esp32_uart_earlycon_write(struct console *con, const char *s, 608 unsigned int n) 609 { 610 struct earlycon_device *dev = con->data; 611 612 uart_console_write(&dev->port, s, n, esp32_uart_earlycon_putchar); 613 } 614 615 #ifdef CONFIG_CONSOLE_POLL 616 static int esp32_uart_earlycon_read(struct console *con, char *s, unsigned int n) 617 { 618 struct earlycon_device *dev = con->data; 619 unsigned int num_read = 0; 620 621 while (num_read < n) { 622 int c = esp32_uart_poll_get_char(&dev->port); 623 624 if (c == NO_POLL_CHAR) 625 break; 626 s[num_read++] = c; 627 } 628 return num_read; 629 } 630 #endif 631 632 static int __init esp32xx_uart_early_console_setup(struct earlycon_device *device, 633 const char *options) 634 { 635 if (!device->port.membase) 636 return -ENODEV; 637 638 device->con->write = esp32_uart_earlycon_write; 639 #ifdef CONFIG_CONSOLE_POLL 640 device->con->read = esp32_uart_earlycon_read; 641 #endif 642 if (device->port.uartclk != BASE_BAUD * 16) 643 esp32_uart_set_baud(&device->port, device->baud); 644 645 return 0; 646 } 647 648 static int __init esp32_uart_early_console_setup(struct earlycon_device *device, 649 const char *options) 650 { 651 device->port.private_data = (void *)&esp32_variant; 652 653 return esp32xx_uart_early_console_setup(device, options); 654 } 655 656 OF_EARLYCON_DECLARE(esp32uart, "esp,esp32-uart", 657 esp32_uart_early_console_setup); 658 659 static int __init esp32s3_uart_early_console_setup(struct earlycon_device *device, 660 const char *options) 661 { 662 device->port.private_data = (void *)&esp32s3_variant; 663 664 return esp32xx_uart_early_console_setup(device, options); 665 } 666 667 OF_EARLYCON_DECLARE(esp32s3uart, "esp,esp32s3-uart", 668 esp32s3_uart_early_console_setup); 669 670 static struct uart_driver esp32_uart_reg = { 671 .owner = THIS_MODULE, 672 .driver_name = DRIVER_NAME, 673 .dev_name = DEV_NAME, 674 .nr = ARRAY_SIZE(esp32_uart_ports), 675 .cons = &esp32_uart_console, 676 }; 677 678 static int esp32_uart_probe(struct platform_device *pdev) 679 { 680 struct device_node *np = pdev->dev.of_node; 681 static const struct of_device_id *match; 682 struct uart_port *port; 683 struct esp32_port *sport; 684 struct resource *res; 685 int ret; 686 687 match = of_match_device(esp32_uart_dt_ids, &pdev->dev); 688 if (!match) 689 return -ENODEV; 690 691 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 692 if (!sport) 693 return -ENOMEM; 694 695 port = &sport->port; 696 697 ret = of_alias_get_id(np, "serial"); 698 if (ret < 0) { 699 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 700 return ret; 701 } 702 if (ret >= UART_NR) { 703 dev_err(&pdev->dev, "driver limited to %d serial ports\n", UART_NR); 704 return -ENOMEM; 705 } 706 707 port->line = ret; 708 709 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 710 if (!res) 711 return -ENODEV; 712 713 port->mapbase = res->start; 714 port->membase = devm_ioremap_resource(&pdev->dev, res); 715 if (IS_ERR(port->membase)) 716 return PTR_ERR(port->membase); 717 718 sport->clk = devm_clk_get(&pdev->dev, NULL); 719 if (IS_ERR(sport->clk)) 720 return PTR_ERR(sport->clk); 721 722 port->uartclk = clk_get_rate(sport->clk); 723 port->dev = &pdev->dev; 724 port->type = PORT_GENERIC; 725 port->iotype = UPIO_MEM; 726 port->irq = platform_get_irq(pdev, 0); 727 port->ops = &esp32_uart_pops; 728 port->flags = UPF_BOOT_AUTOCONF; 729 port->has_sysrq = 1; 730 port->fifosize = ESP32_UART_TX_FIFO_SIZE; 731 port->private_data = (void *)match->data; 732 733 esp32_uart_ports[port->line] = sport; 734 735 platform_set_drvdata(pdev, port); 736 737 return uart_add_one_port(&esp32_uart_reg, port); 738 } 739 740 static int esp32_uart_remove(struct platform_device *pdev) 741 { 742 struct uart_port *port = platform_get_drvdata(pdev); 743 744 uart_remove_one_port(&esp32_uart_reg, port); 745 746 return 0; 747 } 748 749 750 static struct platform_driver esp32_uart_driver = { 751 .probe = esp32_uart_probe, 752 .remove = esp32_uart_remove, 753 .driver = { 754 .name = DRIVER_NAME, 755 .of_match_table = esp32_uart_dt_ids, 756 }, 757 }; 758 759 static int __init esp32_uart_init(void) 760 { 761 int ret; 762 763 ret = uart_register_driver(&esp32_uart_reg); 764 if (ret) 765 return ret; 766 767 ret = platform_driver_register(&esp32_uart_driver); 768 if (ret) 769 uart_unregister_driver(&esp32_uart_reg); 770 771 return ret; 772 } 773 774 static void __exit esp32_uart_exit(void) 775 { 776 platform_driver_unregister(&esp32_uart_driver); 777 uart_unregister_driver(&esp32_uart_reg); 778 } 779 780 module_init(esp32_uart_init); 781 module_exit(esp32_uart_exit); 782 783 MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); 784 MODULE_LICENSE("GPL"); 785