1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for CPM (SCC/SMC) serial ports; core driver 4 * 5 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek 6 * Based on ppc8xx.c by Thomas Gleixner 7 * Based on drivers/serial/amba.c by Russell King 8 * 9 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) 10 * Pantelis Antoniou (panto@intracom.gr) (CPM1) 11 * 12 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. 13 * (C) 2004 Intracom, S.A. 14 * (C) 2005-2006 MontaVista Software, Inc. 15 * Vitaly Bordug <vbordug@ru.mvista.com> 16 */ 17 18 #include <linux/module.h> 19 #include <linux/tty.h> 20 #include <linux/tty_flip.h> 21 #include <linux/ioport.h> 22 #include <linux/init.h> 23 #include <linux/serial.h> 24 #include <linux/console.h> 25 #include <linux/sysrq.h> 26 #include <linux/device.h> 27 #include <linux/memblock.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_platform.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/clk.h> 34 35 #include <sysdev/fsl_soc.h> 36 37 #include <asm/io.h> 38 #include <asm/irq.h> 39 #include <asm/delay.h> 40 #include <asm/udbg.h> 41 42 #include <linux/serial_core.h> 43 #include <linux/kernel.h> 44 45 #include "cpm_uart.h" 46 47 48 /**************************************************************/ 49 50 static int cpm_uart_tx_pump(struct uart_port *port); 51 static void cpm_uart_initbd(struct uart_cpm_port *pinfo); 52 53 /**************************************************************/ 54 55 #define HW_BUF_SPD_THRESHOLD 2400 56 57 static void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd) 58 { 59 cpm_command(port->command, cmd); 60 } 61 62 /* 63 * Check, if transmit buffers are processed 64 */ 65 static unsigned int cpm_uart_tx_empty(struct uart_port *port) 66 { 67 struct uart_cpm_port *pinfo = 68 container_of(port, struct uart_cpm_port, port); 69 cbd_t __iomem *bdp = pinfo->tx_bd_base; 70 int ret = 0; 71 72 while (1) { 73 if (in_be16(&bdp->cbd_sc) & BD_SC_READY) 74 break; 75 76 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { 77 ret = TIOCSER_TEMT; 78 break; 79 } 80 bdp++; 81 } 82 83 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); 84 85 return ret; 86 } 87 88 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 89 { 90 struct uart_cpm_port *pinfo = 91 container_of(port, struct uart_cpm_port, port); 92 93 if (pinfo->gpios[GPIO_RTS]) 94 gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); 95 96 if (pinfo->gpios[GPIO_DTR]) 97 gpiod_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); 98 } 99 100 static unsigned int cpm_uart_get_mctrl(struct uart_port *port) 101 { 102 struct uart_cpm_port *pinfo = 103 container_of(port, struct uart_cpm_port, port); 104 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 105 106 if (pinfo->gpios[GPIO_CTS]) { 107 if (gpiod_get_value(pinfo->gpios[GPIO_CTS])) 108 mctrl &= ~TIOCM_CTS; 109 } 110 111 if (pinfo->gpios[GPIO_DSR]) { 112 if (gpiod_get_value(pinfo->gpios[GPIO_DSR])) 113 mctrl &= ~TIOCM_DSR; 114 } 115 116 if (pinfo->gpios[GPIO_DCD]) { 117 if (gpiod_get_value(pinfo->gpios[GPIO_DCD])) 118 mctrl &= ~TIOCM_CAR; 119 } 120 121 if (pinfo->gpios[GPIO_RI]) { 122 if (!gpiod_get_value(pinfo->gpios[GPIO_RI])) 123 mctrl |= TIOCM_RNG; 124 } 125 126 return mctrl; 127 } 128 129 /* 130 * Stop transmitter 131 */ 132 static void cpm_uart_stop_tx(struct uart_port *port) 133 { 134 struct uart_cpm_port *pinfo = 135 container_of(port, struct uart_cpm_port, port); 136 smc_t __iomem *smcp = pinfo->smcp; 137 scc_t __iomem *sccp = pinfo->sccp; 138 139 pr_debug("CPM uart[%d]:stop tx\n", port->line); 140 141 if (IS_SMC(pinfo)) 142 clrbits8(&smcp->smc_smcm, SMCM_TX); 143 else 144 clrbits16(&sccp->scc_sccm, UART_SCCM_TX); 145 } 146 147 /* 148 * Start transmitter 149 */ 150 static void cpm_uart_start_tx(struct uart_port *port) 151 { 152 struct uart_cpm_port *pinfo = 153 container_of(port, struct uart_cpm_port, port); 154 smc_t __iomem *smcp = pinfo->smcp; 155 scc_t __iomem *sccp = pinfo->sccp; 156 157 pr_debug("CPM uart[%d]:start tx\n", port->line); 158 159 if (IS_SMC(pinfo)) { 160 if (in_8(&smcp->smc_smcm) & SMCM_TX) 161 return; 162 } else { 163 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) 164 return; 165 } 166 167 if (cpm_uart_tx_pump(port) != 0) { 168 if (IS_SMC(pinfo)) { 169 setbits8(&smcp->smc_smcm, SMCM_TX); 170 } else { 171 setbits16(&sccp->scc_sccm, UART_SCCM_TX); 172 } 173 } 174 } 175 176 /* 177 * Stop receiver 178 */ 179 static void cpm_uart_stop_rx(struct uart_port *port) 180 { 181 struct uart_cpm_port *pinfo = 182 container_of(port, struct uart_cpm_port, port); 183 smc_t __iomem *smcp = pinfo->smcp; 184 scc_t __iomem *sccp = pinfo->sccp; 185 186 pr_debug("CPM uart[%d]:stop rx\n", port->line); 187 188 if (IS_SMC(pinfo)) 189 clrbits8(&smcp->smc_smcm, SMCM_RX); 190 else 191 clrbits16(&sccp->scc_sccm, UART_SCCM_RX); 192 } 193 194 /* 195 * Generate a break. 196 */ 197 static void cpm_uart_break_ctl(struct uart_port *port, int break_state) 198 { 199 struct uart_cpm_port *pinfo = 200 container_of(port, struct uart_cpm_port, port); 201 202 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, 203 break_state); 204 205 if (break_state) 206 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 207 else 208 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 209 } 210 211 /* 212 * Transmit characters, refill buffer descriptor, if possible 213 */ 214 static void cpm_uart_int_tx(struct uart_port *port) 215 { 216 pr_debug("CPM uart[%d]:TX INT\n", port->line); 217 218 cpm_uart_tx_pump(port); 219 } 220 221 #ifdef CONFIG_CONSOLE_POLL 222 static int serial_polled; 223 #endif 224 225 /* 226 * Receive characters 227 */ 228 static void cpm_uart_int_rx(struct uart_port *port) 229 { 230 int i; 231 unsigned char ch; 232 u8 *cp; 233 struct tty_port *tport = &port->state->port; 234 struct uart_cpm_port *pinfo = 235 container_of(port, struct uart_cpm_port, port); 236 cbd_t __iomem *bdp; 237 u16 status; 238 unsigned int flg; 239 240 pr_debug("CPM uart[%d]:RX INT\n", port->line); 241 242 /* Just loop through the closed BDs and copy the characters into 243 * the buffer. 244 */ 245 bdp = pinfo->rx_cur; 246 for (;;) { 247 #ifdef CONFIG_CONSOLE_POLL 248 if (unlikely(serial_polled)) { 249 serial_polled = 0; 250 return; 251 } 252 #endif 253 /* get status */ 254 status = in_be16(&bdp->cbd_sc); 255 /* If this one is empty, return happy */ 256 if (status & BD_SC_EMPTY) 257 break; 258 259 /* get number of characters, and check spce in flip-buffer */ 260 i = in_be16(&bdp->cbd_datlen); 261 262 /* If we have not enough room in tty flip buffer, then we try 263 * later, which will be the next rx-interrupt or a timeout 264 */ 265 if (tty_buffer_request_room(tport, i) < i) { 266 printk(KERN_WARNING "No room in flip buffer\n"); 267 return; 268 } 269 270 /* get pointer */ 271 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 272 273 /* loop through the buffer */ 274 while (i-- > 0) { 275 ch = *cp++; 276 port->icount.rx++; 277 flg = TTY_NORMAL; 278 279 if (status & 280 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 281 goto handle_error; 282 if (uart_handle_sysrq_char(port, ch)) 283 continue; 284 #ifdef CONFIG_CONSOLE_POLL 285 if (unlikely(serial_polled)) { 286 serial_polled = 0; 287 return; 288 } 289 #endif 290 error_return: 291 tty_insert_flip_char(tport, ch, flg); 292 293 } /* End while (i--) */ 294 295 /* This BD is ready to be used again. Clear status. get next */ 296 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | 297 BD_SC_OV | BD_SC_ID); 298 setbits16(&bdp->cbd_sc, BD_SC_EMPTY); 299 300 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 301 bdp = pinfo->rx_bd_base; 302 else 303 bdp++; 304 305 } /* End for (;;) */ 306 307 /* Write back buffer pointer */ 308 pinfo->rx_cur = bdp; 309 310 /* activate BH processing */ 311 tty_flip_buffer_push(tport); 312 313 return; 314 315 /* Error processing */ 316 317 handle_error: 318 /* Statistics */ 319 if (status & BD_SC_BR) 320 port->icount.brk++; 321 if (status & BD_SC_PR) 322 port->icount.parity++; 323 if (status & BD_SC_FR) 324 port->icount.frame++; 325 if (status & BD_SC_OV) 326 port->icount.overrun++; 327 328 /* Mask out ignored conditions */ 329 status &= port->read_status_mask; 330 331 /* Handle the remaining ones */ 332 if (status & BD_SC_BR) 333 flg = TTY_BREAK; 334 else if (status & BD_SC_PR) 335 flg = TTY_PARITY; 336 else if (status & BD_SC_FR) 337 flg = TTY_FRAME; 338 339 /* overrun does not affect the current character ! */ 340 if (status & BD_SC_OV) { 341 ch = 0; 342 flg = TTY_OVERRUN; 343 /* We skip this buffer */ 344 /* CHECK: Is really nothing senseful there */ 345 /* ASSUMPTION: it contains nothing valid */ 346 i = 0; 347 } 348 port->sysrq = 0; 349 goto error_return; 350 } 351 352 /* 353 * Asynchron mode interrupt handler 354 */ 355 static irqreturn_t cpm_uart_int(int irq, void *data) 356 { 357 u8 events; 358 struct uart_port *port = data; 359 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 360 smc_t __iomem *smcp = pinfo->smcp; 361 scc_t __iomem *sccp = pinfo->sccp; 362 363 pr_debug("CPM uart[%d]:IRQ\n", port->line); 364 365 if (IS_SMC(pinfo)) { 366 events = in_8(&smcp->smc_smce); 367 out_8(&smcp->smc_smce, events); 368 if (events & SMCM_BRKE) 369 uart_handle_break(port); 370 if (events & SMCM_RX) 371 cpm_uart_int_rx(port); 372 if (events & SMCM_TX) 373 cpm_uart_int_tx(port); 374 } else { 375 events = in_be16(&sccp->scc_scce); 376 out_be16(&sccp->scc_scce, events); 377 if (events & UART_SCCM_BRKE) 378 uart_handle_break(port); 379 if (events & UART_SCCM_RX) 380 cpm_uart_int_rx(port); 381 if (events & UART_SCCM_TX) 382 cpm_uart_int_tx(port); 383 } 384 return (events) ? IRQ_HANDLED : IRQ_NONE; 385 } 386 387 static int cpm_uart_startup(struct uart_port *port) 388 { 389 int retval; 390 struct uart_cpm_port *pinfo = 391 container_of(port, struct uart_cpm_port, port); 392 393 pr_debug("CPM uart[%d]:startup\n", port->line); 394 395 /* If the port is not the console, make sure rx is disabled. */ 396 if (!(pinfo->flags & FLAG_CONSOLE)) { 397 /* Disable UART rx */ 398 if (IS_SMC(pinfo)) { 399 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); 400 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 401 } else { 402 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); 403 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 404 } 405 cpm_uart_initbd(pinfo); 406 if (IS_SMC(pinfo)) { 407 out_be32(&pinfo->smcup->smc_rstate, 0); 408 out_be32(&pinfo->smcup->smc_tstate, 0); 409 out_be16(&pinfo->smcup->smc_rbptr, 410 in_be16(&pinfo->smcup->smc_rbase)); 411 out_be16(&pinfo->smcup->smc_tbptr, 412 in_be16(&pinfo->smcup->smc_tbase)); 413 } else { 414 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 415 } 416 } 417 /* Install interrupt handler. */ 418 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); 419 if (retval) 420 return retval; 421 422 /* Startup rx-int */ 423 if (IS_SMC(pinfo)) { 424 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 425 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); 426 } else { 427 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 428 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); 429 } 430 431 return 0; 432 } 433 434 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) 435 { 436 set_current_state(TASK_UNINTERRUPTIBLE); 437 schedule_timeout(pinfo->wait_closing); 438 } 439 440 /* 441 * Shutdown the uart 442 */ 443 static void cpm_uart_shutdown(struct uart_port *port) 444 { 445 struct uart_cpm_port *pinfo = 446 container_of(port, struct uart_cpm_port, port); 447 448 pr_debug("CPM uart[%d]:shutdown\n", port->line); 449 450 /* free interrupt handler */ 451 free_irq(port->irq, port); 452 453 /* If the port is not the console, disable Rx and Tx. */ 454 if (!(pinfo->flags & FLAG_CONSOLE)) { 455 /* Wait for all the BDs marked sent */ 456 while(!cpm_uart_tx_empty(port)) { 457 set_current_state(TASK_UNINTERRUPTIBLE); 458 schedule_timeout(2); 459 } 460 461 if (pinfo->wait_closing) 462 cpm_uart_wait_until_send(pinfo); 463 464 /* Stop uarts */ 465 if (IS_SMC(pinfo)) { 466 smc_t __iomem *smcp = pinfo->smcp; 467 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 468 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); 469 } else { 470 scc_t __iomem *sccp = pinfo->sccp; 471 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 472 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 473 } 474 475 /* Shut them really down and reinit buffer descriptors */ 476 if (IS_SMC(pinfo)) { 477 out_be16(&pinfo->smcup->smc_brkcr, 0); 478 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 479 } else { 480 out_be16(&pinfo->sccup->scc_brkcr, 0); 481 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 482 } 483 484 cpm_uart_initbd(pinfo); 485 } 486 } 487 488 static void cpm_uart_set_termios(struct uart_port *port, 489 struct ktermios *termios, 490 const struct ktermios *old) 491 { 492 int baud; 493 unsigned long flags; 494 u16 cval, scval, prev_mode; 495 struct uart_cpm_port *pinfo = 496 container_of(port, struct uart_cpm_port, port); 497 smc_t __iomem *smcp = pinfo->smcp; 498 scc_t __iomem *sccp = pinfo->sccp; 499 int maxidl; 500 501 pr_debug("CPM uart[%d]:set_termios\n", port->line); 502 503 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 504 if (baud < HW_BUF_SPD_THRESHOLD || port->flags & UPF_LOW_LATENCY) 505 pinfo->rx_fifosize = 1; 506 else 507 pinfo->rx_fifosize = RX_BUF_SIZE; 508 509 /* MAXIDL is the timeout after which a receive buffer is closed 510 * when not full if no more characters are received. 511 * We calculate it from the baudrate so that the duration is 512 * always the same at standard rates: about 4ms. 513 */ 514 maxidl = baud / 2400; 515 if (maxidl < 1) 516 maxidl = 1; 517 if (maxidl > 0x10) 518 maxidl = 0x10; 519 520 cval = 0; 521 scval = 0; 522 523 if (termios->c_cflag & CSTOPB) { 524 cval |= SMCMR_SL; /* Two stops */ 525 scval |= SCU_PSMR_SL; 526 } 527 528 if (termios->c_cflag & PARENB) { 529 cval |= SMCMR_PEN; 530 scval |= SCU_PSMR_PEN; 531 if (!(termios->c_cflag & PARODD)) { 532 cval |= SMCMR_PM_EVEN; 533 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); 534 } 535 } 536 537 /* 538 * Update the timeout 539 */ 540 uart_update_timeout(port, termios->c_cflag, baud); 541 542 /* 543 * Set up parity check flag 544 */ 545 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); 546 if (termios->c_iflag & INPCK) 547 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 548 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) 549 port->read_status_mask |= BD_SC_BR; 550 551 /* 552 * Characters to ignore 553 */ 554 port->ignore_status_mask = 0; 555 if (termios->c_iflag & IGNPAR) 556 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 557 if (termios->c_iflag & IGNBRK) { 558 port->ignore_status_mask |= BD_SC_BR; 559 /* 560 * If we're ignore parity and break indicators, ignore 561 * overruns too. (For real raw support). 562 */ 563 if (termios->c_iflag & IGNPAR) 564 port->ignore_status_mask |= BD_SC_OV; 565 } 566 /* 567 * !!! ignore all characters if CREAD is not set 568 */ 569 if ((termios->c_cflag & CREAD) == 0) 570 port->read_status_mask &= ~BD_SC_EMPTY; 571 572 uart_port_lock_irqsave(port, &flags); 573 574 if (IS_SMC(pinfo)) { 575 unsigned int bits = tty_get_frame_size(termios->c_cflag); 576 577 /* 578 * MRBLR can be changed while an SMC/SCC is operating only 579 * if it is done in a single bus cycle with one 16-bit move 580 * (not two 8-bit bus cycles back-to-back). This occurs when 581 * the cp shifts control to the next RxBD, so the change does 582 * not take effect immediately. To guarantee the exact RxBD 583 * on which the change occurs, change MRBLR only while the 584 * SMC/SCC receiver is disabled. 585 */ 586 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); 587 out_be16(&pinfo->smcup->smc_maxidl, maxidl); 588 589 /* Set the mode register. We want to keep a copy of the 590 * enables, because we want to put them back if they were 591 * present. 592 */ 593 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); 594 /* Output in *one* operation, so we don't interrupt RX/TX if they 595 * were already enabled. 596 * Character length programmed into the register is frame bits minus 1. 597 */ 598 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits - 1) | cval | 599 SMCMR_SM_UART | prev_mode); 600 } else { 601 unsigned int bits = tty_get_char_size(termios->c_cflag); 602 603 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 604 out_be16(&pinfo->sccup->scc_maxidl, maxidl); 605 out_be16(&sccp->scc_psmr, (UART_LCR_WLEN(bits) << 12) | scval); 606 } 607 608 if (pinfo->clk) 609 clk_set_rate(pinfo->clk, baud); 610 else 611 cpm_setbrg(pinfo->brg - 1, baud); 612 uart_port_unlock_irqrestore(port, flags); 613 } 614 615 static const char *cpm_uart_type(struct uart_port *port) 616 { 617 pr_debug("CPM uart[%d]:uart_type\n", port->line); 618 619 return port->type == PORT_CPM ? "CPM UART" : NULL; 620 } 621 622 /* 623 * verify the new serial_struct (for TIOCSSERIAL). 624 */ 625 static int cpm_uart_verify_port(struct uart_port *port, 626 struct serial_struct *ser) 627 { 628 int ret = 0; 629 630 pr_debug("CPM uart[%d]:verify_port\n", port->line); 631 632 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 633 ret = -EINVAL; 634 if (ser->irq < 0 || ser->irq >= nr_irqs) 635 ret = -EINVAL; 636 if (ser->baud_base < 9600) 637 ret = -EINVAL; 638 return ret; 639 } 640 641 /* 642 * Transmit characters, refill buffer descriptor, if possible 643 */ 644 static int cpm_uart_tx_pump(struct uart_port *port) 645 { 646 cbd_t __iomem *bdp; 647 u8 *p; 648 int count; 649 struct uart_cpm_port *pinfo = 650 container_of(port, struct uart_cpm_port, port); 651 struct tty_port *tport = &port->state->port; 652 653 /* Handle xon/xoff */ 654 if (port->x_char) { 655 /* Pick next descriptor and fill from buffer */ 656 bdp = pinfo->tx_cur; 657 658 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 659 660 *p++ = port->x_char; 661 662 out_be16(&bdp->cbd_datlen, 1); 663 setbits16(&bdp->cbd_sc, BD_SC_READY); 664 /* Get next BD. */ 665 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 666 bdp = pinfo->tx_bd_base; 667 else 668 bdp++; 669 pinfo->tx_cur = bdp; 670 671 port->icount.tx++; 672 port->x_char = 0; 673 return 1; 674 } 675 676 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 677 cpm_uart_stop_tx(port); 678 return 0; 679 } 680 681 /* Pick next descriptor and fill from buffer */ 682 bdp = pinfo->tx_cur; 683 684 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && 685 !kfifo_is_empty(&tport->xmit_fifo)) { 686 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 687 count = uart_fifo_out(port, p, pinfo->tx_fifosize); 688 out_be16(&bdp->cbd_datlen, count); 689 setbits16(&bdp->cbd_sc, BD_SC_READY); 690 /* Get next BD. */ 691 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 692 bdp = pinfo->tx_bd_base; 693 else 694 bdp++; 695 } 696 pinfo->tx_cur = bdp; 697 698 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 699 uart_write_wakeup(port); 700 701 if (kfifo_is_empty(&tport->xmit_fifo)) { 702 cpm_uart_stop_tx(port); 703 return 0; 704 } 705 706 return 1; 707 } 708 709 /* 710 * init buffer descriptors 711 */ 712 static void cpm_uart_initbd(struct uart_cpm_port *pinfo) 713 { 714 int i; 715 u8 *mem_addr; 716 cbd_t __iomem *bdp; 717 718 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); 719 720 /* Set the physical address of the host memory 721 * buffers in the buffer descriptors, and the 722 * virtual address for us to work with. 723 */ 724 mem_addr = pinfo->mem_addr; 725 bdp = pinfo->rx_cur = pinfo->rx_bd_base; 726 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { 727 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 728 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 729 mem_addr += pinfo->rx_fifosize; 730 } 731 732 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 733 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); 734 735 /* Set the physical address of the host memory 736 * buffers in the buffer descriptors, and the 737 * virtual address for us to work with. 738 */ 739 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); 740 bdp = pinfo->tx_cur = pinfo->tx_bd_base; 741 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { 742 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 743 out_be16(&bdp->cbd_sc, BD_SC_INTRPT); 744 mem_addr += pinfo->tx_fifosize; 745 } 746 747 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 748 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); 749 } 750 751 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) 752 { 753 scc_t __iomem *scp; 754 scc_uart_t __iomem *sup; 755 756 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); 757 758 scp = pinfo->sccp; 759 sup = pinfo->sccup; 760 761 /* Store address */ 762 out_be16(&pinfo->sccup->scc_genscc.scc_rbase, 763 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 764 out_be16(&pinfo->sccup->scc_genscc.scc_tbase, 765 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 766 767 /* Set up the uart parameters in the 768 * parameter ram. 769 */ 770 771 out_8(&sup->scc_genscc.scc_rfcr, CPMFCR_GBL | CPMFCR_EB); 772 out_8(&sup->scc_genscc.scc_tfcr, CPMFCR_GBL | CPMFCR_EB); 773 774 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 775 out_be16(&sup->scc_maxidl, 0x10); 776 out_be16(&sup->scc_brkcr, 1); 777 out_be16(&sup->scc_parec, 0); 778 out_be16(&sup->scc_frmec, 0); 779 out_be16(&sup->scc_nosec, 0); 780 out_be16(&sup->scc_brkec, 0); 781 out_be16(&sup->scc_uaddr1, 0); 782 out_be16(&sup->scc_uaddr2, 0); 783 out_be16(&sup->scc_toseq, 0); 784 out_be16(&sup->scc_char1, 0x8000); 785 out_be16(&sup->scc_char2, 0x8000); 786 out_be16(&sup->scc_char3, 0x8000); 787 out_be16(&sup->scc_char4, 0x8000); 788 out_be16(&sup->scc_char5, 0x8000); 789 out_be16(&sup->scc_char6, 0x8000); 790 out_be16(&sup->scc_char7, 0x8000); 791 out_be16(&sup->scc_char8, 0x8000); 792 out_be16(&sup->scc_rccm, 0xc0ff); 793 794 /* Send the CPM an initialize command. 795 */ 796 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 797 798 /* Set UART mode, 8 bit, no parity, one stop. 799 * Enable receive and transmit. 800 */ 801 out_be32(&scp->scc_gsmrh, 0); 802 out_be32(&scp->scc_gsmrl, 803 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); 804 805 /* Enable rx interrupts and clear all pending events. */ 806 out_be16(&scp->scc_sccm, 0); 807 out_be16(&scp->scc_scce, 0xffff); 808 out_be16(&scp->scc_dsr, 0x7e7e); 809 out_be16(&scp->scc_psmr, 0x3000); 810 811 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 812 } 813 814 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) 815 { 816 smc_t __iomem *sp; 817 smc_uart_t __iomem *up; 818 819 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); 820 821 sp = pinfo->smcp; 822 up = pinfo->smcup; 823 824 /* Store address */ 825 out_be16(&pinfo->smcup->smc_rbase, 826 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 827 out_be16(&pinfo->smcup->smc_tbase, 828 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 829 830 /* 831 * In case SMC is being relocated... 832 */ 833 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); 834 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); 835 out_be32(&up->smc_rstate, 0); 836 out_be32(&up->smc_tstate, 0); 837 out_be16(&up->smc_brkcr, 1); /* number of break chars */ 838 out_be16(&up->smc_brkec, 0); 839 840 /* Set up the uart parameters in the 841 * parameter ram. 842 */ 843 out_8(&up->smc_rfcr, CPMFCR_GBL | CPMFCR_EB); 844 out_8(&up->smc_tfcr, CPMFCR_GBL | CPMFCR_EB); 845 846 /* Using idle character time requires some additional tuning. */ 847 out_be16(&up->smc_mrblr, pinfo->rx_fifosize); 848 out_be16(&up->smc_maxidl, 0x10); 849 out_be16(&up->smc_brklen, 0); 850 out_be16(&up->smc_brkec, 0); 851 out_be16(&up->smc_brkcr, 1); 852 853 /* Set UART mode, 8 bit, no parity, one stop. 854 * Enable receive and transmit. 855 */ 856 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); 857 858 /* Enable only rx interrupts clear all pending events. */ 859 out_8(&sp->smc_smcm, 0); 860 out_8(&sp->smc_smce, 0xff); 861 862 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 863 } 864 865 /* 866 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and 867 * receive buffer descriptors from dual port ram, and a character 868 * buffer area from host mem. If we are allocating for the console we need 869 * to do it from bootmem 870 */ 871 static int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con) 872 { 873 int dpmemsz, memsz; 874 u8 __iomem *dp_mem; 875 unsigned long dp_offset; 876 u8 *mem_addr; 877 dma_addr_t dma_addr = 0; 878 879 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line); 880 881 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos); 882 dp_offset = cpm_muram_alloc(dpmemsz, 8); 883 if (IS_ERR_VALUE(dp_offset)) { 884 pr_err("%s: could not allocate buffer descriptors\n", __func__); 885 return -ENOMEM; 886 } 887 888 dp_mem = cpm_muram_addr(dp_offset); 889 890 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) + 891 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize); 892 if (IS_ENABLED(CONFIG_CPM1) && is_con) { 893 /* was hostalloc but changed cause it blows away the */ 894 /* large tlb mapping when pinning the kernel area */ 895 mem_addr = (u8 __force *)cpm_muram_addr(cpm_muram_alloc(memsz, 8)); 896 dma_addr = cpm_muram_dma((void __iomem *)mem_addr); 897 } else if (is_con) { 898 mem_addr = kzalloc(memsz, GFP_NOWAIT); 899 dma_addr = virt_to_bus(mem_addr); 900 } else { 901 mem_addr = dma_alloc_coherent(pinfo->port.dev, memsz, &dma_addr, 902 GFP_KERNEL); 903 } 904 905 if (!mem_addr) { 906 cpm_muram_free(dp_offset); 907 pr_err("%s: could not allocate coherent memory\n", __func__); 908 return -ENOMEM; 909 } 910 911 pinfo->dp_addr = dp_offset; 912 pinfo->mem_addr = mem_addr; 913 pinfo->dma_addr = dma_addr; 914 pinfo->mem_size = memsz; 915 916 pinfo->rx_buf = mem_addr; 917 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos 918 * pinfo->rx_fifosize); 919 920 pinfo->rx_bd_base = (cbd_t __iomem *)dp_mem; 921 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos; 922 923 return 0; 924 } 925 926 static void cpm_uart_freebuf(struct uart_cpm_port *pinfo) 927 { 928 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos * 929 pinfo->rx_fifosize) + 930 L1_CACHE_ALIGN(pinfo->tx_nrfifos * 931 pinfo->tx_fifosize), (void __force *)pinfo->mem_addr, 932 pinfo->dma_addr); 933 934 cpm_muram_free(pinfo->dp_addr); 935 } 936 937 /* 938 * Initialize port. This is called from early_console stuff 939 * so we have to be careful here ! 940 */ 941 static int cpm_uart_request_port(struct uart_port *port) 942 { 943 struct uart_cpm_port *pinfo = 944 container_of(port, struct uart_cpm_port, port); 945 int ret; 946 947 pr_debug("CPM uart[%d]:request port\n", port->line); 948 949 if (pinfo->flags & FLAG_CONSOLE) 950 return 0; 951 952 if (IS_SMC(pinfo)) { 953 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 954 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 955 } else { 956 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 957 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 958 } 959 960 ret = cpm_uart_allocbuf(pinfo, 0); 961 962 if (ret) 963 return ret; 964 965 cpm_uart_initbd(pinfo); 966 if (IS_SMC(pinfo)) 967 cpm_uart_init_smc(pinfo); 968 else 969 cpm_uart_init_scc(pinfo); 970 971 return 0; 972 } 973 974 static void cpm_uart_release_port(struct uart_port *port) 975 { 976 struct uart_cpm_port *pinfo = 977 container_of(port, struct uart_cpm_port, port); 978 979 if (!(pinfo->flags & FLAG_CONSOLE)) 980 cpm_uart_freebuf(pinfo); 981 } 982 983 /* 984 * Configure/autoconfigure the port. 985 */ 986 static void cpm_uart_config_port(struct uart_port *port, int flags) 987 { 988 pr_debug("CPM uart[%d]:config_port\n", port->line); 989 990 if (flags & UART_CONFIG_TYPE) { 991 port->type = PORT_CPM; 992 cpm_uart_request_port(port); 993 } 994 } 995 996 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) 997 /* 998 * Write a string to the serial port 999 * Note that this is called with interrupts already disabled 1000 */ 1001 static void cpm_uart_early_write(struct uart_cpm_port *pinfo, 1002 const char *string, u_int count, bool handle_linefeed) 1003 { 1004 unsigned int i; 1005 cbd_t __iomem *bdp, *bdbase; 1006 unsigned char *cpm_outp_addr; 1007 1008 /* Get the address of the host memory buffer. 1009 */ 1010 bdp = pinfo->tx_cur; 1011 bdbase = pinfo->tx_bd_base; 1012 1013 /* 1014 * Now, do each character. This is not as bad as it looks 1015 * since this is a holding FIFO and not a transmitting FIFO. 1016 * We could add the complexity of filling the entire transmit 1017 * buffer, but we would just wait longer between accesses...... 1018 */ 1019 for (i = 0; i < count; i++, string++) { 1020 /* Wait for transmitter fifo to empty. 1021 * Ready indicates output is ready, and xmt is doing 1022 * that, not that it is ready for us to send. 1023 */ 1024 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1025 ; 1026 1027 /* Send the character out. 1028 * If the buffer address is in the CPM DPRAM, don't 1029 * convert it. 1030 */ 1031 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1032 pinfo); 1033 *cpm_outp_addr = *string; 1034 1035 out_be16(&bdp->cbd_datlen, 1); 1036 setbits16(&bdp->cbd_sc, BD_SC_READY); 1037 1038 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1039 bdp = bdbase; 1040 else 1041 bdp++; 1042 1043 /* if a LF, also do CR... */ 1044 if (handle_linefeed && *string == 10) { 1045 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1046 ; 1047 1048 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1049 pinfo); 1050 *cpm_outp_addr = 13; 1051 1052 out_be16(&bdp->cbd_datlen, 1); 1053 setbits16(&bdp->cbd_sc, BD_SC_READY); 1054 1055 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1056 bdp = bdbase; 1057 else 1058 bdp++; 1059 } 1060 } 1061 1062 /* 1063 * Finally, Wait for transmitter & holding register to empty 1064 * and restore the IER 1065 */ 1066 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1067 ; 1068 1069 pinfo->tx_cur = bdp; 1070 } 1071 #endif 1072 1073 #ifdef CONFIG_CONSOLE_POLL 1074 /* Serial polling routines for writing and reading from the uart while 1075 * in an interrupt or debug context. 1076 */ 1077 1078 #define GDB_BUF_SIZE 512 /* power of 2, please */ 1079 1080 static char poll_buf[GDB_BUF_SIZE]; 1081 static char *pollp; 1082 static int poll_chars; 1083 1084 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) 1085 { 1086 u_char c, *cp; 1087 volatile cbd_t *bdp; 1088 int i; 1089 1090 /* Get the address of the host memory buffer. 1091 */ 1092 bdp = pinfo->rx_cur; 1093 if (bdp->cbd_sc & BD_SC_EMPTY) 1094 return NO_POLL_CHAR; 1095 1096 /* If the buffer address is in the CPM DPRAM, don't 1097 * convert it. 1098 */ 1099 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); 1100 1101 if (obuf) { 1102 i = c = bdp->cbd_datlen; 1103 while (i-- > 0) 1104 *obuf++ = *cp++; 1105 } else 1106 c = *cp; 1107 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); 1108 bdp->cbd_sc |= BD_SC_EMPTY; 1109 1110 if (bdp->cbd_sc & BD_SC_WRAP) 1111 bdp = pinfo->rx_bd_base; 1112 else 1113 bdp++; 1114 pinfo->rx_cur = (cbd_t *)bdp; 1115 1116 return (int)c; 1117 } 1118 1119 static int cpm_get_poll_char(struct uart_port *port) 1120 { 1121 struct uart_cpm_port *pinfo = 1122 container_of(port, struct uart_cpm_port, port); 1123 1124 if (!serial_polled) { 1125 serial_polled = 1; 1126 poll_chars = 0; 1127 } 1128 if (poll_chars <= 0) { 1129 int ret = poll_wait_key(poll_buf, pinfo); 1130 1131 if (ret == NO_POLL_CHAR) 1132 return ret; 1133 poll_chars = ret; 1134 pollp = poll_buf; 1135 } 1136 poll_chars--; 1137 return *pollp++; 1138 } 1139 1140 static void cpm_put_poll_char(struct uart_port *port, 1141 unsigned char c) 1142 { 1143 struct uart_cpm_port *pinfo = 1144 container_of(port, struct uart_cpm_port, port); 1145 static char ch[2]; 1146 1147 ch[0] = (char)c; 1148 cpm_uart_early_write(pinfo, ch, 1, false); 1149 } 1150 1151 #ifdef CONFIG_SERIAL_CPM_CONSOLE 1152 static struct uart_port *udbg_port; 1153 1154 static void udbg_cpm_putc(char c) 1155 { 1156 if (c == '\n') 1157 cpm_put_poll_char(udbg_port, '\r'); 1158 cpm_put_poll_char(udbg_port, c); 1159 } 1160 1161 static int udbg_cpm_getc_poll(void) 1162 { 1163 int c = cpm_get_poll_char(udbg_port); 1164 1165 return c == NO_POLL_CHAR ? -1 : c; 1166 } 1167 1168 static int udbg_cpm_getc(void) 1169 { 1170 int c; 1171 1172 while ((c = udbg_cpm_getc_poll()) == -1) 1173 cpu_relax(); 1174 return c; 1175 } 1176 #endif /* CONFIG_SERIAL_CPM_CONSOLE */ 1177 1178 #endif /* CONFIG_CONSOLE_POLL */ 1179 1180 static const struct uart_ops cpm_uart_pops = { 1181 .tx_empty = cpm_uart_tx_empty, 1182 .set_mctrl = cpm_uart_set_mctrl, 1183 .get_mctrl = cpm_uart_get_mctrl, 1184 .stop_tx = cpm_uart_stop_tx, 1185 .start_tx = cpm_uart_start_tx, 1186 .stop_rx = cpm_uart_stop_rx, 1187 .break_ctl = cpm_uart_break_ctl, 1188 .startup = cpm_uart_startup, 1189 .shutdown = cpm_uart_shutdown, 1190 .set_termios = cpm_uart_set_termios, 1191 .type = cpm_uart_type, 1192 .release_port = cpm_uart_release_port, 1193 .request_port = cpm_uart_request_port, 1194 .config_port = cpm_uart_config_port, 1195 .verify_port = cpm_uart_verify_port, 1196 #ifdef CONFIG_CONSOLE_POLL 1197 .poll_get_char = cpm_get_poll_char, 1198 .poll_put_char = cpm_put_poll_char, 1199 #endif 1200 }; 1201 1202 static struct uart_cpm_port cpm_uart_ports[UART_NR]; 1203 1204 static void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port, 1205 struct device_node *np) 1206 { 1207 void __iomem *pram; 1208 unsigned long offset; 1209 struct resource res; 1210 resource_size_t len; 1211 1212 /* Don't remap parameter RAM if it has already been initialized 1213 * during console setup. 1214 */ 1215 if (IS_SMC(port) && port->smcup) 1216 return port->smcup; 1217 else if (!IS_SMC(port) && port->sccup) 1218 return port->sccup; 1219 1220 if (of_address_to_resource(np, 1, &res)) 1221 return NULL; 1222 1223 len = resource_size(&res); 1224 pram = ioremap(res.start, len); 1225 if (!pram) 1226 return NULL; 1227 1228 if (!IS_ENABLED(CONFIG_CPM2) || !IS_SMC(port)) 1229 return pram; 1230 1231 if (len != 2) { 1232 pr_warn("cpm_uart[%d]: device tree references " 1233 "SMC pram, using boot loader/wrapper pram mapping. " 1234 "Please fix your device tree to reference the pram " 1235 "base register instead.\n", 1236 port->port.line); 1237 return pram; 1238 } 1239 1240 offset = cpm_muram_alloc(64, 64); 1241 out_be16(pram, offset); 1242 iounmap(pram); 1243 return cpm_muram_addr(offset); 1244 } 1245 1246 static void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram) 1247 { 1248 if (!IS_ENABLED(CONFIG_CPM2) || !IS_SMC(port)) 1249 iounmap(pram); 1250 } 1251 1252 static int cpm_uart_init_port(struct device_node *np, 1253 struct uart_cpm_port *pinfo) 1254 { 1255 const u32 *data; 1256 void __iomem *mem, *pram; 1257 struct device *dev = pinfo->port.dev; 1258 int len; 1259 int ret; 1260 int i; 1261 1262 data = of_get_property(np, "clock", NULL); 1263 if (data) { 1264 struct clk *clk = clk_get(NULL, (const char*)data); 1265 if (!IS_ERR(clk)) 1266 pinfo->clk = clk; 1267 } 1268 if (!pinfo->clk) { 1269 data = of_get_property(np, "fsl,cpm-brg", &len); 1270 if (!data || len != 4) { 1271 printk(KERN_ERR "CPM UART %pOFn has no/invalid " 1272 "fsl,cpm-brg property.\n", np); 1273 return -EINVAL; 1274 } 1275 pinfo->brg = *data; 1276 } 1277 1278 data = of_get_property(np, "fsl,cpm-command", &len); 1279 if (!data || len != 4) { 1280 printk(KERN_ERR "CPM UART %pOFn has no/invalid " 1281 "fsl,cpm-command property.\n", np); 1282 return -EINVAL; 1283 } 1284 pinfo->command = *data; 1285 1286 mem = of_iomap(np, 0); 1287 if (!mem) 1288 return -ENOMEM; 1289 1290 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || 1291 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { 1292 pinfo->sccp = mem; 1293 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); 1294 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || 1295 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { 1296 pinfo->flags |= FLAG_SMC; 1297 pinfo->smcp = mem; 1298 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); 1299 } else { 1300 ret = -ENODEV; 1301 goto out_mem; 1302 } 1303 1304 if (!pram) { 1305 ret = -ENOMEM; 1306 goto out_mem; 1307 } 1308 1309 pinfo->tx_nrfifos = TX_NUM_FIFO; 1310 pinfo->tx_fifosize = TX_BUF_SIZE; 1311 pinfo->rx_nrfifos = RX_NUM_FIFO; 1312 pinfo->rx_fifosize = RX_BUF_SIZE; 1313 1314 pinfo->port.uartclk = ppc_proc_freq; 1315 pinfo->port.mapbase = (unsigned long)mem; 1316 pinfo->port.type = PORT_CPM; 1317 pinfo->port.ops = &cpm_uart_pops; 1318 pinfo->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CPM_CONSOLE); 1319 pinfo->port.iotype = UPIO_MEM; 1320 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; 1321 spin_lock_init(&pinfo->port.lock); 1322 1323 for (i = 0; i < NUM_GPIOS; i++) { 1324 struct gpio_desc *gpiod; 1325 1326 pinfo->gpios[i] = NULL; 1327 1328 gpiod = devm_gpiod_get_index_optional(dev, NULL, i, GPIOD_ASIS); 1329 1330 if (IS_ERR(gpiod)) { 1331 ret = PTR_ERR(gpiod); 1332 goto out_pram; 1333 } 1334 1335 if (gpiod) { 1336 if (i == GPIO_RTS || i == GPIO_DTR) 1337 ret = gpiod_direction_output(gpiod, 0); 1338 else 1339 ret = gpiod_direction_input(gpiod); 1340 if (ret) { 1341 pr_err("can't set direction for gpio #%d: %d\n", 1342 i, ret); 1343 continue; 1344 } 1345 pinfo->gpios[i] = gpiod; 1346 } 1347 } 1348 1349 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM 1350 #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_CPM_CONSOLE) 1351 if (!udbg_port) 1352 #endif 1353 udbg_putc = NULL; 1354 #endif 1355 1356 return cpm_uart_request_port(&pinfo->port); 1357 1358 out_pram: 1359 cpm_uart_unmap_pram(pinfo, pram); 1360 out_mem: 1361 iounmap(mem); 1362 return ret; 1363 } 1364 1365 #ifdef CONFIG_SERIAL_CPM_CONSOLE 1366 /* 1367 * Print a string to the serial port trying not to disturb 1368 * any possible real use of the port... 1369 * 1370 * Note that this is called with interrupts already disabled 1371 */ 1372 static void cpm_uart_console_write(struct console *co, const char *s, 1373 u_int count) 1374 { 1375 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; 1376 unsigned long flags; 1377 1378 if (unlikely(oops_in_progress)) { 1379 local_irq_save(flags); 1380 cpm_uart_early_write(pinfo, s, count, true); 1381 local_irq_restore(flags); 1382 } else { 1383 uart_port_lock_irqsave(&pinfo->port, &flags); 1384 cpm_uart_early_write(pinfo, s, count, true); 1385 uart_port_unlock_irqrestore(&pinfo->port, flags); 1386 } 1387 } 1388 1389 1390 static int __init cpm_uart_console_setup(struct console *co, char *options) 1391 { 1392 int baud = 38400; 1393 int bits = 8; 1394 int parity = 'n'; 1395 int flow = 'n'; 1396 int ret; 1397 struct uart_cpm_port *pinfo; 1398 struct uart_port *port; 1399 1400 struct device_node *np; 1401 int i = 0; 1402 1403 if (co->index >= UART_NR) { 1404 printk(KERN_ERR "cpm_uart: console index %d too high\n", 1405 co->index); 1406 return -ENODEV; 1407 } 1408 1409 for_each_node_by_type(np, "serial") { 1410 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && 1411 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && 1412 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && 1413 !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) 1414 continue; 1415 1416 if (i++ == co->index) 1417 break; 1418 } 1419 1420 if (!np) 1421 return -ENODEV; 1422 1423 pinfo = &cpm_uart_ports[co->index]; 1424 1425 pinfo->flags |= FLAG_CONSOLE; 1426 port = &pinfo->port; 1427 1428 ret = cpm_uart_init_port(np, pinfo); 1429 of_node_put(np); 1430 if (ret) 1431 return ret; 1432 1433 if (options) { 1434 uart_parse_options(options, &baud, &parity, &bits, &flow); 1435 } else { 1436 baud = get_baudrate(); 1437 if (baud == -1) 1438 baud = 9600; 1439 } 1440 1441 if (IS_SMC(pinfo)) { 1442 out_be16(&pinfo->smcup->smc_brkcr, 0); 1443 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 1444 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 1445 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 1446 } else { 1447 out_be16(&pinfo->sccup->scc_brkcr, 0); 1448 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 1449 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 1450 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 1451 } 1452 1453 ret = cpm_uart_allocbuf(pinfo, 1); 1454 1455 if (ret) 1456 return ret; 1457 1458 cpm_uart_initbd(pinfo); 1459 1460 if (IS_SMC(pinfo)) 1461 cpm_uart_init_smc(pinfo); 1462 else 1463 cpm_uart_init_scc(pinfo); 1464 1465 uart_set_options(port, co, baud, parity, bits, flow); 1466 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 1467 1468 #ifdef CONFIG_CONSOLE_POLL 1469 if (!udbg_port) { 1470 udbg_port = &pinfo->port; 1471 udbg_putc = udbg_cpm_putc; 1472 udbg_getc = udbg_cpm_getc; 1473 udbg_getc_poll = udbg_cpm_getc_poll; 1474 } 1475 #endif 1476 1477 return 0; 1478 } 1479 1480 static struct uart_driver cpm_reg; 1481 static struct console cpm_scc_uart_console = { 1482 .name = "ttyCPM", 1483 .write = cpm_uart_console_write, 1484 .device = uart_console_device, 1485 .setup = cpm_uart_console_setup, 1486 .flags = CON_PRINTBUFFER, 1487 .index = -1, 1488 .data = &cpm_reg, 1489 }; 1490 1491 static int __init cpm_uart_console_init(void) 1492 { 1493 cpm_muram_init(); 1494 register_console(&cpm_scc_uart_console); 1495 return 0; 1496 } 1497 1498 console_initcall(cpm_uart_console_init); 1499 1500 #define CPM_UART_CONSOLE &cpm_scc_uart_console 1501 #else 1502 #define CPM_UART_CONSOLE NULL 1503 #endif 1504 1505 static struct uart_driver cpm_reg = { 1506 .owner = THIS_MODULE, 1507 .driver_name = "ttyCPM", 1508 .dev_name = "ttyCPM", 1509 .major = SERIAL_CPM_MAJOR, 1510 .minor = SERIAL_CPM_MINOR, 1511 .cons = CPM_UART_CONSOLE, 1512 .nr = UART_NR, 1513 }; 1514 1515 static int probe_index; 1516 1517 static int cpm_uart_probe(struct platform_device *ofdev) 1518 { 1519 int index = probe_index++; 1520 struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; 1521 int ret; 1522 1523 pinfo->port.line = index; 1524 1525 if (index >= UART_NR) 1526 return -ENODEV; 1527 1528 platform_set_drvdata(ofdev, pinfo); 1529 1530 /* initialize the device pointer for the port */ 1531 pinfo->port.dev = &ofdev->dev; 1532 1533 pinfo->port.irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1534 if (!pinfo->port.irq) 1535 return -EINVAL; 1536 1537 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); 1538 if (!ret) 1539 return uart_add_one_port(&cpm_reg, &pinfo->port); 1540 1541 irq_dispose_mapping(pinfo->port.irq); 1542 1543 return ret; 1544 } 1545 1546 static void cpm_uart_remove(struct platform_device *ofdev) 1547 { 1548 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev); 1549 1550 uart_remove_one_port(&cpm_reg, &pinfo->port); 1551 } 1552 1553 static const struct of_device_id cpm_uart_match[] = { 1554 { 1555 .compatible = "fsl,cpm1-smc-uart", 1556 }, 1557 { 1558 .compatible = "fsl,cpm1-scc-uart", 1559 }, 1560 { 1561 .compatible = "fsl,cpm2-smc-uart", 1562 }, 1563 { 1564 .compatible = "fsl,cpm2-scc-uart", 1565 }, 1566 {} 1567 }; 1568 MODULE_DEVICE_TABLE(of, cpm_uart_match); 1569 1570 static struct platform_driver cpm_uart_driver = { 1571 .driver = { 1572 .name = "cpm_uart", 1573 .of_match_table = cpm_uart_match, 1574 }, 1575 .probe = cpm_uart_probe, 1576 .remove_new = cpm_uart_remove, 1577 }; 1578 1579 static int __init cpm_uart_init(void) 1580 { 1581 int ret = uart_register_driver(&cpm_reg); 1582 if (ret) 1583 return ret; 1584 1585 ret = platform_driver_register(&cpm_uart_driver); 1586 if (ret) 1587 uart_unregister_driver(&cpm_reg); 1588 1589 return ret; 1590 } 1591 1592 static void __exit cpm_uart_exit(void) 1593 { 1594 platform_driver_unregister(&cpm_uart_driver); 1595 uart_unregister_driver(&cpm_reg); 1596 } 1597 1598 module_init(cpm_uart_init); 1599 module_exit(cpm_uart_exit); 1600 1601 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); 1602 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); 1603 MODULE_LICENSE("GPL"); 1604 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); 1605