1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for CPM (SCC/SMC) serial ports; core driver 4 * 5 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek 6 * Based on ppc8xx.c by Thomas Gleixner 7 * Based on drivers/serial/amba.c by Russell King 8 * 9 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) 10 * Pantelis Antoniou (panto@intracom.gr) (CPM1) 11 * 12 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. 13 * (C) 2004 Intracom, S.A. 14 * (C) 2005-2006 MontaVista Software, Inc. 15 * Vitaly Bordug <vbordug@ru.mvista.com> 16 */ 17 18 #include <linux/module.h> 19 #include <linux/tty.h> 20 #include <linux/tty_flip.h> 21 #include <linux/ioport.h> 22 #include <linux/init.h> 23 #include <linux/serial.h> 24 #include <linux/console.h> 25 #include <linux/sysrq.h> 26 #include <linux/device.h> 27 #include <linux/memblock.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/of_address.h> 30 #include <linux/of_platform.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/clk.h> 33 34 #include <sysdev/fsl_soc.h> 35 36 #include <asm/io.h> 37 #include <asm/irq.h> 38 #include <asm/delay.h> 39 #include <asm/udbg.h> 40 41 #include <linux/serial_core.h> 42 #include <linux/kernel.h> 43 44 #include "cpm_uart.h" 45 46 47 /**************************************************************/ 48 49 static int cpm_uart_tx_pump(struct uart_port *port); 50 static void cpm_uart_initbd(struct uart_cpm_port *pinfo); 51 52 /**************************************************************/ 53 54 #define HW_BUF_SPD_THRESHOLD 2400 55 56 static void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd) 57 { 58 cpm_command(port->command, cmd); 59 } 60 61 /* 62 * Check, if transmit buffers are processed 63 */ 64 static unsigned int cpm_uart_tx_empty(struct uart_port *port) 65 { 66 struct uart_cpm_port *pinfo = 67 container_of(port, struct uart_cpm_port, port); 68 cbd_t __iomem *bdp = pinfo->tx_bd_base; 69 int ret = 0; 70 71 while (1) { 72 if (in_be16(&bdp->cbd_sc) & BD_SC_READY) 73 break; 74 75 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { 76 ret = TIOCSER_TEMT; 77 break; 78 } 79 bdp++; 80 } 81 82 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); 83 84 return ret; 85 } 86 87 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 88 { 89 struct uart_cpm_port *pinfo = 90 container_of(port, struct uart_cpm_port, port); 91 92 if (pinfo->gpios[GPIO_RTS]) 93 gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); 94 95 if (pinfo->gpios[GPIO_DTR]) 96 gpiod_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); 97 } 98 99 static unsigned int cpm_uart_get_mctrl(struct uart_port *port) 100 { 101 struct uart_cpm_port *pinfo = 102 container_of(port, struct uart_cpm_port, port); 103 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 104 105 if (pinfo->gpios[GPIO_CTS]) { 106 if (gpiod_get_value(pinfo->gpios[GPIO_CTS])) 107 mctrl &= ~TIOCM_CTS; 108 } 109 110 if (pinfo->gpios[GPIO_DSR]) { 111 if (gpiod_get_value(pinfo->gpios[GPIO_DSR])) 112 mctrl &= ~TIOCM_DSR; 113 } 114 115 if (pinfo->gpios[GPIO_DCD]) { 116 if (gpiod_get_value(pinfo->gpios[GPIO_DCD])) 117 mctrl &= ~TIOCM_CAR; 118 } 119 120 if (pinfo->gpios[GPIO_RI]) { 121 if (!gpiod_get_value(pinfo->gpios[GPIO_RI])) 122 mctrl |= TIOCM_RNG; 123 } 124 125 return mctrl; 126 } 127 128 /* 129 * Stop transmitter 130 */ 131 static void cpm_uart_stop_tx(struct uart_port *port) 132 { 133 struct uart_cpm_port *pinfo = 134 container_of(port, struct uart_cpm_port, port); 135 smc_t __iomem *smcp = pinfo->smcp; 136 scc_t __iomem *sccp = pinfo->sccp; 137 138 pr_debug("CPM uart[%d]:stop tx\n", port->line); 139 140 if (IS_SMC(pinfo)) 141 clrbits8(&smcp->smc_smcm, SMCM_TX); 142 else 143 clrbits16(&sccp->scc_sccm, UART_SCCM_TX); 144 } 145 146 /* 147 * Start transmitter 148 */ 149 static void cpm_uart_start_tx(struct uart_port *port) 150 { 151 struct uart_cpm_port *pinfo = 152 container_of(port, struct uart_cpm_port, port); 153 smc_t __iomem *smcp = pinfo->smcp; 154 scc_t __iomem *sccp = pinfo->sccp; 155 156 pr_debug("CPM uart[%d]:start tx\n", port->line); 157 158 if (IS_SMC(pinfo)) { 159 if (in_8(&smcp->smc_smcm) & SMCM_TX) 160 return; 161 } else { 162 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) 163 return; 164 } 165 166 if (cpm_uart_tx_pump(port) != 0) { 167 if (IS_SMC(pinfo)) { 168 setbits8(&smcp->smc_smcm, SMCM_TX); 169 } else { 170 setbits16(&sccp->scc_sccm, UART_SCCM_TX); 171 } 172 } 173 } 174 175 /* 176 * Stop receiver 177 */ 178 static void cpm_uart_stop_rx(struct uart_port *port) 179 { 180 struct uart_cpm_port *pinfo = 181 container_of(port, struct uart_cpm_port, port); 182 smc_t __iomem *smcp = pinfo->smcp; 183 scc_t __iomem *sccp = pinfo->sccp; 184 185 pr_debug("CPM uart[%d]:stop rx\n", port->line); 186 187 if (IS_SMC(pinfo)) 188 clrbits8(&smcp->smc_smcm, SMCM_RX); 189 else 190 clrbits16(&sccp->scc_sccm, UART_SCCM_RX); 191 } 192 193 /* 194 * Generate a break. 195 */ 196 static void cpm_uart_break_ctl(struct uart_port *port, int break_state) 197 { 198 struct uart_cpm_port *pinfo = 199 container_of(port, struct uart_cpm_port, port); 200 201 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, 202 break_state); 203 204 if (break_state) 205 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 206 else 207 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 208 } 209 210 /* 211 * Transmit characters, refill buffer descriptor, if possible 212 */ 213 static void cpm_uart_int_tx(struct uart_port *port) 214 { 215 pr_debug("CPM uart[%d]:TX INT\n", port->line); 216 217 cpm_uart_tx_pump(port); 218 } 219 220 #ifdef CONFIG_CONSOLE_POLL 221 static int serial_polled; 222 #endif 223 224 /* 225 * Receive characters 226 */ 227 static void cpm_uart_int_rx(struct uart_port *port) 228 { 229 int i; 230 unsigned char ch; 231 u8 *cp; 232 struct tty_port *tport = &port->state->port; 233 struct uart_cpm_port *pinfo = 234 container_of(port, struct uart_cpm_port, port); 235 cbd_t __iomem *bdp; 236 u16 status; 237 unsigned int flg; 238 239 pr_debug("CPM uart[%d]:RX INT\n", port->line); 240 241 /* Just loop through the closed BDs and copy the characters into 242 * the buffer. 243 */ 244 bdp = pinfo->rx_cur; 245 for (;;) { 246 #ifdef CONFIG_CONSOLE_POLL 247 if (unlikely(serial_polled)) { 248 serial_polled = 0; 249 return; 250 } 251 #endif 252 /* get status */ 253 status = in_be16(&bdp->cbd_sc); 254 /* If this one is empty, return happy */ 255 if (status & BD_SC_EMPTY) 256 break; 257 258 /* get number of characters, and check spce in flip-buffer */ 259 i = in_be16(&bdp->cbd_datlen); 260 261 /* If we have not enough room in tty flip buffer, then we try 262 * later, which will be the next rx-interrupt or a timeout 263 */ 264 if (tty_buffer_request_room(tport, i) < i) { 265 printk(KERN_WARNING "No room in flip buffer\n"); 266 return; 267 } 268 269 /* get pointer */ 270 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 271 272 /* loop through the buffer */ 273 while (i-- > 0) { 274 ch = *cp++; 275 port->icount.rx++; 276 flg = TTY_NORMAL; 277 278 if (status & 279 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 280 goto handle_error; 281 if (uart_handle_sysrq_char(port, ch)) 282 continue; 283 #ifdef CONFIG_CONSOLE_POLL 284 if (unlikely(serial_polled)) { 285 serial_polled = 0; 286 return; 287 } 288 #endif 289 error_return: 290 tty_insert_flip_char(tport, ch, flg); 291 292 } /* End while (i--) */ 293 294 /* This BD is ready to be used again. Clear status. get next */ 295 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | 296 BD_SC_OV | BD_SC_ID); 297 setbits16(&bdp->cbd_sc, BD_SC_EMPTY); 298 299 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 300 bdp = pinfo->rx_bd_base; 301 else 302 bdp++; 303 304 } /* End for (;;) */ 305 306 /* Write back buffer pointer */ 307 pinfo->rx_cur = bdp; 308 309 /* activate BH processing */ 310 tty_flip_buffer_push(tport); 311 312 return; 313 314 /* Error processing */ 315 316 handle_error: 317 /* Statistics */ 318 if (status & BD_SC_BR) 319 port->icount.brk++; 320 if (status & BD_SC_PR) 321 port->icount.parity++; 322 if (status & BD_SC_FR) 323 port->icount.frame++; 324 if (status & BD_SC_OV) 325 port->icount.overrun++; 326 327 /* Mask out ignored conditions */ 328 status &= port->read_status_mask; 329 330 /* Handle the remaining ones */ 331 if (status & BD_SC_BR) 332 flg = TTY_BREAK; 333 else if (status & BD_SC_PR) 334 flg = TTY_PARITY; 335 else if (status & BD_SC_FR) 336 flg = TTY_FRAME; 337 338 /* overrun does not affect the current character ! */ 339 if (status & BD_SC_OV) { 340 ch = 0; 341 flg = TTY_OVERRUN; 342 /* We skip this buffer */ 343 /* CHECK: Is really nothing senseful there */ 344 /* ASSUMPTION: it contains nothing valid */ 345 i = 0; 346 } 347 port->sysrq = 0; 348 goto error_return; 349 } 350 351 /* 352 * Asynchron mode interrupt handler 353 */ 354 static irqreturn_t cpm_uart_int(int irq, void *data) 355 { 356 u8 events; 357 struct uart_port *port = data; 358 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 359 smc_t __iomem *smcp = pinfo->smcp; 360 scc_t __iomem *sccp = pinfo->sccp; 361 362 pr_debug("CPM uart[%d]:IRQ\n", port->line); 363 364 if (IS_SMC(pinfo)) { 365 events = in_8(&smcp->smc_smce); 366 out_8(&smcp->smc_smce, events); 367 if (events & SMCM_BRKE) 368 uart_handle_break(port); 369 if (events & SMCM_RX) 370 cpm_uart_int_rx(port); 371 if (events & SMCM_TX) 372 cpm_uart_int_tx(port); 373 } else { 374 events = in_be16(&sccp->scc_scce); 375 out_be16(&sccp->scc_scce, events); 376 if (events & UART_SCCM_BRKE) 377 uart_handle_break(port); 378 if (events & UART_SCCM_RX) 379 cpm_uart_int_rx(port); 380 if (events & UART_SCCM_TX) 381 cpm_uart_int_tx(port); 382 } 383 return (events) ? IRQ_HANDLED : IRQ_NONE; 384 } 385 386 static int cpm_uart_startup(struct uart_port *port) 387 { 388 int retval; 389 struct uart_cpm_port *pinfo = 390 container_of(port, struct uart_cpm_port, port); 391 392 pr_debug("CPM uart[%d]:startup\n", port->line); 393 394 /* If the port is not the console, make sure rx is disabled. */ 395 if (!(pinfo->flags & FLAG_CONSOLE)) { 396 /* Disable UART rx */ 397 if (IS_SMC(pinfo)) { 398 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); 399 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 400 } else { 401 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); 402 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 403 } 404 cpm_uart_initbd(pinfo); 405 if (IS_SMC(pinfo)) { 406 out_be32(&pinfo->smcup->smc_rstate, 0); 407 out_be32(&pinfo->smcup->smc_tstate, 0); 408 out_be16(&pinfo->smcup->smc_rbptr, 409 in_be16(&pinfo->smcup->smc_rbase)); 410 out_be16(&pinfo->smcup->smc_tbptr, 411 in_be16(&pinfo->smcup->smc_tbase)); 412 } else { 413 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 414 } 415 } 416 /* Install interrupt handler. */ 417 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); 418 if (retval) 419 return retval; 420 421 /* Startup rx-int */ 422 if (IS_SMC(pinfo)) { 423 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 424 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); 425 } else { 426 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 427 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); 428 } 429 430 return 0; 431 } 432 433 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) 434 { 435 set_current_state(TASK_UNINTERRUPTIBLE); 436 schedule_timeout(pinfo->wait_closing); 437 } 438 439 /* 440 * Shutdown the uart 441 */ 442 static void cpm_uart_shutdown(struct uart_port *port) 443 { 444 struct uart_cpm_port *pinfo = 445 container_of(port, struct uart_cpm_port, port); 446 447 pr_debug("CPM uart[%d]:shutdown\n", port->line); 448 449 /* free interrupt handler */ 450 free_irq(port->irq, port); 451 452 /* If the port is not the console, disable Rx and Tx. */ 453 if (!(pinfo->flags & FLAG_CONSOLE)) { 454 /* Wait for all the BDs marked sent */ 455 while(!cpm_uart_tx_empty(port)) { 456 set_current_state(TASK_UNINTERRUPTIBLE); 457 schedule_timeout(2); 458 } 459 460 if (pinfo->wait_closing) 461 cpm_uart_wait_until_send(pinfo); 462 463 /* Stop uarts */ 464 if (IS_SMC(pinfo)) { 465 smc_t __iomem *smcp = pinfo->smcp; 466 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 467 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); 468 } else { 469 scc_t __iomem *sccp = pinfo->sccp; 470 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 471 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 472 } 473 474 /* Shut them really down and reinit buffer descriptors */ 475 if (IS_SMC(pinfo)) { 476 out_be16(&pinfo->smcup->smc_brkcr, 0); 477 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 478 } else { 479 out_be16(&pinfo->sccup->scc_brkcr, 0); 480 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 481 } 482 483 cpm_uart_initbd(pinfo); 484 } 485 } 486 487 static void cpm_uart_set_termios(struct uart_port *port, 488 struct ktermios *termios, 489 const struct ktermios *old) 490 { 491 int baud; 492 unsigned long flags; 493 u16 cval, scval, prev_mode; 494 struct uart_cpm_port *pinfo = 495 container_of(port, struct uart_cpm_port, port); 496 smc_t __iomem *smcp = pinfo->smcp; 497 scc_t __iomem *sccp = pinfo->sccp; 498 int maxidl; 499 500 pr_debug("CPM uart[%d]:set_termios\n", port->line); 501 502 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 503 if (baud < HW_BUF_SPD_THRESHOLD || port->flags & UPF_LOW_LATENCY) 504 pinfo->rx_fifosize = 1; 505 else 506 pinfo->rx_fifosize = RX_BUF_SIZE; 507 508 /* MAXIDL is the timeout after which a receive buffer is closed 509 * when not full if no more characters are received. 510 * We calculate it from the baudrate so that the duration is 511 * always the same at standard rates: about 4ms. 512 */ 513 maxidl = baud / 2400; 514 if (maxidl < 1) 515 maxidl = 1; 516 if (maxidl > 0x10) 517 maxidl = 0x10; 518 519 cval = 0; 520 scval = 0; 521 522 if (termios->c_cflag & CSTOPB) { 523 cval |= SMCMR_SL; /* Two stops */ 524 scval |= SCU_PSMR_SL; 525 } 526 527 if (termios->c_cflag & PARENB) { 528 cval |= SMCMR_PEN; 529 scval |= SCU_PSMR_PEN; 530 if (!(termios->c_cflag & PARODD)) { 531 cval |= SMCMR_PM_EVEN; 532 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); 533 } 534 } 535 536 /* 537 * Update the timeout 538 */ 539 uart_update_timeout(port, termios->c_cflag, baud); 540 541 /* 542 * Set up parity check flag 543 */ 544 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); 545 if (termios->c_iflag & INPCK) 546 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 547 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) 548 port->read_status_mask |= BD_SC_BR; 549 550 /* 551 * Characters to ignore 552 */ 553 port->ignore_status_mask = 0; 554 if (termios->c_iflag & IGNPAR) 555 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 556 if (termios->c_iflag & IGNBRK) { 557 port->ignore_status_mask |= BD_SC_BR; 558 /* 559 * If we're ignore parity and break indicators, ignore 560 * overruns too. (For real raw support). 561 */ 562 if (termios->c_iflag & IGNPAR) 563 port->ignore_status_mask |= BD_SC_OV; 564 } 565 /* 566 * !!! ignore all characters if CREAD is not set 567 */ 568 if ((termios->c_cflag & CREAD) == 0) 569 port->read_status_mask &= ~BD_SC_EMPTY; 570 571 uart_port_lock_irqsave(port, &flags); 572 573 if (IS_SMC(pinfo)) { 574 unsigned int bits = tty_get_frame_size(termios->c_cflag); 575 576 /* 577 * MRBLR can be changed while an SMC/SCC is operating only 578 * if it is done in a single bus cycle with one 16-bit move 579 * (not two 8-bit bus cycles back-to-back). This occurs when 580 * the cp shifts control to the next RxBD, so the change does 581 * not take effect immediately. To guarantee the exact RxBD 582 * on which the change occurs, change MRBLR only while the 583 * SMC/SCC receiver is disabled. 584 */ 585 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); 586 out_be16(&pinfo->smcup->smc_maxidl, maxidl); 587 588 /* Set the mode register. We want to keep a copy of the 589 * enables, because we want to put them back if they were 590 * present. 591 */ 592 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); 593 /* Output in *one* operation, so we don't interrupt RX/TX if they 594 * were already enabled. 595 * Character length programmed into the register is frame bits minus 1. 596 */ 597 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits - 1) | cval | 598 SMCMR_SM_UART | prev_mode); 599 } else { 600 unsigned int bits = tty_get_char_size(termios->c_cflag); 601 602 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 603 out_be16(&pinfo->sccup->scc_maxidl, maxidl); 604 out_be16(&sccp->scc_psmr, (UART_LCR_WLEN(bits) << 12) | scval); 605 } 606 607 if (pinfo->clk) 608 clk_set_rate(pinfo->clk, baud); 609 else 610 cpm_setbrg(pinfo->brg - 1, baud); 611 uart_port_unlock_irqrestore(port, flags); 612 } 613 614 static const char *cpm_uart_type(struct uart_port *port) 615 { 616 pr_debug("CPM uart[%d]:uart_type\n", port->line); 617 618 return port->type == PORT_CPM ? "CPM UART" : NULL; 619 } 620 621 /* 622 * verify the new serial_struct (for TIOCSSERIAL). 623 */ 624 static int cpm_uart_verify_port(struct uart_port *port, 625 struct serial_struct *ser) 626 { 627 int ret = 0; 628 629 pr_debug("CPM uart[%d]:verify_port\n", port->line); 630 631 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 632 ret = -EINVAL; 633 if (ser->irq < 0 || ser->irq >= irq_get_nr_irqs()) 634 ret = -EINVAL; 635 if (ser->baud_base < 9600) 636 ret = -EINVAL; 637 return ret; 638 } 639 640 /* 641 * Transmit characters, refill buffer descriptor, if possible 642 */ 643 static int cpm_uart_tx_pump(struct uart_port *port) 644 { 645 cbd_t __iomem *bdp; 646 u8 *p; 647 int count; 648 struct uart_cpm_port *pinfo = 649 container_of(port, struct uart_cpm_port, port); 650 struct tty_port *tport = &port->state->port; 651 652 /* Handle xon/xoff */ 653 if (port->x_char) { 654 /* Pick next descriptor and fill from buffer */ 655 bdp = pinfo->tx_cur; 656 657 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 658 659 *p++ = port->x_char; 660 661 out_be16(&bdp->cbd_datlen, 1); 662 setbits16(&bdp->cbd_sc, BD_SC_READY); 663 /* Get next BD. */ 664 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 665 bdp = pinfo->tx_bd_base; 666 else 667 bdp++; 668 pinfo->tx_cur = bdp; 669 670 port->icount.tx++; 671 port->x_char = 0; 672 return 1; 673 } 674 675 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) { 676 cpm_uart_stop_tx(port); 677 return 0; 678 } 679 680 /* Pick next descriptor and fill from buffer */ 681 bdp = pinfo->tx_cur; 682 683 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && 684 !kfifo_is_empty(&tport->xmit_fifo)) { 685 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 686 count = uart_fifo_out(port, p, pinfo->tx_fifosize); 687 out_be16(&bdp->cbd_datlen, count); 688 setbits16(&bdp->cbd_sc, BD_SC_READY); 689 /* Get next BD. */ 690 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 691 bdp = pinfo->tx_bd_base; 692 else 693 bdp++; 694 } 695 pinfo->tx_cur = bdp; 696 697 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 698 uart_write_wakeup(port); 699 700 if (kfifo_is_empty(&tport->xmit_fifo)) { 701 cpm_uart_stop_tx(port); 702 return 0; 703 } 704 705 return 1; 706 } 707 708 /* 709 * init buffer descriptors 710 */ 711 static void cpm_uart_initbd(struct uart_cpm_port *pinfo) 712 { 713 int i; 714 u8 *mem_addr; 715 cbd_t __iomem *bdp; 716 717 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); 718 719 /* Set the physical address of the host memory 720 * buffers in the buffer descriptors, and the 721 * virtual address for us to work with. 722 */ 723 mem_addr = pinfo->mem_addr; 724 bdp = pinfo->rx_cur = pinfo->rx_bd_base; 725 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { 726 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 727 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 728 mem_addr += pinfo->rx_fifosize; 729 } 730 731 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 732 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); 733 734 /* Set the physical address of the host memory 735 * buffers in the buffer descriptors, and the 736 * virtual address for us to work with. 737 */ 738 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); 739 bdp = pinfo->tx_cur = pinfo->tx_bd_base; 740 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { 741 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 742 out_be16(&bdp->cbd_sc, BD_SC_INTRPT); 743 mem_addr += pinfo->tx_fifosize; 744 } 745 746 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 747 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); 748 } 749 750 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) 751 { 752 scc_t __iomem *scp; 753 scc_uart_t __iomem *sup; 754 755 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); 756 757 scp = pinfo->sccp; 758 sup = pinfo->sccup; 759 760 /* Store address */ 761 out_be16(&pinfo->sccup->scc_genscc.scc_rbase, 762 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 763 out_be16(&pinfo->sccup->scc_genscc.scc_tbase, 764 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 765 766 /* Set up the uart parameters in the 767 * parameter ram. 768 */ 769 770 out_8(&sup->scc_genscc.scc_rfcr, CPMFCR_GBL | CPMFCR_EB); 771 out_8(&sup->scc_genscc.scc_tfcr, CPMFCR_GBL | CPMFCR_EB); 772 773 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 774 out_be16(&sup->scc_maxidl, 0x10); 775 out_be16(&sup->scc_brkcr, 1); 776 out_be16(&sup->scc_parec, 0); 777 out_be16(&sup->scc_frmec, 0); 778 out_be16(&sup->scc_nosec, 0); 779 out_be16(&sup->scc_brkec, 0); 780 out_be16(&sup->scc_uaddr1, 0); 781 out_be16(&sup->scc_uaddr2, 0); 782 out_be16(&sup->scc_toseq, 0); 783 out_be16(&sup->scc_char1, 0x8000); 784 out_be16(&sup->scc_char2, 0x8000); 785 out_be16(&sup->scc_char3, 0x8000); 786 out_be16(&sup->scc_char4, 0x8000); 787 out_be16(&sup->scc_char5, 0x8000); 788 out_be16(&sup->scc_char6, 0x8000); 789 out_be16(&sup->scc_char7, 0x8000); 790 out_be16(&sup->scc_char8, 0x8000); 791 out_be16(&sup->scc_rccm, 0xc0ff); 792 793 /* Send the CPM an initialize command. 794 */ 795 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 796 797 /* Set UART mode, 8 bit, no parity, one stop. 798 * Enable receive and transmit. 799 */ 800 out_be32(&scp->scc_gsmrh, 0); 801 out_be32(&scp->scc_gsmrl, 802 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); 803 804 /* Enable rx interrupts and clear all pending events. */ 805 out_be16(&scp->scc_sccm, 0); 806 out_be16(&scp->scc_scce, 0xffff); 807 out_be16(&scp->scc_dsr, 0x7e7e); 808 out_be16(&scp->scc_psmr, 0x3000); 809 810 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 811 } 812 813 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) 814 { 815 smc_t __iomem *sp; 816 smc_uart_t __iomem *up; 817 818 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); 819 820 sp = pinfo->smcp; 821 up = pinfo->smcup; 822 823 /* Store address */ 824 out_be16(&pinfo->smcup->smc_rbase, 825 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 826 out_be16(&pinfo->smcup->smc_tbase, 827 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 828 829 /* 830 * In case SMC is being relocated... 831 */ 832 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); 833 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); 834 out_be32(&up->smc_rstate, 0); 835 out_be32(&up->smc_tstate, 0); 836 out_be16(&up->smc_brkcr, 1); /* number of break chars */ 837 out_be16(&up->smc_brkec, 0); 838 839 /* Set up the uart parameters in the 840 * parameter ram. 841 */ 842 out_8(&up->smc_rfcr, CPMFCR_GBL | CPMFCR_EB); 843 out_8(&up->smc_tfcr, CPMFCR_GBL | CPMFCR_EB); 844 845 /* Using idle character time requires some additional tuning. */ 846 out_be16(&up->smc_mrblr, pinfo->rx_fifosize); 847 out_be16(&up->smc_maxidl, 0x10); 848 out_be16(&up->smc_brklen, 0); 849 out_be16(&up->smc_brkec, 0); 850 out_be16(&up->smc_brkcr, 1); 851 852 /* Set UART mode, 8 bit, no parity, one stop. 853 * Enable receive and transmit. 854 */ 855 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); 856 857 /* Enable only rx interrupts clear all pending events. */ 858 out_8(&sp->smc_smcm, 0); 859 out_8(&sp->smc_smce, 0xff); 860 861 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 862 } 863 864 /* 865 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and 866 * receive buffer descriptors from dual port ram, and a character 867 * buffer area from host mem. If we are allocating for the console we need 868 * to do it from bootmem 869 */ 870 static int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con) 871 { 872 int dpmemsz, memsz; 873 u8 __iomem *dp_mem; 874 unsigned long dp_offset; 875 u8 *mem_addr; 876 dma_addr_t dma_addr = 0; 877 878 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line); 879 880 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos); 881 dp_offset = cpm_muram_alloc(dpmemsz, 8); 882 if (IS_ERR_VALUE(dp_offset)) { 883 pr_err("%s: could not allocate buffer descriptors\n", __func__); 884 return -ENOMEM; 885 } 886 887 dp_mem = cpm_muram_addr(dp_offset); 888 889 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) + 890 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize); 891 if (IS_ENABLED(CONFIG_CPM1) && is_con) { 892 /* was hostalloc but changed cause it blows away the */ 893 /* large tlb mapping when pinning the kernel area */ 894 mem_addr = (u8 __force *)cpm_muram_addr(cpm_muram_alloc(memsz, 8)); 895 dma_addr = cpm_muram_dma((void __iomem *)mem_addr); 896 } else if (is_con) { 897 mem_addr = kzalloc(memsz, GFP_NOWAIT); 898 dma_addr = virt_to_bus(mem_addr); 899 } else { 900 mem_addr = dma_alloc_coherent(pinfo->port.dev, memsz, &dma_addr, 901 GFP_KERNEL); 902 } 903 904 if (!mem_addr) { 905 cpm_muram_free(dp_offset); 906 pr_err("%s: could not allocate coherent memory\n", __func__); 907 return -ENOMEM; 908 } 909 910 pinfo->dp_addr = dp_offset; 911 pinfo->mem_addr = mem_addr; 912 pinfo->dma_addr = dma_addr; 913 pinfo->mem_size = memsz; 914 915 pinfo->rx_buf = mem_addr; 916 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos 917 * pinfo->rx_fifosize); 918 919 pinfo->rx_bd_base = (cbd_t __iomem *)dp_mem; 920 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos; 921 922 return 0; 923 } 924 925 static void cpm_uart_freebuf(struct uart_cpm_port *pinfo) 926 { 927 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos * 928 pinfo->rx_fifosize) + 929 L1_CACHE_ALIGN(pinfo->tx_nrfifos * 930 pinfo->tx_fifosize), (void __force *)pinfo->mem_addr, 931 pinfo->dma_addr); 932 933 cpm_muram_free(pinfo->dp_addr); 934 } 935 936 /* 937 * Initialize port. This is called from early_console stuff 938 * so we have to be careful here ! 939 */ 940 static int cpm_uart_request_port(struct uart_port *port) 941 { 942 struct uart_cpm_port *pinfo = 943 container_of(port, struct uart_cpm_port, port); 944 int ret; 945 946 pr_debug("CPM uart[%d]:request port\n", port->line); 947 948 if (pinfo->flags & FLAG_CONSOLE) 949 return 0; 950 951 if (IS_SMC(pinfo)) { 952 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 953 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 954 } else { 955 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 956 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 957 } 958 959 ret = cpm_uart_allocbuf(pinfo, 0); 960 961 if (ret) 962 return ret; 963 964 cpm_uart_initbd(pinfo); 965 if (IS_SMC(pinfo)) 966 cpm_uart_init_smc(pinfo); 967 else 968 cpm_uart_init_scc(pinfo); 969 970 return 0; 971 } 972 973 static void cpm_uart_release_port(struct uart_port *port) 974 { 975 struct uart_cpm_port *pinfo = 976 container_of(port, struct uart_cpm_port, port); 977 978 if (!(pinfo->flags & FLAG_CONSOLE)) 979 cpm_uart_freebuf(pinfo); 980 } 981 982 /* 983 * Configure/autoconfigure the port. 984 */ 985 static void cpm_uart_config_port(struct uart_port *port, int flags) 986 { 987 pr_debug("CPM uart[%d]:config_port\n", port->line); 988 989 if (flags & UART_CONFIG_TYPE) { 990 port->type = PORT_CPM; 991 cpm_uart_request_port(port); 992 } 993 } 994 995 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) 996 /* 997 * Write a string to the serial port 998 * Note that this is called with interrupts already disabled 999 */ 1000 static void cpm_uart_early_write(struct uart_cpm_port *pinfo, 1001 const char *string, u_int count, bool handle_linefeed) 1002 { 1003 unsigned int i; 1004 cbd_t __iomem *bdp, *bdbase; 1005 unsigned char *cpm_outp_addr; 1006 1007 /* Get the address of the host memory buffer. 1008 */ 1009 bdp = pinfo->tx_cur; 1010 bdbase = pinfo->tx_bd_base; 1011 1012 /* 1013 * Now, do each character. This is not as bad as it looks 1014 * since this is a holding FIFO and not a transmitting FIFO. 1015 * We could add the complexity of filling the entire transmit 1016 * buffer, but we would just wait longer between accesses...... 1017 */ 1018 for (i = 0; i < count; i++, string++) { 1019 /* Wait for transmitter fifo to empty. 1020 * Ready indicates output is ready, and xmt is doing 1021 * that, not that it is ready for us to send. 1022 */ 1023 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1024 ; 1025 1026 /* Send the character out. 1027 * If the buffer address is in the CPM DPRAM, don't 1028 * convert it. 1029 */ 1030 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1031 pinfo); 1032 *cpm_outp_addr = *string; 1033 1034 out_be16(&bdp->cbd_datlen, 1); 1035 setbits16(&bdp->cbd_sc, BD_SC_READY); 1036 1037 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1038 bdp = bdbase; 1039 else 1040 bdp++; 1041 1042 /* if a LF, also do CR... */ 1043 if (handle_linefeed && *string == 10) { 1044 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1045 ; 1046 1047 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1048 pinfo); 1049 *cpm_outp_addr = 13; 1050 1051 out_be16(&bdp->cbd_datlen, 1); 1052 setbits16(&bdp->cbd_sc, BD_SC_READY); 1053 1054 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1055 bdp = bdbase; 1056 else 1057 bdp++; 1058 } 1059 } 1060 1061 /* 1062 * Finally, Wait for transmitter & holding register to empty 1063 * and restore the IER 1064 */ 1065 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1066 ; 1067 1068 pinfo->tx_cur = bdp; 1069 } 1070 #endif 1071 1072 #ifdef CONFIG_CONSOLE_POLL 1073 /* Serial polling routines for writing and reading from the uart while 1074 * in an interrupt or debug context. 1075 */ 1076 1077 #define GDB_BUF_SIZE 512 /* power of 2, please */ 1078 1079 static char poll_buf[GDB_BUF_SIZE]; 1080 static char *pollp; 1081 static int poll_chars; 1082 1083 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) 1084 { 1085 u_char c, *cp; 1086 volatile cbd_t *bdp; 1087 int i; 1088 1089 /* Get the address of the host memory buffer. 1090 */ 1091 bdp = pinfo->rx_cur; 1092 if (bdp->cbd_sc & BD_SC_EMPTY) 1093 return NO_POLL_CHAR; 1094 1095 /* If the buffer address is in the CPM DPRAM, don't 1096 * convert it. 1097 */ 1098 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); 1099 1100 if (obuf) { 1101 i = c = bdp->cbd_datlen; 1102 while (i-- > 0) 1103 *obuf++ = *cp++; 1104 } else 1105 c = *cp; 1106 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); 1107 bdp->cbd_sc |= BD_SC_EMPTY; 1108 1109 if (bdp->cbd_sc & BD_SC_WRAP) 1110 bdp = pinfo->rx_bd_base; 1111 else 1112 bdp++; 1113 pinfo->rx_cur = (cbd_t *)bdp; 1114 1115 return (int)c; 1116 } 1117 1118 static int cpm_get_poll_char(struct uart_port *port) 1119 { 1120 struct uart_cpm_port *pinfo = 1121 container_of(port, struct uart_cpm_port, port); 1122 1123 if (!serial_polled) { 1124 serial_polled = 1; 1125 poll_chars = 0; 1126 } 1127 if (poll_chars <= 0) { 1128 int ret = poll_wait_key(poll_buf, pinfo); 1129 1130 if (ret == NO_POLL_CHAR) 1131 return ret; 1132 poll_chars = ret; 1133 pollp = poll_buf; 1134 } 1135 poll_chars--; 1136 return *pollp++; 1137 } 1138 1139 static void cpm_put_poll_char(struct uart_port *port, 1140 unsigned char c) 1141 { 1142 struct uart_cpm_port *pinfo = 1143 container_of(port, struct uart_cpm_port, port); 1144 static char ch[2]; 1145 1146 ch[0] = (char)c; 1147 cpm_uart_early_write(pinfo, ch, 1, false); 1148 } 1149 1150 #ifdef CONFIG_SERIAL_CPM_CONSOLE 1151 static struct uart_port *udbg_port; 1152 1153 static void udbg_cpm_putc(char c) 1154 { 1155 if (c == '\n') 1156 cpm_put_poll_char(udbg_port, '\r'); 1157 cpm_put_poll_char(udbg_port, c); 1158 } 1159 1160 static int udbg_cpm_getc_poll(void) 1161 { 1162 int c = cpm_get_poll_char(udbg_port); 1163 1164 return c == NO_POLL_CHAR ? -1 : c; 1165 } 1166 1167 static int udbg_cpm_getc(void) 1168 { 1169 int c; 1170 1171 while ((c = udbg_cpm_getc_poll()) == -1) 1172 cpu_relax(); 1173 return c; 1174 } 1175 #endif /* CONFIG_SERIAL_CPM_CONSOLE */ 1176 1177 #endif /* CONFIG_CONSOLE_POLL */ 1178 1179 static const struct uart_ops cpm_uart_pops = { 1180 .tx_empty = cpm_uart_tx_empty, 1181 .set_mctrl = cpm_uart_set_mctrl, 1182 .get_mctrl = cpm_uart_get_mctrl, 1183 .stop_tx = cpm_uart_stop_tx, 1184 .start_tx = cpm_uart_start_tx, 1185 .stop_rx = cpm_uart_stop_rx, 1186 .break_ctl = cpm_uart_break_ctl, 1187 .startup = cpm_uart_startup, 1188 .shutdown = cpm_uart_shutdown, 1189 .set_termios = cpm_uart_set_termios, 1190 .type = cpm_uart_type, 1191 .release_port = cpm_uart_release_port, 1192 .request_port = cpm_uart_request_port, 1193 .config_port = cpm_uart_config_port, 1194 .verify_port = cpm_uart_verify_port, 1195 #ifdef CONFIG_CONSOLE_POLL 1196 .poll_get_char = cpm_get_poll_char, 1197 .poll_put_char = cpm_put_poll_char, 1198 #endif 1199 }; 1200 1201 static struct uart_cpm_port cpm_uart_ports[UART_NR]; 1202 1203 static void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port, 1204 struct device_node *np) 1205 { 1206 void __iomem *pram; 1207 unsigned long offset; 1208 struct resource res; 1209 resource_size_t len; 1210 1211 /* Don't remap parameter RAM if it has already been initialized 1212 * during console setup. 1213 */ 1214 if (IS_SMC(port) && port->smcup) 1215 return port->smcup; 1216 else if (!IS_SMC(port) && port->sccup) 1217 return port->sccup; 1218 1219 if (of_address_to_resource(np, 1, &res)) 1220 return NULL; 1221 1222 len = resource_size(&res); 1223 pram = ioremap(res.start, len); 1224 if (!pram) 1225 return NULL; 1226 1227 if (!IS_ENABLED(CONFIG_CPM2) || !IS_SMC(port)) 1228 return pram; 1229 1230 if (len != 2) { 1231 pr_warn("cpm_uart[%d]: device tree references " 1232 "SMC pram, using boot loader/wrapper pram mapping. " 1233 "Please fix your device tree to reference the pram " 1234 "base register instead.\n", 1235 port->port.line); 1236 return pram; 1237 } 1238 1239 offset = cpm_muram_alloc(64, 64); 1240 out_be16(pram, offset); 1241 iounmap(pram); 1242 return cpm_muram_addr(offset); 1243 } 1244 1245 static void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram) 1246 { 1247 if (!IS_ENABLED(CONFIG_CPM2) || !IS_SMC(port)) 1248 iounmap(pram); 1249 } 1250 1251 static int cpm_uart_init_port(struct device_node *np, 1252 struct uart_cpm_port *pinfo) 1253 { 1254 const u32 *data; 1255 void __iomem *mem, *pram; 1256 struct device *dev = pinfo->port.dev; 1257 int len; 1258 int ret; 1259 int i; 1260 1261 data = of_get_property(np, "clock", NULL); 1262 if (data) { 1263 struct clk *clk = clk_get(NULL, (const char*)data); 1264 if (!IS_ERR(clk)) 1265 pinfo->clk = clk; 1266 } 1267 if (!pinfo->clk) { 1268 data = of_get_property(np, "fsl,cpm-brg", &len); 1269 if (!data || len != 4) { 1270 printk(KERN_ERR "CPM UART %pOFn has no/invalid " 1271 "fsl,cpm-brg property.\n", np); 1272 return -EINVAL; 1273 } 1274 pinfo->brg = *data; 1275 } 1276 1277 data = of_get_property(np, "fsl,cpm-command", &len); 1278 if (!data || len != 4) { 1279 printk(KERN_ERR "CPM UART %pOFn has no/invalid " 1280 "fsl,cpm-command property.\n", np); 1281 return -EINVAL; 1282 } 1283 pinfo->command = *data; 1284 1285 mem = of_iomap(np, 0); 1286 if (!mem) 1287 return -ENOMEM; 1288 1289 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || 1290 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { 1291 pinfo->sccp = mem; 1292 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); 1293 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || 1294 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { 1295 pinfo->flags |= FLAG_SMC; 1296 pinfo->smcp = mem; 1297 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); 1298 } else { 1299 ret = -ENODEV; 1300 goto out_mem; 1301 } 1302 1303 if (!pram) { 1304 ret = -ENOMEM; 1305 goto out_mem; 1306 } 1307 1308 pinfo->tx_nrfifos = TX_NUM_FIFO; 1309 pinfo->tx_fifosize = TX_BUF_SIZE; 1310 pinfo->rx_nrfifos = RX_NUM_FIFO; 1311 pinfo->rx_fifosize = RX_BUF_SIZE; 1312 1313 pinfo->port.uartclk = ppc_proc_freq; 1314 pinfo->port.mapbase = (unsigned long)mem; 1315 pinfo->port.type = PORT_CPM; 1316 pinfo->port.ops = &cpm_uart_pops; 1317 pinfo->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CPM_CONSOLE); 1318 pinfo->port.iotype = UPIO_MEM; 1319 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; 1320 spin_lock_init(&pinfo->port.lock); 1321 1322 for (i = 0; i < NUM_GPIOS; i++) { 1323 struct gpio_desc *gpiod; 1324 1325 pinfo->gpios[i] = NULL; 1326 1327 gpiod = devm_gpiod_get_index_optional(dev, NULL, i, GPIOD_ASIS); 1328 1329 if (IS_ERR(gpiod)) { 1330 ret = PTR_ERR(gpiod); 1331 goto out_pram; 1332 } 1333 1334 if (gpiod) { 1335 if (i == GPIO_RTS || i == GPIO_DTR) 1336 ret = gpiod_direction_output(gpiod, 0); 1337 else 1338 ret = gpiod_direction_input(gpiod); 1339 if (ret) { 1340 pr_err("can't set direction for gpio #%d: %d\n", 1341 i, ret); 1342 continue; 1343 } 1344 pinfo->gpios[i] = gpiod; 1345 } 1346 } 1347 1348 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM 1349 #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_CPM_CONSOLE) 1350 if (!udbg_port) 1351 #endif 1352 udbg_putc = NULL; 1353 #endif 1354 1355 return cpm_uart_request_port(&pinfo->port); 1356 1357 out_pram: 1358 cpm_uart_unmap_pram(pinfo, pram); 1359 out_mem: 1360 iounmap(mem); 1361 return ret; 1362 } 1363 1364 #ifdef CONFIG_SERIAL_CPM_CONSOLE 1365 /* 1366 * Print a string to the serial port trying not to disturb 1367 * any possible real use of the port... 1368 * 1369 * Note that this is called with interrupts already disabled 1370 */ 1371 static void cpm_uart_console_write(struct console *co, const char *s, 1372 u_int count) 1373 { 1374 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; 1375 unsigned long flags; 1376 1377 if (unlikely(oops_in_progress)) { 1378 local_irq_save(flags); 1379 cpm_uart_early_write(pinfo, s, count, true); 1380 local_irq_restore(flags); 1381 } else { 1382 uart_port_lock_irqsave(&pinfo->port, &flags); 1383 cpm_uart_early_write(pinfo, s, count, true); 1384 uart_port_unlock_irqrestore(&pinfo->port, flags); 1385 } 1386 } 1387 1388 1389 static int __init cpm_uart_console_setup(struct console *co, char *options) 1390 { 1391 int baud = 38400; 1392 int bits = 8; 1393 int parity = 'n'; 1394 int flow = 'n'; 1395 int ret; 1396 struct uart_cpm_port *pinfo; 1397 struct uart_port *port; 1398 1399 struct device_node *np; 1400 int i = 0; 1401 1402 if (co->index >= UART_NR) { 1403 printk(KERN_ERR "cpm_uart: console index %d too high\n", 1404 co->index); 1405 return -ENODEV; 1406 } 1407 1408 for_each_node_by_type(np, "serial") { 1409 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && 1410 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && 1411 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && 1412 !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) 1413 continue; 1414 1415 if (i++ == co->index) 1416 break; 1417 } 1418 1419 if (!np) 1420 return -ENODEV; 1421 1422 pinfo = &cpm_uart_ports[co->index]; 1423 1424 pinfo->flags |= FLAG_CONSOLE; 1425 port = &pinfo->port; 1426 1427 ret = cpm_uart_init_port(np, pinfo); 1428 of_node_put(np); 1429 if (ret) 1430 return ret; 1431 1432 if (options) { 1433 uart_parse_options(options, &baud, &parity, &bits, &flow); 1434 } else { 1435 baud = get_baudrate(); 1436 if (baud == -1) 1437 baud = 9600; 1438 } 1439 1440 if (IS_SMC(pinfo)) { 1441 out_be16(&pinfo->smcup->smc_brkcr, 0); 1442 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 1443 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 1444 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 1445 } else { 1446 out_be16(&pinfo->sccup->scc_brkcr, 0); 1447 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 1448 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 1449 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 1450 } 1451 1452 ret = cpm_uart_allocbuf(pinfo, 1); 1453 1454 if (ret) 1455 return ret; 1456 1457 cpm_uart_initbd(pinfo); 1458 1459 if (IS_SMC(pinfo)) 1460 cpm_uart_init_smc(pinfo); 1461 else 1462 cpm_uart_init_scc(pinfo); 1463 1464 uart_set_options(port, co, baud, parity, bits, flow); 1465 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 1466 1467 #ifdef CONFIG_CONSOLE_POLL 1468 if (!udbg_port) { 1469 udbg_port = &pinfo->port; 1470 udbg_putc = udbg_cpm_putc; 1471 udbg_getc = udbg_cpm_getc; 1472 udbg_getc_poll = udbg_cpm_getc_poll; 1473 } 1474 #endif 1475 1476 return 0; 1477 } 1478 1479 static struct uart_driver cpm_reg; 1480 static struct console cpm_scc_uart_console = { 1481 .name = "ttyCPM", 1482 .write = cpm_uart_console_write, 1483 .device = uart_console_device, 1484 .setup = cpm_uart_console_setup, 1485 .flags = CON_PRINTBUFFER, 1486 .index = -1, 1487 .data = &cpm_reg, 1488 }; 1489 1490 static int __init cpm_uart_console_init(void) 1491 { 1492 cpm_muram_init(); 1493 register_console(&cpm_scc_uart_console); 1494 return 0; 1495 } 1496 1497 console_initcall(cpm_uart_console_init); 1498 1499 #define CPM_UART_CONSOLE &cpm_scc_uart_console 1500 #else 1501 #define CPM_UART_CONSOLE NULL 1502 #endif 1503 1504 static struct uart_driver cpm_reg = { 1505 .owner = THIS_MODULE, 1506 .driver_name = "ttyCPM", 1507 .dev_name = "ttyCPM", 1508 .major = SERIAL_CPM_MAJOR, 1509 .minor = SERIAL_CPM_MINOR, 1510 .cons = CPM_UART_CONSOLE, 1511 .nr = UART_NR, 1512 }; 1513 1514 static int probe_index; 1515 1516 static int cpm_uart_probe(struct platform_device *ofdev) 1517 { 1518 int index = probe_index++; 1519 struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; 1520 int ret; 1521 1522 pinfo->port.line = index; 1523 1524 if (index >= UART_NR) 1525 return -ENODEV; 1526 1527 platform_set_drvdata(ofdev, pinfo); 1528 1529 /* initialize the device pointer for the port */ 1530 pinfo->port.dev = &ofdev->dev; 1531 1532 pinfo->port.irq = platform_get_irq(ofdev, 0); 1533 if (pinfo->port.irq < 0) 1534 return pinfo->port.irq; 1535 1536 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); 1537 if (!ret) 1538 return uart_add_one_port(&cpm_reg, &pinfo->port); 1539 1540 return ret; 1541 } 1542 1543 static void cpm_uart_remove(struct platform_device *ofdev) 1544 { 1545 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev); 1546 1547 uart_remove_one_port(&cpm_reg, &pinfo->port); 1548 } 1549 1550 static const struct of_device_id cpm_uart_match[] = { 1551 { 1552 .compatible = "fsl,cpm1-smc-uart", 1553 }, 1554 { 1555 .compatible = "fsl,cpm1-scc-uart", 1556 }, 1557 { 1558 .compatible = "fsl,cpm2-smc-uart", 1559 }, 1560 { 1561 .compatible = "fsl,cpm2-scc-uart", 1562 }, 1563 {} 1564 }; 1565 MODULE_DEVICE_TABLE(of, cpm_uart_match); 1566 1567 static struct platform_driver cpm_uart_driver = { 1568 .driver = { 1569 .name = "cpm_uart", 1570 .of_match_table = cpm_uart_match, 1571 }, 1572 .probe = cpm_uart_probe, 1573 .remove = cpm_uart_remove, 1574 }; 1575 1576 static int __init cpm_uart_init(void) 1577 { 1578 int ret = uart_register_driver(&cpm_reg); 1579 if (ret) 1580 return ret; 1581 1582 ret = platform_driver_register(&cpm_uart_driver); 1583 if (ret) 1584 uart_unregister_driver(&cpm_reg); 1585 1586 return ret; 1587 } 1588 1589 static void __exit cpm_uart_exit(void) 1590 { 1591 platform_driver_unregister(&cpm_uart_driver); 1592 uart_unregister_driver(&cpm_reg); 1593 } 1594 1595 module_init(cpm_uart_init); 1596 module_exit(cpm_uart_exit); 1597 1598 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); 1599 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); 1600 MODULE_LICENSE("GPL"); 1601 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); 1602