xref: /linux/drivers/tty/serial/bcm63xx_uart.c (revision be709d48329a500621d2a05835283150ae137b45) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Derived from many drivers using generic_serial interface.
4  *
5  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6  *
7  *  Serial driver for BCM63xx integrated UART.
8  *
9  * Hardware flow control was _not_ tested since I only have RX/TX on
10  * my board.
11  */
12 
13 #if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
14 #define SUPPORT_SYSRQ
15 #endif
16 
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/console.h>
23 #include <linux/clk.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/sysrq.h>
27 #include <linux/serial.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial_bcm63xx.h>
30 #include <linux/io.h>
31 #include <linux/of.h>
32 
33 #define BCM63XX_NR_UARTS	2
34 
35 static struct uart_port ports[BCM63XX_NR_UARTS];
36 
37 /*
38  * rx interrupt mask / stat
39  *
40  * mask:
41  *  - rx fifo full
42  *  - rx fifo above threshold
43  *  - rx fifo not empty for too long
44  */
45 #define UART_RX_INT_MASK	(UART_IR_MASK(UART_IR_RXOVER) |		\
46 				UART_IR_MASK(UART_IR_RXTHRESH) |	\
47 				UART_IR_MASK(UART_IR_RXTIMEOUT))
48 
49 #define UART_RX_INT_STAT	(UART_IR_STAT(UART_IR_RXOVER) |		\
50 				UART_IR_STAT(UART_IR_RXTHRESH) |	\
51 				UART_IR_STAT(UART_IR_RXTIMEOUT))
52 
53 /*
54  * tx interrupt mask / stat
55  *
56  * mask:
57  * - tx fifo empty
58  * - tx fifo below threshold
59  */
60 #define UART_TX_INT_MASK	(UART_IR_MASK(UART_IR_TXEMPTY) |	\
61 				UART_IR_MASK(UART_IR_TXTRESH))
62 
63 #define UART_TX_INT_STAT	(UART_IR_STAT(UART_IR_TXEMPTY) |	\
64 				UART_IR_STAT(UART_IR_TXTRESH))
65 
66 /*
67  * external input interrupt
68  *
69  * mask: any edge on CTS, DCD
70  */
71 #define UART_EXTINP_INT_MASK	(UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
72 				 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
73 
74 /*
75  * handy uart register accessor
76  */
77 static inline unsigned int bcm_uart_readl(struct uart_port *port,
78 					 unsigned int offset)
79 {
80 	return __raw_readl(port->membase + offset);
81 }
82 
83 static inline void bcm_uart_writel(struct uart_port *port,
84 				  unsigned int value, unsigned int offset)
85 {
86 	__raw_writel(value, port->membase + offset);
87 }
88 
89 /*
90  * serial core request to check if uart tx fifo is empty
91  */
92 static unsigned int bcm_uart_tx_empty(struct uart_port *port)
93 {
94 	unsigned int val;
95 
96 	val = bcm_uart_readl(port, UART_IR_REG);
97 	return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
98 }
99 
100 /*
101  * serial core request to set RTS and DTR pin state and loopback mode
102  */
103 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
104 {
105 	unsigned int val;
106 
107 	val = bcm_uart_readl(port, UART_MCTL_REG);
108 	val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
109 	/* invert of written value is reflected on the pin */
110 	if (!(mctrl & TIOCM_DTR))
111 		val |= UART_MCTL_DTR_MASK;
112 	if (!(mctrl & TIOCM_RTS))
113 		val |= UART_MCTL_RTS_MASK;
114 	bcm_uart_writel(port, val, UART_MCTL_REG);
115 
116 	val = bcm_uart_readl(port, UART_CTL_REG);
117 	if (mctrl & TIOCM_LOOP)
118 		val |= UART_CTL_LOOPBACK_MASK;
119 	else
120 		val &= ~UART_CTL_LOOPBACK_MASK;
121 	bcm_uart_writel(port, val, UART_CTL_REG);
122 }
123 
124 /*
125  * serial core request to return RI, CTS, DCD and DSR pin state
126  */
127 static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
128 {
129 	unsigned int val, mctrl;
130 
131 	mctrl = 0;
132 	val = bcm_uart_readl(port, UART_EXTINP_REG);
133 	if (val & UART_EXTINP_RI_MASK)
134 		mctrl |= TIOCM_RI;
135 	if (val & UART_EXTINP_CTS_MASK)
136 		mctrl |= TIOCM_CTS;
137 	if (val & UART_EXTINP_DCD_MASK)
138 		mctrl |= TIOCM_CD;
139 	if (val & UART_EXTINP_DSR_MASK)
140 		mctrl |= TIOCM_DSR;
141 	return mctrl;
142 }
143 
144 /*
145  * serial core request to disable tx ASAP (used for flow control)
146  */
147 static void bcm_uart_stop_tx(struct uart_port *port)
148 {
149 	unsigned int val;
150 
151 	val = bcm_uart_readl(port, UART_CTL_REG);
152 	val &= ~(UART_CTL_TXEN_MASK);
153 	bcm_uart_writel(port, val, UART_CTL_REG);
154 
155 	val = bcm_uart_readl(port, UART_IR_REG);
156 	val &= ~UART_TX_INT_MASK;
157 	bcm_uart_writel(port, val, UART_IR_REG);
158 }
159 
160 /*
161  * serial core request to (re)enable tx
162  */
163 static void bcm_uart_start_tx(struct uart_port *port)
164 {
165 	unsigned int val;
166 
167 	val = bcm_uart_readl(port, UART_IR_REG);
168 	val |= UART_TX_INT_MASK;
169 	bcm_uart_writel(port, val, UART_IR_REG);
170 
171 	val = bcm_uart_readl(port, UART_CTL_REG);
172 	val |= UART_CTL_TXEN_MASK;
173 	bcm_uart_writel(port, val, UART_CTL_REG);
174 }
175 
176 /*
177  * serial core request to stop rx, called before port shutdown
178  */
179 static void bcm_uart_stop_rx(struct uart_port *port)
180 {
181 	unsigned int val;
182 
183 	val = bcm_uart_readl(port, UART_IR_REG);
184 	val &= ~UART_RX_INT_MASK;
185 	bcm_uart_writel(port, val, UART_IR_REG);
186 }
187 
188 /*
189  * serial core request to enable modem status interrupt reporting
190  */
191 static void bcm_uart_enable_ms(struct uart_port *port)
192 {
193 	unsigned int val;
194 
195 	val = bcm_uart_readl(port, UART_IR_REG);
196 	val |= UART_IR_MASK(UART_IR_EXTIP);
197 	bcm_uart_writel(port, val, UART_IR_REG);
198 }
199 
200 /*
201  * serial core request to start/stop emitting break char
202  */
203 static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
204 {
205 	unsigned long flags;
206 	unsigned int val;
207 
208 	spin_lock_irqsave(&port->lock, flags);
209 
210 	val = bcm_uart_readl(port, UART_CTL_REG);
211 	if (ctl)
212 		val |= UART_CTL_XMITBRK_MASK;
213 	else
214 		val &= ~UART_CTL_XMITBRK_MASK;
215 	bcm_uart_writel(port, val, UART_CTL_REG);
216 
217 	spin_unlock_irqrestore(&port->lock, flags);
218 }
219 
220 /*
221  * return port type in string format
222  */
223 static const char *bcm_uart_type(struct uart_port *port)
224 {
225 	return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
226 }
227 
228 /*
229  * read all chars in rx fifo and send them to core
230  */
231 static void bcm_uart_do_rx(struct uart_port *port)
232 {
233 	struct tty_port *tty_port = &port->state->port;
234 	unsigned int max_count;
235 
236 	/* limit number of char read in interrupt, should not be
237 	 * higher than fifo size anyway since we're much faster than
238 	 * serial port */
239 	max_count = 32;
240 	do {
241 		unsigned int iestat, c, cstat;
242 		char flag;
243 
244 		/* get overrun/fifo empty information from ier
245 		 * register */
246 		iestat = bcm_uart_readl(port, UART_IR_REG);
247 
248 		if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
249 			unsigned int val;
250 
251 			/* fifo reset is required to clear
252 			 * interrupt */
253 			val = bcm_uart_readl(port, UART_CTL_REG);
254 			val |= UART_CTL_RSTRXFIFO_MASK;
255 			bcm_uart_writel(port, val, UART_CTL_REG);
256 
257 			port->icount.overrun++;
258 			tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
259 		}
260 
261 		if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
262 			break;
263 
264 		cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
265 		port->icount.rx++;
266 		flag = TTY_NORMAL;
267 		c &= 0xff;
268 
269 		if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
270 			/* do stats first */
271 			if (cstat & UART_FIFO_BRKDET_MASK) {
272 				port->icount.brk++;
273 				if (uart_handle_break(port))
274 					continue;
275 			}
276 
277 			if (cstat & UART_FIFO_PARERR_MASK)
278 				port->icount.parity++;
279 			if (cstat & UART_FIFO_FRAMEERR_MASK)
280 				port->icount.frame++;
281 
282 			/* update flag wrt read_status_mask */
283 			cstat &= port->read_status_mask;
284 			if (cstat & UART_FIFO_BRKDET_MASK)
285 				flag = TTY_BREAK;
286 			if (cstat & UART_FIFO_FRAMEERR_MASK)
287 				flag = TTY_FRAME;
288 			if (cstat & UART_FIFO_PARERR_MASK)
289 				flag = TTY_PARITY;
290 		}
291 
292 		if (uart_handle_sysrq_char(port, c))
293 			continue;
294 
295 
296 		if ((cstat & port->ignore_status_mask) == 0)
297 			tty_insert_flip_char(tty_port, c, flag);
298 
299 	} while (--max_count);
300 
301 	spin_unlock(&port->lock);
302 	tty_flip_buffer_push(tty_port);
303 	spin_lock(&port->lock);
304 }
305 
306 /*
307  * fill tx fifo with chars to send, stop when fifo is about to be full
308  * or when all chars have been sent.
309  */
310 static void bcm_uart_do_tx(struct uart_port *port)
311 {
312 	struct circ_buf *xmit;
313 	unsigned int val, max_count;
314 
315 	if (port->x_char) {
316 		bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
317 		port->icount.tx++;
318 		port->x_char = 0;
319 		return;
320 	}
321 
322 	if (uart_tx_stopped(port)) {
323 		bcm_uart_stop_tx(port);
324 		return;
325 	}
326 
327 	xmit = &port->state->xmit;
328 	if (uart_circ_empty(xmit))
329 		goto txq_empty;
330 
331 	val = bcm_uart_readl(port, UART_MCTL_REG);
332 	val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
333 	max_count = port->fifosize - val;
334 
335 	while (max_count--) {
336 		unsigned int c;
337 
338 		c = xmit->buf[xmit->tail];
339 		bcm_uart_writel(port, c, UART_FIFO_REG);
340 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
341 		port->icount.tx++;
342 		if (uart_circ_empty(xmit))
343 			break;
344 	}
345 
346 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
347 		uart_write_wakeup(port);
348 
349 	if (uart_circ_empty(xmit))
350 		goto txq_empty;
351 	return;
352 
353 txq_empty:
354 	/* nothing to send, disable transmit interrupt */
355 	val = bcm_uart_readl(port, UART_IR_REG);
356 	val &= ~UART_TX_INT_MASK;
357 	bcm_uart_writel(port, val, UART_IR_REG);
358 	return;
359 }
360 
361 /*
362  * process uart interrupt
363  */
364 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
365 {
366 	struct uart_port *port;
367 	unsigned int irqstat;
368 
369 	port = dev_id;
370 	spin_lock(&port->lock);
371 
372 	irqstat = bcm_uart_readl(port, UART_IR_REG);
373 	if (irqstat & UART_RX_INT_STAT)
374 		bcm_uart_do_rx(port);
375 
376 	if (irqstat & UART_TX_INT_STAT)
377 		bcm_uart_do_tx(port);
378 
379 	if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
380 		unsigned int estat;
381 
382 		estat = bcm_uart_readl(port, UART_EXTINP_REG);
383 		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
384 			uart_handle_cts_change(port,
385 					       estat & UART_EXTINP_CTS_MASK);
386 		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
387 			uart_handle_dcd_change(port,
388 					       estat & UART_EXTINP_DCD_MASK);
389 	}
390 
391 	spin_unlock(&port->lock);
392 	return IRQ_HANDLED;
393 }
394 
395 /*
396  * enable rx & tx operation on uart
397  */
398 static void bcm_uart_enable(struct uart_port *port)
399 {
400 	unsigned int val;
401 
402 	val = bcm_uart_readl(port, UART_CTL_REG);
403 	val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
404 	bcm_uart_writel(port, val, UART_CTL_REG);
405 }
406 
407 /*
408  * disable rx & tx operation on uart
409  */
410 static void bcm_uart_disable(struct uart_port *port)
411 {
412 	unsigned int val;
413 
414 	val = bcm_uart_readl(port, UART_CTL_REG);
415 	val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
416 		 UART_CTL_RXEN_MASK);
417 	bcm_uart_writel(port, val, UART_CTL_REG);
418 }
419 
420 /*
421  * clear all unread data in rx fifo and unsent data in tx fifo
422  */
423 static void bcm_uart_flush(struct uart_port *port)
424 {
425 	unsigned int val;
426 
427 	/* empty rx and tx fifo */
428 	val = bcm_uart_readl(port, UART_CTL_REG);
429 	val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
430 	bcm_uart_writel(port, val, UART_CTL_REG);
431 
432 	/* read any pending char to make sure all irq status are
433 	 * cleared */
434 	(void)bcm_uart_readl(port, UART_FIFO_REG);
435 }
436 
437 /*
438  * serial core request to initialize uart and start rx operation
439  */
440 static int bcm_uart_startup(struct uart_port *port)
441 {
442 	unsigned int val;
443 	int ret;
444 
445 	/* mask all irq and flush port */
446 	bcm_uart_disable(port);
447 	bcm_uart_writel(port, 0, UART_IR_REG);
448 	bcm_uart_flush(port);
449 
450 	/* clear any pending external input interrupt */
451 	(void)bcm_uart_readl(port, UART_EXTINP_REG);
452 
453 	/* set rx/tx fifo thresh to fifo half size */
454 	val = bcm_uart_readl(port, UART_MCTL_REG);
455 	val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
456 	val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
457 	val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
458 	bcm_uart_writel(port, val, UART_MCTL_REG);
459 
460 	/* set rx fifo timeout to 1 char time */
461 	val = bcm_uart_readl(port, UART_CTL_REG);
462 	val &= ~UART_CTL_RXTMOUTCNT_MASK;
463 	val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
464 	bcm_uart_writel(port, val, UART_CTL_REG);
465 
466 	/* report any edge on dcd and cts */
467 	val = UART_EXTINP_INT_MASK;
468 	val |= UART_EXTINP_DCD_NOSENSE_MASK;
469 	val |= UART_EXTINP_CTS_NOSENSE_MASK;
470 	bcm_uart_writel(port, val, UART_EXTINP_REG);
471 
472 	/* register irq and enable rx interrupts */
473 	ret = request_irq(port->irq, bcm_uart_interrupt, 0,
474 			  dev_name(port->dev), port);
475 	if (ret)
476 		return ret;
477 	bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
478 	bcm_uart_enable(port);
479 	return 0;
480 }
481 
482 /*
483  * serial core request to flush & disable uart
484  */
485 static void bcm_uart_shutdown(struct uart_port *port)
486 {
487 	unsigned long flags;
488 
489 	spin_lock_irqsave(&port->lock, flags);
490 	bcm_uart_writel(port, 0, UART_IR_REG);
491 	spin_unlock_irqrestore(&port->lock, flags);
492 
493 	bcm_uart_disable(port);
494 	bcm_uart_flush(port);
495 	free_irq(port->irq, port);
496 }
497 
498 /*
499  * serial core request to change current uart setting
500  */
501 static void bcm_uart_set_termios(struct uart_port *port,
502 				 struct ktermios *new,
503 				 struct ktermios *old)
504 {
505 	unsigned int ctl, baud, quot, ier;
506 	unsigned long flags;
507 	int tries;
508 
509 	spin_lock_irqsave(&port->lock, flags);
510 
511 	/* Drain the hot tub fully before we power it off for the winter. */
512 	for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
513 		mdelay(10);
514 
515 	/* disable uart while changing speed */
516 	bcm_uart_disable(port);
517 	bcm_uart_flush(port);
518 
519 	/* update Control register */
520 	ctl = bcm_uart_readl(port, UART_CTL_REG);
521 	ctl &= ~UART_CTL_BITSPERSYM_MASK;
522 
523 	switch (new->c_cflag & CSIZE) {
524 	case CS5:
525 		ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
526 		break;
527 	case CS6:
528 		ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
529 		break;
530 	case CS7:
531 		ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
532 		break;
533 	default:
534 		ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
535 		break;
536 	}
537 
538 	ctl &= ~UART_CTL_STOPBITS_MASK;
539 	if (new->c_cflag & CSTOPB)
540 		ctl |= UART_CTL_STOPBITS_2;
541 	else
542 		ctl |= UART_CTL_STOPBITS_1;
543 
544 	ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
545 	if (new->c_cflag & PARENB)
546 		ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
547 	ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
548 	if (new->c_cflag & PARODD)
549 		ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
550 	bcm_uart_writel(port, ctl, UART_CTL_REG);
551 
552 	/* update Baudword register */
553 	baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
554 	quot = uart_get_divisor(port, baud) - 1;
555 	bcm_uart_writel(port, quot, UART_BAUD_REG);
556 
557 	/* update Interrupt register */
558 	ier = bcm_uart_readl(port, UART_IR_REG);
559 
560 	ier &= ~UART_IR_MASK(UART_IR_EXTIP);
561 	if (UART_ENABLE_MS(port, new->c_cflag))
562 		ier |= UART_IR_MASK(UART_IR_EXTIP);
563 
564 	bcm_uart_writel(port, ier, UART_IR_REG);
565 
566 	/* update read/ignore mask */
567 	port->read_status_mask = UART_FIFO_VALID_MASK;
568 	if (new->c_iflag & INPCK) {
569 		port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
570 		port->read_status_mask |= UART_FIFO_PARERR_MASK;
571 	}
572 	if (new->c_iflag & (IGNBRK | BRKINT))
573 		port->read_status_mask |= UART_FIFO_BRKDET_MASK;
574 
575 	port->ignore_status_mask = 0;
576 	if (new->c_iflag & IGNPAR)
577 		port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
578 	if (new->c_iflag & IGNBRK)
579 		port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
580 	if (!(new->c_cflag & CREAD))
581 		port->ignore_status_mask |= UART_FIFO_VALID_MASK;
582 
583 	uart_update_timeout(port, new->c_cflag, baud);
584 	bcm_uart_enable(port);
585 	spin_unlock_irqrestore(&port->lock, flags);
586 }
587 
588 /*
589  * serial core request to claim uart iomem
590  */
591 static int bcm_uart_request_port(struct uart_port *port)
592 {
593 	/* UARTs always present */
594 	return 0;
595 }
596 
597 /*
598  * serial core request to release uart iomem
599  */
600 static void bcm_uart_release_port(struct uart_port *port)
601 {
602 	/* Nothing to release ... */
603 }
604 
605 /*
606  * serial core request to do any port required autoconfiguration
607  */
608 static void bcm_uart_config_port(struct uart_port *port, int flags)
609 {
610 	if (flags & UART_CONFIG_TYPE) {
611 		if (bcm_uart_request_port(port))
612 			return;
613 		port->type = PORT_BCM63XX;
614 	}
615 }
616 
617 /*
618  * serial core request to check that port information in serinfo are
619  * suitable
620  */
621 static int bcm_uart_verify_port(struct uart_port *port,
622 				struct serial_struct *serinfo)
623 {
624 	if (port->type != PORT_BCM63XX)
625 		return -EINVAL;
626 	if (port->irq != serinfo->irq)
627 		return -EINVAL;
628 	if (port->iotype != serinfo->io_type)
629 		return -EINVAL;
630 	if (port->mapbase != (unsigned long)serinfo->iomem_base)
631 		return -EINVAL;
632 	return 0;
633 }
634 
635 /* serial core callbacks */
636 static const struct uart_ops bcm_uart_ops = {
637 	.tx_empty	= bcm_uart_tx_empty,
638 	.get_mctrl	= bcm_uart_get_mctrl,
639 	.set_mctrl	= bcm_uart_set_mctrl,
640 	.start_tx	= bcm_uart_start_tx,
641 	.stop_tx	= bcm_uart_stop_tx,
642 	.stop_rx	= bcm_uart_stop_rx,
643 	.enable_ms	= bcm_uart_enable_ms,
644 	.break_ctl	= bcm_uart_break_ctl,
645 	.startup	= bcm_uart_startup,
646 	.shutdown	= bcm_uart_shutdown,
647 	.set_termios	= bcm_uart_set_termios,
648 	.type		= bcm_uart_type,
649 	.release_port	= bcm_uart_release_port,
650 	.request_port	= bcm_uart_request_port,
651 	.config_port	= bcm_uart_config_port,
652 	.verify_port	= bcm_uart_verify_port,
653 };
654 
655 
656 
657 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
658 static void wait_for_xmitr(struct uart_port *port)
659 {
660 	unsigned int tmout;
661 
662 	/* Wait up to 10ms for the character(s) to be sent. */
663 	tmout = 10000;
664 	while (--tmout) {
665 		unsigned int val;
666 
667 		val = bcm_uart_readl(port, UART_IR_REG);
668 		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
669 			break;
670 		udelay(1);
671 	}
672 
673 	/* Wait up to 1s for flow control if necessary */
674 	if (port->flags & UPF_CONS_FLOW) {
675 		tmout = 1000000;
676 		while (--tmout) {
677 			unsigned int val;
678 
679 			val = bcm_uart_readl(port, UART_EXTINP_REG);
680 			if (val & UART_EXTINP_CTS_MASK)
681 				break;
682 			udelay(1);
683 		}
684 	}
685 }
686 
687 /*
688  * output given char
689  */
690 static void bcm_console_putchar(struct uart_port *port, int ch)
691 {
692 	wait_for_xmitr(port);
693 	bcm_uart_writel(port, ch, UART_FIFO_REG);
694 }
695 
696 /*
697  * console core request to output given string
698  */
699 static void bcm_console_write(struct console *co, const char *s,
700 			      unsigned int count)
701 {
702 	struct uart_port *port;
703 	unsigned long flags;
704 	int locked;
705 
706 	port = &ports[co->index];
707 
708 	local_irq_save(flags);
709 	if (port->sysrq) {
710 		/* bcm_uart_interrupt() already took the lock */
711 		locked = 0;
712 	} else if (oops_in_progress) {
713 		locked = spin_trylock(&port->lock);
714 	} else {
715 		spin_lock(&port->lock);
716 		locked = 1;
717 	}
718 
719 	/* call helper to deal with \r\n */
720 	uart_console_write(port, s, count, bcm_console_putchar);
721 
722 	/* and wait for char to be transmitted */
723 	wait_for_xmitr(port);
724 
725 	if (locked)
726 		spin_unlock(&port->lock);
727 	local_irq_restore(flags);
728 }
729 
730 /*
731  * console core request to setup given console, find matching uart
732  * port and setup it.
733  */
734 static int bcm_console_setup(struct console *co, char *options)
735 {
736 	struct uart_port *port;
737 	int baud = 9600;
738 	int bits = 8;
739 	int parity = 'n';
740 	int flow = 'n';
741 
742 	if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
743 		return -EINVAL;
744 	port = &ports[co->index];
745 	if (!port->membase)
746 		return -ENODEV;
747 	if (options)
748 		uart_parse_options(options, &baud, &parity, &bits, &flow);
749 
750 	return uart_set_options(port, co, baud, parity, bits, flow);
751 }
752 
753 static struct uart_driver bcm_uart_driver;
754 
755 static struct console bcm63xx_console = {
756 	.name		= "ttyS",
757 	.write		= bcm_console_write,
758 	.device		= uart_console_device,
759 	.setup		= bcm_console_setup,
760 	.flags		= CON_PRINTBUFFER,
761 	.index		= -1,
762 	.data		= &bcm_uart_driver,
763 };
764 
765 static int __init bcm63xx_console_init(void)
766 {
767 	register_console(&bcm63xx_console);
768 	return 0;
769 }
770 
771 console_initcall(bcm63xx_console_init);
772 
773 static void bcm_early_write(struct console *con, const char *s, unsigned n)
774 {
775 	struct earlycon_device *dev = con->data;
776 
777 	uart_console_write(&dev->port, s, n, bcm_console_putchar);
778 	wait_for_xmitr(&dev->port);
779 }
780 
781 static int __init bcm_early_console_setup(struct earlycon_device *device,
782 					  const char *opt)
783 {
784 	if (!device->port.membase)
785 		return -ENODEV;
786 
787 	device->con->write = bcm_early_write;
788 	return 0;
789 }
790 
791 OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
792 
793 #define BCM63XX_CONSOLE	(&bcm63xx_console)
794 #else
795 #define BCM63XX_CONSOLE	NULL
796 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
797 
798 static struct uart_driver bcm_uart_driver = {
799 	.owner		= THIS_MODULE,
800 	.driver_name	= "bcm63xx_uart",
801 	.dev_name	= "ttyS",
802 	.major		= TTY_MAJOR,
803 	.minor		= 64,
804 	.nr		= BCM63XX_NR_UARTS,
805 	.cons		= BCM63XX_CONSOLE,
806 };
807 
808 /*
809  * platform driver probe/remove callback
810  */
811 static int bcm_uart_probe(struct platform_device *pdev)
812 {
813 	struct resource *res_mem, *res_irq;
814 	struct uart_port *port;
815 	struct clk *clk;
816 	int ret;
817 
818 	if (pdev->dev.of_node) {
819 		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
820 
821 		if (pdev->id < 0)
822 			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
823 	}
824 
825 	if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
826 		return -EINVAL;
827 
828 	port = &ports[pdev->id];
829 	if (port->membase)
830 		return -EBUSY;
831 	memset(port, 0, sizeof(*port));
832 
833 	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
834 	if (!res_mem)
835 		return -ENODEV;
836 
837 	port->mapbase = res_mem->start;
838 	port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
839 	if (IS_ERR(port->membase))
840 		return PTR_ERR(port->membase);
841 
842 	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
843 	if (!res_irq)
844 		return -ENODEV;
845 
846 	clk = clk_get(&pdev->dev, "refclk");
847 	if (IS_ERR(clk) && pdev->dev.of_node)
848 		clk = of_clk_get(pdev->dev.of_node, 0);
849 
850 	if (IS_ERR(clk))
851 		return -ENODEV;
852 
853 	port->iotype = UPIO_MEM;
854 	port->irq = res_irq->start;
855 	port->ops = &bcm_uart_ops;
856 	port->flags = UPF_BOOT_AUTOCONF;
857 	port->dev = &pdev->dev;
858 	port->fifosize = 16;
859 	port->uartclk = clk_get_rate(clk) / 2;
860 	port->line = pdev->id;
861 	clk_put(clk);
862 
863 	ret = uart_add_one_port(&bcm_uart_driver, port);
864 	if (ret) {
865 		ports[pdev->id].membase = NULL;
866 		return ret;
867 	}
868 	platform_set_drvdata(pdev, port);
869 	return 0;
870 }
871 
872 static int bcm_uart_remove(struct platform_device *pdev)
873 {
874 	struct uart_port *port;
875 
876 	port = platform_get_drvdata(pdev);
877 	uart_remove_one_port(&bcm_uart_driver, port);
878 	/* mark port as free */
879 	ports[pdev->id].membase = NULL;
880 	return 0;
881 }
882 
883 static const struct of_device_id bcm63xx_of_match[] = {
884 	{ .compatible = "brcm,bcm6345-uart" },
885 	{ /* sentinel */ }
886 };
887 MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
888 
889 /*
890  * platform driver stuff
891  */
892 static struct platform_driver bcm_uart_platform_driver = {
893 	.probe	= bcm_uart_probe,
894 	.remove	= bcm_uart_remove,
895 	.driver	= {
896 		.name  = "bcm63xx_uart",
897 		.of_match_table = bcm63xx_of_match,
898 	},
899 };
900 
901 static int __init bcm_uart_init(void)
902 {
903 	int ret;
904 
905 	ret = uart_register_driver(&bcm_uart_driver);
906 	if (ret)
907 		return ret;
908 
909 	ret = platform_driver_register(&bcm_uart_platform_driver);
910 	if (ret)
911 		uart_unregister_driver(&bcm_uart_driver);
912 
913 	return ret;
914 }
915 
916 static void __exit bcm_uart_exit(void)
917 {
918 	platform_driver_unregister(&bcm_uart_platform_driver);
919 	uart_unregister_driver(&bcm_uart_driver);
920 }
921 
922 module_init(bcm_uart_init);
923 module_exit(bcm_uart_exit);
924 
925 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
926 MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
927 MODULE_LICENSE("GPL");
928