xref: /linux/drivers/tty/serial/bcm63xx_uart.c (revision 5e3992fe72748ed3892be876f09d4d990548b7af) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Derived from many drivers using generic_serial interface.
4  *
5  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6  *
7  *  Serial driver for BCM63xx integrated UART.
8  *
9  * Hardware flow control was _not_ tested since I only have RX/TX on
10  * my board.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/console.h>
19 #include <linux/clk.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/sysrq.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial_bcm63xx.h>
26 #include <linux/io.h>
27 #include <linux/of.h>
28 
29 #define BCM63XX_NR_UARTS	2
30 
31 static struct uart_port ports[BCM63XX_NR_UARTS];
32 
33 /*
34  * rx interrupt mask / stat
35  *
36  * mask:
37  *  - rx fifo full
38  *  - rx fifo above threshold
39  *  - rx fifo not empty for too long
40  */
41 #define UART_RX_INT_MASK	(UART_IR_MASK(UART_IR_RXOVER) |		\
42 				UART_IR_MASK(UART_IR_RXTHRESH) |	\
43 				UART_IR_MASK(UART_IR_RXTIMEOUT))
44 
45 #define UART_RX_INT_STAT	(UART_IR_STAT(UART_IR_RXOVER) |		\
46 				UART_IR_STAT(UART_IR_RXTHRESH) |	\
47 				UART_IR_STAT(UART_IR_RXTIMEOUT))
48 
49 /*
50  * tx interrupt mask / stat
51  *
52  * mask:
53  * - tx fifo empty
54  * - tx fifo below threshold
55  */
56 #define UART_TX_INT_MASK	(UART_IR_MASK(UART_IR_TXEMPTY) |	\
57 				UART_IR_MASK(UART_IR_TXTRESH))
58 
59 #define UART_TX_INT_STAT	(UART_IR_STAT(UART_IR_TXEMPTY) |	\
60 				UART_IR_STAT(UART_IR_TXTRESH))
61 
62 /*
63  * external input interrupt
64  *
65  * mask: any edge on CTS, DCD
66  */
67 #define UART_EXTINP_INT_MASK	(UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
68 				 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
69 
70 /*
71  * handy uart register accessor
72  */
73 static inline unsigned int bcm_uart_readl(struct uart_port *port,
74 					 unsigned int offset)
75 {
76 	return __raw_readl(port->membase + offset);
77 }
78 
79 static inline void bcm_uart_writel(struct uart_port *port,
80 				  unsigned int value, unsigned int offset)
81 {
82 	__raw_writel(value, port->membase + offset);
83 }
84 
85 /*
86  * serial core request to check if uart tx fifo is empty
87  */
88 static unsigned int bcm_uart_tx_empty(struct uart_port *port)
89 {
90 	unsigned int val;
91 
92 	val = bcm_uart_readl(port, UART_IR_REG);
93 	return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
94 }
95 
96 /*
97  * serial core request to set RTS and DTR pin state and loopback mode
98  */
99 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
100 {
101 	unsigned int val;
102 
103 	val = bcm_uart_readl(port, UART_MCTL_REG);
104 	val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
105 	/* invert of written value is reflected on the pin */
106 	if (!(mctrl & TIOCM_DTR))
107 		val |= UART_MCTL_DTR_MASK;
108 	if (!(mctrl & TIOCM_RTS))
109 		val |= UART_MCTL_RTS_MASK;
110 	bcm_uart_writel(port, val, UART_MCTL_REG);
111 
112 	val = bcm_uart_readl(port, UART_CTL_REG);
113 	if (mctrl & TIOCM_LOOP)
114 		val |= UART_CTL_LOOPBACK_MASK;
115 	else
116 		val &= ~UART_CTL_LOOPBACK_MASK;
117 	bcm_uart_writel(port, val, UART_CTL_REG);
118 }
119 
120 /*
121  * serial core request to return RI, CTS, DCD and DSR pin state
122  */
123 static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
124 {
125 	unsigned int val, mctrl;
126 
127 	mctrl = 0;
128 	val = bcm_uart_readl(port, UART_EXTINP_REG);
129 	if (val & UART_EXTINP_RI_MASK)
130 		mctrl |= TIOCM_RI;
131 	if (val & UART_EXTINP_CTS_MASK)
132 		mctrl |= TIOCM_CTS;
133 	if (val & UART_EXTINP_DCD_MASK)
134 		mctrl |= TIOCM_CD;
135 	if (val & UART_EXTINP_DSR_MASK)
136 		mctrl |= TIOCM_DSR;
137 	return mctrl;
138 }
139 
140 /*
141  * serial core request to disable tx ASAP (used for flow control)
142  */
143 static void bcm_uart_stop_tx(struct uart_port *port)
144 {
145 	unsigned int val;
146 
147 	val = bcm_uart_readl(port, UART_CTL_REG);
148 	val &= ~(UART_CTL_TXEN_MASK);
149 	bcm_uart_writel(port, val, UART_CTL_REG);
150 
151 	val = bcm_uart_readl(port, UART_IR_REG);
152 	val &= ~UART_TX_INT_MASK;
153 	bcm_uart_writel(port, val, UART_IR_REG);
154 }
155 
156 /*
157  * serial core request to (re)enable tx
158  */
159 static void bcm_uart_start_tx(struct uart_port *port)
160 {
161 	unsigned int val;
162 
163 	val = bcm_uart_readl(port, UART_IR_REG);
164 	val |= UART_TX_INT_MASK;
165 	bcm_uart_writel(port, val, UART_IR_REG);
166 
167 	val = bcm_uart_readl(port, UART_CTL_REG);
168 	val |= UART_CTL_TXEN_MASK;
169 	bcm_uart_writel(port, val, UART_CTL_REG);
170 }
171 
172 /*
173  * serial core request to stop rx, called before port shutdown
174  */
175 static void bcm_uart_stop_rx(struct uart_port *port)
176 {
177 	unsigned int val;
178 
179 	val = bcm_uart_readl(port, UART_IR_REG);
180 	val &= ~UART_RX_INT_MASK;
181 	bcm_uart_writel(port, val, UART_IR_REG);
182 }
183 
184 /*
185  * serial core request to enable modem status interrupt reporting
186  */
187 static void bcm_uart_enable_ms(struct uart_port *port)
188 {
189 	unsigned int val;
190 
191 	val = bcm_uart_readl(port, UART_IR_REG);
192 	val |= UART_IR_MASK(UART_IR_EXTIP);
193 	bcm_uart_writel(port, val, UART_IR_REG);
194 }
195 
196 /*
197  * serial core request to start/stop emitting break char
198  */
199 static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
200 {
201 	unsigned long flags;
202 	unsigned int val;
203 
204 	spin_lock_irqsave(&port->lock, flags);
205 
206 	val = bcm_uart_readl(port, UART_CTL_REG);
207 	if (ctl)
208 		val |= UART_CTL_XMITBRK_MASK;
209 	else
210 		val &= ~UART_CTL_XMITBRK_MASK;
211 	bcm_uart_writel(port, val, UART_CTL_REG);
212 
213 	spin_unlock_irqrestore(&port->lock, flags);
214 }
215 
216 /*
217  * return port type in string format
218  */
219 static const char *bcm_uart_type(struct uart_port *port)
220 {
221 	return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
222 }
223 
224 /*
225  * read all chars in rx fifo and send them to core
226  */
227 static void bcm_uart_do_rx(struct uart_port *port)
228 {
229 	struct tty_port *tty_port = &port->state->port;
230 	unsigned int max_count;
231 
232 	/* limit number of char read in interrupt, should not be
233 	 * higher than fifo size anyway since we're much faster than
234 	 * serial port */
235 	max_count = 32;
236 	do {
237 		unsigned int iestat, c, cstat;
238 		char flag;
239 
240 		/* get overrun/fifo empty information from ier
241 		 * register */
242 		iestat = bcm_uart_readl(port, UART_IR_REG);
243 
244 		if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
245 			unsigned int val;
246 
247 			/* fifo reset is required to clear
248 			 * interrupt */
249 			val = bcm_uart_readl(port, UART_CTL_REG);
250 			val |= UART_CTL_RSTRXFIFO_MASK;
251 			bcm_uart_writel(port, val, UART_CTL_REG);
252 
253 			port->icount.overrun++;
254 			tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
255 		}
256 
257 		if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
258 			break;
259 
260 		cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
261 		port->icount.rx++;
262 		flag = TTY_NORMAL;
263 		c &= 0xff;
264 
265 		if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
266 			/* do stats first */
267 			if (cstat & UART_FIFO_BRKDET_MASK) {
268 				port->icount.brk++;
269 				if (uart_handle_break(port))
270 					continue;
271 			}
272 
273 			if (cstat & UART_FIFO_PARERR_MASK)
274 				port->icount.parity++;
275 			if (cstat & UART_FIFO_FRAMEERR_MASK)
276 				port->icount.frame++;
277 
278 			/* update flag wrt read_status_mask */
279 			cstat &= port->read_status_mask;
280 			if (cstat & UART_FIFO_BRKDET_MASK)
281 				flag = TTY_BREAK;
282 			if (cstat & UART_FIFO_FRAMEERR_MASK)
283 				flag = TTY_FRAME;
284 			if (cstat & UART_FIFO_PARERR_MASK)
285 				flag = TTY_PARITY;
286 		}
287 
288 		if (uart_handle_sysrq_char(port, c))
289 			continue;
290 
291 
292 		if ((cstat & port->ignore_status_mask) == 0)
293 			tty_insert_flip_char(tty_port, c, flag);
294 
295 	} while (--max_count);
296 
297 	tty_flip_buffer_push(tty_port);
298 }
299 
300 /*
301  * fill tx fifo with chars to send, stop when fifo is about to be full
302  * or when all chars have been sent.
303  */
304 static void bcm_uart_do_tx(struct uart_port *port)
305 {
306 	unsigned int val;
307 	bool pending;
308 	u8 ch;
309 
310 	val = bcm_uart_readl(port, UART_MCTL_REG);
311 	val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
312 
313 	pending = uart_port_tx_limited(port, ch, port->fifosize - val,
314 		true,
315 		bcm_uart_writel(port, ch, UART_FIFO_REG),
316 		({}));
317 	if (pending)
318 		return;
319 
320 	/* nothing to send, disable transmit interrupt */
321 	val = bcm_uart_readl(port, UART_IR_REG);
322 	val &= ~UART_TX_INT_MASK;
323 	bcm_uart_writel(port, val, UART_IR_REG);
324 }
325 
326 /*
327  * process uart interrupt
328  */
329 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
330 {
331 	struct uart_port *port;
332 	unsigned int irqstat;
333 
334 	port = dev_id;
335 	spin_lock(&port->lock);
336 
337 	irqstat = bcm_uart_readl(port, UART_IR_REG);
338 	if (irqstat & UART_RX_INT_STAT)
339 		bcm_uart_do_rx(port);
340 
341 	if (irqstat & UART_TX_INT_STAT)
342 		bcm_uart_do_tx(port);
343 
344 	if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
345 		unsigned int estat;
346 
347 		estat = bcm_uart_readl(port, UART_EXTINP_REG);
348 		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
349 			uart_handle_cts_change(port,
350 					       estat & UART_EXTINP_CTS_MASK);
351 		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
352 			uart_handle_dcd_change(port,
353 					       estat & UART_EXTINP_DCD_MASK);
354 	}
355 
356 	spin_unlock(&port->lock);
357 	return IRQ_HANDLED;
358 }
359 
360 /*
361  * enable rx & tx operation on uart
362  */
363 static void bcm_uart_enable(struct uart_port *port)
364 {
365 	unsigned int val;
366 
367 	val = bcm_uart_readl(port, UART_CTL_REG);
368 	val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
369 	bcm_uart_writel(port, val, UART_CTL_REG);
370 }
371 
372 /*
373  * disable rx & tx operation on uart
374  */
375 static void bcm_uart_disable(struct uart_port *port)
376 {
377 	unsigned int val;
378 
379 	val = bcm_uart_readl(port, UART_CTL_REG);
380 	val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
381 		 UART_CTL_RXEN_MASK);
382 	bcm_uart_writel(port, val, UART_CTL_REG);
383 }
384 
385 /*
386  * clear all unread data in rx fifo and unsent data in tx fifo
387  */
388 static void bcm_uart_flush(struct uart_port *port)
389 {
390 	unsigned int val;
391 
392 	/* empty rx and tx fifo */
393 	val = bcm_uart_readl(port, UART_CTL_REG);
394 	val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
395 	bcm_uart_writel(port, val, UART_CTL_REG);
396 
397 	/* read any pending char to make sure all irq status are
398 	 * cleared */
399 	(void)bcm_uart_readl(port, UART_FIFO_REG);
400 }
401 
402 /*
403  * serial core request to initialize uart and start rx operation
404  */
405 static int bcm_uart_startup(struct uart_port *port)
406 {
407 	unsigned int val;
408 	int ret;
409 
410 	/* mask all irq and flush port */
411 	bcm_uart_disable(port);
412 	bcm_uart_writel(port, 0, UART_IR_REG);
413 	bcm_uart_flush(port);
414 
415 	/* clear any pending external input interrupt */
416 	(void)bcm_uart_readl(port, UART_EXTINP_REG);
417 
418 	/* set rx/tx fifo thresh to fifo half size */
419 	val = bcm_uart_readl(port, UART_MCTL_REG);
420 	val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
421 	val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
422 	val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
423 	bcm_uart_writel(port, val, UART_MCTL_REG);
424 
425 	/* set rx fifo timeout to 1 char time */
426 	val = bcm_uart_readl(port, UART_CTL_REG);
427 	val &= ~UART_CTL_RXTMOUTCNT_MASK;
428 	val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
429 	bcm_uart_writel(port, val, UART_CTL_REG);
430 
431 	/* report any edge on dcd and cts */
432 	val = UART_EXTINP_INT_MASK;
433 	val |= UART_EXTINP_DCD_NOSENSE_MASK;
434 	val |= UART_EXTINP_CTS_NOSENSE_MASK;
435 	bcm_uart_writel(port, val, UART_EXTINP_REG);
436 
437 	/* register irq and enable rx interrupts */
438 	ret = request_irq(port->irq, bcm_uart_interrupt, 0,
439 			  dev_name(port->dev), port);
440 	if (ret)
441 		return ret;
442 	bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
443 	bcm_uart_enable(port);
444 	return 0;
445 }
446 
447 /*
448  * serial core request to flush & disable uart
449  */
450 static void bcm_uart_shutdown(struct uart_port *port)
451 {
452 	unsigned long flags;
453 
454 	spin_lock_irqsave(&port->lock, flags);
455 	bcm_uart_writel(port, 0, UART_IR_REG);
456 	spin_unlock_irqrestore(&port->lock, flags);
457 
458 	bcm_uart_disable(port);
459 	bcm_uart_flush(port);
460 	free_irq(port->irq, port);
461 }
462 
463 /*
464  * serial core request to change current uart setting
465  */
466 static void bcm_uart_set_termios(struct uart_port *port, struct ktermios *new,
467 				 const struct ktermios *old)
468 {
469 	unsigned int ctl, baud, quot, ier;
470 	unsigned long flags;
471 	int tries;
472 
473 	spin_lock_irqsave(&port->lock, flags);
474 
475 	/* Drain the hot tub fully before we power it off for the winter. */
476 	for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
477 		mdelay(10);
478 
479 	/* disable uart while changing speed */
480 	bcm_uart_disable(port);
481 	bcm_uart_flush(port);
482 
483 	/* update Control register */
484 	ctl = bcm_uart_readl(port, UART_CTL_REG);
485 	ctl &= ~UART_CTL_BITSPERSYM_MASK;
486 
487 	switch (new->c_cflag & CSIZE) {
488 	case CS5:
489 		ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
490 		break;
491 	case CS6:
492 		ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
493 		break;
494 	case CS7:
495 		ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
496 		break;
497 	default:
498 		ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
499 		break;
500 	}
501 
502 	ctl &= ~UART_CTL_STOPBITS_MASK;
503 	if (new->c_cflag & CSTOPB)
504 		ctl |= UART_CTL_STOPBITS_2;
505 	else
506 		ctl |= UART_CTL_STOPBITS_1;
507 
508 	ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
509 	if (new->c_cflag & PARENB)
510 		ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
511 	ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
512 	if (new->c_cflag & PARODD)
513 		ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
514 	bcm_uart_writel(port, ctl, UART_CTL_REG);
515 
516 	/* update Baudword register */
517 	baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
518 	quot = uart_get_divisor(port, baud) - 1;
519 	bcm_uart_writel(port, quot, UART_BAUD_REG);
520 
521 	/* update Interrupt register */
522 	ier = bcm_uart_readl(port, UART_IR_REG);
523 
524 	ier &= ~UART_IR_MASK(UART_IR_EXTIP);
525 	if (UART_ENABLE_MS(port, new->c_cflag))
526 		ier |= UART_IR_MASK(UART_IR_EXTIP);
527 
528 	bcm_uart_writel(port, ier, UART_IR_REG);
529 
530 	/* update read/ignore mask */
531 	port->read_status_mask = UART_FIFO_VALID_MASK;
532 	if (new->c_iflag & INPCK) {
533 		port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
534 		port->read_status_mask |= UART_FIFO_PARERR_MASK;
535 	}
536 	if (new->c_iflag & (IGNBRK | BRKINT))
537 		port->read_status_mask |= UART_FIFO_BRKDET_MASK;
538 
539 	port->ignore_status_mask = 0;
540 	if (new->c_iflag & IGNPAR)
541 		port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
542 	if (new->c_iflag & IGNBRK)
543 		port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
544 	if (!(new->c_cflag & CREAD))
545 		port->ignore_status_mask |= UART_FIFO_VALID_MASK;
546 
547 	uart_update_timeout(port, new->c_cflag, baud);
548 	bcm_uart_enable(port);
549 	spin_unlock_irqrestore(&port->lock, flags);
550 }
551 
552 /*
553  * serial core request to claim uart iomem
554  */
555 static int bcm_uart_request_port(struct uart_port *port)
556 {
557 	/* UARTs always present */
558 	return 0;
559 }
560 
561 /*
562  * serial core request to release uart iomem
563  */
564 static void bcm_uart_release_port(struct uart_port *port)
565 {
566 	/* Nothing to release ... */
567 }
568 
569 /*
570  * serial core request to do any port required autoconfiguration
571  */
572 static void bcm_uart_config_port(struct uart_port *port, int flags)
573 {
574 	if (flags & UART_CONFIG_TYPE) {
575 		if (bcm_uart_request_port(port))
576 			return;
577 		port->type = PORT_BCM63XX;
578 	}
579 }
580 
581 /*
582  * serial core request to check that port information in serinfo are
583  * suitable
584  */
585 static int bcm_uart_verify_port(struct uart_port *port,
586 				struct serial_struct *serinfo)
587 {
588 	if (port->type != PORT_BCM63XX)
589 		return -EINVAL;
590 	if (port->irq != serinfo->irq)
591 		return -EINVAL;
592 	if (port->iotype != serinfo->io_type)
593 		return -EINVAL;
594 	if (port->mapbase != (unsigned long)serinfo->iomem_base)
595 		return -EINVAL;
596 	return 0;
597 }
598 
599 #ifdef CONFIG_CONSOLE_POLL
600 /*
601  * return true when outstanding tx equals fifo size
602  */
603 static bool bcm_uart_tx_full(struct uart_port *port)
604 {
605 	unsigned int val;
606 
607 	val = bcm_uart_readl(port, UART_MCTL_REG);
608 	val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
609 	return !(port->fifosize - val);
610 }
611 
612 static int bcm_uart_poll_get_char(struct uart_port *port)
613 {
614 	unsigned int iestat;
615 
616 	iestat = bcm_uart_readl(port, UART_IR_REG);
617 	if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
618 		return NO_POLL_CHAR;
619 
620 	return bcm_uart_readl(port, UART_FIFO_REG);
621 }
622 
623 static void bcm_uart_poll_put_char(struct uart_port *port, unsigned char c)
624 {
625 	while (bcm_uart_tx_full(port)) {
626 		cpu_relax();
627 	}
628 
629 	bcm_uart_writel(port, c, UART_FIFO_REG);
630 }
631 #endif
632 
633 /* serial core callbacks */
634 static const struct uart_ops bcm_uart_ops = {
635 	.tx_empty	= bcm_uart_tx_empty,
636 	.get_mctrl	= bcm_uart_get_mctrl,
637 	.set_mctrl	= bcm_uart_set_mctrl,
638 	.start_tx	= bcm_uart_start_tx,
639 	.stop_tx	= bcm_uart_stop_tx,
640 	.stop_rx	= bcm_uart_stop_rx,
641 	.enable_ms	= bcm_uart_enable_ms,
642 	.break_ctl	= bcm_uart_break_ctl,
643 	.startup	= bcm_uart_startup,
644 	.shutdown	= bcm_uart_shutdown,
645 	.set_termios	= bcm_uart_set_termios,
646 	.type		= bcm_uart_type,
647 	.release_port	= bcm_uart_release_port,
648 	.request_port	= bcm_uart_request_port,
649 	.config_port	= bcm_uart_config_port,
650 	.verify_port	= bcm_uart_verify_port,
651 #ifdef CONFIG_CONSOLE_POLL
652 	.poll_get_char  = bcm_uart_poll_get_char,
653 	.poll_put_char  = bcm_uart_poll_put_char,
654 #endif
655 };
656 
657 
658 
659 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
660 static void wait_for_xmitr(struct uart_port *port)
661 {
662 	unsigned int tmout;
663 
664 	/* Wait up to 10ms for the character(s) to be sent. */
665 	tmout = 10000;
666 	while (--tmout) {
667 		unsigned int val;
668 
669 		val = bcm_uart_readl(port, UART_IR_REG);
670 		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
671 			break;
672 		udelay(1);
673 	}
674 
675 	/* Wait up to 1s for flow control if necessary */
676 	if (port->flags & UPF_CONS_FLOW) {
677 		tmout = 1000000;
678 		while (--tmout) {
679 			unsigned int val;
680 
681 			val = bcm_uart_readl(port, UART_EXTINP_REG);
682 			if (val & UART_EXTINP_CTS_MASK)
683 				break;
684 			udelay(1);
685 		}
686 	}
687 }
688 
689 /*
690  * output given char
691  */
692 static void bcm_console_putchar(struct uart_port *port, unsigned char ch)
693 {
694 	wait_for_xmitr(port);
695 	bcm_uart_writel(port, ch, UART_FIFO_REG);
696 }
697 
698 /*
699  * console core request to output given string
700  */
701 static void bcm_console_write(struct console *co, const char *s,
702 			      unsigned int count)
703 {
704 	struct uart_port *port;
705 	unsigned long flags;
706 	int locked;
707 
708 	port = &ports[co->index];
709 
710 	local_irq_save(flags);
711 	if (port->sysrq) {
712 		/* bcm_uart_interrupt() already took the lock */
713 		locked = 0;
714 	} else if (oops_in_progress) {
715 		locked = spin_trylock(&port->lock);
716 	} else {
717 		spin_lock(&port->lock);
718 		locked = 1;
719 	}
720 
721 	/* call helper to deal with \r\n */
722 	uart_console_write(port, s, count, bcm_console_putchar);
723 
724 	/* and wait for char to be transmitted */
725 	wait_for_xmitr(port);
726 
727 	if (locked)
728 		spin_unlock(&port->lock);
729 	local_irq_restore(flags);
730 }
731 
732 /*
733  * console core request to setup given console, find matching uart
734  * port and setup it.
735  */
736 static int bcm_console_setup(struct console *co, char *options)
737 {
738 	struct uart_port *port;
739 	int baud = 9600;
740 	int bits = 8;
741 	int parity = 'n';
742 	int flow = 'n';
743 
744 	if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
745 		return -EINVAL;
746 	port = &ports[co->index];
747 	if (!port->membase)
748 		return -ENODEV;
749 	if (options)
750 		uart_parse_options(options, &baud, &parity, &bits, &flow);
751 
752 	return uart_set_options(port, co, baud, parity, bits, flow);
753 }
754 
755 static struct uart_driver bcm_uart_driver;
756 
757 static struct console bcm63xx_console = {
758 	.name		= "ttyS",
759 	.write		= bcm_console_write,
760 	.device		= uart_console_device,
761 	.setup		= bcm_console_setup,
762 	.flags		= CON_PRINTBUFFER,
763 	.index		= -1,
764 	.data		= &bcm_uart_driver,
765 };
766 
767 static int __init bcm63xx_console_init(void)
768 {
769 	register_console(&bcm63xx_console);
770 	return 0;
771 }
772 
773 console_initcall(bcm63xx_console_init);
774 
775 static void bcm_early_write(struct console *con, const char *s, unsigned n)
776 {
777 	struct earlycon_device *dev = con->data;
778 
779 	uart_console_write(&dev->port, s, n, bcm_console_putchar);
780 	wait_for_xmitr(&dev->port);
781 }
782 
783 static int __init bcm_early_console_setup(struct earlycon_device *device,
784 					  const char *opt)
785 {
786 	if (!device->port.membase)
787 		return -ENODEV;
788 
789 	device->con->write = bcm_early_write;
790 	return 0;
791 }
792 
793 OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
794 
795 #define BCM63XX_CONSOLE	(&bcm63xx_console)
796 #else
797 #define BCM63XX_CONSOLE	NULL
798 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
799 
800 static struct uart_driver bcm_uart_driver = {
801 	.owner		= THIS_MODULE,
802 	.driver_name	= "bcm63xx_uart",
803 	.dev_name	= "ttyS",
804 	.major		= TTY_MAJOR,
805 	.minor		= 64,
806 	.nr		= BCM63XX_NR_UARTS,
807 	.cons		= BCM63XX_CONSOLE,
808 };
809 
810 /*
811  * platform driver probe/remove callback
812  */
813 static int bcm_uart_probe(struct platform_device *pdev)
814 {
815 	struct resource *res_mem;
816 	struct uart_port *port;
817 	struct clk *clk;
818 	int ret;
819 
820 	if (pdev->dev.of_node) {
821 		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
822 
823 		if (pdev->id < 0)
824 			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
825 	}
826 
827 	if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
828 		return -EINVAL;
829 
830 	port = &ports[pdev->id];
831 	if (port->membase)
832 		return -EBUSY;
833 	memset(port, 0, sizeof(*port));
834 
835 	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
836 	if (!res_mem)
837 		return -ENODEV;
838 
839 	port->mapbase = res_mem->start;
840 	port->membase = devm_ioremap_resource(&pdev->dev, res_mem);
841 	if (IS_ERR(port->membase))
842 		return PTR_ERR(port->membase);
843 
844 	ret = platform_get_irq(pdev, 0);
845 	if (ret < 0)
846 		return ret;
847 	port->irq = ret;
848 
849 	clk = clk_get(&pdev->dev, "refclk");
850 	if (IS_ERR(clk) && pdev->dev.of_node)
851 		clk = of_clk_get(pdev->dev.of_node, 0);
852 
853 	if (IS_ERR(clk))
854 		return -ENODEV;
855 
856 	port->iotype = UPIO_MEM;
857 	port->ops = &bcm_uart_ops;
858 	port->flags = UPF_BOOT_AUTOCONF;
859 	port->dev = &pdev->dev;
860 	port->fifosize = 16;
861 	port->uartclk = clk_get_rate(clk) / 2;
862 	port->line = pdev->id;
863 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BCM63XX_CONSOLE);
864 	clk_put(clk);
865 
866 	ret = uart_add_one_port(&bcm_uart_driver, port);
867 	if (ret) {
868 		ports[pdev->id].membase = NULL;
869 		return ret;
870 	}
871 	platform_set_drvdata(pdev, port);
872 	return 0;
873 }
874 
875 static int bcm_uart_remove(struct platform_device *pdev)
876 {
877 	struct uart_port *port;
878 
879 	port = platform_get_drvdata(pdev);
880 	uart_remove_one_port(&bcm_uart_driver, port);
881 	/* mark port as free */
882 	ports[pdev->id].membase = NULL;
883 	return 0;
884 }
885 
886 static const struct of_device_id bcm63xx_of_match[] = {
887 	{ .compatible = "brcm,bcm6345-uart" },
888 	{ /* sentinel */ }
889 };
890 MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
891 
892 /*
893  * platform driver stuff
894  */
895 static struct platform_driver bcm_uart_platform_driver = {
896 	.probe	= bcm_uart_probe,
897 	.remove	= bcm_uart_remove,
898 	.driver	= {
899 		.name  = "bcm63xx_uart",
900 		.of_match_table = bcm63xx_of_match,
901 	},
902 };
903 
904 static int __init bcm_uart_init(void)
905 {
906 	int ret;
907 
908 	ret = uart_register_driver(&bcm_uart_driver);
909 	if (ret)
910 		return ret;
911 
912 	ret = platform_driver_register(&bcm_uart_platform_driver);
913 	if (ret)
914 		uart_unregister_driver(&bcm_uart_driver);
915 
916 	return ret;
917 }
918 
919 static void __exit bcm_uart_exit(void)
920 {
921 	platform_driver_unregister(&bcm_uart_platform_driver);
922 	uart_unregister_driver(&bcm_uart_driver);
923 }
924 
925 module_init(bcm_uart_init);
926 module_exit(bcm_uart_exit);
927 
928 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
929 MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
930 MODULE_LICENSE("GPL");
931