xref: /linux/drivers/tty/serial/bcm63xx_uart.c (revision 45d8b572fac3aa8b49d53c946b3685eaf78a2824) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Derived from many drivers using generic_serial interface.
4  *
5  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
6  *
7  *  Serial driver for BCM63xx integrated UART.
8  *
9  * Hardware flow control was _not_ tested since I only have RX/TX on
10  * my board.
11  */
12 
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/console.h>
19 #include <linux/clk.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/sysrq.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial_bcm63xx.h>
26 #include <linux/io.h>
27 #include <linux/of.h>
28 
29 #define BCM63XX_NR_UARTS	2
30 
31 static struct uart_port ports[BCM63XX_NR_UARTS];
32 
33 /*
34  * rx interrupt mask / stat
35  *
36  * mask:
37  *  - rx fifo full
38  *  - rx fifo above threshold
39  *  - rx fifo not empty for too long
40  */
41 #define UART_RX_INT_MASK	(UART_IR_MASK(UART_IR_RXOVER) |		\
42 				UART_IR_MASK(UART_IR_RXTHRESH) |	\
43 				UART_IR_MASK(UART_IR_RXTIMEOUT))
44 
45 #define UART_RX_INT_STAT	(UART_IR_STAT(UART_IR_RXOVER) |		\
46 				UART_IR_STAT(UART_IR_RXTHRESH) |	\
47 				UART_IR_STAT(UART_IR_RXTIMEOUT))
48 
49 /*
50  * tx interrupt mask / stat
51  *
52  * mask:
53  * - tx fifo empty
54  * - tx fifo below threshold
55  */
56 #define UART_TX_INT_MASK	(UART_IR_MASK(UART_IR_TXEMPTY) |	\
57 				UART_IR_MASK(UART_IR_TXTRESH))
58 
59 #define UART_TX_INT_STAT	(UART_IR_STAT(UART_IR_TXEMPTY) |	\
60 				UART_IR_STAT(UART_IR_TXTRESH))
61 
62 /*
63  * external input interrupt
64  *
65  * mask: any edge on CTS, DCD
66  */
67 #define UART_EXTINP_INT_MASK	(UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
68 				 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
69 
70 /*
71  * handy uart register accessor
72  */
73 static inline unsigned int bcm_uart_readl(struct uart_port *port,
74 					 unsigned int offset)
75 {
76 	return __raw_readl(port->membase + offset);
77 }
78 
79 static inline void bcm_uart_writel(struct uart_port *port,
80 				  unsigned int value, unsigned int offset)
81 {
82 	__raw_writel(value, port->membase + offset);
83 }
84 
85 /*
86  * serial core request to check if uart tx fifo is empty
87  */
88 static unsigned int bcm_uart_tx_empty(struct uart_port *port)
89 {
90 	unsigned int val;
91 
92 	val = bcm_uart_readl(port, UART_IR_REG);
93 	return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
94 }
95 
96 /*
97  * serial core request to set RTS and DTR pin state and loopback mode
98  */
99 static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
100 {
101 	unsigned int val;
102 
103 	val = bcm_uart_readl(port, UART_MCTL_REG);
104 	val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
105 	/* invert of written value is reflected on the pin */
106 	if (!(mctrl & TIOCM_DTR))
107 		val |= UART_MCTL_DTR_MASK;
108 	if (!(mctrl & TIOCM_RTS))
109 		val |= UART_MCTL_RTS_MASK;
110 	bcm_uart_writel(port, val, UART_MCTL_REG);
111 
112 	val = bcm_uart_readl(port, UART_CTL_REG);
113 	if (mctrl & TIOCM_LOOP)
114 		val |= UART_CTL_LOOPBACK_MASK;
115 	else
116 		val &= ~UART_CTL_LOOPBACK_MASK;
117 	bcm_uart_writel(port, val, UART_CTL_REG);
118 }
119 
120 /*
121  * serial core request to return RI, CTS, DCD and DSR pin state
122  */
123 static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
124 {
125 	unsigned int val, mctrl;
126 
127 	mctrl = 0;
128 	val = bcm_uart_readl(port, UART_EXTINP_REG);
129 	if (val & UART_EXTINP_RI_MASK)
130 		mctrl |= TIOCM_RI;
131 	if (val & UART_EXTINP_CTS_MASK)
132 		mctrl |= TIOCM_CTS;
133 	if (val & UART_EXTINP_DCD_MASK)
134 		mctrl |= TIOCM_CD;
135 	if (val & UART_EXTINP_DSR_MASK)
136 		mctrl |= TIOCM_DSR;
137 	return mctrl;
138 }
139 
140 /*
141  * serial core request to disable tx ASAP (used for flow control)
142  */
143 static void bcm_uart_stop_tx(struct uart_port *port)
144 {
145 	unsigned int val;
146 
147 	val = bcm_uart_readl(port, UART_CTL_REG);
148 	val &= ~(UART_CTL_TXEN_MASK);
149 	bcm_uart_writel(port, val, UART_CTL_REG);
150 
151 	val = bcm_uart_readl(port, UART_IR_REG);
152 	val &= ~UART_TX_INT_MASK;
153 	bcm_uart_writel(port, val, UART_IR_REG);
154 }
155 
156 /*
157  * serial core request to (re)enable tx
158  */
159 static void bcm_uart_start_tx(struct uart_port *port)
160 {
161 	unsigned int val;
162 
163 	val = bcm_uart_readl(port, UART_IR_REG);
164 	val |= UART_TX_INT_MASK;
165 	bcm_uart_writel(port, val, UART_IR_REG);
166 
167 	val = bcm_uart_readl(port, UART_CTL_REG);
168 	val |= UART_CTL_TXEN_MASK;
169 	bcm_uart_writel(port, val, UART_CTL_REG);
170 }
171 
172 /*
173  * serial core request to stop rx, called before port shutdown
174  */
175 static void bcm_uart_stop_rx(struct uart_port *port)
176 {
177 	unsigned int val;
178 
179 	val = bcm_uart_readl(port, UART_IR_REG);
180 	val &= ~UART_RX_INT_MASK;
181 	bcm_uart_writel(port, val, UART_IR_REG);
182 }
183 
184 /*
185  * serial core request to enable modem status interrupt reporting
186  */
187 static void bcm_uart_enable_ms(struct uart_port *port)
188 {
189 	unsigned int val;
190 
191 	val = bcm_uart_readl(port, UART_IR_REG);
192 	val |= UART_IR_MASK(UART_IR_EXTIP);
193 	bcm_uart_writel(port, val, UART_IR_REG);
194 }
195 
196 /*
197  * serial core request to start/stop emitting break char
198  */
199 static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
200 {
201 	unsigned long flags;
202 	unsigned int val;
203 
204 	uart_port_lock_irqsave(port, &flags);
205 
206 	val = bcm_uart_readl(port, UART_CTL_REG);
207 	if (ctl)
208 		val |= UART_CTL_XMITBRK_MASK;
209 	else
210 		val &= ~UART_CTL_XMITBRK_MASK;
211 	bcm_uart_writel(port, val, UART_CTL_REG);
212 
213 	uart_port_unlock_irqrestore(port, flags);
214 }
215 
216 /*
217  * return port type in string format
218  */
219 static const char *bcm_uart_type(struct uart_port *port)
220 {
221 	return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
222 }
223 
224 /*
225  * read all chars in rx fifo and send them to core
226  */
227 static void bcm_uart_do_rx(struct uart_port *port)
228 {
229 	struct tty_port *tty_port = &port->state->port;
230 	unsigned int max_count;
231 
232 	/* limit number of char read in interrupt, should not be
233 	 * higher than fifo size anyway since we're much faster than
234 	 * serial port */
235 	max_count = 32;
236 	do {
237 		unsigned int iestat, c, cstat;
238 		char flag;
239 
240 		/* get overrun/fifo empty information from ier
241 		 * register */
242 		iestat = bcm_uart_readl(port, UART_IR_REG);
243 
244 		if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
245 			unsigned int val;
246 
247 			/* fifo reset is required to clear
248 			 * interrupt */
249 			val = bcm_uart_readl(port, UART_CTL_REG);
250 			val |= UART_CTL_RSTRXFIFO_MASK;
251 			bcm_uart_writel(port, val, UART_CTL_REG);
252 
253 			port->icount.overrun++;
254 			tty_insert_flip_char(tty_port, 0, TTY_OVERRUN);
255 		}
256 
257 		if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
258 			break;
259 
260 		cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
261 		port->icount.rx++;
262 		flag = TTY_NORMAL;
263 		c &= 0xff;
264 
265 		if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
266 			/* do stats first */
267 			if (cstat & UART_FIFO_BRKDET_MASK) {
268 				port->icount.brk++;
269 				if (uart_handle_break(port))
270 					continue;
271 			}
272 
273 			if (cstat & UART_FIFO_PARERR_MASK)
274 				port->icount.parity++;
275 			if (cstat & UART_FIFO_FRAMEERR_MASK)
276 				port->icount.frame++;
277 
278 			/* update flag wrt read_status_mask */
279 			cstat &= port->read_status_mask;
280 			if (cstat & UART_FIFO_BRKDET_MASK)
281 				flag = TTY_BREAK;
282 			if (cstat & UART_FIFO_FRAMEERR_MASK)
283 				flag = TTY_FRAME;
284 			if (cstat & UART_FIFO_PARERR_MASK)
285 				flag = TTY_PARITY;
286 		}
287 
288 		if (uart_prepare_sysrq_char(port, c))
289 			continue;
290 
291 		if ((cstat & port->ignore_status_mask) == 0)
292 			tty_insert_flip_char(tty_port, c, flag);
293 
294 	} while (--max_count);
295 
296 	tty_flip_buffer_push(tty_port);
297 }
298 
299 /*
300  * fill tx fifo with chars to send, stop when fifo is about to be full
301  * or when all chars have been sent.
302  */
303 static void bcm_uart_do_tx(struct uart_port *port)
304 {
305 	unsigned int val;
306 	bool pending;
307 	u8 ch;
308 
309 	val = bcm_uart_readl(port, UART_MCTL_REG);
310 	val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
311 
312 	pending = uart_port_tx_limited(port, ch, port->fifosize - val,
313 		true,
314 		bcm_uart_writel(port, ch, UART_FIFO_REG),
315 		({}));
316 	if (pending)
317 		return;
318 
319 	/* nothing to send, disable transmit interrupt */
320 	val = bcm_uart_readl(port, UART_IR_REG);
321 	val &= ~UART_TX_INT_MASK;
322 	bcm_uart_writel(port, val, UART_IR_REG);
323 }
324 
325 /*
326  * process uart interrupt
327  */
328 static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
329 {
330 	struct uart_port *port;
331 	unsigned int irqstat;
332 
333 	port = dev_id;
334 	uart_port_lock(port);
335 
336 	irqstat = bcm_uart_readl(port, UART_IR_REG);
337 	if (irqstat & UART_RX_INT_STAT)
338 		bcm_uart_do_rx(port);
339 
340 	if (irqstat & UART_TX_INT_STAT)
341 		bcm_uart_do_tx(port);
342 
343 	if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
344 		unsigned int estat;
345 
346 		estat = bcm_uart_readl(port, UART_EXTINP_REG);
347 		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
348 			uart_handle_cts_change(port,
349 					       estat & UART_EXTINP_CTS_MASK);
350 		if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
351 			uart_handle_dcd_change(port,
352 					       estat & UART_EXTINP_DCD_MASK);
353 	}
354 
355 	uart_unlock_and_check_sysrq(port);
356 	return IRQ_HANDLED;
357 }
358 
359 /*
360  * enable rx & tx operation on uart
361  */
362 static void bcm_uart_enable(struct uart_port *port)
363 {
364 	unsigned int val;
365 
366 	val = bcm_uart_readl(port, UART_CTL_REG);
367 	val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
368 	bcm_uart_writel(port, val, UART_CTL_REG);
369 }
370 
371 /*
372  * disable rx & tx operation on uart
373  */
374 static void bcm_uart_disable(struct uart_port *port)
375 {
376 	unsigned int val;
377 
378 	val = bcm_uart_readl(port, UART_CTL_REG);
379 	val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
380 		 UART_CTL_RXEN_MASK);
381 	bcm_uart_writel(port, val, UART_CTL_REG);
382 }
383 
384 /*
385  * clear all unread data in rx fifo and unsent data in tx fifo
386  */
387 static void bcm_uart_flush(struct uart_port *port)
388 {
389 	unsigned int val;
390 
391 	/* empty rx and tx fifo */
392 	val = bcm_uart_readl(port, UART_CTL_REG);
393 	val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
394 	bcm_uart_writel(port, val, UART_CTL_REG);
395 
396 	/* read any pending char to make sure all irq status are
397 	 * cleared */
398 	(void)bcm_uart_readl(port, UART_FIFO_REG);
399 }
400 
401 /*
402  * serial core request to initialize uart and start rx operation
403  */
404 static int bcm_uart_startup(struct uart_port *port)
405 {
406 	unsigned int val;
407 	int ret;
408 
409 	/* mask all irq and flush port */
410 	bcm_uart_disable(port);
411 	bcm_uart_writel(port, 0, UART_IR_REG);
412 	bcm_uart_flush(port);
413 
414 	/* clear any pending external input interrupt */
415 	(void)bcm_uart_readl(port, UART_EXTINP_REG);
416 
417 	/* set rx/tx fifo thresh to fifo half size */
418 	val = bcm_uart_readl(port, UART_MCTL_REG);
419 	val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
420 	val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
421 	val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
422 	bcm_uart_writel(port, val, UART_MCTL_REG);
423 
424 	/* set rx fifo timeout to 1 char time */
425 	val = bcm_uart_readl(port, UART_CTL_REG);
426 	val &= ~UART_CTL_RXTMOUTCNT_MASK;
427 	val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
428 	bcm_uart_writel(port, val, UART_CTL_REG);
429 
430 	/* report any edge on dcd and cts */
431 	val = UART_EXTINP_INT_MASK;
432 	val |= UART_EXTINP_DCD_NOSENSE_MASK;
433 	val |= UART_EXTINP_CTS_NOSENSE_MASK;
434 	bcm_uart_writel(port, val, UART_EXTINP_REG);
435 
436 	/* register irq and enable rx interrupts */
437 	ret = request_irq(port->irq, bcm_uart_interrupt, 0,
438 			  dev_name(port->dev), port);
439 	if (ret)
440 		return ret;
441 	bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
442 	bcm_uart_enable(port);
443 	return 0;
444 }
445 
446 /*
447  * serial core request to flush & disable uart
448  */
449 static void bcm_uart_shutdown(struct uart_port *port)
450 {
451 	unsigned long flags;
452 
453 	uart_port_lock_irqsave(port, &flags);
454 	bcm_uart_writel(port, 0, UART_IR_REG);
455 	uart_port_unlock_irqrestore(port, flags);
456 
457 	bcm_uart_disable(port);
458 	bcm_uart_flush(port);
459 	free_irq(port->irq, port);
460 }
461 
462 /*
463  * serial core request to change current uart setting
464  */
465 static void bcm_uart_set_termios(struct uart_port *port, struct ktermios *new,
466 				 const struct ktermios *old)
467 {
468 	unsigned int ctl, baud, quot, ier;
469 	unsigned long flags;
470 	int tries;
471 
472 	uart_port_lock_irqsave(port, &flags);
473 
474 	/* Drain the hot tub fully before we power it off for the winter. */
475 	for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--)
476 		mdelay(10);
477 
478 	/* disable uart while changing speed */
479 	bcm_uart_disable(port);
480 	bcm_uart_flush(port);
481 
482 	/* update Control register */
483 	ctl = bcm_uart_readl(port, UART_CTL_REG);
484 	ctl &= ~UART_CTL_BITSPERSYM_MASK;
485 
486 	switch (new->c_cflag & CSIZE) {
487 	case CS5:
488 		ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
489 		break;
490 	case CS6:
491 		ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
492 		break;
493 	case CS7:
494 		ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
495 		break;
496 	default:
497 		ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
498 		break;
499 	}
500 
501 	ctl &= ~UART_CTL_STOPBITS_MASK;
502 	if (new->c_cflag & CSTOPB)
503 		ctl |= UART_CTL_STOPBITS_2;
504 	else
505 		ctl |= UART_CTL_STOPBITS_1;
506 
507 	ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
508 	if (new->c_cflag & PARENB)
509 		ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
510 	ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
511 	if (new->c_cflag & PARODD)
512 		ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
513 	bcm_uart_writel(port, ctl, UART_CTL_REG);
514 
515 	/* update Baudword register */
516 	baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
517 	quot = uart_get_divisor(port, baud) - 1;
518 	bcm_uart_writel(port, quot, UART_BAUD_REG);
519 
520 	/* update Interrupt register */
521 	ier = bcm_uart_readl(port, UART_IR_REG);
522 
523 	ier &= ~UART_IR_MASK(UART_IR_EXTIP);
524 	if (UART_ENABLE_MS(port, new->c_cflag))
525 		ier |= UART_IR_MASK(UART_IR_EXTIP);
526 
527 	bcm_uart_writel(port, ier, UART_IR_REG);
528 
529 	/* update read/ignore mask */
530 	port->read_status_mask = UART_FIFO_VALID_MASK;
531 	if (new->c_iflag & INPCK) {
532 		port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
533 		port->read_status_mask |= UART_FIFO_PARERR_MASK;
534 	}
535 	if (new->c_iflag & (IGNBRK | BRKINT))
536 		port->read_status_mask |= UART_FIFO_BRKDET_MASK;
537 
538 	port->ignore_status_mask = 0;
539 	if (new->c_iflag & IGNPAR)
540 		port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
541 	if (new->c_iflag & IGNBRK)
542 		port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
543 	if (!(new->c_cflag & CREAD))
544 		port->ignore_status_mask |= UART_FIFO_VALID_MASK;
545 
546 	uart_update_timeout(port, new->c_cflag, baud);
547 	bcm_uart_enable(port);
548 	uart_port_unlock_irqrestore(port, flags);
549 }
550 
551 /*
552  * serial core request to claim uart iomem
553  */
554 static int bcm_uart_request_port(struct uart_port *port)
555 {
556 	/* UARTs always present */
557 	return 0;
558 }
559 
560 /*
561  * serial core request to release uart iomem
562  */
563 static void bcm_uart_release_port(struct uart_port *port)
564 {
565 	/* Nothing to release ... */
566 }
567 
568 /*
569  * serial core request to do any port required autoconfiguration
570  */
571 static void bcm_uart_config_port(struct uart_port *port, int flags)
572 {
573 	if (flags & UART_CONFIG_TYPE) {
574 		if (bcm_uart_request_port(port))
575 			return;
576 		port->type = PORT_BCM63XX;
577 	}
578 }
579 
580 /*
581  * serial core request to check that port information in serinfo are
582  * suitable
583  */
584 static int bcm_uart_verify_port(struct uart_port *port,
585 				struct serial_struct *serinfo)
586 {
587 	if (port->type != PORT_BCM63XX)
588 		return -EINVAL;
589 	if (port->irq != serinfo->irq)
590 		return -EINVAL;
591 	if (port->iotype != serinfo->io_type)
592 		return -EINVAL;
593 	if (port->mapbase != (unsigned long)serinfo->iomem_base)
594 		return -EINVAL;
595 	return 0;
596 }
597 
598 #ifdef CONFIG_CONSOLE_POLL
599 /*
600  * return true when outstanding tx equals fifo size
601  */
602 static bool bcm_uart_tx_full(struct uart_port *port)
603 {
604 	unsigned int val;
605 
606 	val = bcm_uart_readl(port, UART_MCTL_REG);
607 	val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
608 	return !(port->fifosize - val);
609 }
610 
611 static int bcm_uart_poll_get_char(struct uart_port *port)
612 {
613 	unsigned int iestat;
614 
615 	iestat = bcm_uart_readl(port, UART_IR_REG);
616 	if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
617 		return NO_POLL_CHAR;
618 
619 	return bcm_uart_readl(port, UART_FIFO_REG);
620 }
621 
622 static void bcm_uart_poll_put_char(struct uart_port *port, unsigned char c)
623 {
624 	while (bcm_uart_tx_full(port)) {
625 		cpu_relax();
626 	}
627 
628 	bcm_uart_writel(port, c, UART_FIFO_REG);
629 }
630 #endif
631 
632 /* serial core callbacks */
633 static const struct uart_ops bcm_uart_ops = {
634 	.tx_empty	= bcm_uart_tx_empty,
635 	.get_mctrl	= bcm_uart_get_mctrl,
636 	.set_mctrl	= bcm_uart_set_mctrl,
637 	.start_tx	= bcm_uart_start_tx,
638 	.stop_tx	= bcm_uart_stop_tx,
639 	.stop_rx	= bcm_uart_stop_rx,
640 	.enable_ms	= bcm_uart_enable_ms,
641 	.break_ctl	= bcm_uart_break_ctl,
642 	.startup	= bcm_uart_startup,
643 	.shutdown	= bcm_uart_shutdown,
644 	.set_termios	= bcm_uart_set_termios,
645 	.type		= bcm_uart_type,
646 	.release_port	= bcm_uart_release_port,
647 	.request_port	= bcm_uart_request_port,
648 	.config_port	= bcm_uart_config_port,
649 	.verify_port	= bcm_uart_verify_port,
650 #ifdef CONFIG_CONSOLE_POLL
651 	.poll_get_char  = bcm_uart_poll_get_char,
652 	.poll_put_char  = bcm_uart_poll_put_char,
653 #endif
654 };
655 
656 
657 
658 #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
659 static void wait_for_xmitr(struct uart_port *port)
660 {
661 	unsigned int tmout;
662 
663 	/* Wait up to 10ms for the character(s) to be sent. */
664 	tmout = 10000;
665 	while (--tmout) {
666 		unsigned int val;
667 
668 		val = bcm_uart_readl(port, UART_IR_REG);
669 		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
670 			break;
671 		udelay(1);
672 	}
673 
674 	/* Wait up to 1s for flow control if necessary */
675 	if (port->flags & UPF_CONS_FLOW) {
676 		tmout = 1000000;
677 		while (--tmout) {
678 			unsigned int val;
679 
680 			val = bcm_uart_readl(port, UART_EXTINP_REG);
681 			if (val & UART_EXTINP_CTS_MASK)
682 				break;
683 			udelay(1);
684 		}
685 	}
686 }
687 
688 /*
689  * output given char
690  */
691 static void bcm_console_putchar(struct uart_port *port, unsigned char ch)
692 {
693 	wait_for_xmitr(port);
694 	bcm_uart_writel(port, ch, UART_FIFO_REG);
695 }
696 
697 /*
698  * console core request to output given string
699  */
700 static void bcm_console_write(struct console *co, const char *s,
701 			      unsigned int count)
702 {
703 	struct uart_port *port;
704 	unsigned long flags;
705 	int locked = 1;
706 
707 	port = &ports[co->index];
708 
709 	if (oops_in_progress)
710 		locked = uart_port_trylock_irqsave(port, &flags);
711 	else
712 		uart_port_lock_irqsave(port, &flags);
713 
714 	/* call helper to deal with \r\n */
715 	uart_console_write(port, s, count, bcm_console_putchar);
716 
717 	/* and wait for char to be transmitted */
718 	wait_for_xmitr(port);
719 
720 	if (locked)
721 		uart_port_unlock_irqrestore(port, flags);
722 }
723 
724 /*
725  * console core request to setup given console, find matching uart
726  * port and setup it.
727  */
728 static int bcm_console_setup(struct console *co, char *options)
729 {
730 	struct uart_port *port;
731 	int baud = 9600;
732 	int bits = 8;
733 	int parity = 'n';
734 	int flow = 'n';
735 
736 	if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
737 		return -EINVAL;
738 	port = &ports[co->index];
739 	if (!port->membase)
740 		return -ENODEV;
741 	if (options)
742 		uart_parse_options(options, &baud, &parity, &bits, &flow);
743 
744 	return uart_set_options(port, co, baud, parity, bits, flow);
745 }
746 
747 static struct uart_driver bcm_uart_driver;
748 
749 static struct console bcm63xx_console = {
750 	.name		= "ttyS",
751 	.write		= bcm_console_write,
752 	.device		= uart_console_device,
753 	.setup		= bcm_console_setup,
754 	.flags		= CON_PRINTBUFFER,
755 	.index		= -1,
756 	.data		= &bcm_uart_driver,
757 };
758 
759 static int __init bcm63xx_console_init(void)
760 {
761 	register_console(&bcm63xx_console);
762 	return 0;
763 }
764 
765 console_initcall(bcm63xx_console_init);
766 
767 static void bcm_early_write(struct console *con, const char *s, unsigned n)
768 {
769 	struct earlycon_device *dev = con->data;
770 
771 	uart_console_write(&dev->port, s, n, bcm_console_putchar);
772 	wait_for_xmitr(&dev->port);
773 }
774 
775 static int __init bcm_early_console_setup(struct earlycon_device *device,
776 					  const char *opt)
777 {
778 	if (!device->port.membase)
779 		return -ENODEV;
780 
781 	device->con->write = bcm_early_write;
782 	return 0;
783 }
784 
785 OF_EARLYCON_DECLARE(bcm63xx_uart, "brcm,bcm6345-uart", bcm_early_console_setup);
786 
787 #define BCM63XX_CONSOLE	(&bcm63xx_console)
788 #else
789 #define BCM63XX_CONSOLE	NULL
790 #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
791 
792 static struct uart_driver bcm_uart_driver = {
793 	.owner		= THIS_MODULE,
794 	.driver_name	= "bcm63xx_uart",
795 	.dev_name	= "ttyS",
796 	.major		= TTY_MAJOR,
797 	.minor		= 64,
798 	.nr		= BCM63XX_NR_UARTS,
799 	.cons		= BCM63XX_CONSOLE,
800 };
801 
802 /*
803  * platform driver probe/remove callback
804  */
805 static int bcm_uart_probe(struct platform_device *pdev)
806 {
807 	struct resource *res_mem;
808 	struct uart_port *port;
809 	struct clk *clk;
810 	int ret;
811 
812 	if (pdev->dev.of_node) {
813 		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
814 
815 		if (pdev->id < 0)
816 			pdev->id = of_alias_get_id(pdev->dev.of_node, "uart");
817 	}
818 
819 	if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
820 		return -EINVAL;
821 
822 	port = &ports[pdev->id];
823 	if (port->membase)
824 		return -EBUSY;
825 	memset(port, 0, sizeof(*port));
826 
827 	port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res_mem);
828 	if (IS_ERR(port->membase))
829 		return PTR_ERR(port->membase);
830 	port->mapbase = res_mem->start;
831 
832 	ret = platform_get_irq(pdev, 0);
833 	if (ret < 0)
834 		return ret;
835 	port->irq = ret;
836 
837 	clk = clk_get(&pdev->dev, "refclk");
838 	if (IS_ERR(clk) && pdev->dev.of_node)
839 		clk = of_clk_get(pdev->dev.of_node, 0);
840 
841 	if (IS_ERR(clk))
842 		return -ENODEV;
843 
844 	port->iotype = UPIO_MEM;
845 	port->ops = &bcm_uart_ops;
846 	port->flags = UPF_BOOT_AUTOCONF;
847 	port->dev = &pdev->dev;
848 	port->fifosize = 16;
849 	port->uartclk = clk_get_rate(clk) / 2;
850 	port->line = pdev->id;
851 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BCM63XX_CONSOLE);
852 	clk_put(clk);
853 
854 	ret = uart_add_one_port(&bcm_uart_driver, port);
855 	if (ret) {
856 		ports[pdev->id].membase = NULL;
857 		return ret;
858 	}
859 	platform_set_drvdata(pdev, port);
860 	return 0;
861 }
862 
863 static void bcm_uart_remove(struct platform_device *pdev)
864 {
865 	struct uart_port *port;
866 
867 	port = platform_get_drvdata(pdev);
868 	uart_remove_one_port(&bcm_uart_driver, port);
869 	/* mark port as free */
870 	ports[pdev->id].membase = NULL;
871 }
872 
873 static const struct of_device_id bcm63xx_of_match[] = {
874 	{ .compatible = "brcm,bcm6345-uart" },
875 	{ /* sentinel */ }
876 };
877 MODULE_DEVICE_TABLE(of, bcm63xx_of_match);
878 
879 /*
880  * platform driver stuff
881  */
882 static struct platform_driver bcm_uart_platform_driver = {
883 	.probe	= bcm_uart_probe,
884 	.remove_new = bcm_uart_remove,
885 	.driver	= {
886 		.name  = "bcm63xx_uart",
887 		.of_match_table = bcm63xx_of_match,
888 	},
889 };
890 
891 static int __init bcm_uart_init(void)
892 {
893 	int ret;
894 
895 	ret = uart_register_driver(&bcm_uart_driver);
896 	if (ret)
897 		return ret;
898 
899 	ret = platform_driver_register(&bcm_uart_platform_driver);
900 	if (ret)
901 		uart_unregister_driver(&bcm_uart_driver);
902 
903 	return ret;
904 }
905 
906 static void __exit bcm_uart_exit(void)
907 {
908 	platform_driver_unregister(&bcm_uart_platform_driver);
909 	uart_unregister_driver(&bcm_uart_driver);
910 }
911 
912 module_init(bcm_uart_init);
913 module_exit(bcm_uart_exit);
914 
915 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
916 MODULE_DESCRIPTION("Broadcom 63xx integrated uart driver");
917 MODULE_LICENSE("GPL");
918