1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * include/linux/atmel_serial.h 4 * 5 * Copyright (C) 2005 Ivan Kokshaysky 6 * Copyright (C) SAN People 7 * 8 * USART registers. 9 * Based on AT91RM9200 datasheet revision E. 10 */ 11 12 #include <linux/bitfield.h> 13 14 #ifndef ATMEL_SERIAL_H 15 #define ATMEL_SERIAL_H 16 17 #define ATMEL_US_CR 0x00 /* Control Register */ 18 #define ATMEL_US_RSTRX BIT(2) /* Reset Receiver */ 19 #define ATMEL_US_RSTTX BIT(3) /* Reset Transmitter */ 20 #define ATMEL_US_RXEN BIT(4) /* Receiver Enable */ 21 #define ATMEL_US_RXDIS BIT(5) /* Receiver Disable */ 22 #define ATMEL_US_TXEN BIT(6) /* Transmitter Enable */ 23 #define ATMEL_US_TXDIS BIT(7) /* Transmitter Disable */ 24 #define ATMEL_US_RSTSTA BIT(8) /* Reset Status Bits */ 25 #define ATMEL_US_STTBRK BIT(9) /* Start Break */ 26 #define ATMEL_US_STPBRK BIT(10) /* Stop Break */ 27 #define ATMEL_US_STTTO BIT(11) /* Start Time-out */ 28 #define ATMEL_US_SENDA BIT(12) /* Send Address */ 29 #define ATMEL_US_RSTIT BIT(13) /* Reset Iterations */ 30 #define ATMEL_US_RSTNACK BIT(14) /* Reset Non Acknowledge */ 31 #define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */ 32 #define ATMEL_US_DTREN BIT(16) /* Data Terminal Ready Enable */ 33 #define ATMEL_US_DTRDIS BIT(17) /* Data Terminal Ready Disable */ 34 #define ATMEL_US_RTSEN BIT(18) /* Request To Send Enable */ 35 #define ATMEL_US_RTSDIS BIT(19) /* Request To Send Disable */ 36 #define ATMEL_US_TXFCLR BIT(24) /* Transmit FIFO Clear */ 37 #define ATMEL_US_RXFCLR BIT(25) /* Receive FIFO Clear */ 38 #define ATMEL_US_TXFLCLR BIT(26) /* Transmit FIFO Lock Clear */ 39 #define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */ 40 #define ATMEL_US_FIFODIS BIT(31) /* FIFO disable */ 41 42 #define ATMEL_US_MR 0x04 /* Mode Register */ 43 #define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */ 44 #define ATMEL_US_USMODE_NORMAL FIELD_PREP(ATMEL_US_USMODE, 0) 45 #define ATMEL_US_USMODE_RS485 FIELD_PREP(ATMEL_US_USMODE, 1) 46 #define ATMEL_US_USMODE_HWHS FIELD_PREP(ATMEL_US_USMODE, 2) 47 #define ATMEL_US_USMODE_MODEM FIELD_PREP(ATMEL_US_USMODE, 3) 48 #define ATMEL_US_USMODE_ISO7816_T0 FIELD_PREP(ATMEL_US_USMODE, 4) 49 #define ATMEL_US_USMODE_ISO7816_T1 FIELD_PREP(ATMEL_US_USMODE, 6) 50 #define ATMEL_US_USMODE_IRDA FIELD_PREP(ATMEL_US_USMODE, 8) 51 #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ 52 #define ATMEL_US_USCLKS_MCK FIELD_PREP(ATMEL_US_USCLKS, 0) 53 #define ATMEL_US_USCLKS_MCK_DIV8 FIELD_PREP(ATMEL_US_USCLKS, 1) 54 #define ATMEL_US_USCLKS_GCLK FIELD_PREP(ATMEL_US_USCLKS, 2) 55 #define ATMEL_US_USCLKS_SCK FIELD_PREP(ATMEL_US_USCLKS, 3) 56 #define ATMEL_UA_FILTER BIT(4) 57 #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ 58 #define ATMEL_US_CHRL_5 FIELD_PREP(ATMEL_US_CHRL, 0) 59 #define ATMEL_US_CHRL_6 FIELD_PREP(ATMEL_US_CHRL, 1) 60 #define ATMEL_US_CHRL_7 FIELD_PREP(ATMEL_US_CHRL, 2) 61 #define ATMEL_US_CHRL_8 FIELD_PREP(ATMEL_US_CHRL, 3) 62 #define ATMEL_US_SYNC BIT(8) /* Synchronous Mode Select */ 63 #define ATMEL_US_PAR GENMASK(11, 9) /* Parity Type */ 64 #define ATMEL_US_PAR_EVEN FIELD_PREP(ATMEL_US_PAR, 0) 65 #define ATMEL_US_PAR_ODD FIELD_PREP(ATMEL_US_PAR, 1) 66 #define ATMEL_US_PAR_SPACE FIELD_PREP(ATMEL_US_PAR, 2) 67 #define ATMEL_US_PAR_MARK FIELD_PREP(ATMEL_US_PAR, 3) 68 #define ATMEL_US_PAR_NONE FIELD_PREP(ATMEL_US_PAR, 4) 69 #define ATMEL_US_PAR_MULTI_DROP FIELD_PREP(ATMEL_US_PAR, 6) 70 #define ATMEL_US_NBSTOP GENMASK(13, 12) /* Number of Stop Bits */ 71 #define ATMEL_US_NBSTOP_1 FIELD_PREP(ATMEL_US_NBSTOP, 0) 72 #define ATMEL_US_NBSTOP_1_5 FIELD_PREP(ATMEL_US_NBSTOP, 1) 73 #define ATMEL_US_NBSTOP_2 FIELD_PREP(ATMEL_US_NBSTOP, 2) 74 #define ATMEL_UA_BRSRCCK BIT(12) /* Clock Selection for UART */ 75 #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */ 76 #define ATMEL_US_CHMODE_NORMAL FIELD_PREP(ATMEL_US_CHMODE, 0) 77 #define ATMEL_US_CHMODE_ECHO FIELD_PREP(ATMEL_US_CHMODE, 1) 78 #define ATMEL_US_CHMODE_LOC_LOOP FIELD_PREP(ATMEL_US_CHMODE, 2) 79 #define ATMEL_US_CHMODE_REM_LOOP FIELD_PREP(ATMEL_US_CHMODE, 3) 80 #define ATMEL_US_MSBF BIT(16) /* Bit Order */ 81 #define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */ 82 #define ATMEL_US_CLKO BIT(18) /* Clock Output Select */ 83 #define ATMEL_US_OVER BIT(19) /* Oversampling Mode */ 84 #define ATMEL_US_INACK BIT(20) /* Inhibit Non Acknowledge */ 85 #define ATMEL_US_DSNACK BIT(21) /* Disable Successive NACK */ 86 #define ATMEL_US_MAX_ITER_MASK GENMASK(26, 24) /* Max Iterations */ 87 #define ATMEL_US_MAX_ITER(n) FIELD_PREP(ATMEL_US_MAX_ITER_MASK, (n)) 88 #define ATMEL_US_FILTER BIT(28) /* Infrared Receive Line Filter */ 89 90 #define ATMEL_US_IER 0x08 /* Interrupt Enable Register */ 91 #define ATMEL_US_RXRDY BIT(0) /* Receiver Ready */ 92 #define ATMEL_US_TXRDY BIT(1) /* Transmitter Ready */ 93 #define ATMEL_US_RXBRK BIT(2) /* Break Received / End of Break */ 94 #define ATMEL_US_ENDRX BIT(3) /* End of Receiver Transfer */ 95 #define ATMEL_US_ENDTX BIT(4) /* End of Transmitter Transfer */ 96 #define ATMEL_US_OVRE BIT(5) /* Overrun Error */ 97 #define ATMEL_US_FRAME BIT(6) /* Framing Error */ 98 #define ATMEL_US_PARE BIT(7) /* Parity Error */ 99 #define ATMEL_US_TIMEOUT BIT(8) /* Receiver Time-out */ 100 #define ATMEL_US_TXEMPTY BIT(9) /* Transmitter Empty */ 101 #define ATMEL_US_ITERATION BIT(10) /* Max number of Repetitions Reached */ 102 #define ATMEL_US_TXBUFE BIT(11) /* Transmission Buffer Empty */ 103 #define ATMEL_US_RXBUFF BIT(12) /* Reception Buffer Full */ 104 #define ATMEL_US_NACK BIT(13) /* Non Acknowledge */ 105 #define ATMEL_US_RIIC BIT(16) /* Ring Indicator Input Change */ 106 #define ATMEL_US_DSRIC BIT(17) /* Data Set Ready Input Change */ 107 #define ATMEL_US_DCDIC BIT(18) /* Data Carrier Detect Input Change */ 108 #define ATMEL_US_CTSIC BIT(19) /* Clear to Send Input Change */ 109 #define ATMEL_US_RI BIT(20) /* RI */ 110 #define ATMEL_US_DSR BIT(21) /* DSR */ 111 #define ATMEL_US_DCD BIT(22) /* DCD */ 112 #define ATMEL_US_CTS BIT(23) /* CTS */ 113 114 #define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */ 115 #define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */ 116 #define ATMEL_US_CSR 0x14 /* Channel Status Register */ 117 #define ATMEL_US_RHR 0x18 /* Receiver Holding Register */ 118 #define ATMEL_US_THR 0x1c /* Transmitter Holding Register */ 119 #define ATMEL_US_SYNH BIT(15) /* Transmit/Receive Sync */ 120 121 #define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ 122 #define ATMEL_US_CD GENMASK(15, 0) /* Clock Divider */ 123 #define ATMEL_US_FP_OFFSET 16 /* Fractional Part */ 124 #define ATMEL_US_FP_MASK 0x7 125 126 #define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register for USART */ 127 #define ATMEL_UA_RTOR 0x28 /* Receiver Time-out Register for UART */ 128 #define ATMEL_US_TO GENMASK(15, 0) /* Time-out Value */ 129 130 #define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */ 131 #define ATMEL_US_TG GENMASK(7, 0) /* Timeguard Value */ 132 133 #define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */ 134 #define ATMEL_US_NER 0x44 /* Number of Errors Register */ 135 #define ATMEL_US_IF 0x4c /* IrDA Filter Register */ 136 137 #define ATMEL_US_CMPR 0x90 /* Comparaison Register */ 138 #define ATMEL_US_FMR 0xa0 /* FIFO Mode Register */ 139 #define ATMEL_US_TXRDYM(data) FIELD_PREP(GENMASK(1, 0), (data)) /* TX Ready Mode */ 140 #define ATMEL_US_RXRDYM(data) FIELD_PREP(GENMASK(5, 4), (data)) /* RX Ready Mode */ 141 #define ATMEL_US_ONE_DATA 0x0 142 #define ATMEL_US_TWO_DATA 0x1 143 #define ATMEL_US_FOUR_DATA 0x2 144 #define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */ 145 #define ATMEL_US_TXFTHRES(thr) FIELD_PREP(GENMASK(13, 8), (thr)) /* TX FIFO Threshold */ 146 #define ATMEL_US_RXFTHRES(thr) FIELD_PREP(GENMASK(21, 16), (thr)) /* RX FIFO Threshold */ 147 #define ATMEL_US_RXFTHRES2(thr) FIELD_PREP(GENMASK(29, 24), (thr)) /* RX FIFO Threshold2 */ 148 149 #define ATMEL_US_FLR 0xa4 /* FIFO Level Register */ 150 #define ATMEL_US_TXFL(reg) FIELD_GET(GENMASK(5, 0), (reg)) /* TX FIFO Level */ 151 #define ATMEL_US_RXFL(reg) FIELD_GET(GENMASK(21, 16), (reg)) /* RX FIFO Level */ 152 153 #define ATMEL_US_FIER 0xa8 /* FIFO Interrupt Enable Register */ 154 #define ATMEL_US_FIDR 0xac /* FIFO Interrupt Disable Register */ 155 #define ATMEL_US_FIMR 0xb0 /* FIFO Interrupt Mask Register */ 156 #define ATMEL_US_FESR 0xb4 /* FIFO Event Status Register */ 157 #define ATMEL_US_TXFEF BIT(0) /* Transmit FIFO Empty Flag */ 158 #define ATMEL_US_TXFFF BIT(1) /* Transmit FIFO Full Flag */ 159 #define ATMEL_US_TXFTHF BIT(2) /* Transmit FIFO Threshold Flag */ 160 #define ATMEL_US_RXFEF BIT(3) /* Receive FIFO Empty Flag */ 161 #define ATMEL_US_RXFFF BIT(4) /* Receive FIFO Full Flag */ 162 #define ATMEL_US_RXFTHF BIT(5) /* Receive FIFO Threshold Flag */ 163 #define ATMEL_US_TXFPTEF BIT(6) /* Transmit FIFO Pointer Error Flag */ 164 #define ATMEL_US_RXFPTEF BIT(7) /* Receive FIFO Pointer Error Flag */ 165 #define ATMEL_US_TXFLOCK BIT(8) /* Transmit FIFO Lock (FESR only) */ 166 #define ATMEL_US_RXFTHF2 BIT(9) /* Receive FIFO Threshold Flag 2 */ 167 168 #define ATMEL_US_NAME 0xf0 /* Ip Name */ 169 #define ATMEL_US_VERSION 0xfc /* Ip Version */ 170 171 #endif 172