1 /* 2 * Driver for Atmel AT91 / AT32 Serial ports 3 * Copyright (C) 2003 Rick Bronson 4 * 5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * DMA support added by Chip Coldwell. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 #include <linux/tty.h> 26 #include <linux/ioport.h> 27 #include <linux/slab.h> 28 #include <linux/init.h> 29 #include <linux/serial.h> 30 #include <linux/clk.h> 31 #include <linux/console.h> 32 #include <linux/sysrq.h> 33 #include <linux/tty_flip.h> 34 #include <linux/platform_device.h> 35 #include <linux/of.h> 36 #include <linux/of_device.h> 37 #include <linux/of_gpio.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/dmaengine.h> 40 #include <linux/atmel_pdc.h> 41 #include <linux/atmel_serial.h> 42 #include <linux/uaccess.h> 43 #include <linux/platform_data/atmel.h> 44 #include <linux/timer.h> 45 #include <linux/gpio.h> 46 #include <linux/gpio/consumer.h> 47 #include <linux/err.h> 48 #include <linux/irq.h> 49 #include <linux/suspend.h> 50 51 #include <asm/io.h> 52 #include <asm/ioctls.h> 53 54 #define PDC_BUFFER_SIZE 512 55 /* Revisit: We should calculate this based on the actual port settings */ 56 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 57 58 /* The minium number of data FIFOs should be able to contain */ 59 #define ATMEL_MIN_FIFO_SIZE 8 60 /* 61 * These two offsets are substracted from the RX FIFO size to define the RTS 62 * high and low thresholds 63 */ 64 #define ATMEL_RTS_HIGH_OFFSET 16 65 #define ATMEL_RTS_LOW_OFFSET 20 66 67 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 68 #define SUPPORT_SYSRQ 69 #endif 70 71 #include <linux/serial_core.h> 72 73 #include "serial_mctrl_gpio.h" 74 75 static void atmel_start_rx(struct uart_port *port); 76 static void atmel_stop_rx(struct uart_port *port); 77 78 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 79 80 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 81 * should coexist with the 8250 driver, such as if we have an external 16C550 82 * UART. */ 83 #define SERIAL_ATMEL_MAJOR 204 84 #define MINOR_START 154 85 #define ATMEL_DEVICENAME "ttyAT" 86 87 #else 88 89 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 90 * name, but it is legally reserved for the 8250 driver. */ 91 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 92 #define MINOR_START 64 93 #define ATMEL_DEVICENAME "ttyS" 94 95 #endif 96 97 #define ATMEL_ISR_PASS_LIMIT 256 98 99 struct atmel_dma_buffer { 100 unsigned char *buf; 101 dma_addr_t dma_addr; 102 unsigned int dma_size; 103 unsigned int ofs; 104 }; 105 106 struct atmel_uart_char { 107 u16 status; 108 u16 ch; 109 }; 110 111 #define ATMEL_SERIAL_RINGSIZE 1024 112 113 /* 114 * at91: 6 USARTs and one DBGU port (SAM9260) 115 * avr32: 4 116 */ 117 #define ATMEL_MAX_UART 7 118 119 /* 120 * We wrap our port structure around the generic uart_port. 121 */ 122 struct atmel_uart_port { 123 struct uart_port uart; /* uart */ 124 struct clk *clk; /* uart clock */ 125 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 126 u32 backup_imr; /* IMR saved during suspend */ 127 int break_active; /* break being received */ 128 129 bool use_dma_rx; /* enable DMA receiver */ 130 bool use_pdc_rx; /* enable PDC receiver */ 131 short pdc_rx_idx; /* current PDC RX buffer */ 132 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 133 134 bool use_dma_tx; /* enable DMA transmitter */ 135 bool use_pdc_tx; /* enable PDC transmitter */ 136 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 137 138 spinlock_t lock_tx; /* port lock */ 139 spinlock_t lock_rx; /* port lock */ 140 struct dma_chan *chan_tx; 141 struct dma_chan *chan_rx; 142 struct dma_async_tx_descriptor *desc_tx; 143 struct dma_async_tx_descriptor *desc_rx; 144 dma_cookie_t cookie_tx; 145 dma_cookie_t cookie_rx; 146 struct scatterlist sg_tx; 147 struct scatterlist sg_rx; 148 struct tasklet_struct tasklet; 149 unsigned int irq_status; 150 unsigned int irq_status_prev; 151 unsigned int status_change; 152 unsigned int tx_len; 153 154 struct circ_buf rx_ring; 155 156 struct mctrl_gpios *gpios; 157 unsigned int tx_done_mask; 158 u32 fifo_size; 159 u32 rts_high; 160 u32 rts_low; 161 bool ms_irq_enabled; 162 u32 rtor; /* address of receiver timeout register if it exists */ 163 bool has_hw_timer; 164 struct timer_list uart_timer; 165 166 bool suspended; 167 unsigned int pending; 168 unsigned int pending_status; 169 spinlock_t lock_suspended; 170 171 int (*prepare_rx)(struct uart_port *port); 172 int (*prepare_tx)(struct uart_port *port); 173 void (*schedule_rx)(struct uart_port *port); 174 void (*schedule_tx)(struct uart_port *port); 175 void (*release_rx)(struct uart_port *port); 176 void (*release_tx)(struct uart_port *port); 177 }; 178 179 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 180 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 181 182 #ifdef SUPPORT_SYSRQ 183 static struct console atmel_console; 184 #endif 185 186 #if defined(CONFIG_OF) 187 static const struct of_device_id atmel_serial_dt_ids[] = { 188 { .compatible = "atmel,at91rm9200-usart" }, 189 { .compatible = "atmel,at91sam9260-usart" }, 190 { /* sentinel */ } 191 }; 192 #endif 193 194 static inline struct atmel_uart_port * 195 to_atmel_uart_port(struct uart_port *uart) 196 { 197 return container_of(uart, struct atmel_uart_port, uart); 198 } 199 200 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) 201 { 202 return __raw_readl(port->membase + reg); 203 } 204 205 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) 206 { 207 __raw_writel(value, port->membase + reg); 208 } 209 210 #ifdef CONFIG_AVR32 211 212 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */ 213 static inline u8 atmel_uart_read_char(struct uart_port *port) 214 { 215 return __raw_readl(port->membase + ATMEL_US_RHR); 216 } 217 218 static inline void atmel_uart_write_char(struct uart_port *port, u8 value) 219 { 220 __raw_writel(value, port->membase + ATMEL_US_THR); 221 } 222 223 #else 224 225 static inline u8 atmel_uart_read_char(struct uart_port *port) 226 { 227 return __raw_readb(port->membase + ATMEL_US_RHR); 228 } 229 230 static inline void atmel_uart_write_char(struct uart_port *port, u8 value) 231 { 232 __raw_writeb(value, port->membase + ATMEL_US_THR); 233 } 234 235 #endif 236 237 #ifdef CONFIG_SERIAL_ATMEL_PDC 238 static bool atmel_use_pdc_rx(struct uart_port *port) 239 { 240 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 241 242 return atmel_port->use_pdc_rx; 243 } 244 245 static bool atmel_use_pdc_tx(struct uart_port *port) 246 { 247 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 248 249 return atmel_port->use_pdc_tx; 250 } 251 #else 252 static bool atmel_use_pdc_rx(struct uart_port *port) 253 { 254 return false; 255 } 256 257 static bool atmel_use_pdc_tx(struct uart_port *port) 258 { 259 return false; 260 } 261 #endif 262 263 static bool atmel_use_dma_tx(struct uart_port *port) 264 { 265 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 266 267 return atmel_port->use_dma_tx; 268 } 269 270 static bool atmel_use_dma_rx(struct uart_port *port) 271 { 272 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 273 274 return atmel_port->use_dma_rx; 275 } 276 277 static unsigned int atmel_get_lines_status(struct uart_port *port) 278 { 279 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 280 unsigned int status, ret = 0; 281 282 status = atmel_uart_readl(port, ATMEL_US_CSR); 283 284 mctrl_gpio_get(atmel_port->gpios, &ret); 285 286 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 287 UART_GPIO_CTS))) { 288 if (ret & TIOCM_CTS) 289 status &= ~ATMEL_US_CTS; 290 else 291 status |= ATMEL_US_CTS; 292 } 293 294 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 295 UART_GPIO_DSR))) { 296 if (ret & TIOCM_DSR) 297 status &= ~ATMEL_US_DSR; 298 else 299 status |= ATMEL_US_DSR; 300 } 301 302 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 303 UART_GPIO_RI))) { 304 if (ret & TIOCM_RI) 305 status &= ~ATMEL_US_RI; 306 else 307 status |= ATMEL_US_RI; 308 } 309 310 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, 311 UART_GPIO_DCD))) { 312 if (ret & TIOCM_CD) 313 status &= ~ATMEL_US_DCD; 314 else 315 status |= ATMEL_US_DCD; 316 } 317 318 return status; 319 } 320 321 /* Enable or disable the rs485 support */ 322 static int atmel_config_rs485(struct uart_port *port, 323 struct serial_rs485 *rs485conf) 324 { 325 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 326 unsigned int mode; 327 328 /* Disable interrupts */ 329 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 330 331 mode = atmel_uart_readl(port, ATMEL_US_MR); 332 333 /* Resetting serial mode to RS232 (0x0) */ 334 mode &= ~ATMEL_US_USMODE; 335 336 port->rs485 = *rs485conf; 337 338 if (rs485conf->flags & SER_RS485_ENABLED) { 339 dev_dbg(port->dev, "Setting UART to RS485\n"); 340 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 341 atmel_uart_writel(port, ATMEL_US_TTGR, 342 rs485conf->delay_rts_after_send); 343 mode |= ATMEL_US_USMODE_RS485; 344 } else { 345 dev_dbg(port->dev, "Setting UART to RS232\n"); 346 if (atmel_use_pdc_tx(port)) 347 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 348 ATMEL_US_TXBUFE; 349 else 350 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 351 } 352 atmel_uart_writel(port, ATMEL_US_MR, mode); 353 354 /* Enable interrupts */ 355 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 356 357 return 0; 358 } 359 360 /* 361 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 362 */ 363 static u_int atmel_tx_empty(struct uart_port *port) 364 { 365 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ? 366 TIOCSER_TEMT : 367 0; 368 } 369 370 /* 371 * Set state of the modem control output lines 372 */ 373 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 374 { 375 unsigned int control = 0; 376 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR); 377 unsigned int rts_paused, rts_ready; 378 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 379 380 /* override mode to RS485 if needed, otherwise keep the current mode */ 381 if (port->rs485.flags & SER_RS485_ENABLED) { 382 atmel_uart_writel(port, ATMEL_US_TTGR, 383 port->rs485.delay_rts_after_send); 384 mode &= ~ATMEL_US_USMODE; 385 mode |= ATMEL_US_USMODE_RS485; 386 } 387 388 /* set the RTS line state according to the mode */ 389 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 390 /* force RTS line to high level */ 391 rts_paused = ATMEL_US_RTSEN; 392 393 /* give the control of the RTS line back to the hardware */ 394 rts_ready = ATMEL_US_RTSDIS; 395 } else { 396 /* force RTS line to high level */ 397 rts_paused = ATMEL_US_RTSDIS; 398 399 /* force RTS line to low level */ 400 rts_ready = ATMEL_US_RTSEN; 401 } 402 403 if (mctrl & TIOCM_RTS) 404 control |= rts_ready; 405 else 406 control |= rts_paused; 407 408 if (mctrl & TIOCM_DTR) 409 control |= ATMEL_US_DTREN; 410 else 411 control |= ATMEL_US_DTRDIS; 412 413 atmel_uart_writel(port, ATMEL_US_CR, control); 414 415 mctrl_gpio_set(atmel_port->gpios, mctrl); 416 417 /* Local loopback mode? */ 418 mode &= ~ATMEL_US_CHMODE; 419 if (mctrl & TIOCM_LOOP) 420 mode |= ATMEL_US_CHMODE_LOC_LOOP; 421 else 422 mode |= ATMEL_US_CHMODE_NORMAL; 423 424 atmel_uart_writel(port, ATMEL_US_MR, mode); 425 } 426 427 /* 428 * Get state of the modem control input lines 429 */ 430 static u_int atmel_get_mctrl(struct uart_port *port) 431 { 432 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 433 unsigned int ret = 0, status; 434 435 status = atmel_uart_readl(port, ATMEL_US_CSR); 436 437 /* 438 * The control signals are active low. 439 */ 440 if (!(status & ATMEL_US_DCD)) 441 ret |= TIOCM_CD; 442 if (!(status & ATMEL_US_CTS)) 443 ret |= TIOCM_CTS; 444 if (!(status & ATMEL_US_DSR)) 445 ret |= TIOCM_DSR; 446 if (!(status & ATMEL_US_RI)) 447 ret |= TIOCM_RI; 448 449 return mctrl_gpio_get(atmel_port->gpios, &ret); 450 } 451 452 /* 453 * Stop transmitting. 454 */ 455 static void atmel_stop_tx(struct uart_port *port) 456 { 457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 458 459 if (atmel_use_pdc_tx(port)) { 460 /* disable PDC transmit */ 461 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 462 } 463 /* Disable interrupts */ 464 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 465 466 if ((port->rs485.flags & SER_RS485_ENABLED) && 467 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 468 atmel_start_rx(port); 469 } 470 471 /* 472 * Start transmitting. 473 */ 474 static void atmel_start_tx(struct uart_port *port) 475 { 476 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 477 478 if (atmel_use_pdc_tx(port)) { 479 if (atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN) 480 /* The transmitter is already running. Yes, we 481 really need this.*/ 482 return; 483 484 if ((port->rs485.flags & SER_RS485_ENABLED) && 485 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 486 atmel_stop_rx(port); 487 488 /* re-enable PDC transmit */ 489 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 490 } 491 /* Enable interrupts */ 492 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 493 } 494 495 /* 496 * start receiving - port is in process of being opened. 497 */ 498 static void atmel_start_rx(struct uart_port *port) 499 { 500 /* reset status and receiver */ 501 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 502 503 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN); 504 505 if (atmel_use_pdc_rx(port)) { 506 /* enable PDC controller */ 507 atmel_uart_writel(port, ATMEL_US_IER, 508 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 509 port->read_status_mask); 510 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 511 } else { 512 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 513 } 514 } 515 516 /* 517 * Stop receiving - port is in process of being closed. 518 */ 519 static void atmel_stop_rx(struct uart_port *port) 520 { 521 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS); 522 523 if (atmel_use_pdc_rx(port)) { 524 /* disable PDC receive */ 525 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS); 526 atmel_uart_writel(port, ATMEL_US_IDR, 527 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 528 port->read_status_mask); 529 } else { 530 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY); 531 } 532 } 533 534 /* 535 * Enable modem status interrupts 536 */ 537 static void atmel_enable_ms(struct uart_port *port) 538 { 539 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 540 uint32_t ier = 0; 541 542 /* 543 * Interrupt should not be enabled twice 544 */ 545 if (atmel_port->ms_irq_enabled) 546 return; 547 548 atmel_port->ms_irq_enabled = true; 549 550 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 551 ier |= ATMEL_US_CTSIC; 552 553 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 554 ier |= ATMEL_US_DSRIC; 555 556 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 557 ier |= ATMEL_US_RIIC; 558 559 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 560 ier |= ATMEL_US_DCDIC; 561 562 atmel_uart_writel(port, ATMEL_US_IER, ier); 563 564 mctrl_gpio_enable_ms(atmel_port->gpios); 565 } 566 567 /* 568 * Disable modem status interrupts 569 */ 570 static void atmel_disable_ms(struct uart_port *port) 571 { 572 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 573 uint32_t idr = 0; 574 575 /* 576 * Interrupt should not be disabled twice 577 */ 578 if (!atmel_port->ms_irq_enabled) 579 return; 580 581 atmel_port->ms_irq_enabled = false; 582 583 mctrl_gpio_disable_ms(atmel_port->gpios); 584 585 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 586 idr |= ATMEL_US_CTSIC; 587 588 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 589 idr |= ATMEL_US_DSRIC; 590 591 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 592 idr |= ATMEL_US_RIIC; 593 594 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 595 idr |= ATMEL_US_DCDIC; 596 597 atmel_uart_writel(port, ATMEL_US_IDR, idr); 598 } 599 600 /* 601 * Control the transmission of a break signal 602 */ 603 static void atmel_break_ctl(struct uart_port *port, int break_state) 604 { 605 if (break_state != 0) 606 /* start break */ 607 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK); 608 else 609 /* stop break */ 610 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK); 611 } 612 613 /* 614 * Stores the incoming character in the ring buffer 615 */ 616 static void 617 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 618 unsigned int ch) 619 { 620 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 621 struct circ_buf *ring = &atmel_port->rx_ring; 622 struct atmel_uart_char *c; 623 624 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 625 /* Buffer overflow, ignore char */ 626 return; 627 628 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 629 c->status = status; 630 c->ch = ch; 631 632 /* Make sure the character is stored before we update head. */ 633 smp_wmb(); 634 635 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 636 } 637 638 /* 639 * Deal with parity, framing and overrun errors. 640 */ 641 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 642 { 643 /* clear error */ 644 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 645 646 if (status & ATMEL_US_RXBRK) { 647 /* ignore side-effect */ 648 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 649 port->icount.brk++; 650 } 651 if (status & ATMEL_US_PARE) 652 port->icount.parity++; 653 if (status & ATMEL_US_FRAME) 654 port->icount.frame++; 655 if (status & ATMEL_US_OVRE) 656 port->icount.overrun++; 657 } 658 659 /* 660 * Characters received (called from interrupt handler) 661 */ 662 static void atmel_rx_chars(struct uart_port *port) 663 { 664 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 665 unsigned int status, ch; 666 667 status = atmel_uart_readl(port, ATMEL_US_CSR); 668 while (status & ATMEL_US_RXRDY) { 669 ch = atmel_uart_read_char(port); 670 671 /* 672 * note that the error handling code is 673 * out of the main execution path 674 */ 675 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 676 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 677 || atmel_port->break_active)) { 678 679 /* clear error */ 680 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 681 682 if (status & ATMEL_US_RXBRK 683 && !atmel_port->break_active) { 684 atmel_port->break_active = 1; 685 atmel_uart_writel(port, ATMEL_US_IER, 686 ATMEL_US_RXBRK); 687 } else { 688 /* 689 * This is either the end-of-break 690 * condition or we've received at 691 * least one character without RXBRK 692 * being set. In both cases, the next 693 * RXBRK will indicate start-of-break. 694 */ 695 atmel_uart_writel(port, ATMEL_US_IDR, 696 ATMEL_US_RXBRK); 697 status &= ~ATMEL_US_RXBRK; 698 atmel_port->break_active = 0; 699 } 700 } 701 702 atmel_buffer_rx_char(port, status, ch); 703 status = atmel_uart_readl(port, ATMEL_US_CSR); 704 } 705 706 tasklet_schedule(&atmel_port->tasklet); 707 } 708 709 /* 710 * Transmit characters (called from tasklet with TXRDY interrupt 711 * disabled) 712 */ 713 static void atmel_tx_chars(struct uart_port *port) 714 { 715 struct circ_buf *xmit = &port->state->xmit; 716 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 717 718 if (port->x_char && 719 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) { 720 atmel_uart_write_char(port, port->x_char); 721 port->icount.tx++; 722 port->x_char = 0; 723 } 724 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 725 return; 726 727 while (atmel_uart_readl(port, ATMEL_US_CSR) & 728 atmel_port->tx_done_mask) { 729 atmel_uart_write_char(port, xmit->buf[xmit->tail]); 730 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 731 port->icount.tx++; 732 if (uart_circ_empty(xmit)) 733 break; 734 } 735 736 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 737 uart_write_wakeup(port); 738 739 if (!uart_circ_empty(xmit)) 740 /* Enable interrupts */ 741 atmel_uart_writel(port, ATMEL_US_IER, 742 atmel_port->tx_done_mask); 743 } 744 745 static void atmel_complete_tx_dma(void *arg) 746 { 747 struct atmel_uart_port *atmel_port = arg; 748 struct uart_port *port = &atmel_port->uart; 749 struct circ_buf *xmit = &port->state->xmit; 750 struct dma_chan *chan = atmel_port->chan_tx; 751 unsigned long flags; 752 753 spin_lock_irqsave(&port->lock, flags); 754 755 if (chan) 756 dmaengine_terminate_all(chan); 757 xmit->tail += atmel_port->tx_len; 758 xmit->tail &= UART_XMIT_SIZE - 1; 759 760 port->icount.tx += atmel_port->tx_len; 761 762 spin_lock_irq(&atmel_port->lock_tx); 763 async_tx_ack(atmel_port->desc_tx); 764 atmel_port->cookie_tx = -EINVAL; 765 atmel_port->desc_tx = NULL; 766 spin_unlock_irq(&atmel_port->lock_tx); 767 768 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 769 uart_write_wakeup(port); 770 771 /* 772 * xmit is a circular buffer so, if we have just send data from 773 * xmit->tail to the end of xmit->buf, now we have to transmit the 774 * remaining data from the beginning of xmit->buf to xmit->head. 775 */ 776 if (!uart_circ_empty(xmit)) 777 tasklet_schedule(&atmel_port->tasklet); 778 779 spin_unlock_irqrestore(&port->lock, flags); 780 } 781 782 static void atmel_release_tx_dma(struct uart_port *port) 783 { 784 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 785 struct dma_chan *chan = atmel_port->chan_tx; 786 787 if (chan) { 788 dmaengine_terminate_all(chan); 789 dma_release_channel(chan); 790 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 791 DMA_TO_DEVICE); 792 } 793 794 atmel_port->desc_tx = NULL; 795 atmel_port->chan_tx = NULL; 796 atmel_port->cookie_tx = -EINVAL; 797 } 798 799 /* 800 * Called from tasklet with TXRDY interrupt is disabled. 801 */ 802 static void atmel_tx_dma(struct uart_port *port) 803 { 804 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 805 struct circ_buf *xmit = &port->state->xmit; 806 struct dma_chan *chan = atmel_port->chan_tx; 807 struct dma_async_tx_descriptor *desc; 808 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx; 809 unsigned int tx_len, part1_len, part2_len, sg_len; 810 dma_addr_t phys_addr; 811 812 /* Make sure we have an idle channel */ 813 if (atmel_port->desc_tx != NULL) 814 return; 815 816 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 817 /* 818 * DMA is idle now. 819 * Port xmit buffer is already mapped, 820 * and it is one page... Just adjust 821 * offsets and lengths. Since it is a circular buffer, 822 * we have to transmit till the end, and then the rest. 823 * Take the port lock to get a 824 * consistent xmit buffer state. 825 */ 826 tx_len = CIRC_CNT_TO_END(xmit->head, 827 xmit->tail, 828 UART_XMIT_SIZE); 829 830 if (atmel_port->fifo_size) { 831 /* multi data mode */ 832 part1_len = (tx_len & ~0x3); /* DWORD access */ 833 part2_len = (tx_len & 0x3); /* BYTE access */ 834 } else { 835 /* single data (legacy) mode */ 836 part1_len = 0; 837 part2_len = tx_len; /* BYTE access only */ 838 } 839 840 sg_init_table(sgl, 2); 841 sg_len = 0; 842 phys_addr = sg_dma_address(sg_tx) + xmit->tail; 843 if (part1_len) { 844 sg = &sgl[sg_len++]; 845 sg_dma_address(sg) = phys_addr; 846 sg_dma_len(sg) = part1_len; 847 848 phys_addr += part1_len; 849 } 850 851 if (part2_len) { 852 sg = &sgl[sg_len++]; 853 sg_dma_address(sg) = phys_addr; 854 sg_dma_len(sg) = part2_len; 855 } 856 857 /* 858 * save tx_len so atmel_complete_tx_dma() will increase 859 * xmit->tail correctly 860 */ 861 atmel_port->tx_len = tx_len; 862 863 desc = dmaengine_prep_slave_sg(chan, 864 sgl, 865 sg_len, 866 DMA_MEM_TO_DEV, 867 DMA_PREP_INTERRUPT | 868 DMA_CTRL_ACK); 869 if (!desc) { 870 dev_err(port->dev, "Failed to send via dma!\n"); 871 return; 872 } 873 874 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE); 875 876 atmel_port->desc_tx = desc; 877 desc->callback = atmel_complete_tx_dma; 878 desc->callback_param = atmel_port; 879 atmel_port->cookie_tx = dmaengine_submit(desc); 880 881 } else { 882 if (port->rs485.flags & SER_RS485_ENABLED) { 883 /* DMA done, stop TX, start RX for RS485 */ 884 atmel_start_rx(port); 885 } 886 } 887 888 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 889 uart_write_wakeup(port); 890 } 891 892 static int atmel_prepare_tx_dma(struct uart_port *port) 893 { 894 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 895 dma_cap_mask_t mask; 896 struct dma_slave_config config; 897 int ret, nent; 898 899 dma_cap_zero(mask); 900 dma_cap_set(DMA_SLAVE, mask); 901 902 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); 903 if (atmel_port->chan_tx == NULL) 904 goto chan_err; 905 dev_info(port->dev, "using %s for tx DMA transfers\n", 906 dma_chan_name(atmel_port->chan_tx)); 907 908 spin_lock_init(&atmel_port->lock_tx); 909 sg_init_table(&atmel_port->sg_tx, 1); 910 /* UART circular tx buffer is an aligned page. */ 911 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 912 sg_set_page(&atmel_port->sg_tx, 913 virt_to_page(port->state->xmit.buf), 914 UART_XMIT_SIZE, 915 (unsigned long)port->state->xmit.buf & ~PAGE_MASK); 916 nent = dma_map_sg(port->dev, 917 &atmel_port->sg_tx, 918 1, 919 DMA_TO_DEVICE); 920 921 if (!nent) { 922 dev_dbg(port->dev, "need to release resource of dma\n"); 923 goto chan_err; 924 } else { 925 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 926 sg_dma_len(&atmel_port->sg_tx), 927 port->state->xmit.buf, 928 &sg_dma_address(&atmel_port->sg_tx)); 929 } 930 931 /* Configure the slave DMA */ 932 memset(&config, 0, sizeof(config)); 933 config.direction = DMA_MEM_TO_DEV; 934 config.dst_addr_width = (atmel_port->fifo_size) ? 935 DMA_SLAVE_BUSWIDTH_4_BYTES : 936 DMA_SLAVE_BUSWIDTH_1_BYTE; 937 config.dst_addr = port->mapbase + ATMEL_US_THR; 938 config.dst_maxburst = 1; 939 940 ret = dmaengine_slave_config(atmel_port->chan_tx, 941 &config); 942 if (ret) { 943 dev_err(port->dev, "DMA tx slave configuration failed\n"); 944 goto chan_err; 945 } 946 947 return 0; 948 949 chan_err: 950 dev_err(port->dev, "TX channel not available, switch to pio\n"); 951 atmel_port->use_dma_tx = 0; 952 if (atmel_port->chan_tx) 953 atmel_release_tx_dma(port); 954 return -EINVAL; 955 } 956 957 static void atmel_complete_rx_dma(void *arg) 958 { 959 struct uart_port *port = arg; 960 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 961 962 tasklet_schedule(&atmel_port->tasklet); 963 } 964 965 static void atmel_release_rx_dma(struct uart_port *port) 966 { 967 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 968 struct dma_chan *chan = atmel_port->chan_rx; 969 970 if (chan) { 971 dmaengine_terminate_all(chan); 972 dma_release_channel(chan); 973 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 974 DMA_FROM_DEVICE); 975 } 976 977 atmel_port->desc_rx = NULL; 978 atmel_port->chan_rx = NULL; 979 atmel_port->cookie_rx = -EINVAL; 980 } 981 982 static void atmel_rx_from_dma(struct uart_port *port) 983 { 984 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 985 struct tty_port *tport = &port->state->port; 986 struct circ_buf *ring = &atmel_port->rx_ring; 987 struct dma_chan *chan = atmel_port->chan_rx; 988 struct dma_tx_state state; 989 enum dma_status dmastat; 990 size_t count; 991 992 993 /* Reset the UART timeout early so that we don't miss one */ 994 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 995 dmastat = dmaengine_tx_status(chan, 996 atmel_port->cookie_rx, 997 &state); 998 /* Restart a new tasklet if DMA status is error */ 999 if (dmastat == DMA_ERROR) { 1000 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 1001 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1002 tasklet_schedule(&atmel_port->tasklet); 1003 return; 1004 } 1005 1006 /* CPU claims ownership of RX DMA buffer */ 1007 dma_sync_sg_for_cpu(port->dev, 1008 &atmel_port->sg_rx, 1009 1, 1010 DMA_FROM_DEVICE); 1011 1012 /* 1013 * ring->head points to the end of data already written by the DMA. 1014 * ring->tail points to the beginning of data to be read by the 1015 * framework. 1016 * The current transfer size should not be larger than the dma buffer 1017 * length. 1018 */ 1019 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 1020 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 1021 /* 1022 * At this point ring->head may point to the first byte right after the 1023 * last byte of the dma buffer: 1024 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 1025 * 1026 * However ring->tail must always points inside the dma buffer: 1027 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 1028 * 1029 * Since we use a ring buffer, we have to handle the case 1030 * where head is lower than tail. In such a case, we first read from 1031 * tail to the end of the buffer then reset tail. 1032 */ 1033 if (ring->head < ring->tail) { 1034 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 1035 1036 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1037 ring->tail = 0; 1038 port->icount.rx += count; 1039 } 1040 1041 /* Finally we read data from tail to head */ 1042 if (ring->tail < ring->head) { 1043 count = ring->head - ring->tail; 1044 1045 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1046 /* Wrap ring->head if needed */ 1047 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 1048 ring->head = 0; 1049 ring->tail = ring->head; 1050 port->icount.rx += count; 1051 } 1052 1053 /* USART retreives ownership of RX DMA buffer */ 1054 dma_sync_sg_for_device(port->dev, 1055 &atmel_port->sg_rx, 1056 1, 1057 DMA_FROM_DEVICE); 1058 1059 /* 1060 * Drop the lock here since it might end up calling 1061 * uart_start(), which takes the lock. 1062 */ 1063 spin_unlock(&port->lock); 1064 tty_flip_buffer_push(tport); 1065 spin_lock(&port->lock); 1066 1067 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1068 } 1069 1070 static int atmel_prepare_rx_dma(struct uart_port *port) 1071 { 1072 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1073 struct dma_async_tx_descriptor *desc; 1074 dma_cap_mask_t mask; 1075 struct dma_slave_config config; 1076 struct circ_buf *ring; 1077 int ret, nent; 1078 1079 ring = &atmel_port->rx_ring; 1080 1081 dma_cap_zero(mask); 1082 dma_cap_set(DMA_CYCLIC, mask); 1083 1084 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); 1085 if (atmel_port->chan_rx == NULL) 1086 goto chan_err; 1087 dev_info(port->dev, "using %s for rx DMA transfers\n", 1088 dma_chan_name(atmel_port->chan_rx)); 1089 1090 spin_lock_init(&atmel_port->lock_rx); 1091 sg_init_table(&atmel_port->sg_rx, 1); 1092 /* UART circular rx buffer is an aligned page. */ 1093 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1094 sg_set_page(&atmel_port->sg_rx, 1095 virt_to_page(ring->buf), 1096 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1097 (unsigned long)ring->buf & ~PAGE_MASK); 1098 nent = dma_map_sg(port->dev, 1099 &atmel_port->sg_rx, 1100 1, 1101 DMA_FROM_DEVICE); 1102 1103 if (!nent) { 1104 dev_dbg(port->dev, "need to release resource of dma\n"); 1105 goto chan_err; 1106 } else { 1107 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1108 sg_dma_len(&atmel_port->sg_rx), 1109 ring->buf, 1110 &sg_dma_address(&atmel_port->sg_rx)); 1111 } 1112 1113 /* Configure the slave DMA */ 1114 memset(&config, 0, sizeof(config)); 1115 config.direction = DMA_DEV_TO_MEM; 1116 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1117 config.src_addr = port->mapbase + ATMEL_US_RHR; 1118 config.src_maxburst = 1; 1119 1120 ret = dmaengine_slave_config(atmel_port->chan_rx, 1121 &config); 1122 if (ret) { 1123 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1124 goto chan_err; 1125 } 1126 /* 1127 * Prepare a cyclic dma transfer, assign 2 descriptors, 1128 * each one is half ring buffer size 1129 */ 1130 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1131 sg_dma_address(&atmel_port->sg_rx), 1132 sg_dma_len(&atmel_port->sg_rx), 1133 sg_dma_len(&atmel_port->sg_rx)/2, 1134 DMA_DEV_TO_MEM, 1135 DMA_PREP_INTERRUPT); 1136 desc->callback = atmel_complete_rx_dma; 1137 desc->callback_param = port; 1138 atmel_port->desc_rx = desc; 1139 atmel_port->cookie_rx = dmaengine_submit(desc); 1140 1141 return 0; 1142 1143 chan_err: 1144 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1145 atmel_port->use_dma_rx = 0; 1146 if (atmel_port->chan_rx) 1147 atmel_release_rx_dma(port); 1148 return -EINVAL; 1149 } 1150 1151 static void atmel_uart_timer_callback(unsigned long data) 1152 { 1153 struct uart_port *port = (void *)data; 1154 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1155 1156 tasklet_schedule(&atmel_port->tasklet); 1157 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); 1158 } 1159 1160 /* 1161 * receive interrupt handler. 1162 */ 1163 static void 1164 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1165 { 1166 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1167 1168 if (atmel_use_pdc_rx(port)) { 1169 /* 1170 * PDC receive. Just schedule the tasklet and let it 1171 * figure out the details. 1172 * 1173 * TODO: We're not handling error flags correctly at 1174 * the moment. 1175 */ 1176 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1177 atmel_uart_writel(port, ATMEL_US_IDR, 1178 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)); 1179 tasklet_schedule(&atmel_port->tasklet); 1180 } 1181 1182 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1183 ATMEL_US_FRAME | ATMEL_US_PARE)) 1184 atmel_pdc_rxerr(port, pending); 1185 } 1186 1187 if (atmel_use_dma_rx(port)) { 1188 if (pending & ATMEL_US_TIMEOUT) { 1189 atmel_uart_writel(port, ATMEL_US_IDR, 1190 ATMEL_US_TIMEOUT); 1191 tasklet_schedule(&atmel_port->tasklet); 1192 } 1193 } 1194 1195 /* Interrupt receive */ 1196 if (pending & ATMEL_US_RXRDY) 1197 atmel_rx_chars(port); 1198 else if (pending & ATMEL_US_RXBRK) { 1199 /* 1200 * End of break detected. If it came along with a 1201 * character, atmel_rx_chars will handle it. 1202 */ 1203 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 1204 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK); 1205 atmel_port->break_active = 0; 1206 } 1207 } 1208 1209 /* 1210 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1211 */ 1212 static void 1213 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1214 { 1215 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1216 1217 if (pending & atmel_port->tx_done_mask) { 1218 /* Either PDC or interrupt transmission */ 1219 atmel_uart_writel(port, ATMEL_US_IDR, 1220 atmel_port->tx_done_mask); 1221 tasklet_schedule(&atmel_port->tasklet); 1222 } 1223 } 1224 1225 /* 1226 * status flags interrupt handler. 1227 */ 1228 static void 1229 atmel_handle_status(struct uart_port *port, unsigned int pending, 1230 unsigned int status) 1231 { 1232 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1233 1234 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1235 | ATMEL_US_CTSIC)) { 1236 atmel_port->irq_status = status; 1237 atmel_port->status_change = atmel_port->irq_status ^ 1238 atmel_port->irq_status_prev; 1239 atmel_port->irq_status_prev = status; 1240 tasklet_schedule(&atmel_port->tasklet); 1241 } 1242 } 1243 1244 /* 1245 * Interrupt handler 1246 */ 1247 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1248 { 1249 struct uart_port *port = dev_id; 1250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1251 unsigned int status, pending, mask, pass_counter = 0; 1252 1253 spin_lock(&atmel_port->lock_suspended); 1254 1255 do { 1256 status = atmel_get_lines_status(port); 1257 mask = atmel_uart_readl(port, ATMEL_US_IMR); 1258 pending = status & mask; 1259 if (!pending) 1260 break; 1261 1262 if (atmel_port->suspended) { 1263 atmel_port->pending |= pending; 1264 atmel_port->pending_status = status; 1265 atmel_uart_writel(port, ATMEL_US_IDR, mask); 1266 pm_system_wakeup(); 1267 break; 1268 } 1269 1270 atmel_handle_receive(port, pending); 1271 atmel_handle_status(port, pending, status); 1272 atmel_handle_transmit(port, pending); 1273 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1274 1275 spin_unlock(&atmel_port->lock_suspended); 1276 1277 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1278 } 1279 1280 static void atmel_release_tx_pdc(struct uart_port *port) 1281 { 1282 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1283 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1284 1285 dma_unmap_single(port->dev, 1286 pdc->dma_addr, 1287 pdc->dma_size, 1288 DMA_TO_DEVICE); 1289 } 1290 1291 /* 1292 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1293 */ 1294 static void atmel_tx_pdc(struct uart_port *port) 1295 { 1296 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1297 struct circ_buf *xmit = &port->state->xmit; 1298 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1299 int count; 1300 1301 /* nothing left to transmit? */ 1302 if (atmel_uart_readl(port, ATMEL_PDC_TCR)) 1303 return; 1304 1305 xmit->tail += pdc->ofs; 1306 xmit->tail &= UART_XMIT_SIZE - 1; 1307 1308 port->icount.tx += pdc->ofs; 1309 pdc->ofs = 0; 1310 1311 /* more to transmit - setup next transfer */ 1312 1313 /* disable PDC transmit */ 1314 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 1315 1316 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1317 dma_sync_single_for_device(port->dev, 1318 pdc->dma_addr, 1319 pdc->dma_size, 1320 DMA_TO_DEVICE); 1321 1322 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1323 pdc->ofs = count; 1324 1325 atmel_uart_writel(port, ATMEL_PDC_TPR, 1326 pdc->dma_addr + xmit->tail); 1327 atmel_uart_writel(port, ATMEL_PDC_TCR, count); 1328 /* re-enable PDC transmit */ 1329 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1330 /* Enable interrupts */ 1331 atmel_uart_writel(port, ATMEL_US_IER, 1332 atmel_port->tx_done_mask); 1333 } else { 1334 if ((port->rs485.flags & SER_RS485_ENABLED) && 1335 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 1336 /* DMA done, stop TX, start RX for RS485 */ 1337 atmel_start_rx(port); 1338 } 1339 } 1340 1341 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1342 uart_write_wakeup(port); 1343 } 1344 1345 static int atmel_prepare_tx_pdc(struct uart_port *port) 1346 { 1347 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1348 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1349 struct circ_buf *xmit = &port->state->xmit; 1350 1351 pdc->buf = xmit->buf; 1352 pdc->dma_addr = dma_map_single(port->dev, 1353 pdc->buf, 1354 UART_XMIT_SIZE, 1355 DMA_TO_DEVICE); 1356 pdc->dma_size = UART_XMIT_SIZE; 1357 pdc->ofs = 0; 1358 1359 return 0; 1360 } 1361 1362 static void atmel_rx_from_ring(struct uart_port *port) 1363 { 1364 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1365 struct circ_buf *ring = &atmel_port->rx_ring; 1366 unsigned int flg; 1367 unsigned int status; 1368 1369 while (ring->head != ring->tail) { 1370 struct atmel_uart_char c; 1371 1372 /* Make sure c is loaded after head. */ 1373 smp_rmb(); 1374 1375 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1376 1377 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1378 1379 port->icount.rx++; 1380 status = c.status; 1381 flg = TTY_NORMAL; 1382 1383 /* 1384 * note that the error handling code is 1385 * out of the main execution path 1386 */ 1387 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1388 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1389 if (status & ATMEL_US_RXBRK) { 1390 /* ignore side-effect */ 1391 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1392 1393 port->icount.brk++; 1394 if (uart_handle_break(port)) 1395 continue; 1396 } 1397 if (status & ATMEL_US_PARE) 1398 port->icount.parity++; 1399 if (status & ATMEL_US_FRAME) 1400 port->icount.frame++; 1401 if (status & ATMEL_US_OVRE) 1402 port->icount.overrun++; 1403 1404 status &= port->read_status_mask; 1405 1406 if (status & ATMEL_US_RXBRK) 1407 flg = TTY_BREAK; 1408 else if (status & ATMEL_US_PARE) 1409 flg = TTY_PARITY; 1410 else if (status & ATMEL_US_FRAME) 1411 flg = TTY_FRAME; 1412 } 1413 1414 1415 if (uart_handle_sysrq_char(port, c.ch)) 1416 continue; 1417 1418 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1419 } 1420 1421 /* 1422 * Drop the lock here since it might end up calling 1423 * uart_start(), which takes the lock. 1424 */ 1425 spin_unlock(&port->lock); 1426 tty_flip_buffer_push(&port->state->port); 1427 spin_lock(&port->lock); 1428 } 1429 1430 static void atmel_release_rx_pdc(struct uart_port *port) 1431 { 1432 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1433 int i; 1434 1435 for (i = 0; i < 2; i++) { 1436 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1437 1438 dma_unmap_single(port->dev, 1439 pdc->dma_addr, 1440 pdc->dma_size, 1441 DMA_FROM_DEVICE); 1442 kfree(pdc->buf); 1443 } 1444 } 1445 1446 static void atmel_rx_from_pdc(struct uart_port *port) 1447 { 1448 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1449 struct tty_port *tport = &port->state->port; 1450 struct atmel_dma_buffer *pdc; 1451 int rx_idx = atmel_port->pdc_rx_idx; 1452 unsigned int head; 1453 unsigned int tail; 1454 unsigned int count; 1455 1456 do { 1457 /* Reset the UART timeout early so that we don't miss one */ 1458 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1459 1460 pdc = &atmel_port->pdc_rx[rx_idx]; 1461 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr; 1462 tail = pdc->ofs; 1463 1464 /* If the PDC has switched buffers, RPR won't contain 1465 * any address within the current buffer. Since head 1466 * is unsigned, we just need a one-way comparison to 1467 * find out. 1468 * 1469 * In this case, we just need to consume the entire 1470 * buffer and resubmit it for DMA. This will clear the 1471 * ENDRX bit as well, so that we can safely re-enable 1472 * all interrupts below. 1473 */ 1474 head = min(head, pdc->dma_size); 1475 1476 if (likely(head != tail)) { 1477 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1478 pdc->dma_size, DMA_FROM_DEVICE); 1479 1480 /* 1481 * head will only wrap around when we recycle 1482 * the DMA buffer, and when that happens, we 1483 * explicitly set tail to 0. So head will 1484 * always be greater than tail. 1485 */ 1486 count = head - tail; 1487 1488 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1489 count); 1490 1491 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1492 pdc->dma_size, DMA_FROM_DEVICE); 1493 1494 port->icount.rx += count; 1495 pdc->ofs = head; 1496 } 1497 1498 /* 1499 * If the current buffer is full, we need to check if 1500 * the next one contains any additional data. 1501 */ 1502 if (head >= pdc->dma_size) { 1503 pdc->ofs = 0; 1504 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr); 1505 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size); 1506 1507 rx_idx = !rx_idx; 1508 atmel_port->pdc_rx_idx = rx_idx; 1509 } 1510 } while (head >= pdc->dma_size); 1511 1512 /* 1513 * Drop the lock here since it might end up calling 1514 * uart_start(), which takes the lock. 1515 */ 1516 spin_unlock(&port->lock); 1517 tty_flip_buffer_push(tport); 1518 spin_lock(&port->lock); 1519 1520 atmel_uart_writel(port, ATMEL_US_IER, 1521 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1522 } 1523 1524 static int atmel_prepare_rx_pdc(struct uart_port *port) 1525 { 1526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1527 int i; 1528 1529 for (i = 0; i < 2; i++) { 1530 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1531 1532 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1533 if (pdc->buf == NULL) { 1534 if (i != 0) { 1535 dma_unmap_single(port->dev, 1536 atmel_port->pdc_rx[0].dma_addr, 1537 PDC_BUFFER_SIZE, 1538 DMA_FROM_DEVICE); 1539 kfree(atmel_port->pdc_rx[0].buf); 1540 } 1541 atmel_port->use_pdc_rx = 0; 1542 return -ENOMEM; 1543 } 1544 pdc->dma_addr = dma_map_single(port->dev, 1545 pdc->buf, 1546 PDC_BUFFER_SIZE, 1547 DMA_FROM_DEVICE); 1548 pdc->dma_size = PDC_BUFFER_SIZE; 1549 pdc->ofs = 0; 1550 } 1551 1552 atmel_port->pdc_rx_idx = 0; 1553 1554 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr); 1555 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE); 1556 1557 atmel_uart_writel(port, ATMEL_PDC_RNPR, 1558 atmel_port->pdc_rx[1].dma_addr); 1559 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE); 1560 1561 return 0; 1562 } 1563 1564 /* 1565 * tasklet handling tty stuff outside the interrupt handler. 1566 */ 1567 static void atmel_tasklet_func(unsigned long data) 1568 { 1569 struct uart_port *port = (struct uart_port *)data; 1570 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1571 unsigned int status = atmel_port->irq_status; 1572 unsigned int status_change = atmel_port->status_change; 1573 1574 /* The interrupt handler does not take the lock */ 1575 spin_lock(&port->lock); 1576 1577 atmel_port->schedule_tx(port); 1578 1579 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1580 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1581 /* TODO: All reads to CSR will clear these interrupts! */ 1582 if (status_change & ATMEL_US_RI) 1583 port->icount.rng++; 1584 if (status_change & ATMEL_US_DSR) 1585 port->icount.dsr++; 1586 if (status_change & ATMEL_US_DCD) 1587 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1588 if (status_change & ATMEL_US_CTS) 1589 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1590 1591 wake_up_interruptible(&port->state->port.delta_msr_wait); 1592 1593 atmel_port->status_change = 0; 1594 } 1595 1596 atmel_port->schedule_rx(port); 1597 1598 spin_unlock(&port->lock); 1599 } 1600 1601 static void atmel_init_property(struct atmel_uart_port *atmel_port, 1602 struct platform_device *pdev) 1603 { 1604 struct device_node *np = pdev->dev.of_node; 1605 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1606 1607 if (np) { 1608 /* DMA/PDC usage specification */ 1609 if (of_get_property(np, "atmel,use-dma-rx", NULL)) { 1610 if (of_get_property(np, "dmas", NULL)) { 1611 atmel_port->use_dma_rx = true; 1612 atmel_port->use_pdc_rx = false; 1613 } else { 1614 atmel_port->use_dma_rx = false; 1615 atmel_port->use_pdc_rx = true; 1616 } 1617 } else { 1618 atmel_port->use_dma_rx = false; 1619 atmel_port->use_pdc_rx = false; 1620 } 1621 1622 if (of_get_property(np, "atmel,use-dma-tx", NULL)) { 1623 if (of_get_property(np, "dmas", NULL)) { 1624 atmel_port->use_dma_tx = true; 1625 atmel_port->use_pdc_tx = false; 1626 } else { 1627 atmel_port->use_dma_tx = false; 1628 atmel_port->use_pdc_tx = true; 1629 } 1630 } else { 1631 atmel_port->use_dma_tx = false; 1632 atmel_port->use_pdc_tx = false; 1633 } 1634 1635 } else { 1636 atmel_port->use_pdc_rx = pdata->use_dma_rx; 1637 atmel_port->use_pdc_tx = pdata->use_dma_tx; 1638 atmel_port->use_dma_rx = false; 1639 atmel_port->use_dma_tx = false; 1640 } 1641 1642 } 1643 1644 static void atmel_init_rs485(struct uart_port *port, 1645 struct platform_device *pdev) 1646 { 1647 struct device_node *np = pdev->dev.of_node; 1648 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 1649 1650 if (np) { 1651 struct serial_rs485 *rs485conf = &port->rs485; 1652 u32 rs485_delay[2]; 1653 /* rs485 properties */ 1654 if (of_property_read_u32_array(np, "rs485-rts-delay", 1655 rs485_delay, 2) == 0) { 1656 rs485conf->delay_rts_before_send = rs485_delay[0]; 1657 rs485conf->delay_rts_after_send = rs485_delay[1]; 1658 rs485conf->flags = 0; 1659 } 1660 1661 if (of_get_property(np, "rs485-rx-during-tx", NULL)) 1662 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1663 1664 if (of_get_property(np, "linux,rs485-enabled-at-boot-time", 1665 NULL)) 1666 rs485conf->flags |= SER_RS485_ENABLED; 1667 } else { 1668 port->rs485 = pdata->rs485; 1669 } 1670 1671 } 1672 1673 static void atmel_set_ops(struct uart_port *port) 1674 { 1675 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1676 1677 if (atmel_use_dma_rx(port)) { 1678 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1679 atmel_port->schedule_rx = &atmel_rx_from_dma; 1680 atmel_port->release_rx = &atmel_release_rx_dma; 1681 } else if (atmel_use_pdc_rx(port)) { 1682 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1683 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1684 atmel_port->release_rx = &atmel_release_rx_pdc; 1685 } else { 1686 atmel_port->prepare_rx = NULL; 1687 atmel_port->schedule_rx = &atmel_rx_from_ring; 1688 atmel_port->release_rx = NULL; 1689 } 1690 1691 if (atmel_use_dma_tx(port)) { 1692 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1693 atmel_port->schedule_tx = &atmel_tx_dma; 1694 atmel_port->release_tx = &atmel_release_tx_dma; 1695 } else if (atmel_use_pdc_tx(port)) { 1696 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1697 atmel_port->schedule_tx = &atmel_tx_pdc; 1698 atmel_port->release_tx = &atmel_release_tx_pdc; 1699 } else { 1700 atmel_port->prepare_tx = NULL; 1701 atmel_port->schedule_tx = &atmel_tx_chars; 1702 atmel_port->release_tx = NULL; 1703 } 1704 } 1705 1706 /* 1707 * Get ip name usart or uart 1708 */ 1709 static void atmel_get_ip_name(struct uart_port *port) 1710 { 1711 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1712 int name = atmel_uart_readl(port, ATMEL_US_NAME); 1713 u32 version; 1714 u32 usart, dbgu_uart, new_uart; 1715 /* ASCII decoding for IP version */ 1716 usart = 0x55534152; /* USAR(T) */ 1717 dbgu_uart = 0x44424755; /* DBGU */ 1718 new_uart = 0x55415254; /* UART */ 1719 1720 atmel_port->has_hw_timer = false; 1721 1722 if (name == new_uart) { 1723 dev_dbg(port->dev, "Uart with hw timer"); 1724 atmel_port->has_hw_timer = true; 1725 atmel_port->rtor = ATMEL_UA_RTOR; 1726 } else if (name == usart) { 1727 dev_dbg(port->dev, "Usart\n"); 1728 atmel_port->has_hw_timer = true; 1729 atmel_port->rtor = ATMEL_US_RTOR; 1730 } else if (name == dbgu_uart) { 1731 dev_dbg(port->dev, "Dbgu or uart without hw timer\n"); 1732 } else { 1733 /* fallback for older SoCs: use version field */ 1734 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1735 switch (version) { 1736 case 0x302: 1737 case 0x10213: 1738 dev_dbg(port->dev, "This version is usart\n"); 1739 atmel_port->has_hw_timer = true; 1740 atmel_port->rtor = ATMEL_US_RTOR; 1741 break; 1742 case 0x203: 1743 case 0x10202: 1744 dev_dbg(port->dev, "This version is uart\n"); 1745 break; 1746 default: 1747 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1748 } 1749 } 1750 } 1751 1752 /* 1753 * Perform initialization and enable port for reception 1754 */ 1755 static int atmel_startup(struct uart_port *port) 1756 { 1757 struct platform_device *pdev = to_platform_device(port->dev); 1758 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1759 struct tty_struct *tty = port->state->port.tty; 1760 int retval; 1761 1762 /* 1763 * Ensure that no interrupts are enabled otherwise when 1764 * request_irq() is called we could get stuck trying to 1765 * handle an unexpected interrupt 1766 */ 1767 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1768 atmel_port->ms_irq_enabled = false; 1769 1770 /* 1771 * Allocate the IRQ 1772 */ 1773 retval = request_irq(port->irq, atmel_interrupt, 1774 IRQF_SHARED | IRQF_COND_SUSPEND, 1775 tty ? tty->name : "atmel_serial", port); 1776 if (retval) { 1777 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1778 return retval; 1779 } 1780 1781 tasklet_enable(&atmel_port->tasklet); 1782 1783 /* 1784 * Initialize DMA (if necessary) 1785 */ 1786 atmel_init_property(atmel_port, pdev); 1787 atmel_set_ops(port); 1788 1789 if (atmel_port->prepare_rx) { 1790 retval = atmel_port->prepare_rx(port); 1791 if (retval < 0) 1792 atmel_set_ops(port); 1793 } 1794 1795 if (atmel_port->prepare_tx) { 1796 retval = atmel_port->prepare_tx(port); 1797 if (retval < 0) 1798 atmel_set_ops(port); 1799 } 1800 1801 /* 1802 * Enable FIFO when available 1803 */ 1804 if (atmel_port->fifo_size) { 1805 unsigned int txrdym = ATMEL_US_ONE_DATA; 1806 unsigned int rxrdym = ATMEL_US_ONE_DATA; 1807 unsigned int fmr; 1808 1809 atmel_uart_writel(port, ATMEL_US_CR, 1810 ATMEL_US_FIFOEN | 1811 ATMEL_US_RXFCLR | 1812 ATMEL_US_TXFLCLR); 1813 1814 if (atmel_use_dma_tx(port)) 1815 txrdym = ATMEL_US_FOUR_DATA; 1816 1817 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym); 1818 if (atmel_port->rts_high && 1819 atmel_port->rts_low) 1820 fmr |= ATMEL_US_FRTSC | 1821 ATMEL_US_RXFTHRES(atmel_port->rts_high) | 1822 ATMEL_US_RXFTHRES2(atmel_port->rts_low); 1823 1824 atmel_uart_writel(port, ATMEL_US_FMR, fmr); 1825 } 1826 1827 /* Save current CSR for comparison in atmel_tasklet_func() */ 1828 atmel_port->irq_status_prev = atmel_get_lines_status(port); 1829 atmel_port->irq_status = atmel_port->irq_status_prev; 1830 1831 /* 1832 * Finally, enable the serial port 1833 */ 1834 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1835 /* enable xmit & rcvr */ 1836 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 1837 1838 setup_timer(&atmel_port->uart_timer, 1839 atmel_uart_timer_callback, 1840 (unsigned long)port); 1841 1842 if (atmel_use_pdc_rx(port)) { 1843 /* set UART timeout */ 1844 if (!atmel_port->has_hw_timer) { 1845 mod_timer(&atmel_port->uart_timer, 1846 jiffies + uart_poll_timeout(port)); 1847 /* set USART timeout */ 1848 } else { 1849 atmel_uart_writel(port, atmel_port->rtor, 1850 PDC_RX_TIMEOUT); 1851 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1852 1853 atmel_uart_writel(port, ATMEL_US_IER, 1854 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1855 } 1856 /* enable PDC controller */ 1857 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1858 } else if (atmel_use_dma_rx(port)) { 1859 /* set UART timeout */ 1860 if (!atmel_port->has_hw_timer) { 1861 mod_timer(&atmel_port->uart_timer, 1862 jiffies + uart_poll_timeout(port)); 1863 /* set USART timeout */ 1864 } else { 1865 atmel_uart_writel(port, atmel_port->rtor, 1866 PDC_RX_TIMEOUT); 1867 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1868 1869 atmel_uart_writel(port, ATMEL_US_IER, 1870 ATMEL_US_TIMEOUT); 1871 } 1872 } else { 1873 /* enable receive only */ 1874 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 1875 } 1876 1877 return 0; 1878 } 1879 1880 /* 1881 * Flush any TX data submitted for DMA. Called when the TX circular 1882 * buffer is reset. 1883 */ 1884 static void atmel_flush_buffer(struct uart_port *port) 1885 { 1886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1887 1888 if (atmel_use_pdc_tx(port)) { 1889 atmel_uart_writel(port, ATMEL_PDC_TCR, 0); 1890 atmel_port->pdc_tx.ofs = 0; 1891 } 1892 } 1893 1894 /* 1895 * Disable the port 1896 */ 1897 static void atmel_shutdown(struct uart_port *port) 1898 { 1899 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1900 1901 /* 1902 * Prevent any tasklets being scheduled during 1903 * cleanup 1904 */ 1905 del_timer_sync(&atmel_port->uart_timer); 1906 1907 /* 1908 * Clear out any scheduled tasklets before 1909 * we destroy the buffers 1910 */ 1911 tasklet_disable(&atmel_port->tasklet); 1912 tasklet_kill(&atmel_port->tasklet); 1913 1914 /* 1915 * Ensure everything is stopped and 1916 * disable all interrupts, port and break condition. 1917 */ 1918 atmel_stop_rx(port); 1919 atmel_stop_tx(port); 1920 1921 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 1922 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1923 1924 1925 /* 1926 * Shut-down the DMA. 1927 */ 1928 if (atmel_port->release_rx) 1929 atmel_port->release_rx(port); 1930 if (atmel_port->release_tx) 1931 atmel_port->release_tx(port); 1932 1933 /* 1934 * Reset ring buffer pointers 1935 */ 1936 atmel_port->rx_ring.head = 0; 1937 atmel_port->rx_ring.tail = 0; 1938 1939 /* 1940 * Free the interrupts 1941 */ 1942 free_irq(port->irq, port); 1943 1944 atmel_port->ms_irq_enabled = false; 1945 1946 atmel_flush_buffer(port); 1947 } 1948 1949 /* 1950 * Power / Clock management. 1951 */ 1952 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 1953 unsigned int oldstate) 1954 { 1955 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1956 1957 switch (state) { 1958 case 0: 1959 /* 1960 * Enable the peripheral clock for this serial port. 1961 * This is called on uart_open() or a resume event. 1962 */ 1963 clk_prepare_enable(atmel_port->clk); 1964 1965 /* re-enable interrupts if we disabled some on suspend */ 1966 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr); 1967 break; 1968 case 3: 1969 /* Back up the interrupt mask and disable all interrupts */ 1970 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR); 1971 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1972 1973 /* 1974 * Disable the peripheral clock for this serial port. 1975 * This is called on uart_close() or a suspend event. 1976 */ 1977 clk_disable_unprepare(atmel_port->clk); 1978 break; 1979 default: 1980 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 1981 } 1982 } 1983 1984 /* 1985 * Change the port parameters 1986 */ 1987 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 1988 struct ktermios *old) 1989 { 1990 unsigned long flags; 1991 unsigned int old_mode, mode, imr, quot, baud; 1992 1993 /* save the current mode register */ 1994 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); 1995 1996 /* reset the mode, clock divisor, parity, stop bits and data size */ 1997 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 1998 ATMEL_US_PAR | ATMEL_US_USMODE); 1999 2000 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 2001 quot = uart_get_divisor(port, baud); 2002 2003 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 2004 quot /= 8; 2005 mode |= ATMEL_US_USCLKS_MCK_DIV8; 2006 } 2007 2008 /* byte size */ 2009 switch (termios->c_cflag & CSIZE) { 2010 case CS5: 2011 mode |= ATMEL_US_CHRL_5; 2012 break; 2013 case CS6: 2014 mode |= ATMEL_US_CHRL_6; 2015 break; 2016 case CS7: 2017 mode |= ATMEL_US_CHRL_7; 2018 break; 2019 default: 2020 mode |= ATMEL_US_CHRL_8; 2021 break; 2022 } 2023 2024 /* stop bits */ 2025 if (termios->c_cflag & CSTOPB) 2026 mode |= ATMEL_US_NBSTOP_2; 2027 2028 /* parity */ 2029 if (termios->c_cflag & PARENB) { 2030 /* Mark or Space parity */ 2031 if (termios->c_cflag & CMSPAR) { 2032 if (termios->c_cflag & PARODD) 2033 mode |= ATMEL_US_PAR_MARK; 2034 else 2035 mode |= ATMEL_US_PAR_SPACE; 2036 } else if (termios->c_cflag & PARODD) 2037 mode |= ATMEL_US_PAR_ODD; 2038 else 2039 mode |= ATMEL_US_PAR_EVEN; 2040 } else 2041 mode |= ATMEL_US_PAR_NONE; 2042 2043 spin_lock_irqsave(&port->lock, flags); 2044 2045 port->read_status_mask = ATMEL_US_OVRE; 2046 if (termios->c_iflag & INPCK) 2047 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2048 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2049 port->read_status_mask |= ATMEL_US_RXBRK; 2050 2051 if (atmel_use_pdc_rx(port)) 2052 /* need to enable error interrupts */ 2053 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask); 2054 2055 /* 2056 * Characters to ignore 2057 */ 2058 port->ignore_status_mask = 0; 2059 if (termios->c_iflag & IGNPAR) 2060 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2061 if (termios->c_iflag & IGNBRK) { 2062 port->ignore_status_mask |= ATMEL_US_RXBRK; 2063 /* 2064 * If we're ignoring parity and break indicators, 2065 * ignore overruns too (for real raw support). 2066 */ 2067 if (termios->c_iflag & IGNPAR) 2068 port->ignore_status_mask |= ATMEL_US_OVRE; 2069 } 2070 /* TODO: Ignore all characters if CREAD is set.*/ 2071 2072 /* update the per-port timeout */ 2073 uart_update_timeout(port, termios->c_cflag, baud); 2074 2075 /* 2076 * save/disable interrupts. The tty layer will ensure that the 2077 * transmitter is empty if requested by the caller, so there's 2078 * no need to wait for it here. 2079 */ 2080 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2081 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2082 2083 /* disable receiver and transmitter */ 2084 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2085 2086 /* mode */ 2087 if (port->rs485.flags & SER_RS485_ENABLED) { 2088 atmel_uart_writel(port, ATMEL_US_TTGR, 2089 port->rs485.delay_rts_after_send); 2090 mode |= ATMEL_US_USMODE_RS485; 2091 } else if (termios->c_cflag & CRTSCTS) { 2092 /* RS232 with hardware handshake (RTS/CTS) */ 2093 mode |= ATMEL_US_USMODE_HWHS; 2094 } else { 2095 /* RS232 without hadware handshake */ 2096 mode |= ATMEL_US_USMODE_NORMAL; 2097 } 2098 2099 /* set the mode, clock divisor, parity, stop bits and data size */ 2100 atmel_uart_writel(port, ATMEL_US_MR, mode); 2101 2102 /* 2103 * when switching the mode, set the RTS line state according to the 2104 * new mode, otherwise keep the former state 2105 */ 2106 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2107 unsigned int rts_state; 2108 2109 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2110 /* let the hardware control the RTS line */ 2111 rts_state = ATMEL_US_RTSDIS; 2112 } else { 2113 /* force RTS line to low level */ 2114 rts_state = ATMEL_US_RTSEN; 2115 } 2116 2117 atmel_uart_writel(port, ATMEL_US_CR, rts_state); 2118 } 2119 2120 /* set the baud rate */ 2121 atmel_uart_writel(port, ATMEL_US_BRGR, quot); 2122 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2123 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2124 2125 /* restore interrupts */ 2126 atmel_uart_writel(port, ATMEL_US_IER, imr); 2127 2128 /* CTS flow-control and modem-status interrupts */ 2129 if (UART_ENABLE_MS(port, termios->c_cflag)) 2130 atmel_enable_ms(port); 2131 else 2132 atmel_disable_ms(port); 2133 2134 spin_unlock_irqrestore(&port->lock, flags); 2135 } 2136 2137 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2138 { 2139 if (termios->c_line == N_PPS) { 2140 port->flags |= UPF_HARDPPS_CD; 2141 spin_lock_irq(&port->lock); 2142 atmel_enable_ms(port); 2143 spin_unlock_irq(&port->lock); 2144 } else { 2145 port->flags &= ~UPF_HARDPPS_CD; 2146 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2147 spin_lock_irq(&port->lock); 2148 atmel_disable_ms(port); 2149 spin_unlock_irq(&port->lock); 2150 } 2151 } 2152 } 2153 2154 /* 2155 * Return string describing the specified port 2156 */ 2157 static const char *atmel_type(struct uart_port *port) 2158 { 2159 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2160 } 2161 2162 /* 2163 * Release the memory region(s) being used by 'port'. 2164 */ 2165 static void atmel_release_port(struct uart_port *port) 2166 { 2167 struct platform_device *pdev = to_platform_device(port->dev); 2168 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2169 2170 release_mem_region(port->mapbase, size); 2171 2172 if (port->flags & UPF_IOREMAP) { 2173 iounmap(port->membase); 2174 port->membase = NULL; 2175 } 2176 } 2177 2178 /* 2179 * Request the memory region(s) being used by 'port'. 2180 */ 2181 static int atmel_request_port(struct uart_port *port) 2182 { 2183 struct platform_device *pdev = to_platform_device(port->dev); 2184 int size = pdev->resource[0].end - pdev->resource[0].start + 1; 2185 2186 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2187 return -EBUSY; 2188 2189 if (port->flags & UPF_IOREMAP) { 2190 port->membase = ioremap(port->mapbase, size); 2191 if (port->membase == NULL) { 2192 release_mem_region(port->mapbase, size); 2193 return -ENOMEM; 2194 } 2195 } 2196 2197 return 0; 2198 } 2199 2200 /* 2201 * Configure/autoconfigure the port. 2202 */ 2203 static void atmel_config_port(struct uart_port *port, int flags) 2204 { 2205 if (flags & UART_CONFIG_TYPE) { 2206 port->type = PORT_ATMEL; 2207 atmel_request_port(port); 2208 } 2209 } 2210 2211 /* 2212 * Verify the new serial_struct (for TIOCSSERIAL). 2213 */ 2214 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2215 { 2216 int ret = 0; 2217 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2218 ret = -EINVAL; 2219 if (port->irq != ser->irq) 2220 ret = -EINVAL; 2221 if (ser->io_type != SERIAL_IO_MEM) 2222 ret = -EINVAL; 2223 if (port->uartclk / 16 != ser->baud_base) 2224 ret = -EINVAL; 2225 if (port->mapbase != (unsigned long)ser->iomem_base) 2226 ret = -EINVAL; 2227 if (port->iobase != ser->port) 2228 ret = -EINVAL; 2229 if (ser->hub6 != 0) 2230 ret = -EINVAL; 2231 return ret; 2232 } 2233 2234 #ifdef CONFIG_CONSOLE_POLL 2235 static int atmel_poll_get_char(struct uart_port *port) 2236 { 2237 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY)) 2238 cpu_relax(); 2239 2240 return atmel_uart_read_char(port); 2241 } 2242 2243 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2244 { 2245 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2246 cpu_relax(); 2247 2248 atmel_uart_write_char(port, ch); 2249 } 2250 #endif 2251 2252 static struct uart_ops atmel_pops = { 2253 .tx_empty = atmel_tx_empty, 2254 .set_mctrl = atmel_set_mctrl, 2255 .get_mctrl = atmel_get_mctrl, 2256 .stop_tx = atmel_stop_tx, 2257 .start_tx = atmel_start_tx, 2258 .stop_rx = atmel_stop_rx, 2259 .enable_ms = atmel_enable_ms, 2260 .break_ctl = atmel_break_ctl, 2261 .startup = atmel_startup, 2262 .shutdown = atmel_shutdown, 2263 .flush_buffer = atmel_flush_buffer, 2264 .set_termios = atmel_set_termios, 2265 .set_ldisc = atmel_set_ldisc, 2266 .type = atmel_type, 2267 .release_port = atmel_release_port, 2268 .request_port = atmel_request_port, 2269 .config_port = atmel_config_port, 2270 .verify_port = atmel_verify_port, 2271 .pm = atmel_serial_pm, 2272 #ifdef CONFIG_CONSOLE_POLL 2273 .poll_get_char = atmel_poll_get_char, 2274 .poll_put_char = atmel_poll_put_char, 2275 #endif 2276 }; 2277 2278 /* 2279 * Configure the port from the platform device resource info. 2280 */ 2281 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2282 struct platform_device *pdev) 2283 { 2284 int ret; 2285 struct uart_port *port = &atmel_port->uart; 2286 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2287 2288 atmel_init_property(atmel_port, pdev); 2289 atmel_set_ops(port); 2290 2291 atmel_init_rs485(port, pdev); 2292 2293 port->iotype = UPIO_MEM; 2294 port->flags = UPF_BOOT_AUTOCONF; 2295 port->ops = &atmel_pops; 2296 port->fifosize = 1; 2297 port->dev = &pdev->dev; 2298 port->mapbase = pdev->resource[0].start; 2299 port->irq = pdev->resource[1].start; 2300 port->rs485_config = atmel_config_rs485; 2301 2302 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, 2303 (unsigned long)port); 2304 tasklet_disable(&atmel_port->tasklet); 2305 2306 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2307 2308 if (pdata && pdata->regs) { 2309 /* Already mapped by setup code */ 2310 port->membase = pdata->regs; 2311 } else { 2312 port->flags |= UPF_IOREMAP; 2313 port->membase = NULL; 2314 } 2315 2316 /* for console, the clock could already be configured */ 2317 if (!atmel_port->clk) { 2318 atmel_port->clk = clk_get(&pdev->dev, "usart"); 2319 if (IS_ERR(atmel_port->clk)) { 2320 ret = PTR_ERR(atmel_port->clk); 2321 atmel_port->clk = NULL; 2322 return ret; 2323 } 2324 ret = clk_prepare_enable(atmel_port->clk); 2325 if (ret) { 2326 clk_put(atmel_port->clk); 2327 atmel_port->clk = NULL; 2328 return ret; 2329 } 2330 port->uartclk = clk_get_rate(atmel_port->clk); 2331 clk_disable_unprepare(atmel_port->clk); 2332 /* only enable clock when USART is in use */ 2333 } 2334 2335 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ 2336 if (port->rs485.flags & SER_RS485_ENABLED) 2337 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2338 else if (atmel_use_pdc_tx(port)) { 2339 port->fifosize = PDC_BUFFER_SIZE; 2340 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2341 } else { 2342 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2343 } 2344 2345 return 0; 2346 } 2347 2348 struct platform_device *atmel_default_console_device; /* the serial console device */ 2349 2350 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2351 static void atmel_console_putchar(struct uart_port *port, int ch) 2352 { 2353 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2354 cpu_relax(); 2355 atmel_uart_write_char(port, ch); 2356 } 2357 2358 /* 2359 * Interrupts are disabled on entering 2360 */ 2361 static void atmel_console_write(struct console *co, const char *s, u_int count) 2362 { 2363 struct uart_port *port = &atmel_ports[co->index].uart; 2364 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2365 unsigned int status, imr; 2366 unsigned int pdc_tx; 2367 2368 /* 2369 * First, save IMR and then disable interrupts 2370 */ 2371 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2372 atmel_uart_writel(port, ATMEL_US_IDR, 2373 ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2374 2375 /* Store PDC transmit status and disable it */ 2376 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN; 2377 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 2378 2379 uart_console_write(port, s, count, atmel_console_putchar); 2380 2381 /* 2382 * Finally, wait for transmitter to become empty 2383 * and restore IMR 2384 */ 2385 do { 2386 status = atmel_uart_readl(port, ATMEL_US_CSR); 2387 } while (!(status & ATMEL_US_TXRDY)); 2388 2389 /* Restore PDC transmit status */ 2390 if (pdc_tx) 2391 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 2392 2393 /* set interrupts back the way they were */ 2394 atmel_uart_writel(port, ATMEL_US_IER, imr); 2395 } 2396 2397 /* 2398 * If the port was already initialised (eg, by a boot loader), 2399 * try to determine the current setup. 2400 */ 2401 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2402 int *parity, int *bits) 2403 { 2404 unsigned int mr, quot; 2405 2406 /* 2407 * If the baud rate generator isn't running, the port wasn't 2408 * initialized by the boot loader. 2409 */ 2410 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD; 2411 if (!quot) 2412 return; 2413 2414 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL; 2415 if (mr == ATMEL_US_CHRL_8) 2416 *bits = 8; 2417 else 2418 *bits = 7; 2419 2420 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR; 2421 if (mr == ATMEL_US_PAR_EVEN) 2422 *parity = 'e'; 2423 else if (mr == ATMEL_US_PAR_ODD) 2424 *parity = 'o'; 2425 2426 /* 2427 * The serial core only rounds down when matching this to a 2428 * supported baud rate. Make sure we don't end up slightly 2429 * lower than one of those, as it would make us fall through 2430 * to a much lower baud rate than we really want. 2431 */ 2432 *baud = port->uartclk / (16 * (quot - 1)); 2433 } 2434 2435 static int __init atmel_console_setup(struct console *co, char *options) 2436 { 2437 int ret; 2438 struct uart_port *port = &atmel_ports[co->index].uart; 2439 int baud = 115200; 2440 int bits = 8; 2441 int parity = 'n'; 2442 int flow = 'n'; 2443 2444 if (port->membase == NULL) { 2445 /* Port not initialized yet - delay setup */ 2446 return -ENODEV; 2447 } 2448 2449 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2450 if (ret) 2451 return ret; 2452 2453 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2454 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2455 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2456 2457 if (options) 2458 uart_parse_options(options, &baud, &parity, &bits, &flow); 2459 else 2460 atmel_console_get_options(port, &baud, &parity, &bits); 2461 2462 return uart_set_options(port, co, baud, parity, bits, flow); 2463 } 2464 2465 static struct uart_driver atmel_uart; 2466 2467 static struct console atmel_console = { 2468 .name = ATMEL_DEVICENAME, 2469 .write = atmel_console_write, 2470 .device = uart_console_device, 2471 .setup = atmel_console_setup, 2472 .flags = CON_PRINTBUFFER, 2473 .index = -1, 2474 .data = &atmel_uart, 2475 }; 2476 2477 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2478 2479 /* 2480 * Early console initialization (before VM subsystem initialized). 2481 */ 2482 static int __init atmel_console_init(void) 2483 { 2484 int ret; 2485 if (atmel_default_console_device) { 2486 struct atmel_uart_data *pdata = 2487 dev_get_platdata(&atmel_default_console_device->dev); 2488 int id = pdata->num; 2489 struct atmel_uart_port *atmel_port = &atmel_ports[id]; 2490 2491 atmel_port->backup_imr = 0; 2492 atmel_port->uart.line = id; 2493 2494 add_preferred_console(ATMEL_DEVICENAME, id, NULL); 2495 ret = atmel_init_port(atmel_port, atmel_default_console_device); 2496 if (ret) 2497 return ret; 2498 register_console(&atmel_console); 2499 } 2500 2501 return 0; 2502 } 2503 2504 console_initcall(atmel_console_init); 2505 2506 /* 2507 * Late console initialization. 2508 */ 2509 static int __init atmel_late_console_init(void) 2510 { 2511 if (atmel_default_console_device 2512 && !(atmel_console.flags & CON_ENABLED)) 2513 register_console(&atmel_console); 2514 2515 return 0; 2516 } 2517 2518 core_initcall(atmel_late_console_init); 2519 2520 static inline bool atmel_is_console_port(struct uart_port *port) 2521 { 2522 return port->cons && port->cons->index == port->line; 2523 } 2524 2525 #else 2526 #define ATMEL_CONSOLE_DEVICE NULL 2527 2528 static inline bool atmel_is_console_port(struct uart_port *port) 2529 { 2530 return false; 2531 } 2532 #endif 2533 2534 static struct uart_driver atmel_uart = { 2535 .owner = THIS_MODULE, 2536 .driver_name = "atmel_serial", 2537 .dev_name = ATMEL_DEVICENAME, 2538 .major = SERIAL_ATMEL_MAJOR, 2539 .minor = MINOR_START, 2540 .nr = ATMEL_MAX_UART, 2541 .cons = ATMEL_CONSOLE_DEVICE, 2542 }; 2543 2544 #ifdef CONFIG_PM 2545 static bool atmel_serial_clk_will_stop(void) 2546 { 2547 #ifdef CONFIG_ARCH_AT91 2548 return at91_suspend_entering_slow_clock(); 2549 #else 2550 return false; 2551 #endif 2552 } 2553 2554 static int atmel_serial_suspend(struct platform_device *pdev, 2555 pm_message_t state) 2556 { 2557 struct uart_port *port = platform_get_drvdata(pdev); 2558 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2559 2560 if (atmel_is_console_port(port) && console_suspend_enabled) { 2561 /* Drain the TX shifter */ 2562 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & 2563 ATMEL_US_TXEMPTY)) 2564 cpu_relax(); 2565 } 2566 2567 /* we can not wake up if we're running on slow clock */ 2568 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2569 if (atmel_serial_clk_will_stop()) { 2570 unsigned long flags; 2571 2572 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2573 atmel_port->suspended = true; 2574 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2575 device_set_wakeup_enable(&pdev->dev, 0); 2576 } 2577 2578 uart_suspend_port(&atmel_uart, port); 2579 2580 return 0; 2581 } 2582 2583 static int atmel_serial_resume(struct platform_device *pdev) 2584 { 2585 struct uart_port *port = platform_get_drvdata(pdev); 2586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2587 unsigned long flags; 2588 2589 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2590 if (atmel_port->pending) { 2591 atmel_handle_receive(port, atmel_port->pending); 2592 atmel_handle_status(port, atmel_port->pending, 2593 atmel_port->pending_status); 2594 atmel_handle_transmit(port, atmel_port->pending); 2595 atmel_port->pending = 0; 2596 } 2597 atmel_port->suspended = false; 2598 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2599 2600 uart_resume_port(&atmel_uart, port); 2601 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2602 2603 return 0; 2604 } 2605 #else 2606 #define atmel_serial_suspend NULL 2607 #define atmel_serial_resume NULL 2608 #endif 2609 2610 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port, 2611 struct platform_device *pdev) 2612 { 2613 atmel_port->fifo_size = 0; 2614 atmel_port->rts_low = 0; 2615 atmel_port->rts_high = 0; 2616 2617 if (of_property_read_u32(pdev->dev.of_node, 2618 "atmel,fifo-size", 2619 &atmel_port->fifo_size)) 2620 return; 2621 2622 if (!atmel_port->fifo_size) 2623 return; 2624 2625 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) { 2626 atmel_port->fifo_size = 0; 2627 dev_err(&pdev->dev, "Invalid FIFO size\n"); 2628 return; 2629 } 2630 2631 /* 2632 * 0 <= rts_low <= rts_high <= fifo_size 2633 * Once their CTS line asserted by the remote peer, some x86 UARTs tend 2634 * to flush their internal TX FIFO, commonly up to 16 data, before 2635 * actually stopping to send new data. So we try to set the RTS High 2636 * Threshold to a reasonably high value respecting this 16 data 2637 * empirical rule when possible. 2638 */ 2639 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1, 2640 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET); 2641 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2, 2642 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET); 2643 2644 dev_info(&pdev->dev, "Using FIFO (%u data)\n", 2645 atmel_port->fifo_size); 2646 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n", 2647 atmel_port->rts_high); 2648 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n", 2649 atmel_port->rts_low); 2650 } 2651 2652 static int atmel_serial_probe(struct platform_device *pdev) 2653 { 2654 struct atmel_uart_port *atmel_port; 2655 struct device_node *np = pdev->dev.of_node; 2656 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); 2657 void *data; 2658 int ret = -ENODEV; 2659 bool rs485_enabled; 2660 2661 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2662 2663 if (np) 2664 ret = of_alias_get_id(np, "serial"); 2665 else 2666 if (pdata) 2667 ret = pdata->num; 2668 2669 if (ret < 0) 2670 /* port id not found in platform data nor device-tree aliases: 2671 * auto-enumerate it */ 2672 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2673 2674 if (ret >= ATMEL_MAX_UART) { 2675 ret = -ENODEV; 2676 goto err; 2677 } 2678 2679 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2680 /* port already in use */ 2681 ret = -EBUSY; 2682 goto err; 2683 } 2684 2685 atmel_port = &atmel_ports[ret]; 2686 atmel_port->backup_imr = 0; 2687 atmel_port->uart.line = ret; 2688 atmel_serial_probe_fifos(atmel_port, pdev); 2689 2690 spin_lock_init(&atmel_port->lock_suspended); 2691 2692 ret = atmel_init_port(atmel_port, pdev); 2693 if (ret) 2694 goto err_clear_bit; 2695 2696 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0); 2697 if (IS_ERR(atmel_port->gpios)) { 2698 ret = PTR_ERR(atmel_port->gpios); 2699 goto err_clear_bit; 2700 } 2701 2702 if (!atmel_use_pdc_rx(&atmel_port->uart)) { 2703 ret = -ENOMEM; 2704 data = kmalloc(sizeof(struct atmel_uart_char) 2705 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); 2706 if (!data) 2707 goto err_alloc_ring; 2708 atmel_port->rx_ring.buf = data; 2709 } 2710 2711 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED; 2712 2713 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart); 2714 if (ret) 2715 goto err_add_port; 2716 2717 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2718 if (atmel_is_console_port(&atmel_port->uart) 2719 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2720 /* 2721 * The serial core enabled the clock for us, so undo 2722 * the clk_prepare_enable() in atmel_console_setup() 2723 */ 2724 clk_disable_unprepare(atmel_port->clk); 2725 } 2726 #endif 2727 2728 device_init_wakeup(&pdev->dev, 1); 2729 platform_set_drvdata(pdev, atmel_port); 2730 2731 /* 2732 * The peripheral clock has been disabled by atmel_init_port(): 2733 * enable it before accessing I/O registers 2734 */ 2735 clk_prepare_enable(atmel_port->clk); 2736 2737 if (rs485_enabled) { 2738 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR, 2739 ATMEL_US_USMODE_NORMAL); 2740 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR, 2741 ATMEL_US_RTSEN); 2742 } 2743 2744 /* 2745 * Get port name of usart or uart 2746 */ 2747 atmel_get_ip_name(&atmel_port->uart); 2748 2749 /* 2750 * The peripheral clock can now safely be disabled till the port 2751 * is used 2752 */ 2753 clk_disable_unprepare(atmel_port->clk); 2754 2755 return 0; 2756 2757 err_add_port: 2758 kfree(atmel_port->rx_ring.buf); 2759 atmel_port->rx_ring.buf = NULL; 2760 err_alloc_ring: 2761 if (!atmel_is_console_port(&atmel_port->uart)) { 2762 clk_put(atmel_port->clk); 2763 atmel_port->clk = NULL; 2764 } 2765 err_clear_bit: 2766 clear_bit(atmel_port->uart.line, atmel_ports_in_use); 2767 err: 2768 return ret; 2769 } 2770 2771 /* 2772 * Even if the driver is not modular, it makes sense to be able to 2773 * unbind a device: there can be many bound devices, and there are 2774 * situations where dynamic binding and unbinding can be useful. 2775 * 2776 * For example, a connected device can require a specific firmware update 2777 * protocol that needs bitbanging on IO lines, but use the regular serial 2778 * port in the normal case. 2779 */ 2780 static int atmel_serial_remove(struct platform_device *pdev) 2781 { 2782 struct uart_port *port = platform_get_drvdata(pdev); 2783 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2784 int ret = 0; 2785 2786 tasklet_kill(&atmel_port->tasklet); 2787 2788 device_init_wakeup(&pdev->dev, 0); 2789 2790 ret = uart_remove_one_port(&atmel_uart, port); 2791 2792 kfree(atmel_port->rx_ring.buf); 2793 2794 /* "port" is allocated statically, so we shouldn't free it */ 2795 2796 clear_bit(port->line, atmel_ports_in_use); 2797 2798 clk_put(atmel_port->clk); 2799 atmel_port->clk = NULL; 2800 2801 return ret; 2802 } 2803 2804 static struct platform_driver atmel_serial_driver = { 2805 .probe = atmel_serial_probe, 2806 .remove = atmel_serial_remove, 2807 .suspend = atmel_serial_suspend, 2808 .resume = atmel_serial_resume, 2809 .driver = { 2810 .name = "atmel_usart", 2811 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 2812 }, 2813 }; 2814 2815 static int __init atmel_serial_init(void) 2816 { 2817 int ret; 2818 2819 ret = uart_register_driver(&atmel_uart); 2820 if (ret) 2821 return ret; 2822 2823 ret = platform_driver_register(&atmel_serial_driver); 2824 if (ret) 2825 uart_unregister_driver(&atmel_uart); 2826 2827 return ret; 2828 } 2829 device_initcall(atmel_serial_init); 2830