1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * Copyright (C) 2010 ST-Ericsson SA 10 * 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 13 * Note that although they do have CTS, DCD and DSR inputs, they do 14 * not have an RI input, nor do they have DTR or RTS outputs. If 15 * required, these have to be supplied via some other means (eg, GPIO) 16 * and hooked into this driver. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/ioport.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/platform_device.h> 24 #include <linux/sysrq.h> 25 #include <linux/device.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/amba/bus.h> 31 #include <linux/amba/serial.h> 32 #include <linux/clk.h> 33 #include <linux/slab.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/scatterlist.h> 37 #include <linux/delay.h> 38 #include <linux/types.h> 39 #include <linux/of.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/sizes.h> 42 #include <linux/io.h> 43 #include <linux/acpi.h> 44 45 #define UART_NR 14 46 47 #define SERIAL_AMBA_MAJOR 204 48 #define SERIAL_AMBA_MINOR 64 49 #define SERIAL_AMBA_NR UART_NR 50 51 #define AMBA_ISR_PASS_LIMIT 256 52 53 #define UART_DR_ERROR (UART011_DR_OE | UART011_DR_BE | UART011_DR_PE | UART011_DR_FE) 54 #define UART_DUMMY_DR_RX BIT(16) 55 56 enum { 57 REG_DR, 58 REG_ST_DMAWM, 59 REG_ST_TIMEOUT, 60 REG_FR, 61 REG_LCRH_RX, 62 REG_LCRH_TX, 63 REG_IBRD, 64 REG_FBRD, 65 REG_CR, 66 REG_IFLS, 67 REG_IMSC, 68 REG_RIS, 69 REG_MIS, 70 REG_ICR, 71 REG_DMACR, 72 REG_ST_XFCR, 73 REG_ST_XON1, 74 REG_ST_XON2, 75 REG_ST_XOFF1, 76 REG_ST_XOFF2, 77 REG_ST_ITCR, 78 REG_ST_ITIP, 79 REG_ST_ABCR, 80 REG_ST_ABIMSC, 81 82 /* The size of the array - must be last */ 83 REG_ARRAY_SIZE, 84 }; 85 86 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 87 [REG_DR] = UART01x_DR, 88 [REG_FR] = UART01x_FR, 89 [REG_LCRH_RX] = UART011_LCRH, 90 [REG_LCRH_TX] = UART011_LCRH, 91 [REG_IBRD] = UART011_IBRD, 92 [REG_FBRD] = UART011_FBRD, 93 [REG_CR] = UART011_CR, 94 [REG_IFLS] = UART011_IFLS, 95 [REG_IMSC] = UART011_IMSC, 96 [REG_RIS] = UART011_RIS, 97 [REG_MIS] = UART011_MIS, 98 [REG_ICR] = UART011_ICR, 99 [REG_DMACR] = UART011_DMACR, 100 }; 101 102 /* There is by now at least one vendor with differing details, so handle it */ 103 struct vendor_data { 104 const u16 *reg_offset; 105 unsigned int ifls; 106 unsigned int fr_busy; 107 unsigned int fr_dsr; 108 unsigned int fr_cts; 109 unsigned int fr_ri; 110 unsigned int inv_fr; 111 bool access_32b; 112 bool oversampling; 113 bool dma_threshold; 114 bool cts_event_workaround; 115 bool always_enabled; 116 bool fixed_options; 117 bool skip_ibrd_fbrd; 118 bool set_uartclk_rate; 119 120 unsigned int (*get_fifosize)(struct amba_device *dev); 121 }; 122 123 static unsigned int get_fifosize_arm(struct amba_device *dev) 124 { 125 return amba_rev(dev) < 3 ? 16 : 32; 126 } 127 128 static struct vendor_data vendor_arm = { 129 .reg_offset = pl011_std_offsets, 130 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, 131 .fr_busy = UART01x_FR_BUSY, 132 .fr_dsr = UART01x_FR_DSR, 133 .fr_cts = UART01x_FR_CTS, 134 .fr_ri = UART011_FR_RI, 135 .oversampling = false, 136 .dma_threshold = false, 137 .cts_event_workaround = false, 138 .always_enabled = false, 139 .fixed_options = false, 140 .get_fifosize = get_fifosize_arm, 141 }; 142 143 static const struct vendor_data vendor_sbsa = { 144 .reg_offset = pl011_std_offsets, 145 .fr_busy = UART01x_FR_BUSY, 146 .fr_dsr = UART01x_FR_DSR, 147 .fr_cts = UART01x_FR_CTS, 148 .fr_ri = UART011_FR_RI, 149 .access_32b = true, 150 .oversampling = false, 151 .dma_threshold = false, 152 .cts_event_workaround = false, 153 .always_enabled = true, 154 .fixed_options = true, 155 }; 156 157 #ifdef CONFIG_ACPI_SPCR_TABLE 158 static const struct vendor_data vendor_qdt_qdf2400_e44 = { 159 .reg_offset = pl011_std_offsets, 160 .fr_busy = UART011_FR_TXFE, 161 .fr_dsr = UART01x_FR_DSR, 162 .fr_cts = UART01x_FR_CTS, 163 .fr_ri = UART011_FR_RI, 164 .inv_fr = UART011_FR_TXFE, 165 .access_32b = true, 166 .oversampling = false, 167 .dma_threshold = false, 168 .cts_event_workaround = false, 169 .always_enabled = true, 170 .fixed_options = true, 171 }; 172 #endif 173 174 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 175 [REG_DR] = UART01x_DR, 176 [REG_ST_DMAWM] = ST_UART011_DMAWM, 177 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 178 [REG_FR] = UART01x_FR, 179 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 180 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 181 [REG_IBRD] = UART011_IBRD, 182 [REG_FBRD] = UART011_FBRD, 183 [REG_CR] = UART011_CR, 184 [REG_IFLS] = UART011_IFLS, 185 [REG_IMSC] = UART011_IMSC, 186 [REG_RIS] = UART011_RIS, 187 [REG_MIS] = UART011_MIS, 188 [REG_ICR] = UART011_ICR, 189 [REG_DMACR] = UART011_DMACR, 190 [REG_ST_XFCR] = ST_UART011_XFCR, 191 [REG_ST_XON1] = ST_UART011_XON1, 192 [REG_ST_XON2] = ST_UART011_XON2, 193 [REG_ST_XOFF1] = ST_UART011_XOFF1, 194 [REG_ST_XOFF2] = ST_UART011_XOFF2, 195 [REG_ST_ITCR] = ST_UART011_ITCR, 196 [REG_ST_ITIP] = ST_UART011_ITIP, 197 [REG_ST_ABCR] = ST_UART011_ABCR, 198 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 199 }; 200 201 static unsigned int get_fifosize_st(struct amba_device *dev) 202 { 203 return 64; 204 } 205 206 static struct vendor_data vendor_st = { 207 .reg_offset = pl011_st_offsets, 208 .ifls = UART011_IFLS_RX_HALF | UART011_IFLS_TX_HALF, 209 .fr_busy = UART01x_FR_BUSY, 210 .fr_dsr = UART01x_FR_DSR, 211 .fr_cts = UART01x_FR_CTS, 212 .fr_ri = UART011_FR_RI, 213 .oversampling = true, 214 .dma_threshold = true, 215 .cts_event_workaround = true, 216 .always_enabled = false, 217 .fixed_options = false, 218 .get_fifosize = get_fifosize_st, 219 }; 220 221 static unsigned int get_fifosize_nvidia(struct amba_device *dev) 222 { 223 return 32; 224 } 225 226 static struct vendor_data vendor_nvidia = { 227 .reg_offset = pl011_std_offsets, 228 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, 229 .fr_busy = UART01x_FR_BUSY, 230 .fr_dsr = UART01x_FR_DSR, 231 .fr_cts = UART01x_FR_CTS, 232 .fr_ri = UART011_FR_RI, 233 .oversampling = false, 234 .dma_threshold = false, 235 .cts_event_workaround = false, 236 .always_enabled = false, 237 .fixed_options = false, 238 .skip_ibrd_fbrd = true, 239 .set_uartclk_rate = true, 240 .get_fifosize = get_fifosize_nvidia, 241 }; 242 243 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { 244 [REG_DR] = ZX_UART011_DR, 245 [REG_FR] = ZX_UART011_FR, 246 [REG_LCRH_RX] = ZX_UART011_LCRH, 247 [REG_LCRH_TX] = ZX_UART011_LCRH, 248 [REG_IBRD] = ZX_UART011_IBRD, 249 [REG_FBRD] = ZX_UART011_FBRD, 250 [REG_CR] = ZX_UART011_CR, 251 [REG_IFLS] = ZX_UART011_IFLS, 252 [REG_IMSC] = ZX_UART011_IMSC, 253 [REG_RIS] = ZX_UART011_RIS, 254 [REG_MIS] = ZX_UART011_MIS, 255 [REG_ICR] = ZX_UART011_ICR, 256 [REG_DMACR] = ZX_UART011_DMACR, 257 }; 258 259 static unsigned int get_fifosize_zte(struct amba_device *dev) 260 { 261 return 16; 262 } 263 264 static struct vendor_data vendor_zte = { 265 .reg_offset = pl011_zte_offsets, 266 .access_32b = true, 267 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, 268 .fr_busy = ZX_UART01x_FR_BUSY, 269 .fr_dsr = ZX_UART01x_FR_DSR, 270 .fr_cts = ZX_UART01x_FR_CTS, 271 .fr_ri = ZX_UART011_FR_RI, 272 .get_fifosize = get_fifosize_zte, 273 }; 274 275 /* Deals with DMA transactions */ 276 277 struct pl011_dmabuf { 278 dma_addr_t dma; 279 size_t len; 280 char *buf; 281 }; 282 283 struct pl011_dmarx_data { 284 struct dma_chan *chan; 285 struct completion complete; 286 bool use_buf_b; 287 struct pl011_dmabuf dbuf_a; 288 struct pl011_dmabuf dbuf_b; 289 dma_cookie_t cookie; 290 bool running; 291 struct timer_list timer; 292 unsigned int last_residue; 293 unsigned long last_jiffies; 294 bool auto_poll_rate; 295 unsigned int poll_rate; 296 unsigned int poll_timeout; 297 }; 298 299 struct pl011_dmatx_data { 300 struct dma_chan *chan; 301 dma_addr_t dma; 302 size_t len; 303 char *buf; 304 bool queued; 305 }; 306 307 enum pl011_rs485_tx_state { 308 OFF, 309 WAIT_AFTER_RTS, 310 SEND, 311 WAIT_AFTER_SEND, 312 }; 313 314 /* 315 * We wrap our port structure around the generic uart_port. 316 */ 317 struct uart_amba_port { 318 struct uart_port port; 319 const u16 *reg_offset; 320 struct clk *clk; 321 const struct vendor_data *vendor; 322 unsigned int im; /* interrupt mask */ 323 unsigned int old_status; 324 unsigned int fifosize; /* vendor-specific */ 325 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 326 char type[12]; 327 ktime_t rs485_tx_drain_interval; /* nano */ 328 enum pl011_rs485_tx_state rs485_tx_state; 329 struct hrtimer trigger_start_tx; 330 struct hrtimer trigger_stop_tx; 331 bool console_line_ended; 332 #ifdef CONFIG_DMA_ENGINE 333 /* DMA stuff */ 334 unsigned int dmacr; /* dma control reg */ 335 bool using_tx_dma; 336 bool using_rx_dma; 337 struct pl011_dmarx_data dmarx; 338 struct pl011_dmatx_data dmatx; 339 bool dma_probed; 340 #endif 341 }; 342 343 static unsigned int pl011_tx_empty(struct uart_port *port); 344 345 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 346 unsigned int reg) 347 { 348 return uap->reg_offset[reg]; 349 } 350 351 static unsigned int pl011_read(const struct uart_amba_port *uap, 352 unsigned int reg) 353 { 354 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 355 356 return (uap->port.iotype == UPIO_MEM32) ? 357 readl_relaxed(addr) : readw_relaxed(addr); 358 } 359 360 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 361 unsigned int reg) 362 { 363 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 364 365 if (uap->port.iotype == UPIO_MEM32) 366 writel_relaxed(val, addr); 367 else 368 writew_relaxed(val, addr); 369 } 370 371 /* 372 * Reads up to 256 characters from the FIFO or until it's empty and 373 * inserts them into the TTY layer. Returns the number of characters 374 * read from the FIFO. 375 */ 376 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 377 { 378 unsigned int ch, fifotaken; 379 int sysrq; 380 u16 status; 381 u8 flag; 382 383 for (fifotaken = 0; fifotaken != 256; fifotaken++) { 384 status = pl011_read(uap, REG_FR); 385 if (status & UART01x_FR_RXFE) 386 break; 387 388 /* Take chars from the FIFO and update status */ 389 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 390 flag = TTY_NORMAL; 391 uap->port.icount.rx++; 392 393 if (unlikely(ch & UART_DR_ERROR)) { 394 if (ch & UART011_DR_BE) { 395 ch &= ~(UART011_DR_FE | UART011_DR_PE); 396 uap->port.icount.brk++; 397 if (uart_handle_break(&uap->port)) 398 continue; 399 } else if (ch & UART011_DR_PE) { 400 uap->port.icount.parity++; 401 } else if (ch & UART011_DR_FE) { 402 uap->port.icount.frame++; 403 } 404 if (ch & UART011_DR_OE) 405 uap->port.icount.overrun++; 406 407 ch &= uap->port.read_status_mask; 408 409 if (ch & UART011_DR_BE) 410 flag = TTY_BREAK; 411 else if (ch & UART011_DR_PE) 412 flag = TTY_PARITY; 413 else if (ch & UART011_DR_FE) 414 flag = TTY_FRAME; 415 } 416 417 sysrq = uart_prepare_sysrq_char(&uap->port, ch & 255); 418 if (!sysrq) 419 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 420 } 421 422 return fifotaken; 423 } 424 425 /* 426 * All the DMA operation mode stuff goes inside this ifdef. 427 * This assumes that you have a generic DMA device interface, 428 * no custom DMA interfaces are supported. 429 */ 430 #ifdef CONFIG_DMA_ENGINE 431 432 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 433 434 static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db, 435 enum dma_data_direction dir) 436 { 437 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE, 438 &db->dma, GFP_KERNEL); 439 if (!db->buf) 440 return -ENOMEM; 441 db->len = PL011_DMA_BUFFER_SIZE; 442 443 return 0; 444 } 445 446 static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db, 447 enum dma_data_direction dir) 448 { 449 if (db->buf) { 450 dma_free_coherent(chan->device->dev, 451 PL011_DMA_BUFFER_SIZE, db->buf, db->dma); 452 } 453 } 454 455 static void pl011_dma_probe(struct uart_amba_port *uap) 456 { 457 /* DMA is the sole user of the platform data right now */ 458 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 459 struct device *dev = uap->port.dev; 460 struct dma_slave_config tx_conf = { 461 .dst_addr = uap->port.mapbase + 462 pl011_reg_to_offset(uap, REG_DR), 463 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 464 .direction = DMA_MEM_TO_DEV, 465 .dst_maxburst = uap->fifosize >> 1, 466 .device_fc = false, 467 }; 468 struct dma_chan *chan; 469 dma_cap_mask_t mask; 470 471 uap->dma_probed = true; 472 chan = dma_request_chan(dev, "tx"); 473 if (IS_ERR(chan)) { 474 if (PTR_ERR(chan) == -EPROBE_DEFER) { 475 uap->dma_probed = false; 476 return; 477 } 478 479 /* We need platform data */ 480 if (!plat || !plat->dma_filter) { 481 dev_dbg(uap->port.dev, "no DMA platform data\n"); 482 return; 483 } 484 485 /* Try to acquire a generic DMA engine slave TX channel */ 486 dma_cap_zero(mask); 487 dma_cap_set(DMA_SLAVE, mask); 488 489 chan = dma_request_channel(mask, plat->dma_filter, 490 plat->dma_tx_param); 491 if (!chan) { 492 dev_err(uap->port.dev, "no TX DMA channel!\n"); 493 return; 494 } 495 } 496 497 dmaengine_slave_config(chan, &tx_conf); 498 uap->dmatx.chan = chan; 499 500 dev_info(uap->port.dev, "DMA channel TX %s\n", 501 dma_chan_name(uap->dmatx.chan)); 502 503 /* Optionally make use of an RX channel as well */ 504 chan = dma_request_chan(dev, "rx"); 505 506 if (IS_ERR(chan) && plat && plat->dma_rx_param) { 507 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 508 509 if (!chan) { 510 dev_err(uap->port.dev, "no RX DMA channel!\n"); 511 return; 512 } 513 } 514 515 if (!IS_ERR(chan)) { 516 struct dma_slave_config rx_conf = { 517 .src_addr = uap->port.mapbase + 518 pl011_reg_to_offset(uap, REG_DR), 519 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 520 .direction = DMA_DEV_TO_MEM, 521 .src_maxburst = uap->fifosize >> 2, 522 .device_fc = false, 523 }; 524 struct dma_slave_caps caps; 525 526 /* 527 * Some DMA controllers provide information on their capabilities. 528 * If the controller does, check for suitable residue processing 529 * otherwise assime all is well. 530 */ 531 if (dma_get_slave_caps(chan, &caps) == 0) { 532 if (caps.residue_granularity == 533 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 534 dma_release_channel(chan); 535 dev_info(uap->port.dev, 536 "RX DMA disabled - no residue processing\n"); 537 return; 538 } 539 } 540 dmaengine_slave_config(chan, &rx_conf); 541 uap->dmarx.chan = chan; 542 543 uap->dmarx.auto_poll_rate = false; 544 if (plat && plat->dma_rx_poll_enable) { 545 /* Set poll rate if specified. */ 546 if (plat->dma_rx_poll_rate) { 547 uap->dmarx.auto_poll_rate = false; 548 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 549 } else { 550 /* 551 * 100 ms defaults to poll rate if not 552 * specified. This will be adjusted with 553 * the baud rate at set_termios. 554 */ 555 uap->dmarx.auto_poll_rate = true; 556 uap->dmarx.poll_rate = 100; 557 } 558 /* 3 secs defaults poll_timeout if not specified. */ 559 if (plat->dma_rx_poll_timeout) 560 uap->dmarx.poll_timeout = 561 plat->dma_rx_poll_timeout; 562 else 563 uap->dmarx.poll_timeout = 3000; 564 } else if (!plat && dev->of_node) { 565 uap->dmarx.auto_poll_rate = 566 of_property_read_bool(dev->of_node, "auto-poll"); 567 if (uap->dmarx.auto_poll_rate) { 568 u32 x; 569 570 if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0) 571 uap->dmarx.poll_rate = x; 572 else 573 uap->dmarx.poll_rate = 100; 574 if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0) 575 uap->dmarx.poll_timeout = x; 576 else 577 uap->dmarx.poll_timeout = 3000; 578 } 579 } 580 dev_info(uap->port.dev, "DMA channel RX %s\n", 581 dma_chan_name(uap->dmarx.chan)); 582 } 583 } 584 585 static void pl011_dma_remove(struct uart_amba_port *uap) 586 { 587 if (uap->dmatx.chan) 588 dma_release_channel(uap->dmatx.chan); 589 if (uap->dmarx.chan) 590 dma_release_channel(uap->dmarx.chan); 591 } 592 593 /* Forward declare these for the refill routine */ 594 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 595 static void pl011_start_tx_pio(struct uart_amba_port *uap); 596 597 /* 598 * The current DMA TX buffer has been sent. 599 * Try to queue up another DMA buffer. 600 */ 601 static void pl011_dma_tx_callback(void *data) 602 { 603 struct uart_amba_port *uap = data; 604 struct tty_port *tport = &uap->port.state->port; 605 struct pl011_dmatx_data *dmatx = &uap->dmatx; 606 unsigned long flags; 607 u16 dmacr; 608 609 uart_port_lock_irqsave(&uap->port, &flags); 610 if (uap->dmatx.queued) 611 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma, 612 dmatx->len, DMA_TO_DEVICE); 613 614 dmacr = uap->dmacr; 615 uap->dmacr = dmacr & ~UART011_TXDMAE; 616 pl011_write(uap->dmacr, uap, REG_DMACR); 617 618 /* 619 * If TX DMA was disabled, it means that we've stopped the DMA for 620 * some reason (eg, XOFF received, or we want to send an X-char.) 621 * 622 * Note: we need to be careful here of a potential race between DMA 623 * and the rest of the driver - if the driver disables TX DMA while 624 * a TX buffer completing, we must update the tx queued status to 625 * get further refills (hence we check dmacr). 626 */ 627 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 628 kfifo_is_empty(&tport->xmit_fifo)) { 629 uap->dmatx.queued = false; 630 uart_port_unlock_irqrestore(&uap->port, flags); 631 return; 632 } 633 634 if (pl011_dma_tx_refill(uap) <= 0) 635 /* 636 * We didn't queue a DMA buffer for some reason, but we 637 * have data pending to be sent. Re-enable the TX IRQ. 638 */ 639 pl011_start_tx_pio(uap); 640 641 uart_port_unlock_irqrestore(&uap->port, flags); 642 } 643 644 /* 645 * Try to refill the TX DMA buffer. 646 * Locking: called with port lock held and IRQs disabled. 647 * Returns: 648 * 1 if we queued up a TX DMA buffer. 649 * 0 if we didn't want to handle this by DMA 650 * <0 on error 651 */ 652 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 653 { 654 struct pl011_dmatx_data *dmatx = &uap->dmatx; 655 struct dma_chan *chan = dmatx->chan; 656 struct dma_device *dma_dev = chan->device; 657 struct dma_async_tx_descriptor *desc; 658 struct tty_port *tport = &uap->port.state->port; 659 unsigned int count; 660 661 /* 662 * Try to avoid the overhead involved in using DMA if the 663 * transaction fits in the first half of the FIFO, by using 664 * the standard interrupt handling. This ensures that we 665 * issue a uart_write_wakeup() at the appropriate time. 666 */ 667 count = kfifo_len(&tport->xmit_fifo); 668 if (count < (uap->fifosize >> 1)) { 669 uap->dmatx.queued = false; 670 return 0; 671 } 672 673 /* 674 * Bodge: don't send the last character by DMA, as this 675 * will prevent XON from notifying us to restart DMA. 676 */ 677 count -= 1; 678 679 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 680 if (count > PL011_DMA_BUFFER_SIZE) 681 count = PL011_DMA_BUFFER_SIZE; 682 683 count = kfifo_out_peek(&tport->xmit_fifo, dmatx->buf, count); 684 685 /* 686 * Align the TX buffer length to the DMA controller's copy_align 687 * requirements. Some DMA controllers (e.g., Tegra GPC DMA) require 688 * word-aligned transfers. Unaligned bytes will be sent via PIO. 689 */ 690 if (chan->device->copy_align) 691 count = ALIGN_DOWN(count, 1 << chan->device->copy_align); 692 693 dmatx->len = count; 694 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, 695 DMA_TO_DEVICE); 696 if (dma_mapping_error(dma_dev->dev, dmatx->dma)) { 697 uap->dmatx.queued = false; 698 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 699 return -EBUSY; 700 } 701 702 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV, 703 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 704 if (!desc) { 705 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE); 706 uap->dmatx.queued = false; 707 /* 708 * If DMA cannot be used right now, we complete this 709 * transaction via IRQ and let the TTY layer retry. 710 */ 711 dev_dbg(uap->port.dev, "TX DMA busy\n"); 712 return -EBUSY; 713 } 714 715 /* Some data to go along to the callback */ 716 desc->callback = pl011_dma_tx_callback; 717 desc->callback_param = uap; 718 719 /* All errors should happen at prepare time */ 720 dmaengine_submit(desc); 721 722 /* Fire the DMA transaction */ 723 dma_dev->device_issue_pending(chan); 724 725 uap->dmacr |= UART011_TXDMAE; 726 pl011_write(uap->dmacr, uap, REG_DMACR); 727 uap->dmatx.queued = true; 728 729 /* 730 * Now we know that DMA will fire, so advance the ring buffer 731 * with the stuff we just dispatched. 732 */ 733 uart_xmit_advance(&uap->port, count); 734 735 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 736 uart_write_wakeup(&uap->port); 737 738 return 1; 739 } 740 741 /* 742 * We received a transmit interrupt without a pending X-char but with 743 * pending characters. 744 * Locking: called with port lock held and IRQs disabled. 745 * Returns: 746 * false if we want to use PIO to transmit 747 * true if we queued a DMA buffer 748 */ 749 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 750 { 751 if (!uap->using_tx_dma) 752 return false; 753 754 /* 755 * If we already have a TX buffer queued, but received a 756 * TX interrupt, it will be because we've just sent an X-char. 757 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 758 */ 759 if (uap->dmatx.queued) { 760 uap->dmacr |= UART011_TXDMAE; 761 pl011_write(uap->dmacr, uap, REG_DMACR); 762 uap->im &= ~UART011_TXIM; 763 pl011_write(uap->im, uap, REG_IMSC); 764 return true; 765 } 766 767 /* 768 * We don't have a TX buffer queued, so try to queue one. 769 * If we successfully queued a buffer, mask the TX IRQ. 770 */ 771 if (pl011_dma_tx_refill(uap) > 0) { 772 uap->im &= ~UART011_TXIM; 773 pl011_write(uap->im, uap, REG_IMSC); 774 return true; 775 } 776 return false; 777 } 778 779 /* 780 * Stop the DMA transmit (eg, due to received XOFF). 781 * Locking: called with port lock held and IRQs disabled. 782 */ 783 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 784 { 785 if (uap->dmatx.queued) { 786 uap->dmacr &= ~UART011_TXDMAE; 787 pl011_write(uap->dmacr, uap, REG_DMACR); 788 } 789 } 790 791 /* 792 * Try to start a DMA transmit, or in the case of an XON/OFF 793 * character queued for send, try to get that character out ASAP. 794 * Locking: called with port lock held and IRQs disabled. 795 * Returns: 796 * false if we want the TX IRQ to be enabled 797 * true if we have a buffer queued 798 */ 799 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 800 { 801 u16 dmacr; 802 803 if (!uap->using_tx_dma) 804 return false; 805 806 if (!uap->port.x_char) { 807 /* no X-char, try to push chars out in DMA mode */ 808 bool ret = true; 809 810 if (!uap->dmatx.queued) { 811 if (pl011_dma_tx_refill(uap) > 0) { 812 uap->im &= ~UART011_TXIM; 813 pl011_write(uap->im, uap, REG_IMSC); 814 } else { 815 ret = false; 816 } 817 } else if (!(uap->dmacr & UART011_TXDMAE)) { 818 uap->dmacr |= UART011_TXDMAE; 819 pl011_write(uap->dmacr, uap, REG_DMACR); 820 } 821 return ret; 822 } 823 824 /* 825 * We have an X-char to send. Disable DMA to prevent it loading 826 * the TX fifo, and then see if we can stuff it into the FIFO. 827 */ 828 dmacr = uap->dmacr; 829 uap->dmacr &= ~UART011_TXDMAE; 830 pl011_write(uap->dmacr, uap, REG_DMACR); 831 832 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 833 /* 834 * No space in the FIFO, so enable the transmit interrupt 835 * so we know when there is space. Note that once we've 836 * loaded the character, we should just re-enable DMA. 837 */ 838 return false; 839 } 840 841 pl011_write(uap->port.x_char, uap, REG_DR); 842 uap->port.icount.tx++; 843 uap->port.x_char = 0; 844 845 /* Success - restore the DMA state */ 846 uap->dmacr = dmacr; 847 pl011_write(dmacr, uap, REG_DMACR); 848 849 return true; 850 } 851 852 /* 853 * Flush the transmit buffer. 854 * Locking: called with port lock held and IRQs disabled. 855 */ 856 static void pl011_dma_flush_buffer(struct uart_port *port) 857 __releases(&uap->port.lock) 858 __acquires(&uap->port.lock) 859 { 860 struct uart_amba_port *uap = 861 container_of(port, struct uart_amba_port, port); 862 863 if (!uap->using_tx_dma) 864 return; 865 866 dmaengine_terminate_async(uap->dmatx.chan); 867 868 if (uap->dmatx.queued) { 869 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, 870 uap->dmatx.len, DMA_TO_DEVICE); 871 uap->dmatx.queued = false; 872 uap->dmacr &= ~UART011_TXDMAE; 873 pl011_write(uap->dmacr, uap, REG_DMACR); 874 } 875 } 876 877 static void pl011_dma_rx_callback(void *data); 878 879 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 880 { 881 struct dma_chan *rxchan = uap->dmarx.chan; 882 struct pl011_dmarx_data *dmarx = &uap->dmarx; 883 struct dma_async_tx_descriptor *desc; 884 struct pl011_dmabuf *dbuf; 885 886 if (!rxchan) 887 return -EIO; 888 889 /* Start the RX DMA job */ 890 dbuf = uap->dmarx.use_buf_b ? 891 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 892 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len, 893 DMA_DEV_TO_MEM, 894 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 895 /* 896 * If the DMA engine is busy and cannot prepare a 897 * channel, no big deal, the driver will fall back 898 * to interrupt mode as a result of this error code. 899 */ 900 if (!desc) { 901 uap->dmarx.running = false; 902 dmaengine_terminate_all(rxchan); 903 return -EBUSY; 904 } 905 906 /* Some data to go along to the callback */ 907 desc->callback = pl011_dma_rx_callback; 908 desc->callback_param = uap; 909 dmarx->cookie = dmaengine_submit(desc); 910 dma_async_issue_pending(rxchan); 911 912 uap->dmacr |= UART011_RXDMAE; 913 pl011_write(uap->dmacr, uap, REG_DMACR); 914 uap->dmarx.running = true; 915 916 uap->im &= ~UART011_RXIM; 917 pl011_write(uap->im, uap, REG_IMSC); 918 919 return 0; 920 } 921 922 /* 923 * This is called when either the DMA job is complete, or 924 * the FIFO timeout interrupt occurred. This must be called 925 * with the port spinlock uap->port.lock held. 926 */ 927 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 928 u32 pending, bool use_buf_b, 929 bool readfifo) 930 { 931 struct tty_port *port = &uap->port.state->port; 932 struct pl011_dmabuf *dbuf = use_buf_b ? 933 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 934 int dma_count = 0; 935 u32 fifotaken = 0; /* only used for vdbg() */ 936 937 struct pl011_dmarx_data *dmarx = &uap->dmarx; 938 int dmataken = 0; 939 940 if (uap->dmarx.poll_rate) { 941 /* The data can be taken by polling */ 942 dmataken = dbuf->len - dmarx->last_residue; 943 /* Recalculate the pending size */ 944 if (pending >= dmataken) 945 pending -= dmataken; 946 } 947 948 /* Pick the remain data from the DMA */ 949 if (pending) { 950 /* 951 * First take all chars in the DMA pipe, then look in the FIFO. 952 * Note that tty_insert_flip_buf() tries to take as many chars 953 * as it can. 954 */ 955 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending); 956 957 uap->port.icount.rx += dma_count; 958 if (dma_count < pending) 959 dev_warn(uap->port.dev, 960 "couldn't insert all characters (TTY is full?)\n"); 961 } 962 963 /* Reset the last_residue for Rx DMA poll */ 964 if (uap->dmarx.poll_rate) 965 dmarx->last_residue = dbuf->len; 966 967 /* 968 * Only continue with trying to read the FIFO if all DMA chars have 969 * been taken first. 970 */ 971 if (dma_count == pending && readfifo) { 972 /* Clear any error flags */ 973 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 974 UART011_FEIS, uap, REG_ICR); 975 976 /* 977 * If we read all the DMA'd characters, and we had an 978 * incomplete buffer, that could be due to an rx error, or 979 * maybe we just timed out. Read any pending chars and check 980 * the error status. 981 * 982 * Error conditions will only occur in the FIFO, these will 983 * trigger an immediate interrupt and stop the DMA job, so we 984 * will always find the error in the FIFO, never in the DMA 985 * buffer. 986 */ 987 fifotaken = pl011_fifo_to_tty(uap); 988 } 989 990 dev_vdbg(uap->port.dev, 991 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 992 dma_count, fifotaken); 993 tty_flip_buffer_push(port); 994 } 995 996 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 997 { 998 struct pl011_dmarx_data *dmarx = &uap->dmarx; 999 struct dma_chan *rxchan = dmarx->chan; 1000 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? 1001 &dmarx->dbuf_b : &dmarx->dbuf_a; 1002 size_t pending; 1003 struct dma_tx_state state; 1004 enum dma_status dmastat; 1005 1006 /* 1007 * Pause the transfer so we can trust the current counter, 1008 * do this before we pause the PL011 block, else we may 1009 * overflow the FIFO. 1010 */ 1011 if (dmaengine_pause(rxchan)) 1012 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 1013 dmastat = rxchan->device->device_tx_status(rxchan, 1014 dmarx->cookie, &state); 1015 if (dmastat != DMA_PAUSED) 1016 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 1017 1018 /* Disable RX DMA - incoming data will wait in the FIFO */ 1019 uap->dmacr &= ~UART011_RXDMAE; 1020 pl011_write(uap->dmacr, uap, REG_DMACR); 1021 uap->dmarx.running = false; 1022 1023 pending = dbuf->len - state.residue; 1024 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1025 /* Then we terminate the transfer - we now know our residue */ 1026 dmaengine_terminate_all(rxchan); 1027 1028 /* 1029 * This will take the chars we have so far and insert 1030 * into the framework. 1031 */ 1032 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 1033 1034 /* Switch buffer & re-trigger DMA job */ 1035 dmarx->use_buf_b = !dmarx->use_buf_b; 1036 if (pl011_dma_rx_trigger_dma(uap)) { 1037 dev_dbg(uap->port.dev, 1038 "could not retrigger RX DMA job fall back to interrupt mode\n"); 1039 uap->im |= UART011_RXIM; 1040 pl011_write(uap->im, uap, REG_IMSC); 1041 } 1042 } 1043 1044 static void pl011_dma_rx_callback(void *data) 1045 { 1046 struct uart_amba_port *uap = data; 1047 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1048 struct dma_chan *rxchan = dmarx->chan; 1049 bool lastbuf = dmarx->use_buf_b; 1050 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? 1051 &dmarx->dbuf_b : &dmarx->dbuf_a; 1052 size_t pending; 1053 struct dma_tx_state state; 1054 int ret; 1055 1056 /* 1057 * This completion interrupt occurs typically when the 1058 * RX buffer is totally stuffed but no timeout has yet 1059 * occurred. When that happens, we just want the RX 1060 * routine to flush out the secondary DMA buffer while 1061 * we immediately trigger the next DMA job. 1062 */ 1063 uart_port_lock_irq(&uap->port); 1064 /* 1065 * Rx data can be taken by the UART interrupts during 1066 * the DMA irq handler. So we check the residue here. 1067 */ 1068 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1069 pending = dbuf->len - state.residue; 1070 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1071 /* Then we terminate the transfer - we now know our residue */ 1072 dmaengine_terminate_all(rxchan); 1073 1074 uap->dmarx.running = false; 1075 dmarx->use_buf_b = !lastbuf; 1076 ret = pl011_dma_rx_trigger_dma(uap); 1077 1078 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1079 uart_unlock_and_check_sysrq(&uap->port); 1080 /* 1081 * Do this check after we picked the DMA chars so we don't 1082 * get some IRQ immediately from RX. 1083 */ 1084 if (ret) { 1085 dev_dbg(uap->port.dev, 1086 "could not retrigger RX DMA job fall back to interrupt mode\n"); 1087 uap->im |= UART011_RXIM; 1088 pl011_write(uap->im, uap, REG_IMSC); 1089 } 1090 } 1091 1092 /* 1093 * Stop accepting received characters, when we're shutting down or 1094 * suspending this port. 1095 * Locking: called with port lock held and IRQs disabled. 1096 */ 1097 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1098 { 1099 if (!uap->using_rx_dma) 1100 return; 1101 1102 /* FIXME. Just disable the DMA enable */ 1103 uap->dmacr &= ~UART011_RXDMAE; 1104 pl011_write(uap->dmacr, uap, REG_DMACR); 1105 } 1106 1107 /* 1108 * Timer handler for Rx DMA polling. 1109 * Every polling, It checks the residue in the dma buffer and transfer 1110 * data to the tty. Also, last_residue is updated for the next polling. 1111 */ 1112 static void pl011_dma_rx_poll(struct timer_list *t) 1113 { 1114 struct uart_amba_port *uap = timer_container_of(uap, t, dmarx.timer); 1115 struct tty_port *port = &uap->port.state->port; 1116 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1117 struct dma_chan *rxchan = uap->dmarx.chan; 1118 unsigned long flags; 1119 unsigned int dmataken = 0; 1120 unsigned int size = 0; 1121 struct pl011_dmabuf *dbuf; 1122 int dma_count; 1123 struct dma_tx_state state; 1124 1125 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 1126 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1127 if (likely(state.residue < dmarx->last_residue)) { 1128 dmataken = dbuf->len - dmarx->last_residue; 1129 size = dmarx->last_residue - state.residue; 1130 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, 1131 size); 1132 if (dma_count == size) 1133 dmarx->last_residue = state.residue; 1134 dmarx->last_jiffies = jiffies; 1135 } 1136 tty_flip_buffer_push(port); 1137 1138 /* 1139 * If no data is received in poll_timeout, the driver will fall back 1140 * to interrupt mode. We will retrigger DMA at the first interrupt. 1141 */ 1142 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1143 > uap->dmarx.poll_timeout) { 1144 uart_port_lock_irqsave(&uap->port, &flags); 1145 pl011_dma_rx_stop(uap); 1146 uap->im |= UART011_RXIM; 1147 pl011_write(uap->im, uap, REG_IMSC); 1148 uart_port_unlock_irqrestore(&uap->port, flags); 1149 1150 uap->dmarx.running = false; 1151 dmaengine_terminate_all(rxchan); 1152 timer_delete(&uap->dmarx.timer); 1153 } else { 1154 mod_timer(&uap->dmarx.timer, 1155 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1156 } 1157 } 1158 1159 static void pl011_dma_startup(struct uart_amba_port *uap) 1160 { 1161 int ret; 1162 1163 if (!uap->dma_probed) 1164 pl011_dma_probe(uap); 1165 1166 if (!uap->dmatx.chan) 1167 return; 1168 1169 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1170 if (!uap->dmatx.buf) { 1171 uap->port.fifosize = uap->fifosize; 1172 return; 1173 } 1174 1175 uap->dmatx.len = PL011_DMA_BUFFER_SIZE; 1176 1177 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1178 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1179 uap->using_tx_dma = true; 1180 1181 if (!uap->dmarx.chan) 1182 goto skip_rx; 1183 1184 /* Allocate and map DMA RX buffers */ 1185 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, 1186 DMA_FROM_DEVICE); 1187 if (ret) { 1188 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1189 "RX buffer A", ret); 1190 goto skip_rx; 1191 } 1192 1193 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, 1194 DMA_FROM_DEVICE); 1195 if (ret) { 1196 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1197 "RX buffer B", ret); 1198 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, 1199 DMA_FROM_DEVICE); 1200 goto skip_rx; 1201 } 1202 1203 uap->using_rx_dma = true; 1204 1205 skip_rx: 1206 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1207 uap->dmacr |= UART011_DMAONERR; 1208 pl011_write(uap->dmacr, uap, REG_DMACR); 1209 1210 /* 1211 * ST Micro variants has some specific dma burst threshold 1212 * compensation. Set this to 16 bytes, so burst will only 1213 * be issued above/below 16 bytes. 1214 */ 1215 if (uap->vendor->dma_threshold) 1216 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1217 uap, REG_ST_DMAWM); 1218 1219 if (uap->using_rx_dma) { 1220 if (pl011_dma_rx_trigger_dma(uap)) 1221 dev_dbg(uap->port.dev, 1222 "could not trigger initial RX DMA job, fall back to interrupt mode\n"); 1223 if (uap->dmarx.poll_rate) { 1224 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); 1225 mod_timer(&uap->dmarx.timer, 1226 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1227 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1228 uap->dmarx.last_jiffies = jiffies; 1229 } 1230 } 1231 } 1232 1233 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1234 { 1235 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1236 return; 1237 1238 /* Disable RX and TX DMA */ 1239 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1240 cpu_relax(); 1241 1242 uart_port_lock_irq(&uap->port); 1243 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1244 pl011_write(uap->dmacr, uap, REG_DMACR); 1245 uart_port_unlock_irq(&uap->port); 1246 1247 if (uap->using_tx_dma) { 1248 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1249 dmaengine_terminate_all(uap->dmatx.chan); 1250 if (uap->dmatx.queued) { 1251 dma_unmap_single(uap->dmatx.chan->device->dev, 1252 uap->dmatx.dma, uap->dmatx.len, 1253 DMA_TO_DEVICE); 1254 uap->dmatx.queued = false; 1255 } 1256 1257 kfree(uap->dmatx.buf); 1258 uap->using_tx_dma = false; 1259 } 1260 1261 if (uap->using_rx_dma) { 1262 dmaengine_terminate_all(uap->dmarx.chan); 1263 /* Clean up the RX DMA */ 1264 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); 1265 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); 1266 if (uap->dmarx.poll_rate) 1267 timer_delete_sync(&uap->dmarx.timer); 1268 uap->using_rx_dma = false; 1269 } 1270 } 1271 1272 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1273 { 1274 return uap->using_rx_dma; 1275 } 1276 1277 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1278 { 1279 return uap->using_rx_dma && uap->dmarx.running; 1280 } 1281 1282 #else 1283 /* Blank functions if the DMA engine is not available */ 1284 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1285 { 1286 } 1287 1288 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1289 { 1290 } 1291 1292 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1293 { 1294 } 1295 1296 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1297 { 1298 return false; 1299 } 1300 1301 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1302 { 1303 } 1304 1305 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1306 { 1307 return false; 1308 } 1309 1310 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1311 { 1312 } 1313 1314 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1315 { 1316 } 1317 1318 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1319 { 1320 return -EIO; 1321 } 1322 1323 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1324 { 1325 return false; 1326 } 1327 1328 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1329 { 1330 return false; 1331 } 1332 1333 #define pl011_dma_flush_buffer NULL 1334 #endif 1335 1336 static void pl011_rs485_tx_stop(struct uart_amba_port *uap) 1337 { 1338 struct uart_port *port = &uap->port; 1339 u32 cr; 1340 1341 if (uap->rs485_tx_state == SEND) 1342 uap->rs485_tx_state = WAIT_AFTER_SEND; 1343 1344 if (uap->rs485_tx_state == WAIT_AFTER_SEND) { 1345 /* Schedule hrtimer if tx queue not empty */ 1346 if (!pl011_tx_empty(port)) { 1347 hrtimer_start(&uap->trigger_stop_tx, 1348 uap->rs485_tx_drain_interval, 1349 HRTIMER_MODE_REL); 1350 return; 1351 } 1352 if (port->rs485.delay_rts_after_send > 0) { 1353 hrtimer_start(&uap->trigger_stop_tx, 1354 ms_to_ktime(port->rs485.delay_rts_after_send), 1355 HRTIMER_MODE_REL); 1356 return; 1357 } 1358 /* Continue without any delay */ 1359 } else if (uap->rs485_tx_state == WAIT_AFTER_RTS) { 1360 hrtimer_try_to_cancel(&uap->trigger_start_tx); 1361 } 1362 1363 cr = pl011_read(uap, REG_CR); 1364 1365 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1366 cr &= ~UART011_CR_RTS; 1367 else 1368 cr |= UART011_CR_RTS; 1369 1370 /* Disable the transmitter and reenable the transceiver */ 1371 cr &= ~UART011_CR_TXE; 1372 cr |= UART011_CR_RXE; 1373 pl011_write(cr, uap, REG_CR); 1374 1375 uap->rs485_tx_state = OFF; 1376 } 1377 1378 static void pl011_stop_tx(struct uart_port *port) 1379 { 1380 struct uart_amba_port *uap = 1381 container_of(port, struct uart_amba_port, port); 1382 1383 if (port->rs485.flags & SER_RS485_ENABLED && 1384 uap->rs485_tx_state == WAIT_AFTER_RTS) { 1385 pl011_rs485_tx_stop(uap); 1386 return; 1387 } 1388 1389 uap->im &= ~UART011_TXIM; 1390 pl011_write(uap->im, uap, REG_IMSC); 1391 pl011_dma_tx_stop(uap); 1392 1393 if (port->rs485.flags & SER_RS485_ENABLED && 1394 uap->rs485_tx_state != OFF) 1395 pl011_rs485_tx_stop(uap); 1396 } 1397 1398 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1399 1400 /* Start TX with programmed I/O only (no DMA) */ 1401 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1402 { 1403 if (pl011_tx_chars(uap, false)) { 1404 uap->im |= UART011_TXIM; 1405 pl011_write(uap->im, uap, REG_IMSC); 1406 } 1407 } 1408 1409 static void pl011_rs485_tx_start(struct uart_amba_port *uap) 1410 { 1411 struct uart_port *port = &uap->port; 1412 u32 cr; 1413 1414 if (uap->rs485_tx_state == WAIT_AFTER_RTS) { 1415 uap->rs485_tx_state = SEND; 1416 return; 1417 } 1418 if (uap->rs485_tx_state == WAIT_AFTER_SEND) { 1419 hrtimer_try_to_cancel(&uap->trigger_stop_tx); 1420 uap->rs485_tx_state = SEND; 1421 return; 1422 } 1423 /* uap->rs485_tx_state == OFF */ 1424 /* Enable transmitter */ 1425 cr = pl011_read(uap, REG_CR); 1426 cr |= UART011_CR_TXE; 1427 /* Disable receiver if half-duplex */ 1428 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1429 cr &= ~UART011_CR_RXE; 1430 1431 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 1432 cr &= ~UART011_CR_RTS; 1433 else 1434 cr |= UART011_CR_RTS; 1435 1436 pl011_write(cr, uap, REG_CR); 1437 1438 if (port->rs485.delay_rts_before_send > 0) { 1439 uap->rs485_tx_state = WAIT_AFTER_RTS; 1440 hrtimer_start(&uap->trigger_start_tx, 1441 ms_to_ktime(port->rs485.delay_rts_before_send), 1442 HRTIMER_MODE_REL); 1443 } else { 1444 uap->rs485_tx_state = SEND; 1445 } 1446 } 1447 1448 static void pl011_start_tx(struct uart_port *port) 1449 { 1450 struct uart_amba_port *uap = 1451 container_of(port, struct uart_amba_port, port); 1452 1453 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && 1454 uap->rs485_tx_state != SEND) { 1455 pl011_rs485_tx_start(uap); 1456 if (uap->rs485_tx_state == WAIT_AFTER_RTS) 1457 return; 1458 } 1459 1460 if (!pl011_dma_tx_start(uap)) 1461 pl011_start_tx_pio(uap); 1462 } 1463 1464 static enum hrtimer_restart pl011_trigger_start_tx(struct hrtimer *t) 1465 { 1466 struct uart_amba_port *uap = 1467 container_of(t, struct uart_amba_port, trigger_start_tx); 1468 unsigned long flags; 1469 1470 uart_port_lock_irqsave(&uap->port, &flags); 1471 if (uap->rs485_tx_state == WAIT_AFTER_RTS) 1472 pl011_start_tx(&uap->port); 1473 uart_port_unlock_irqrestore(&uap->port, flags); 1474 1475 return HRTIMER_NORESTART; 1476 } 1477 1478 static enum hrtimer_restart pl011_trigger_stop_tx(struct hrtimer *t) 1479 { 1480 struct uart_amba_port *uap = 1481 container_of(t, struct uart_amba_port, trigger_stop_tx); 1482 unsigned long flags; 1483 1484 uart_port_lock_irqsave(&uap->port, &flags); 1485 if (uap->rs485_tx_state == WAIT_AFTER_SEND) 1486 pl011_rs485_tx_stop(uap); 1487 uart_port_unlock_irqrestore(&uap->port, flags); 1488 1489 return HRTIMER_NORESTART; 1490 } 1491 1492 static void pl011_stop_rx(struct uart_port *port) 1493 { 1494 struct uart_amba_port *uap = 1495 container_of(port, struct uart_amba_port, port); 1496 1497 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM | 1498 UART011_PEIM | UART011_BEIM | UART011_OEIM); 1499 pl011_write(uap->im, uap, REG_IMSC); 1500 1501 pl011_dma_rx_stop(uap); 1502 } 1503 1504 static void pl011_throttle_rx(struct uart_port *port) 1505 { 1506 unsigned long flags; 1507 1508 uart_port_lock_irqsave(port, &flags); 1509 pl011_stop_rx(port); 1510 uart_port_unlock_irqrestore(port, flags); 1511 } 1512 1513 static void pl011_enable_ms(struct uart_port *port) 1514 { 1515 struct uart_amba_port *uap = 1516 container_of(port, struct uart_amba_port, port); 1517 1518 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM; 1519 pl011_write(uap->im, uap, REG_IMSC); 1520 } 1521 1522 static void pl011_rx_chars(struct uart_amba_port *uap) 1523 __releases(&uap->port.lock) 1524 __acquires(&uap->port.lock) 1525 { 1526 pl011_fifo_to_tty(uap); 1527 1528 uart_port_unlock(&uap->port); 1529 tty_flip_buffer_push(&uap->port.state->port); 1530 /* 1531 * If we were temporarily out of DMA mode for a while, 1532 * attempt to switch back to DMA mode again. 1533 */ 1534 if (pl011_dma_rx_available(uap)) { 1535 if (pl011_dma_rx_trigger_dma(uap)) { 1536 dev_dbg(uap->port.dev, 1537 "could not trigger RX DMA job fall back to interrupt mode again\n"); 1538 uap->im |= UART011_RXIM; 1539 pl011_write(uap->im, uap, REG_IMSC); 1540 } else { 1541 #ifdef CONFIG_DMA_ENGINE 1542 /* Start Rx DMA poll */ 1543 if (uap->dmarx.poll_rate) { 1544 uap->dmarx.last_jiffies = jiffies; 1545 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1546 mod_timer(&uap->dmarx.timer, 1547 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1548 } 1549 #endif 1550 } 1551 } 1552 uart_port_lock(&uap->port); 1553 } 1554 1555 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1556 bool from_irq) 1557 { 1558 if (unlikely(!from_irq) && 1559 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1560 return false; /* unable to transmit character */ 1561 1562 pl011_write(c, uap, REG_DR); 1563 uap->port.icount.tx++; 1564 1565 return true; 1566 } 1567 1568 /* Returns true if tx interrupts have to be (kept) enabled */ 1569 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1570 { 1571 struct tty_port *tport = &uap->port.state->port; 1572 int count = uap->fifosize >> 1; 1573 1574 if (uap->port.x_char) { 1575 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1576 return true; 1577 uap->port.x_char = 0; 1578 --count; 1579 } 1580 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(&uap->port)) { 1581 pl011_stop_tx(&uap->port); 1582 return false; 1583 } 1584 1585 /* If we are using DMA mode, try to send some characters. */ 1586 if (pl011_dma_tx_irq(uap)) 1587 return true; 1588 1589 while (1) { 1590 unsigned char c; 1591 1592 if (likely(from_irq) && count-- == 0) 1593 break; 1594 1595 if (!kfifo_peek(&tport->xmit_fifo, &c)) 1596 break; 1597 1598 if (!pl011_tx_char(uap, c, from_irq)) 1599 break; 1600 1601 kfifo_skip(&tport->xmit_fifo); 1602 } 1603 1604 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1605 uart_write_wakeup(&uap->port); 1606 1607 if (kfifo_is_empty(&tport->xmit_fifo)) { 1608 pl011_stop_tx(&uap->port); 1609 return false; 1610 } 1611 return true; 1612 } 1613 1614 static void pl011_modem_status(struct uart_amba_port *uap) 1615 { 1616 unsigned int status, delta; 1617 1618 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1619 1620 delta = status ^ uap->old_status; 1621 uap->old_status = status; 1622 1623 if (!delta) 1624 return; 1625 1626 if (delta & UART01x_FR_DCD) 1627 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1628 1629 if (delta & uap->vendor->fr_dsr) 1630 uap->port.icount.dsr++; 1631 1632 if (delta & uap->vendor->fr_cts) 1633 uart_handle_cts_change(&uap->port, 1634 status & uap->vendor->fr_cts); 1635 1636 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1637 } 1638 1639 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1640 { 1641 if (!uap->vendor->cts_event_workaround) 1642 return; 1643 1644 /* workaround to make sure that all bits are unlocked.. */ 1645 pl011_write(0x00, uap, REG_ICR); 1646 1647 /* 1648 * WA: introduce 26ns(1 uart clk) delay before W1C; 1649 * single apb access will incur 2 pclk(133.12Mhz) delay, 1650 * so add 2 dummy reads 1651 */ 1652 pl011_read(uap, REG_ICR); 1653 pl011_read(uap, REG_ICR); 1654 } 1655 1656 static irqreturn_t pl011_int(int irq, void *dev_id) 1657 { 1658 struct uart_amba_port *uap = dev_id; 1659 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1660 int handled = 0; 1661 1662 uart_port_lock(&uap->port); 1663 status = pl011_read(uap, REG_RIS) & uap->im; 1664 if (status) { 1665 do { 1666 check_apply_cts_event_workaround(uap); 1667 1668 pl011_write(status & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS), 1669 uap, REG_ICR); 1670 1671 if (status & (UART011_RTIS | UART011_RXIS)) { 1672 if (pl011_dma_rx_running(uap)) 1673 pl011_dma_rx_irq(uap); 1674 else 1675 pl011_rx_chars(uap); 1676 } 1677 if (status & (UART011_DSRMIS | UART011_DCDMIS | 1678 UART011_CTSMIS | UART011_RIMIS)) 1679 pl011_modem_status(uap); 1680 if (status & UART011_TXIS) 1681 pl011_tx_chars(uap, true); 1682 1683 if (pass_counter-- == 0) 1684 break; 1685 1686 status = pl011_read(uap, REG_RIS) & uap->im; 1687 } while (status != 0); 1688 handled = 1; 1689 } 1690 1691 uart_unlock_and_check_sysrq(&uap->port); 1692 1693 return IRQ_RETVAL(handled); 1694 } 1695 1696 static unsigned int pl011_tx_empty(struct uart_port *port) 1697 { 1698 struct uart_amba_port *uap = 1699 container_of(port, struct uart_amba_port, port); 1700 1701 /* Allow feature register bits to be inverted to work around errata */ 1702 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; 1703 1704 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1705 0 : TIOCSER_TEMT; 1706 } 1707 1708 static void pl011_maybe_set_bit(bool cond, unsigned int *ptr, unsigned int mask) 1709 { 1710 if (cond) 1711 *ptr |= mask; 1712 } 1713 1714 static unsigned int pl011_get_mctrl(struct uart_port *port) 1715 { 1716 struct uart_amba_port *uap = 1717 container_of(port, struct uart_amba_port, port); 1718 unsigned int result = 0; 1719 unsigned int status = pl011_read(uap, REG_FR); 1720 1721 pl011_maybe_set_bit(status & UART01x_FR_DCD, &result, TIOCM_CAR); 1722 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR); 1723 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS); 1724 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG); 1725 1726 return result; 1727 } 1728 1729 static void pl011_assign_bit(bool cond, unsigned int *ptr, unsigned int mask) 1730 { 1731 if (cond) 1732 *ptr |= mask; 1733 else 1734 *ptr &= ~mask; 1735 } 1736 1737 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1738 { 1739 struct uart_amba_port *uap = 1740 container_of(port, struct uart_amba_port, port); 1741 unsigned int cr; 1742 1743 cr = pl011_read(uap, REG_CR); 1744 1745 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTS); 1746 pl011_assign_bit(mctrl & TIOCM_DTR, &cr, UART011_CR_DTR); 1747 pl011_assign_bit(mctrl & TIOCM_OUT1, &cr, UART011_CR_OUT1); 1748 pl011_assign_bit(mctrl & TIOCM_OUT2, &cr, UART011_CR_OUT2); 1749 pl011_assign_bit(mctrl & TIOCM_LOOP, &cr, UART011_CR_LBE); 1750 1751 if (port->status & UPSTAT_AUTORTS) { 1752 /* We need to disable auto-RTS if we want to turn RTS off */ 1753 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTSEN); 1754 } 1755 1756 pl011_write(cr, uap, REG_CR); 1757 } 1758 1759 static void pl011_break_ctl(struct uart_port *port, int break_state) 1760 { 1761 struct uart_amba_port *uap = 1762 container_of(port, struct uart_amba_port, port); 1763 unsigned long flags; 1764 unsigned int lcr_h; 1765 1766 uart_port_lock_irqsave(&uap->port, &flags); 1767 lcr_h = pl011_read(uap, REG_LCRH_TX); 1768 if (break_state == -1) 1769 lcr_h |= UART01x_LCRH_BRK; 1770 else 1771 lcr_h &= ~UART01x_LCRH_BRK; 1772 pl011_write(lcr_h, uap, REG_LCRH_TX); 1773 uart_port_unlock_irqrestore(&uap->port, flags); 1774 } 1775 1776 #ifdef CONFIG_CONSOLE_POLL 1777 1778 static void pl011_quiesce_irqs(struct uart_port *port) 1779 { 1780 struct uart_amba_port *uap = 1781 container_of(port, struct uart_amba_port, port); 1782 1783 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1784 /* 1785 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1786 * we simply mask it. start_tx() will unmask it. 1787 * 1788 * Note we can race with start_tx(), and if the race happens, the 1789 * polling user might get another interrupt just after we clear it. 1790 * But it should be OK and can happen even w/o the race, e.g. 1791 * controller immediately got some new data and raised the IRQ. 1792 * 1793 * And whoever uses polling routines assumes that it manages the device 1794 * (including tx queue), so we're also fine with start_tx()'s caller 1795 * side. 1796 */ 1797 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1798 REG_IMSC); 1799 } 1800 1801 static int pl011_get_poll_char(struct uart_port *port) 1802 { 1803 struct uart_amba_port *uap = 1804 container_of(port, struct uart_amba_port, port); 1805 unsigned int status; 1806 1807 /* 1808 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1809 * debugger. 1810 */ 1811 pl011_quiesce_irqs(port); 1812 1813 status = pl011_read(uap, REG_FR); 1814 if (status & UART01x_FR_RXFE) 1815 return NO_POLL_CHAR; 1816 1817 return pl011_read(uap, REG_DR); 1818 } 1819 1820 static void pl011_put_poll_char(struct uart_port *port, unsigned char ch) 1821 { 1822 struct uart_amba_port *uap = 1823 container_of(port, struct uart_amba_port, port); 1824 1825 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1826 cpu_relax(); 1827 1828 pl011_write(ch, uap, REG_DR); 1829 } 1830 1831 #endif /* CONFIG_CONSOLE_POLL */ 1832 1833 static int pl011_hwinit(struct uart_port *port) 1834 { 1835 struct uart_amba_port *uap = 1836 container_of(port, struct uart_amba_port, port); 1837 int retval; 1838 1839 /* Optionaly enable pins to be muxed in and configured */ 1840 pinctrl_pm_select_default_state(port->dev); 1841 1842 /* 1843 * Try to enable the clock producer. 1844 */ 1845 retval = clk_prepare_enable(uap->clk); 1846 if (retval) 1847 return retval; 1848 1849 uap->port.uartclk = clk_get_rate(uap->clk); 1850 1851 /* Clear pending error and receive interrupts */ 1852 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1853 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1854 uap, REG_ICR); 1855 1856 /* 1857 * Save interrupts enable mask, and enable RX interrupts in case if 1858 * the interrupt is used for NMI entry. 1859 */ 1860 uap->im = pl011_read(uap, REG_IMSC); 1861 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1862 1863 if (dev_get_platdata(uap->port.dev)) { 1864 struct amba_pl011_data *plat; 1865 1866 plat = dev_get_platdata(uap->port.dev); 1867 if (plat->init) 1868 plat->init(); 1869 } 1870 return 0; 1871 } 1872 1873 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1874 { 1875 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1876 pl011_reg_to_offset(uap, REG_LCRH_TX); 1877 } 1878 1879 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1880 { 1881 pl011_write(lcr_h, uap, REG_LCRH_RX); 1882 if (pl011_split_lcrh(uap)) { 1883 int i; 1884 /* 1885 * Wait 10 PCLKs before writing LCRH_TX register, 1886 * to get this delay write read only register 10 times 1887 */ 1888 for (i = 0; i < 10; ++i) 1889 pl011_write(0xff, uap, REG_MIS); 1890 pl011_write(lcr_h, uap, REG_LCRH_TX); 1891 } 1892 } 1893 1894 static int pl011_allocate_irq(struct uart_amba_port *uap) 1895 { 1896 pl011_write(uap->im, uap, REG_IMSC); 1897 1898 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); 1899 } 1900 1901 /* 1902 * Enable interrupts, only timeouts when using DMA 1903 * if initial RX DMA job failed, start in interrupt mode 1904 * as well. 1905 */ 1906 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1907 { 1908 unsigned long flags; 1909 unsigned int i; 1910 1911 uart_port_lock_irqsave(&uap->port, &flags); 1912 1913 /* Clear out any spuriously appearing RX interrupts */ 1914 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1915 1916 /* 1917 * RXIS is asserted only when the RX FIFO transitions from below 1918 * to above the trigger threshold. If the RX FIFO is already 1919 * full to the threshold this can't happen and RXIS will now be 1920 * stuck off. Drain the RX FIFO explicitly to fix this: 1921 */ 1922 for (i = 0; i < uap->fifosize * 2; ++i) { 1923 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) 1924 break; 1925 1926 pl011_read(uap, REG_DR); 1927 } 1928 1929 uap->im = UART011_RTIM; 1930 if (!pl011_dma_rx_running(uap)) 1931 uap->im |= UART011_RXIM; 1932 pl011_write(uap->im, uap, REG_IMSC); 1933 uart_port_unlock_irqrestore(&uap->port, flags); 1934 } 1935 1936 static void pl011_unthrottle_rx(struct uart_port *port) 1937 { 1938 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); 1939 unsigned long flags; 1940 1941 uart_port_lock_irqsave(&uap->port, &flags); 1942 1943 uap->im = UART011_RTIM; 1944 if (!pl011_dma_rx_running(uap)) 1945 uap->im |= UART011_RXIM; 1946 1947 pl011_write(uap->im, uap, REG_IMSC); 1948 1949 #ifdef CONFIG_DMA_ENGINE 1950 if (uap->using_rx_dma) { 1951 uap->dmacr |= UART011_RXDMAE; 1952 pl011_write(uap->dmacr, uap, REG_DMACR); 1953 } 1954 #endif 1955 1956 uart_port_unlock_irqrestore(&uap->port, flags); 1957 } 1958 1959 static int pl011_startup(struct uart_port *port) 1960 { 1961 struct uart_amba_port *uap = 1962 container_of(port, struct uart_amba_port, port); 1963 unsigned int cr; 1964 int retval; 1965 1966 retval = pl011_hwinit(port); 1967 if (retval) 1968 goto clk_dis; 1969 1970 retval = pl011_allocate_irq(uap); 1971 if (retval) 1972 goto clk_dis; 1973 1974 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1975 1976 uart_port_lock_irq(&uap->port); 1977 1978 cr = pl011_read(uap, REG_CR); 1979 cr &= UART011_CR_RTS | UART011_CR_DTR; 1980 cr |= UART01x_CR_UARTEN | UART011_CR_RXE; 1981 1982 if (!(port->rs485.flags & SER_RS485_ENABLED)) 1983 cr |= UART011_CR_TXE; 1984 1985 pl011_write(cr, uap, REG_CR); 1986 1987 uart_port_unlock_irq(&uap->port); 1988 1989 /* 1990 * initialise the old status of the modem signals 1991 */ 1992 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1993 1994 /* Startup DMA */ 1995 pl011_dma_startup(uap); 1996 1997 pl011_enable_interrupts(uap); 1998 1999 return 0; 2000 2001 clk_dis: 2002 clk_disable_unprepare(uap->clk); 2003 return retval; 2004 } 2005 2006 static int sbsa_uart_startup(struct uart_port *port) 2007 { 2008 struct uart_amba_port *uap = 2009 container_of(port, struct uart_amba_port, port); 2010 int retval; 2011 2012 retval = pl011_hwinit(port); 2013 if (retval) 2014 return retval; 2015 2016 retval = pl011_allocate_irq(uap); 2017 if (retval) 2018 return retval; 2019 2020 /* The SBSA UART does not support any modem status lines. */ 2021 uap->old_status = 0; 2022 2023 pl011_enable_interrupts(uap); 2024 2025 return 0; 2026 } 2027 2028 static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh) 2029 { 2030 unsigned long val; 2031 2032 val = pl011_read(uap, lcrh); 2033 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 2034 pl011_write(val, uap, lcrh); 2035 } 2036 2037 /* 2038 * disable the port. It should not disable RTS and DTR. 2039 * Also RTS and DTR state should be preserved to restore 2040 * it during startup(). 2041 */ 2042 static void pl011_disable_uart(struct uart_amba_port *uap) 2043 { 2044 unsigned int cr; 2045 2046 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2047 uart_port_lock_irq(&uap->port); 2048 cr = pl011_read(uap, REG_CR); 2049 cr &= UART011_CR_RTS | UART011_CR_DTR; 2050 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2051 pl011_write(cr, uap, REG_CR); 2052 uart_port_unlock_irq(&uap->port); 2053 2054 /* 2055 * disable break condition and fifos 2056 */ 2057 pl011_shutdown_channel(uap, REG_LCRH_RX); 2058 if (pl011_split_lcrh(uap)) 2059 pl011_shutdown_channel(uap, REG_LCRH_TX); 2060 } 2061 2062 static void pl011_disable_interrupts(struct uart_amba_port *uap) 2063 { 2064 uart_port_lock_irq(&uap->port); 2065 2066 /* mask all interrupts and clear all pending ones */ 2067 uap->im = 0; 2068 pl011_write(uap->im, uap, REG_IMSC); 2069 pl011_write(0xffff, uap, REG_ICR); 2070 2071 uart_port_unlock_irq(&uap->port); 2072 } 2073 2074 static void pl011_shutdown(struct uart_port *port) 2075 { 2076 struct uart_amba_port *uap = 2077 container_of(port, struct uart_amba_port, port); 2078 2079 pl011_disable_interrupts(uap); 2080 2081 pl011_dma_shutdown(uap); 2082 2083 if ((port->rs485.flags & SER_RS485_ENABLED && uap->rs485_tx_state != OFF)) 2084 pl011_rs485_tx_stop(uap); 2085 2086 free_irq(uap->port.irq, uap); 2087 2088 pl011_disable_uart(uap); 2089 2090 /* 2091 * Shut down the clock producer 2092 */ 2093 clk_disable_unprepare(uap->clk); 2094 /* Optionally let pins go into sleep states */ 2095 pinctrl_pm_select_sleep_state(port->dev); 2096 2097 if (dev_get_platdata(uap->port.dev)) { 2098 struct amba_pl011_data *plat; 2099 2100 plat = dev_get_platdata(uap->port.dev); 2101 if (plat->exit) 2102 plat->exit(); 2103 } 2104 2105 if (uap->port.ops->flush_buffer) 2106 uap->port.ops->flush_buffer(port); 2107 } 2108 2109 static void sbsa_uart_shutdown(struct uart_port *port) 2110 { 2111 struct uart_amba_port *uap = 2112 container_of(port, struct uart_amba_port, port); 2113 2114 pl011_disable_interrupts(uap); 2115 2116 free_irq(uap->port.irq, uap); 2117 2118 if (uap->port.ops->flush_buffer) 2119 uap->port.ops->flush_buffer(port); 2120 } 2121 2122 static void 2123 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 2124 { 2125 port->read_status_mask = UART011_DR_OE | 255; 2126 if (termios->c_iflag & INPCK) 2127 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 2128 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2129 port->read_status_mask |= UART011_DR_BE; 2130 2131 /* 2132 * Characters to ignore 2133 */ 2134 port->ignore_status_mask = 0; 2135 if (termios->c_iflag & IGNPAR) 2136 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 2137 if (termios->c_iflag & IGNBRK) { 2138 port->ignore_status_mask |= UART011_DR_BE; 2139 /* 2140 * If we're ignoring parity and break indicators, 2141 * ignore overruns too (for real raw support). 2142 */ 2143 if (termios->c_iflag & IGNPAR) 2144 port->ignore_status_mask |= UART011_DR_OE; 2145 } 2146 2147 /* 2148 * Ignore all characters if CREAD is not set. 2149 */ 2150 if ((termios->c_cflag & CREAD) == 0) 2151 port->ignore_status_mask |= UART_DUMMY_DR_RX; 2152 } 2153 2154 static void 2155 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 2156 const struct ktermios *old) 2157 { 2158 struct uart_amba_port *uap = 2159 container_of(port, struct uart_amba_port, port); 2160 unsigned int lcr_h, old_cr; 2161 unsigned long flags; 2162 unsigned int baud, quot, clkdiv; 2163 unsigned int max_baud; 2164 unsigned int bits; 2165 2166 if (uap->vendor->oversampling) 2167 clkdiv = 8; 2168 else 2169 clkdiv = 16; 2170 2171 max_baud = port->uartclk / clkdiv; 2172 2173 if (uap->vendor->set_uartclk_rate) { 2174 long max_clkrate = clk_round_rate(uap->clk, UINT_MAX); 2175 2176 /* 2177 * Clock is reprogrammable - determine max baud from the clock's 2178 * maximum rate, not the current uartclk. 2179 */ 2180 if (max_clkrate > 0) 2181 max_baud = max_clkrate / clkdiv; 2182 } 2183 2184 /* 2185 * Ask the core to calculate the divisor for us. 2186 */ 2187 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 2188 2189 if (uap->vendor->set_uartclk_rate) { 2190 int err; 2191 2192 err = clk_set_rate(uap->clk, baud * clkdiv); 2193 if (err) { 2194 dev_err(port->dev, "Failed to set clock rate: %d\n", err); 2195 return; 2196 } 2197 } 2198 2199 #ifdef CONFIG_DMA_ENGINE 2200 /* 2201 * Adjust RX DMA polling rate with baud rate if not specified. 2202 */ 2203 if (uap->dmarx.auto_poll_rate) 2204 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 2205 #endif 2206 2207 switch (termios->c_cflag & CSIZE) { 2208 case CS5: 2209 lcr_h = UART01x_LCRH_WLEN_5; 2210 break; 2211 case CS6: 2212 lcr_h = UART01x_LCRH_WLEN_6; 2213 break; 2214 case CS7: 2215 lcr_h = UART01x_LCRH_WLEN_7; 2216 break; 2217 default: // CS8 2218 lcr_h = UART01x_LCRH_WLEN_8; 2219 break; 2220 } 2221 if (termios->c_cflag & CSTOPB) 2222 lcr_h |= UART01x_LCRH_STP2; 2223 if (termios->c_cflag & PARENB) { 2224 lcr_h |= UART01x_LCRH_PEN; 2225 if (!(termios->c_cflag & PARODD)) 2226 lcr_h |= UART01x_LCRH_EPS; 2227 if (termios->c_cflag & CMSPAR) 2228 lcr_h |= UART011_LCRH_SPS; 2229 } 2230 if (uap->fifosize > 1) 2231 lcr_h |= UART01x_LCRH_FEN; 2232 2233 bits = tty_get_frame_size(termios->c_cflag); 2234 2235 uart_port_lock_irqsave(port, &flags); 2236 2237 /* 2238 * Update the per-port timeout. 2239 */ 2240 uart_update_timeout(port, termios->c_cflag, baud); 2241 2242 /* 2243 * Calculate the approximated time it takes to transmit one character 2244 * with the given baud rate. We use this as the poll interval when we 2245 * wait for the tx queue to empty. 2246 */ 2247 uap->rs485_tx_drain_interval = ns_to_ktime(DIV_ROUND_UP(bits * NSEC_PER_SEC, baud)); 2248 2249 pl011_setup_status_masks(port, termios); 2250 2251 if (UART_ENABLE_MS(port, termios->c_cflag)) 2252 pl011_enable_ms(port); 2253 2254 if (port->rs485.flags & SER_RS485_ENABLED) 2255 termios->c_cflag &= ~CRTSCTS; 2256 2257 old_cr = pl011_read(uap, REG_CR); 2258 2259 if (termios->c_cflag & CRTSCTS) { 2260 if (old_cr & UART011_CR_RTS) 2261 old_cr |= UART011_CR_RTSEN; 2262 2263 old_cr |= UART011_CR_CTSEN; 2264 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 2265 } else { 2266 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2267 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2268 } 2269 2270 if (uap->vendor->oversampling) { 2271 if (baud > port->uartclk / 16) 2272 old_cr |= ST_UART011_CR_OVSFACT; 2273 else 2274 old_cr &= ~ST_UART011_CR_OVSFACT; 2275 } 2276 2277 if (!uap->vendor->skip_ibrd_fbrd) { 2278 if (baud > port->uartclk / 16) 2279 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 2280 else 2281 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 2282 2283 /* 2284 * Workaround for the ST Micro oversampling variants to 2285 * increase the bitrate slightly, by lowering the divisor, 2286 * to avoid delayed sampling of start bit at high speeds, 2287 * else we see data corruption. 2288 */ 2289 if (uap->vendor->oversampling) { 2290 if (baud >= 3000000 && baud < 3250000 && quot > 1) 2291 quot -= 1; 2292 else if (baud > 3250000 && quot > 2) 2293 quot -= 2; 2294 } 2295 /* Set baud rate */ 2296 pl011_write(quot & 0x3f, uap, REG_FBRD); 2297 pl011_write(quot >> 6, uap, REG_IBRD); 2298 } 2299 2300 /* 2301 * ----------v----------v----------v----------v----- 2302 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2303 * REG_FBRD & REG_IBRD. 2304 * ----------^----------^----------^----------^----- 2305 */ 2306 pl011_write_lcr_h(uap, lcr_h); 2307 2308 /* 2309 * Receive was disabled by pl011_disable_uart during shutdown. 2310 * Need to reenable receive if you need to use a tty_driver 2311 * returns from tty_find_polling_driver() after a port shutdown. 2312 */ 2313 old_cr |= UART011_CR_RXE; 2314 pl011_write(old_cr, uap, REG_CR); 2315 2316 uart_port_unlock_irqrestore(port, flags); 2317 } 2318 2319 static void 2320 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2321 const struct ktermios *old) 2322 { 2323 struct uart_amba_port *uap = 2324 container_of(port, struct uart_amba_port, port); 2325 unsigned long flags; 2326 2327 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2328 2329 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2330 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2331 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2332 termios->c_cflag |= CS8 | CLOCAL; 2333 2334 uart_port_lock_irqsave(port, &flags); 2335 uart_update_timeout(port, CS8, uap->fixed_baud); 2336 pl011_setup_status_masks(port, termios); 2337 uart_port_unlock_irqrestore(port, flags); 2338 } 2339 2340 static const char *pl011_type(struct uart_port *port) 2341 { 2342 struct uart_amba_port *uap = 2343 container_of(port, struct uart_amba_port, port); 2344 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2345 } 2346 2347 /* 2348 * Configure/autoconfigure the port. 2349 */ 2350 static void pl011_config_port(struct uart_port *port, int flags) 2351 { 2352 if (flags & UART_CONFIG_TYPE) 2353 port->type = PORT_AMBA; 2354 } 2355 2356 /* 2357 * verify the new serial_struct (for TIOCSSERIAL). 2358 */ 2359 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2360 { 2361 int ret = 0; 2362 2363 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2364 ret = -EINVAL; 2365 if (ser->irq < 0 || ser->irq >= irq_get_nr_irqs()) 2366 ret = -EINVAL; 2367 if (ser->baud_base < 9600) 2368 ret = -EINVAL; 2369 if (port->mapbase != (unsigned long)ser->iomem_base) 2370 ret = -EINVAL; 2371 return ret; 2372 } 2373 2374 static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios, 2375 struct serial_rs485 *rs485) 2376 { 2377 struct uart_amba_port *uap = 2378 container_of(port, struct uart_amba_port, port); 2379 2380 if (port->rs485.flags & SER_RS485_ENABLED) 2381 pl011_rs485_tx_stop(uap); 2382 2383 /* Make sure auto RTS is disabled */ 2384 if (rs485->flags & SER_RS485_ENABLED) { 2385 u32 cr = pl011_read(uap, REG_CR); 2386 2387 cr &= ~UART011_CR_RTSEN; 2388 pl011_write(cr, uap, REG_CR); 2389 port->status &= ~UPSTAT_AUTORTS; 2390 } 2391 2392 return 0; 2393 } 2394 2395 static const struct uart_ops amba_pl011_pops = { 2396 .tx_empty = pl011_tx_empty, 2397 .set_mctrl = pl011_set_mctrl, 2398 .get_mctrl = pl011_get_mctrl, 2399 .stop_tx = pl011_stop_tx, 2400 .start_tx = pl011_start_tx, 2401 .stop_rx = pl011_stop_rx, 2402 .throttle = pl011_throttle_rx, 2403 .unthrottle = pl011_unthrottle_rx, 2404 .enable_ms = pl011_enable_ms, 2405 .break_ctl = pl011_break_ctl, 2406 .startup = pl011_startup, 2407 .shutdown = pl011_shutdown, 2408 .flush_buffer = pl011_dma_flush_buffer, 2409 .set_termios = pl011_set_termios, 2410 .type = pl011_type, 2411 .config_port = pl011_config_port, 2412 .verify_port = pl011_verify_port, 2413 #ifdef CONFIG_CONSOLE_POLL 2414 .poll_init = pl011_hwinit, 2415 .poll_get_char = pl011_get_poll_char, 2416 .poll_put_char = pl011_put_poll_char, 2417 #endif 2418 }; 2419 2420 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2421 { 2422 } 2423 2424 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2425 { 2426 return 0; 2427 } 2428 2429 static const struct uart_ops sbsa_uart_pops = { 2430 .tx_empty = pl011_tx_empty, 2431 .set_mctrl = sbsa_uart_set_mctrl, 2432 .get_mctrl = sbsa_uart_get_mctrl, 2433 .stop_tx = pl011_stop_tx, 2434 .start_tx = pl011_start_tx, 2435 .stop_rx = pl011_stop_rx, 2436 .startup = sbsa_uart_startup, 2437 .shutdown = sbsa_uart_shutdown, 2438 .set_termios = sbsa_uart_set_termios, 2439 .type = pl011_type, 2440 .config_port = pl011_config_port, 2441 .verify_port = pl011_verify_port, 2442 #ifdef CONFIG_CONSOLE_POLL 2443 .poll_init = pl011_hwinit, 2444 .poll_get_char = pl011_get_poll_char, 2445 .poll_put_char = pl011_put_poll_char, 2446 #endif 2447 }; 2448 2449 static struct uart_amba_port *amba_ports[UART_NR]; 2450 2451 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2452 2453 static void pl011_console_putchar(struct uart_port *port, unsigned char ch) 2454 { 2455 struct uart_amba_port *uap = 2456 container_of(port, struct uart_amba_port, port); 2457 2458 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2459 cpu_relax(); 2460 pl011_write(ch, uap, REG_DR); 2461 uap->console_line_ended = (ch == '\n'); 2462 } 2463 2464 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2465 int *parity, int *bits) 2466 { 2467 unsigned int lcr_h, ibrd, fbrd; 2468 unsigned int clkdiv; 2469 2470 if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN)) 2471 return; 2472 2473 lcr_h = pl011_read(uap, REG_LCRH_TX); 2474 2475 *parity = 'n'; 2476 if (lcr_h & UART01x_LCRH_PEN) { 2477 if (lcr_h & UART01x_LCRH_EPS) 2478 *parity = 'e'; 2479 else 2480 *parity = 'o'; 2481 } 2482 2483 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2484 *bits = 7; 2485 else 2486 *bits = 8; 2487 2488 if (uap->vendor->skip_ibrd_fbrd) { 2489 clkdiv = 64; 2490 } else { 2491 ibrd = pl011_read(uap, REG_IBRD); 2492 fbrd = pl011_read(uap, REG_FBRD); 2493 clkdiv = 64 * ibrd + fbrd; 2494 } 2495 2496 *baud = uap->port.uartclk * 4 / clkdiv; 2497 2498 if (uap->vendor->oversampling && 2499 (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT)) 2500 *baud *= 2; 2501 } 2502 2503 static int pl011_console_setup(struct console *co, char *options) 2504 { 2505 struct uart_amba_port *uap; 2506 int baud = 38400; 2507 int bits = 8; 2508 int parity = 'n'; 2509 int flow = 'n'; 2510 int ret; 2511 2512 /* 2513 * Check whether an invalid uart number has been specified, and 2514 * if so, search for the first available port that does have 2515 * console support. 2516 */ 2517 if (co->index >= UART_NR) 2518 co->index = 0; 2519 uap = amba_ports[co->index]; 2520 if (!uap) 2521 return -ENODEV; 2522 2523 /* Allow pins to be muxed in and configured */ 2524 pinctrl_pm_select_default_state(uap->port.dev); 2525 2526 ret = clk_prepare(uap->clk); 2527 if (ret) 2528 return ret; 2529 2530 uap->console_line_ended = true; 2531 2532 if (dev_get_platdata(uap->port.dev)) { 2533 struct amba_pl011_data *plat; 2534 2535 plat = dev_get_platdata(uap->port.dev); 2536 if (plat->init) 2537 plat->init(); 2538 } 2539 2540 uap->port.uartclk = clk_get_rate(uap->clk); 2541 2542 if (uap->vendor->fixed_options) { 2543 baud = uap->fixed_baud; 2544 } else { 2545 if (options) 2546 uart_parse_options(options, 2547 &baud, &parity, &bits, &flow); 2548 else 2549 pl011_console_get_options(uap, &baud, &parity, &bits); 2550 } 2551 2552 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2553 } 2554 2555 /** 2556 * pl011_console_match - non-standard console matching 2557 * @co: registering console 2558 * @name: name from console command line 2559 * @idx: index from console command line 2560 * @options: ptr to option string from console command line 2561 * 2562 * Only attempts to match console command lines of the form: 2563 * console=pl011,mmio|mmio32,<addr>[,<options>] 2564 * console=pl011,0x<addr>[,<options>] 2565 * This form is used to register an initial earlycon boot console and 2566 * replace it with the amba_console at pl011 driver init. 2567 * 2568 * Performs console setup for a match (as required by interface) 2569 * If no <options> are specified, then assume the h/w is already setup. 2570 * 2571 * Returns 0 if console matches; otherwise non-zero to use default matching 2572 */ 2573 static int pl011_console_match(struct console *co, char *name, int idx, 2574 char *options) 2575 { 2576 enum uart_iotype iotype; 2577 resource_size_t addr; 2578 int i; 2579 2580 /* 2581 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum 2582 * have a distinct console name, so make sure we check for that. 2583 * The actual implementation of the erratum occurs in the probe 2584 * function. 2585 */ 2586 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) 2587 return -ENODEV; 2588 2589 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 2590 return -ENODEV; 2591 2592 if (iotype != UPIO_MEM && iotype != UPIO_MEM32) 2593 return -ENODEV; 2594 2595 /* try to match the port specified on the command line */ 2596 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2597 struct uart_port *port; 2598 2599 if (!amba_ports[i]) 2600 continue; 2601 2602 port = &amba_ports[i]->port; 2603 2604 if (port->mapbase != addr) 2605 continue; 2606 2607 co->index = i; 2608 uart_port_set_cons(port, co); 2609 return pl011_console_setup(co, options); 2610 } 2611 2612 return -ENODEV; 2613 } 2614 2615 static void 2616 pl011_console_write_atomic(struct console *co, struct nbcon_write_context *wctxt) 2617 { 2618 struct uart_amba_port *uap = amba_ports[co->index]; 2619 unsigned int old_cr = 0; 2620 2621 if (!nbcon_enter_unsafe(wctxt)) 2622 return; 2623 2624 clk_enable(uap->clk); 2625 2626 if (!uap->vendor->always_enabled) { 2627 old_cr = pl011_read(uap, REG_CR); 2628 pl011_write((old_cr & ~UART011_CR_CTSEN) | (UART01x_CR_UARTEN | UART011_CR_TXE), 2629 uap, REG_CR); 2630 } 2631 2632 if (!uap->console_line_ended) 2633 uart_console_write(&uap->port, "\n", 1, pl011_console_putchar); 2634 uart_console_write(&uap->port, wctxt->outbuf, wctxt->len, pl011_console_putchar); 2635 2636 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) & uap->vendor->fr_busy) 2637 cpu_relax(); 2638 2639 if (!uap->vendor->always_enabled) 2640 pl011_write(old_cr, uap, REG_CR); 2641 2642 clk_disable(uap->clk); 2643 2644 nbcon_exit_unsafe(wctxt); 2645 } 2646 2647 static void 2648 pl011_console_write_thread(struct console *co, struct nbcon_write_context *wctxt) 2649 { 2650 struct uart_amba_port *uap = amba_ports[co->index]; 2651 unsigned int old_cr = 0; 2652 2653 if (!nbcon_enter_unsafe(wctxt)) 2654 return; 2655 2656 clk_enable(uap->clk); 2657 2658 if (!uap->vendor->always_enabled) { 2659 old_cr = pl011_read(uap, REG_CR); 2660 pl011_write((old_cr & ~UART011_CR_CTSEN) | (UART01x_CR_UARTEN | UART011_CR_TXE), 2661 uap, REG_CR); 2662 } 2663 2664 if (nbcon_exit_unsafe(wctxt)) { 2665 int i; 2666 unsigned int len = READ_ONCE(wctxt->len); 2667 2668 for (i = 0; i < len; i++) { 2669 if (!nbcon_enter_unsafe(wctxt)) 2670 break; 2671 uart_console_write(&uap->port, wctxt->outbuf + i, 1, pl011_console_putchar); 2672 if (!nbcon_exit_unsafe(wctxt)) 2673 break; 2674 } 2675 } 2676 2677 while (!nbcon_enter_unsafe(wctxt)) 2678 nbcon_reacquire_nobuf(wctxt); 2679 2680 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) & uap->vendor->fr_busy) 2681 cpu_relax(); 2682 2683 if (!uap->vendor->always_enabled) 2684 pl011_write(old_cr, uap, REG_CR); 2685 2686 clk_disable(uap->clk); 2687 2688 nbcon_exit_unsafe(wctxt); 2689 } 2690 2691 static void 2692 pl011_console_device_lock(struct console *co, unsigned long *flags) 2693 { 2694 __uart_port_lock_irqsave(&amba_ports[co->index]->port, flags); 2695 } 2696 2697 static void 2698 pl011_console_device_unlock(struct console *co, unsigned long flags) 2699 { 2700 __uart_port_unlock_irqrestore(&amba_ports[co->index]->port, flags); 2701 } 2702 2703 static struct uart_driver amba_reg; 2704 static struct console amba_console = { 2705 .name = "ttyAMA", 2706 .device = uart_console_device, 2707 .setup = pl011_console_setup, 2708 .match = pl011_console_match, 2709 .write_atomic = pl011_console_write_atomic, 2710 .write_thread = pl011_console_write_thread, 2711 .device_lock = pl011_console_device_lock, 2712 .device_unlock = pl011_console_device_unlock, 2713 .flags = CON_PRINTBUFFER | CON_ANYTIME | CON_NBCON, 2714 .index = -1, 2715 .data = &amba_reg, 2716 }; 2717 2718 #define AMBA_CONSOLE (&amba_console) 2719 2720 static void qdf2400_e44_putc(struct uart_port *port, unsigned char c) 2721 { 2722 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2723 cpu_relax(); 2724 writel(c, port->membase + UART01x_DR); 2725 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) 2726 cpu_relax(); 2727 } 2728 2729 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned int n) 2730 { 2731 struct earlycon_device *dev = con->data; 2732 2733 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); 2734 } 2735 2736 static void pl011_putc(struct uart_port *port, unsigned char c) 2737 { 2738 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2739 cpu_relax(); 2740 if (port->iotype == UPIO_MEM32) 2741 writel(c, port->membase + UART01x_DR); 2742 else 2743 writeb(c, port->membase + UART01x_DR); 2744 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2745 cpu_relax(); 2746 } 2747 2748 static void pl011_early_write(struct console *con, const char *s, unsigned int n) 2749 { 2750 struct earlycon_device *dev = con->data; 2751 2752 uart_console_write(&dev->port, s, n, pl011_putc); 2753 } 2754 2755 #ifdef CONFIG_CONSOLE_POLL 2756 static int pl011_getc(struct uart_port *port) 2757 { 2758 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) 2759 return NO_POLL_CHAR; 2760 2761 if (port->iotype == UPIO_MEM32) 2762 return readl(port->membase + UART01x_DR); 2763 else 2764 return readb(port->membase + UART01x_DR); 2765 } 2766 2767 static int pl011_early_read(struct console *con, char *s, unsigned int n) 2768 { 2769 struct earlycon_device *dev = con->data; 2770 int ch, num_read = 0; 2771 2772 while (num_read < n) { 2773 ch = pl011_getc(&dev->port); 2774 if (ch == NO_POLL_CHAR) 2775 break; 2776 2777 s[num_read++] = ch; 2778 } 2779 2780 return num_read; 2781 } 2782 #else 2783 #define pl011_early_read NULL 2784 #endif 2785 2786 /* 2787 * On non-ACPI systems, earlycon is enabled by specifying 2788 * "earlycon=pl011,<address>" on the kernel command line. 2789 * 2790 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, 2791 * by specifying only "earlycon" on the command line. Because it requires 2792 * SPCR, the console starts after ACPI is parsed, which is later than a 2793 * traditional early console. 2794 * 2795 * To get the traditional early console that starts before ACPI is parsed, 2796 * specify the full "earlycon=pl011,<address>" option. 2797 */ 2798 static int __init pl011_early_console_setup(struct earlycon_device *device, 2799 const char *opt) 2800 { 2801 unsigned int cr; 2802 2803 if (!device->port.membase) 2804 return -ENODEV; 2805 2806 device->con->write = pl011_early_write; 2807 device->con->read = pl011_early_read; 2808 2809 if (device->port.iotype == UPIO_MEM32) 2810 cr = readl(device->port.membase + UART011_CR); 2811 else 2812 cr = readw(device->port.membase + UART011_CR); 2813 cr &= UART011_CR_RTS | UART011_CR_DTR; 2814 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 2815 if (device->port.iotype == UPIO_MEM32) 2816 writel(cr, device->port.membase + UART011_CR); 2817 else 2818 writew(cr, device->port.membase + UART011_CR); 2819 2820 return 0; 2821 } 2822 2823 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2824 2825 /* 2826 * The SBSA UART has no defined control register and is assumed to 2827 * be pre-enabled by firmware, so we do not write to UART011_CR. 2828 */ 2829 static int __init sbsa_uart_early_console_setup(struct earlycon_device *device, 2830 const char *opt) 2831 { 2832 if (!device->port.membase) 2833 return -ENODEV; 2834 2835 device->con->write = pl011_early_write; 2836 device->con->read = pl011_early_read; 2837 2838 return 0; 2839 } 2840 2841 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", sbsa_uart_early_console_setup); 2842 2843 /* 2844 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by 2845 * Erratum 44, traditional earlycon can be enabled by specifying 2846 * "earlycon=qdf2400_e44,<address>". Any options are ignored. 2847 * 2848 * Alternatively, you can just specify "earlycon", and the early console 2849 * will be enabled with the information from the SPCR table. In this 2850 * case, the SPCR code will detect the need for the E44 work-around, 2851 * and set the console name to "qdf2400_e44". 2852 */ 2853 static int __init 2854 qdf2400_e44_early_console_setup(struct earlycon_device *device, 2855 const char *opt) 2856 { 2857 if (!device->port.membase) 2858 return -ENODEV; 2859 2860 device->con->write = qdf2400_e44_early_write; 2861 return 0; 2862 } 2863 2864 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); 2865 2866 #else 2867 #define AMBA_CONSOLE NULL 2868 #endif 2869 2870 static struct uart_driver amba_reg = { 2871 .owner = THIS_MODULE, 2872 .driver_name = "ttyAMA", 2873 .dev_name = "ttyAMA", 2874 .major = SERIAL_AMBA_MAJOR, 2875 .minor = SERIAL_AMBA_MINOR, 2876 .nr = UART_NR, 2877 .cons = AMBA_CONSOLE, 2878 }; 2879 2880 static int pl011_probe_dt_alias(int index, struct device *dev) 2881 { 2882 struct device_node *np; 2883 static bool seen_dev_with_alias; 2884 static bool seen_dev_without_alias; 2885 int ret = index; 2886 2887 if (!IS_ENABLED(CONFIG_OF)) 2888 return ret; 2889 2890 np = dev->of_node; 2891 if (!np) 2892 return ret; 2893 2894 ret = of_alias_get_id(np, "serial"); 2895 if (ret < 0) { 2896 seen_dev_without_alias = true; 2897 ret = index; 2898 } else { 2899 seen_dev_with_alias = true; 2900 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret]) { 2901 dev_warn(dev, "requested serial port %d not available.\n", ret); 2902 ret = index; 2903 } 2904 } 2905 2906 if (seen_dev_with_alias && seen_dev_without_alias) 2907 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2908 2909 return ret; 2910 } 2911 2912 /* unregisters the driver also if no more ports are left */ 2913 static void pl011_unregister_port(struct uart_amba_port *uap) 2914 { 2915 int i; 2916 bool busy = false; 2917 2918 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2919 if (amba_ports[i] == uap) 2920 amba_ports[i] = NULL; 2921 else if (amba_ports[i]) 2922 busy = true; 2923 } 2924 pl011_dma_remove(uap); 2925 if (!busy) 2926 uart_unregister_driver(&amba_reg); 2927 } 2928 2929 static int pl011_find_free_port(void) 2930 { 2931 int i; 2932 2933 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2934 if (!amba_ports[i]) 2935 return i; 2936 2937 return -EBUSY; 2938 } 2939 2940 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2941 struct resource *mmiobase, int index) 2942 { 2943 void __iomem *base; 2944 int ret; 2945 2946 base = devm_ioremap_resource(dev, mmiobase); 2947 if (IS_ERR(base)) 2948 return PTR_ERR(base); 2949 2950 index = pl011_probe_dt_alias(index, dev); 2951 2952 uap->port.dev = dev; 2953 uap->port.mapbase = mmiobase->start; 2954 uap->port.membase = base; 2955 uap->port.fifosize = uap->fifosize; 2956 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); 2957 uap->port.flags = UPF_BOOT_AUTOCONF; 2958 uap->port.line = index; 2959 2960 ret = uart_get_rs485_mode(&uap->port); 2961 if (ret) 2962 return ret; 2963 2964 amba_ports[index] = uap; 2965 2966 return 0; 2967 } 2968 2969 static int pl011_register_port(struct uart_amba_port *uap) 2970 { 2971 int ret, i; 2972 2973 /* Ensure interrupts from this UART are masked and cleared */ 2974 pl011_write(0, uap, REG_IMSC); 2975 pl011_write(0xffff, uap, REG_ICR); 2976 2977 if (!amba_reg.state) { 2978 ret = uart_register_driver(&amba_reg); 2979 if (ret < 0) { 2980 dev_err(uap->port.dev, 2981 "Failed to register AMBA-PL011 driver\n"); 2982 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2983 if (amba_ports[i] == uap) 2984 amba_ports[i] = NULL; 2985 return ret; 2986 } 2987 } 2988 2989 ret = uart_add_one_port(&amba_reg, &uap->port); 2990 if (ret) 2991 pl011_unregister_port(uap); 2992 2993 return ret; 2994 } 2995 2996 static const struct serial_rs485 pl011_rs485_supported = { 2997 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 2998 SER_RS485_RX_DURING_TX, 2999 .delay_rts_before_send = 1, 3000 .delay_rts_after_send = 1, 3001 }; 3002 3003 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 3004 { 3005 struct uart_amba_port *uap; 3006 struct vendor_data *vendor = id->data; 3007 int portnr, ret; 3008 u32 val; 3009 3010 portnr = pl011_find_free_port(); 3011 if (portnr < 0) 3012 return portnr; 3013 3014 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 3015 GFP_KERNEL); 3016 if (!uap) 3017 return -ENOMEM; 3018 3019 uap->clk = devm_clk_get(&dev->dev, NULL); 3020 if (IS_ERR(uap->clk)) 3021 return PTR_ERR(uap->clk); 3022 3023 uap->reg_offset = vendor->reg_offset; 3024 uap->vendor = vendor; 3025 uap->fifosize = vendor->get_fifosize(dev); 3026 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 3027 uap->port.irq = dev->irq[0]; 3028 uap->port.ops = &amba_pl011_pops; 3029 uap->port.rs485_config = pl011_rs485_config; 3030 uap->port.rs485_supported = pl011_rs485_supported; 3031 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 3032 3033 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { 3034 switch (val) { 3035 case 1: 3036 uap->port.iotype = UPIO_MEM; 3037 break; 3038 case 4: 3039 uap->port.iotype = UPIO_MEM32; 3040 break; 3041 default: 3042 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n", 3043 val); 3044 return -EINVAL; 3045 } 3046 } 3047 hrtimer_setup(&uap->trigger_start_tx, pl011_trigger_start_tx, CLOCK_MONOTONIC, 3048 HRTIMER_MODE_REL); 3049 hrtimer_setup(&uap->trigger_stop_tx, pl011_trigger_stop_tx, CLOCK_MONOTONIC, 3050 HRTIMER_MODE_REL); 3051 3052 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 3053 if (ret) 3054 return ret; 3055 3056 amba_set_drvdata(dev, uap); 3057 3058 return pl011_register_port(uap); 3059 } 3060 3061 static void pl011_remove(struct amba_device *dev) 3062 { 3063 struct uart_amba_port *uap = amba_get_drvdata(dev); 3064 3065 uart_remove_one_port(&amba_reg, &uap->port); 3066 pl011_unregister_port(uap); 3067 } 3068 3069 #ifdef CONFIG_PM_SLEEP 3070 static int pl011_suspend(struct device *dev) 3071 { 3072 struct uart_amba_port *uap = dev_get_drvdata(dev); 3073 3074 if (!uap) 3075 return -EINVAL; 3076 3077 return uart_suspend_port(&amba_reg, &uap->port); 3078 } 3079 3080 static int pl011_resume(struct device *dev) 3081 { 3082 struct uart_amba_port *uap = dev_get_drvdata(dev); 3083 3084 if (!uap) 3085 return -EINVAL; 3086 3087 return uart_resume_port(&amba_reg, &uap->port); 3088 } 3089 #endif 3090 3091 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 3092 3093 #ifdef CONFIG_ACPI_SPCR_TABLE 3094 static void qpdf2400_erratum44_workaround(struct device *dev, 3095 struct uart_amba_port *uap) 3096 { 3097 if (!qdf2400_e44_present) 3098 return; 3099 3100 dev_info(dev, "working around QDF2400 SoC erratum 44\n"); 3101 uap->vendor = &vendor_qdt_qdf2400_e44; 3102 } 3103 #else 3104 static void qpdf2400_erratum44_workaround(struct device *dev, 3105 struct uart_amba_port *uap) 3106 { /* empty */ } 3107 #endif 3108 3109 static int sbsa_uart_probe(struct platform_device *pdev) 3110 { 3111 struct uart_amba_port *uap; 3112 struct resource *r; 3113 int portnr, ret; 3114 int baudrate; 3115 3116 /* 3117 * Check the mandatory baud rate parameter in the DT node early 3118 * so that we can easily exit with the error. 3119 */ 3120 if (pdev->dev.of_node) { 3121 struct device_node *np = pdev->dev.of_node; 3122 3123 ret = of_property_read_u32(np, "current-speed", &baudrate); 3124 if (ret) 3125 return ret; 3126 } else { 3127 baudrate = 115200; 3128 } 3129 3130 portnr = pl011_find_free_port(); 3131 if (portnr < 0) 3132 return portnr; 3133 3134 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 3135 GFP_KERNEL); 3136 if (!uap) 3137 return -ENOMEM; 3138 3139 ret = platform_get_irq(pdev, 0); 3140 if (ret < 0) 3141 return ret; 3142 uap->port.irq = ret; 3143 3144 uap->vendor = &vendor_sbsa; 3145 qpdf2400_erratum44_workaround(&pdev->dev, uap); 3146 3147 uap->reg_offset = uap->vendor->reg_offset; 3148 uap->fifosize = 32; 3149 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 3150 uap->port.ops = &sbsa_uart_pops; 3151 uap->fixed_baud = baudrate; 3152 3153 snprintf(uap->type, sizeof(uap->type), "SBSA"); 3154 3155 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3156 3157 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 3158 if (ret) 3159 return ret; 3160 3161 platform_set_drvdata(pdev, uap); 3162 3163 return pl011_register_port(uap); 3164 } 3165 3166 static void sbsa_uart_remove(struct platform_device *pdev) 3167 { 3168 struct uart_amba_port *uap = platform_get_drvdata(pdev); 3169 3170 uart_remove_one_port(&amba_reg, &uap->port); 3171 pl011_unregister_port(uap); 3172 } 3173 3174 static const struct of_device_id sbsa_uart_of_match[] = { 3175 { .compatible = "arm,sbsa-uart", }, 3176 {}, 3177 }; 3178 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 3179 3180 static const struct acpi_device_id sbsa_uart_acpi_match[] = { 3181 { "ARMH0011", 0 }, 3182 { "ARMHB000", 0 }, 3183 {}, 3184 }; 3185 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 3186 3187 static struct platform_driver arm_sbsa_uart_platform_driver = { 3188 .probe = sbsa_uart_probe, 3189 .remove = sbsa_uart_remove, 3190 .driver = { 3191 .name = "sbsa-uart", 3192 .pm = &pl011_dev_pm_ops, 3193 .of_match_table = sbsa_uart_of_match, 3194 .acpi_match_table = sbsa_uart_acpi_match, 3195 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 3196 }, 3197 }; 3198 3199 static const struct amba_id pl011_ids[] = { 3200 { 3201 .id = 0x00041011, 3202 .mask = 0x000fffff, 3203 .data = &vendor_arm, 3204 }, 3205 { 3206 .id = 0x00380802, 3207 .mask = 0x00ffffff, 3208 .data = &vendor_st, 3209 }, 3210 { 3211 .id = 0x0006b011, 3212 .mask = 0x000fffff, 3213 .data = &vendor_nvidia, 3214 }, 3215 { 3216 /* This is an invented ID. The actual hardware that contains 3217 * these ZTE UARTs (zx29 boards) has no AMBA PIDs stored. ZTE 3218 * JEDEC ID (ignoring banks) and the "011" part number as used 3219 * by ARM. 3220 */ 3221 .id = 0x0008c011, 3222 .mask = 0x000fffff, 3223 .data = &vendor_zte, 3224 }, 3225 { 0, 0 }, 3226 }; 3227 3228 MODULE_DEVICE_TABLE(amba, pl011_ids); 3229 3230 static struct amba_driver pl011_driver = { 3231 .drv = { 3232 .name = "uart-pl011", 3233 .pm = &pl011_dev_pm_ops, 3234 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 3235 }, 3236 .id_table = pl011_ids, 3237 .probe = pl011_probe, 3238 .remove = pl011_remove, 3239 }; 3240 3241 static int __init pl011_init(void) 3242 { 3243 pr_info("Serial: AMBA PL011 UART driver\n"); 3244 3245 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 3246 pr_warn("could not register SBSA UART platform driver\n"); 3247 return amba_driver_register(&pl011_driver); 3248 } 3249 3250 static void __exit pl011_exit(void) 3251 { 3252 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 3253 amba_driver_unregister(&pl011_driver); 3254 } 3255 3256 /* 3257 * While this can be a module, if builtin it's most likely the console 3258 * So let's leave module_exit but move module_init to an earlier place 3259 */ 3260 arch_initcall(pl011_init); 3261 module_exit(pl011_exit); 3262 3263 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 3264 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 3265 MODULE_LICENSE("GPL"); 3266