1 /* 2 * Driver for AMBA serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * Copyright (C) 2010 ST-Ericsson SA 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 * This is a generic driver for ARM AMBA-type serial ports. They 25 * have a lot of 16550-like features, but are not register compatible. 26 * Note that although they do have CTS, DCD and DSR inputs, they do 27 * not have an RI input, nor do they have DTR or RTS outputs. If 28 * required, these have to be supplied via some other means (eg, GPIO) 29 * and hooked into this driver. 30 */ 31 32 33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 34 #define SUPPORT_SYSRQ 35 #endif 36 37 #include <linux/module.h> 38 #include <linux/ioport.h> 39 #include <linux/init.h> 40 #include <linux/console.h> 41 #include <linux/sysrq.h> 42 #include <linux/device.h> 43 #include <linux/tty.h> 44 #include <linux/tty_flip.h> 45 #include <linux/serial_core.h> 46 #include <linux/serial.h> 47 #include <linux/amba/bus.h> 48 #include <linux/amba/serial.h> 49 #include <linux/clk.h> 50 #include <linux/slab.h> 51 #include <linux/dmaengine.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/scatterlist.h> 54 #include <linux/delay.h> 55 #include <linux/types.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/pinctrl/consumer.h> 59 #include <linux/sizes.h> 60 #include <linux/io.h> 61 #include <linux/acpi.h> 62 63 #define UART_NR 14 64 65 #define SERIAL_AMBA_MAJOR 204 66 #define SERIAL_AMBA_MINOR 64 67 #define SERIAL_AMBA_NR UART_NR 68 69 #define AMBA_ISR_PASS_LIMIT 256 70 71 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 72 #define UART_DUMMY_DR_RX (1 << 16) 73 74 /* There is by now at least one vendor with differing details, so handle it */ 75 struct vendor_data { 76 unsigned int ifls; 77 unsigned int fr_busy; 78 unsigned int fr_dsr; 79 unsigned int fr_cts; 80 unsigned int fr_ri; 81 unsigned int lcrh_tx; 82 unsigned int lcrh_rx; 83 u16 *reg_lut; 84 bool oversampling; 85 bool dma_threshold; 86 bool cts_event_workaround; 87 bool always_enabled; 88 bool fixed_options; 89 90 unsigned int (*get_fifosize)(struct amba_device *dev); 91 }; 92 93 /* Max address offset of register in use is 0x48 */ 94 #define REG_NR (0x48 >> 2) 95 #define IDX(x) (x >> 2) 96 enum reg_idx { 97 REG_DR = IDX(UART01x_DR), 98 REG_RSR = IDX(UART01x_RSR), 99 REG_ST_DMAWM = IDX(ST_UART011_DMAWM), 100 REG_FR = IDX(UART01x_FR), 101 REG_ST_LCRH_RX = IDX(ST_UART011_LCRH_RX), 102 REG_ILPR = IDX(UART01x_ILPR), 103 REG_IBRD = IDX(UART011_IBRD), 104 REG_FBRD = IDX(UART011_FBRD), 105 REG_LCRH = IDX(UART011_LCRH), 106 REG_CR = IDX(UART011_CR), 107 REG_IFLS = IDX(UART011_IFLS), 108 REG_IMSC = IDX(UART011_IMSC), 109 REG_RIS = IDX(UART011_RIS), 110 REG_MIS = IDX(UART011_MIS), 111 REG_ICR = IDX(UART011_ICR), 112 REG_DMACR = IDX(UART011_DMACR), 113 }; 114 115 static u16 arm_reg[] = { 116 [REG_DR] = UART01x_DR, 117 [REG_RSR] = UART01x_RSR, 118 [REG_ST_DMAWM] = ~0, 119 [REG_FR] = UART01x_FR, 120 [REG_ST_LCRH_RX] = ~0, 121 [REG_ILPR] = UART01x_ILPR, 122 [REG_IBRD] = UART011_IBRD, 123 [REG_FBRD] = UART011_FBRD, 124 [REG_LCRH] = UART011_LCRH, 125 [REG_CR] = UART011_CR, 126 [REG_IFLS] = UART011_IFLS, 127 [REG_IMSC] = UART011_IMSC, 128 [REG_RIS] = UART011_RIS, 129 [REG_MIS] = UART011_MIS, 130 [REG_ICR] = UART011_ICR, 131 [REG_DMACR] = UART011_DMACR, 132 }; 133 134 #ifdef CONFIG_ARM_AMBA 135 static unsigned int get_fifosize_arm(struct amba_device *dev) 136 { 137 return amba_rev(dev) < 3 ? 16 : 32; 138 } 139 140 static struct vendor_data vendor_arm = { 141 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 142 .fr_busy = UART01x_FR_BUSY, 143 .fr_dsr = UART01x_FR_DSR, 144 .fr_cts = UART01x_FR_CTS, 145 .fr_ri = UART011_FR_RI, 146 .lcrh_tx = REG_LCRH, 147 .lcrh_rx = REG_LCRH, 148 .reg_lut = arm_reg, 149 .oversampling = false, 150 .dma_threshold = false, 151 .cts_event_workaround = false, 152 .always_enabled = false, 153 .fixed_options = false, 154 .get_fifosize = get_fifosize_arm, 155 }; 156 #endif 157 158 static struct vendor_data vendor_sbsa = { 159 .fr_busy = UART01x_FR_BUSY, 160 .fr_dsr = UART01x_FR_DSR, 161 .fr_cts = UART01x_FR_CTS, 162 .fr_ri = UART011_FR_RI, 163 .reg_lut = arm_reg, 164 .oversampling = false, 165 .dma_threshold = false, 166 .cts_event_workaround = false, 167 .always_enabled = true, 168 .fixed_options = true, 169 }; 170 171 #ifdef CONFIG_ARM_AMBA 172 static u16 st_reg[] = { 173 [REG_DR] = UART01x_DR, 174 [REG_RSR] = UART01x_RSR, 175 [REG_ST_DMAWM] = ST_UART011_DMAWM, 176 [REG_FR] = UART01x_FR, 177 [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX, 178 [REG_ILPR] = UART01x_ILPR, 179 [REG_IBRD] = UART011_IBRD, 180 [REG_FBRD] = UART011_FBRD, 181 [REG_LCRH] = UART011_LCRH, 182 [REG_CR] = UART011_CR, 183 [REG_IFLS] = UART011_IFLS, 184 [REG_IMSC] = UART011_IMSC, 185 [REG_RIS] = UART011_RIS, 186 [REG_MIS] = UART011_MIS, 187 [REG_ICR] = UART011_ICR, 188 [REG_DMACR] = UART011_DMACR, 189 }; 190 191 static unsigned int get_fifosize_st(struct amba_device *dev) 192 { 193 return 64; 194 } 195 196 static struct vendor_data vendor_st = { 197 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 198 .fr_busy = UART01x_FR_BUSY, 199 .fr_dsr = UART01x_FR_DSR, 200 .fr_cts = UART01x_FR_CTS, 201 .fr_ri = UART011_FR_RI, 202 .lcrh_tx = REG_LCRH, 203 .lcrh_rx = REG_ST_LCRH_RX, 204 .reg_lut = st_reg, 205 .oversampling = true, 206 .dma_threshold = true, 207 .cts_event_workaround = true, 208 .always_enabled = false, 209 .fixed_options = false, 210 .get_fifosize = get_fifosize_st, 211 }; 212 #endif 213 214 #ifdef CONFIG_SOC_ZX296702 215 static u16 zte_reg[] = { 216 [REG_DR] = ZX_UART01x_DR, 217 [REG_RSR] = UART01x_RSR, 218 [REG_ST_DMAWM] = ST_UART011_DMAWM, 219 [REG_FR] = ZX_UART01x_FR, 220 [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX, 221 [REG_ILPR] = UART01x_ILPR, 222 [REG_IBRD] = UART011_IBRD, 223 [REG_FBRD] = UART011_FBRD, 224 [REG_LCRH] = ZX_UART011_LCRH_TX, 225 [REG_CR] = ZX_UART011_CR, 226 [REG_IFLS] = ZX_UART011_IFLS, 227 [REG_IMSC] = ZX_UART011_IMSC, 228 [REG_RIS] = ZX_UART011_RIS, 229 [REG_MIS] = ZX_UART011_MIS, 230 [REG_ICR] = ZX_UART011_ICR, 231 [REG_DMACR] = ZX_UART011_DMACR, 232 }; 233 234 static struct vendor_data vendor_zte = { 235 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 236 .fr_busy = ZX_UART01x_FR_BUSY, 237 .fr_dsr = ZX_UART01x_FR_DSR, 238 .fr_cts = ZX_UART01x_FR_CTS, 239 .fr_ri = ZX_UART011_FR_RI, 240 .lcrh_tx = REG_LCRH, 241 .lcrh_rx = REG_ST_LCRH_RX, 242 .reg_lut = zte_reg, 243 .oversampling = false, 244 .dma_threshold = false, 245 .cts_event_workaround = false, 246 .fixed_options = false, 247 }; 248 #endif 249 250 /* Deals with DMA transactions */ 251 252 struct pl011_sgbuf { 253 struct scatterlist sg; 254 char *buf; 255 }; 256 257 struct pl011_dmarx_data { 258 struct dma_chan *chan; 259 struct completion complete; 260 bool use_buf_b; 261 struct pl011_sgbuf sgbuf_a; 262 struct pl011_sgbuf sgbuf_b; 263 dma_cookie_t cookie; 264 bool running; 265 struct timer_list timer; 266 unsigned int last_residue; 267 unsigned long last_jiffies; 268 bool auto_poll_rate; 269 unsigned int poll_rate; 270 unsigned int poll_timeout; 271 }; 272 273 struct pl011_dmatx_data { 274 struct dma_chan *chan; 275 struct scatterlist sg; 276 char *buf; 277 bool queued; 278 }; 279 280 /* 281 * We wrap our port structure around the generic uart_port. 282 */ 283 struct uart_amba_port { 284 struct uart_port port; 285 struct clk *clk; 286 const struct vendor_data *vendor; 287 u16 *reg_lut; 288 unsigned int dmacr; /* dma control reg */ 289 unsigned int im; /* interrupt mask */ 290 unsigned int old_status; 291 unsigned int fifosize; /* vendor-specific */ 292 unsigned int fr_busy; /* vendor-specific */ 293 unsigned int fr_dsr; /* vendor-specific */ 294 unsigned int fr_cts; /* vendor-specific */ 295 unsigned int fr_ri; /* vendor-specific */ 296 unsigned int lcrh_tx; /* vendor-specific */ 297 unsigned int lcrh_rx; /* vendor-specific */ 298 unsigned int old_cr; /* state during shutdown */ 299 bool autorts; 300 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 301 char type[12]; 302 #ifdef CONFIG_DMA_ENGINE 303 /* DMA stuff */ 304 bool using_tx_dma; 305 bool using_rx_dma; 306 struct pl011_dmarx_data dmarx; 307 struct pl011_dmatx_data dmatx; 308 bool dma_probed; 309 #endif 310 }; 311 312 static bool is_implemented(struct uart_amba_port *uap, unsigned int reg) 313 { 314 return uap->reg_lut[reg] != (u16)~0; 315 } 316 317 static unsigned int pl011_readw(struct uart_amba_port *uap, int index) 318 { 319 WARN_ON(index > REG_NR); 320 return readw_relaxed(uap->port.membase + uap->reg_lut[index]); 321 } 322 323 static void pl011_writew(struct uart_amba_port *uap, int val, int index) 324 { 325 WARN_ON(index > REG_NR); 326 writew_relaxed(val, uap->port.membase + uap->reg_lut[index]); 327 } 328 329 static void pl011_writeb(struct uart_amba_port *uap, u8 val, int index) 330 { 331 WARN_ON(index > REG_NR); 332 writeb_relaxed(val, uap->port.membase + uap->reg_lut[index]); 333 } 334 335 /* 336 * Reads up to 256 characters from the FIFO or until it's empty and 337 * inserts them into the TTY layer. Returns the number of characters 338 * read from the FIFO. 339 */ 340 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 341 { 342 u16 status, ch; 343 unsigned int flag, max_count = 256; 344 int fifotaken = 0; 345 346 while (max_count--) { 347 status = pl011_readw(uap, REG_FR); 348 if (status & UART01x_FR_RXFE) 349 break; 350 351 /* Take chars from the FIFO and update status */ 352 ch = pl011_readw(uap, REG_DR) | 353 UART_DUMMY_DR_RX; 354 flag = TTY_NORMAL; 355 uap->port.icount.rx++; 356 fifotaken++; 357 358 if (unlikely(ch & UART_DR_ERROR)) { 359 if (ch & UART011_DR_BE) { 360 ch &= ~(UART011_DR_FE | UART011_DR_PE); 361 uap->port.icount.brk++; 362 if (uart_handle_break(&uap->port)) 363 continue; 364 } else if (ch & UART011_DR_PE) 365 uap->port.icount.parity++; 366 else if (ch & UART011_DR_FE) 367 uap->port.icount.frame++; 368 if (ch & UART011_DR_OE) 369 uap->port.icount.overrun++; 370 371 ch &= uap->port.read_status_mask; 372 373 if (ch & UART011_DR_BE) 374 flag = TTY_BREAK; 375 else if (ch & UART011_DR_PE) 376 flag = TTY_PARITY; 377 else if (ch & UART011_DR_FE) 378 flag = TTY_FRAME; 379 } 380 381 if (uart_handle_sysrq_char(&uap->port, ch & 255)) 382 continue; 383 384 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 385 } 386 387 return fifotaken; 388 } 389 390 391 /* 392 * All the DMA operation mode stuff goes inside this ifdef. 393 * This assumes that you have a generic DMA device interface, 394 * no custom DMA interfaces are supported. 395 */ 396 #ifdef CONFIG_DMA_ENGINE 397 398 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 399 400 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 401 enum dma_data_direction dir) 402 { 403 dma_addr_t dma_addr; 404 405 sg->buf = dma_alloc_coherent(chan->device->dev, 406 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 407 if (!sg->buf) 408 return -ENOMEM; 409 410 sg_init_table(&sg->sg, 1); 411 sg_set_page(&sg->sg, phys_to_page(dma_addr), 412 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 413 sg_dma_address(&sg->sg) = dma_addr; 414 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 415 416 return 0; 417 } 418 419 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 420 enum dma_data_direction dir) 421 { 422 if (sg->buf) { 423 dma_free_coherent(chan->device->dev, 424 PL011_DMA_BUFFER_SIZE, sg->buf, 425 sg_dma_address(&sg->sg)); 426 } 427 } 428 429 static void pl011_dma_probe(struct uart_amba_port *uap) 430 { 431 /* DMA is the sole user of the platform data right now */ 432 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 433 struct device *dev = uap->port.dev; 434 struct dma_slave_config tx_conf = { 435 .dst_addr = uap->port.mapbase + uap->reg_lut[REG_DR], 436 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 437 .direction = DMA_MEM_TO_DEV, 438 .dst_maxburst = uap->fifosize >> 1, 439 .device_fc = false, 440 }; 441 struct dma_chan *chan; 442 dma_cap_mask_t mask; 443 444 uap->dma_probed = true; 445 chan = dma_request_slave_channel_reason(dev, "tx"); 446 if (IS_ERR(chan)) { 447 if (PTR_ERR(chan) == -EPROBE_DEFER) { 448 uap->dma_probed = false; 449 return; 450 } 451 452 /* We need platform data */ 453 if (!plat || !plat->dma_filter) { 454 dev_info(uap->port.dev, "no DMA platform data\n"); 455 return; 456 } 457 458 /* Try to acquire a generic DMA engine slave TX channel */ 459 dma_cap_zero(mask); 460 dma_cap_set(DMA_SLAVE, mask); 461 462 chan = dma_request_channel(mask, plat->dma_filter, 463 plat->dma_tx_param); 464 if (!chan) { 465 dev_err(uap->port.dev, "no TX DMA channel!\n"); 466 return; 467 } 468 } 469 470 dmaengine_slave_config(chan, &tx_conf); 471 uap->dmatx.chan = chan; 472 473 dev_info(uap->port.dev, "DMA channel TX %s\n", 474 dma_chan_name(uap->dmatx.chan)); 475 476 /* Optionally make use of an RX channel as well */ 477 chan = dma_request_slave_channel(dev, "rx"); 478 479 if (!chan && plat->dma_rx_param) { 480 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 481 482 if (!chan) { 483 dev_err(uap->port.dev, "no RX DMA channel!\n"); 484 return; 485 } 486 } 487 488 if (chan) { 489 struct dma_slave_config rx_conf = { 490 .src_addr = uap->port.mapbase + uap->reg_lut[REG_DR], 491 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 492 .direction = DMA_DEV_TO_MEM, 493 .src_maxburst = uap->fifosize >> 2, 494 .device_fc = false, 495 }; 496 struct dma_slave_caps caps; 497 498 /* 499 * Some DMA controllers provide information on their capabilities. 500 * If the controller does, check for suitable residue processing 501 * otherwise assime all is well. 502 */ 503 if (0 == dma_get_slave_caps(chan, &caps)) { 504 if (caps.residue_granularity == 505 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 506 dma_release_channel(chan); 507 dev_info(uap->port.dev, 508 "RX DMA disabled - no residue processing\n"); 509 return; 510 } 511 } 512 dmaengine_slave_config(chan, &rx_conf); 513 uap->dmarx.chan = chan; 514 515 uap->dmarx.auto_poll_rate = false; 516 if (plat && plat->dma_rx_poll_enable) { 517 /* Set poll rate if specified. */ 518 if (plat->dma_rx_poll_rate) { 519 uap->dmarx.auto_poll_rate = false; 520 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 521 } else { 522 /* 523 * 100 ms defaults to poll rate if not 524 * specified. This will be adjusted with 525 * the baud rate at set_termios. 526 */ 527 uap->dmarx.auto_poll_rate = true; 528 uap->dmarx.poll_rate = 100; 529 } 530 /* 3 secs defaults poll_timeout if not specified. */ 531 if (plat->dma_rx_poll_timeout) 532 uap->dmarx.poll_timeout = 533 plat->dma_rx_poll_timeout; 534 else 535 uap->dmarx.poll_timeout = 3000; 536 } else if (!plat && dev->of_node) { 537 uap->dmarx.auto_poll_rate = of_property_read_bool( 538 dev->of_node, "auto-poll"); 539 if (uap->dmarx.auto_poll_rate) { 540 u32 x; 541 542 if (0 == of_property_read_u32(dev->of_node, 543 "poll-rate-ms", &x)) 544 uap->dmarx.poll_rate = x; 545 else 546 uap->dmarx.poll_rate = 100; 547 if (0 == of_property_read_u32(dev->of_node, 548 "poll-timeout-ms", &x)) 549 uap->dmarx.poll_timeout = x; 550 else 551 uap->dmarx.poll_timeout = 3000; 552 } 553 } 554 dev_info(uap->port.dev, "DMA channel RX %s\n", 555 dma_chan_name(uap->dmarx.chan)); 556 } 557 } 558 559 static void pl011_dma_remove(struct uart_amba_port *uap) 560 { 561 if (uap->dmatx.chan) 562 dma_release_channel(uap->dmatx.chan); 563 if (uap->dmarx.chan) 564 dma_release_channel(uap->dmarx.chan); 565 } 566 567 /* Forward declare these for the refill routine */ 568 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 569 static void pl011_start_tx_pio(struct uart_amba_port *uap); 570 571 /* 572 * The current DMA TX buffer has been sent. 573 * Try to queue up another DMA buffer. 574 */ 575 static void pl011_dma_tx_callback(void *data) 576 { 577 struct uart_amba_port *uap = data; 578 struct pl011_dmatx_data *dmatx = &uap->dmatx; 579 unsigned long flags; 580 u16 dmacr; 581 582 spin_lock_irqsave(&uap->port.lock, flags); 583 if (uap->dmatx.queued) 584 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 585 DMA_TO_DEVICE); 586 587 dmacr = uap->dmacr; 588 uap->dmacr = dmacr & ~UART011_TXDMAE; 589 pl011_writew(uap, uap->dmacr, REG_DMACR); 590 591 /* 592 * If TX DMA was disabled, it means that we've stopped the DMA for 593 * some reason (eg, XOFF received, or we want to send an X-char.) 594 * 595 * Note: we need to be careful here of a potential race between DMA 596 * and the rest of the driver - if the driver disables TX DMA while 597 * a TX buffer completing, we must update the tx queued status to 598 * get further refills (hence we check dmacr). 599 */ 600 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 601 uart_circ_empty(&uap->port.state->xmit)) { 602 uap->dmatx.queued = false; 603 spin_unlock_irqrestore(&uap->port.lock, flags); 604 return; 605 } 606 607 if (pl011_dma_tx_refill(uap) <= 0) 608 /* 609 * We didn't queue a DMA buffer for some reason, but we 610 * have data pending to be sent. Re-enable the TX IRQ. 611 */ 612 pl011_start_tx_pio(uap); 613 614 spin_unlock_irqrestore(&uap->port.lock, flags); 615 } 616 617 /* 618 * Try to refill the TX DMA buffer. 619 * Locking: called with port lock held and IRQs disabled. 620 * Returns: 621 * 1 if we queued up a TX DMA buffer. 622 * 0 if we didn't want to handle this by DMA 623 * <0 on error 624 */ 625 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 626 { 627 struct pl011_dmatx_data *dmatx = &uap->dmatx; 628 struct dma_chan *chan = dmatx->chan; 629 struct dma_device *dma_dev = chan->device; 630 struct dma_async_tx_descriptor *desc; 631 struct circ_buf *xmit = &uap->port.state->xmit; 632 unsigned int count; 633 634 /* 635 * Try to avoid the overhead involved in using DMA if the 636 * transaction fits in the first half of the FIFO, by using 637 * the standard interrupt handling. This ensures that we 638 * issue a uart_write_wakeup() at the appropriate time. 639 */ 640 count = uart_circ_chars_pending(xmit); 641 if (count < (uap->fifosize >> 1)) { 642 uap->dmatx.queued = false; 643 return 0; 644 } 645 646 /* 647 * Bodge: don't send the last character by DMA, as this 648 * will prevent XON from notifying us to restart DMA. 649 */ 650 count -= 1; 651 652 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 653 if (count > PL011_DMA_BUFFER_SIZE) 654 count = PL011_DMA_BUFFER_SIZE; 655 656 if (xmit->tail < xmit->head) 657 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 658 else { 659 size_t first = UART_XMIT_SIZE - xmit->tail; 660 size_t second; 661 662 if (first > count) 663 first = count; 664 second = count - first; 665 666 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 667 if (second) 668 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 669 } 670 671 dmatx->sg.length = count; 672 673 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 674 uap->dmatx.queued = false; 675 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 676 return -EBUSY; 677 } 678 679 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 680 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 681 if (!desc) { 682 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 683 uap->dmatx.queued = false; 684 /* 685 * If DMA cannot be used right now, we complete this 686 * transaction via IRQ and let the TTY layer retry. 687 */ 688 dev_dbg(uap->port.dev, "TX DMA busy\n"); 689 return -EBUSY; 690 } 691 692 /* Some data to go along to the callback */ 693 desc->callback = pl011_dma_tx_callback; 694 desc->callback_param = uap; 695 696 /* All errors should happen at prepare time */ 697 dmaengine_submit(desc); 698 699 /* Fire the DMA transaction */ 700 dma_dev->device_issue_pending(chan); 701 702 uap->dmacr |= UART011_TXDMAE; 703 pl011_writew(uap, uap->dmacr, REG_DMACR); 704 uap->dmatx.queued = true; 705 706 /* 707 * Now we know that DMA will fire, so advance the ring buffer 708 * with the stuff we just dispatched. 709 */ 710 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 711 uap->port.icount.tx += count; 712 713 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 714 uart_write_wakeup(&uap->port); 715 716 return 1; 717 } 718 719 /* 720 * We received a transmit interrupt without a pending X-char but with 721 * pending characters. 722 * Locking: called with port lock held and IRQs disabled. 723 * Returns: 724 * false if we want to use PIO to transmit 725 * true if we queued a DMA buffer 726 */ 727 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 728 { 729 if (!uap->using_tx_dma) 730 return false; 731 732 /* 733 * If we already have a TX buffer queued, but received a 734 * TX interrupt, it will be because we've just sent an X-char. 735 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 736 */ 737 if (uap->dmatx.queued) { 738 uap->dmacr |= UART011_TXDMAE; 739 pl011_writew(uap, uap->dmacr, REG_DMACR); 740 uap->im &= ~UART011_TXIM; 741 pl011_writew(uap, uap->im, REG_IMSC); 742 return true; 743 } 744 745 /* 746 * We don't have a TX buffer queued, so try to queue one. 747 * If we successfully queued a buffer, mask the TX IRQ. 748 */ 749 if (pl011_dma_tx_refill(uap) > 0) { 750 uap->im &= ~UART011_TXIM; 751 pl011_writew(uap, uap->im, REG_IMSC); 752 return true; 753 } 754 return false; 755 } 756 757 /* 758 * Stop the DMA transmit (eg, due to received XOFF). 759 * Locking: called with port lock held and IRQs disabled. 760 */ 761 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 762 { 763 if (uap->dmatx.queued) { 764 uap->dmacr &= ~UART011_TXDMAE; 765 pl011_writew(uap, uap->dmacr, REG_DMACR); 766 } 767 } 768 769 /* 770 * Try to start a DMA transmit, or in the case of an XON/OFF 771 * character queued for send, try to get that character out ASAP. 772 * Locking: called with port lock held and IRQs disabled. 773 * Returns: 774 * false if we want the TX IRQ to be enabled 775 * true if we have a buffer queued 776 */ 777 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 778 { 779 u16 dmacr; 780 781 if (!uap->using_tx_dma) 782 return false; 783 784 if (!uap->port.x_char) { 785 /* no X-char, try to push chars out in DMA mode */ 786 bool ret = true; 787 788 if (!uap->dmatx.queued) { 789 if (pl011_dma_tx_refill(uap) > 0) { 790 uap->im &= ~UART011_TXIM; 791 pl011_writew(uap, uap->im, REG_IMSC); 792 } else 793 ret = false; 794 } else if (!(uap->dmacr & UART011_TXDMAE)) { 795 uap->dmacr |= UART011_TXDMAE; 796 pl011_writew(uap, uap->dmacr, REG_DMACR); 797 } 798 return ret; 799 } 800 801 /* 802 * We have an X-char to send. Disable DMA to prevent it loading 803 * the TX fifo, and then see if we can stuff it into the FIFO. 804 */ 805 dmacr = uap->dmacr; 806 uap->dmacr &= ~UART011_TXDMAE; 807 pl011_writew(uap, uap->dmacr, REG_DMACR); 808 809 if (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) { 810 /* 811 * No space in the FIFO, so enable the transmit interrupt 812 * so we know when there is space. Note that once we've 813 * loaded the character, we should just re-enable DMA. 814 */ 815 return false; 816 } 817 818 pl011_writew(uap, uap->port.x_char, REG_DR); 819 uap->port.icount.tx++; 820 uap->port.x_char = 0; 821 822 /* Success - restore the DMA state */ 823 uap->dmacr = dmacr; 824 pl011_writew(uap, dmacr, REG_DMACR); 825 826 return true; 827 } 828 829 /* 830 * Flush the transmit buffer. 831 * Locking: called with port lock held and IRQs disabled. 832 */ 833 static void pl011_dma_flush_buffer(struct uart_port *port) 834 __releases(&uap->port.lock) 835 __acquires(&uap->port.lock) 836 { 837 struct uart_amba_port *uap = 838 container_of(port, struct uart_amba_port, port); 839 840 if (!uap->using_tx_dma) 841 return; 842 843 /* Avoid deadlock with the DMA engine callback */ 844 spin_unlock(&uap->port.lock); 845 dmaengine_terminate_all(uap->dmatx.chan); 846 spin_lock(&uap->port.lock); 847 if (uap->dmatx.queued) { 848 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 849 DMA_TO_DEVICE); 850 uap->dmatx.queued = false; 851 uap->dmacr &= ~UART011_TXDMAE; 852 pl011_writew(uap, uap->dmacr, REG_DMACR); 853 } 854 } 855 856 static void pl011_dma_rx_callback(void *data); 857 858 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 859 { 860 struct dma_chan *rxchan = uap->dmarx.chan; 861 struct pl011_dmarx_data *dmarx = &uap->dmarx; 862 struct dma_async_tx_descriptor *desc; 863 struct pl011_sgbuf *sgbuf; 864 865 if (!rxchan) 866 return -EIO; 867 868 /* Start the RX DMA job */ 869 sgbuf = uap->dmarx.use_buf_b ? 870 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 871 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 872 DMA_DEV_TO_MEM, 873 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 874 /* 875 * If the DMA engine is busy and cannot prepare a 876 * channel, no big deal, the driver will fall back 877 * to interrupt mode as a result of this error code. 878 */ 879 if (!desc) { 880 uap->dmarx.running = false; 881 dmaengine_terminate_all(rxchan); 882 return -EBUSY; 883 } 884 885 /* Some data to go along to the callback */ 886 desc->callback = pl011_dma_rx_callback; 887 desc->callback_param = uap; 888 dmarx->cookie = dmaengine_submit(desc); 889 dma_async_issue_pending(rxchan); 890 891 uap->dmacr |= UART011_RXDMAE; 892 pl011_writew(uap, uap->dmacr, REG_DMACR); 893 uap->dmarx.running = true; 894 895 uap->im &= ~UART011_RXIM; 896 pl011_writew(uap, uap->im, REG_IMSC); 897 898 return 0; 899 } 900 901 /* 902 * This is called when either the DMA job is complete, or 903 * the FIFO timeout interrupt occurred. This must be called 904 * with the port spinlock uap->port.lock held. 905 */ 906 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 907 u32 pending, bool use_buf_b, 908 bool readfifo) 909 { 910 struct tty_port *port = &uap->port.state->port; 911 struct pl011_sgbuf *sgbuf = use_buf_b ? 912 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 913 int dma_count = 0; 914 u32 fifotaken = 0; /* only used for vdbg() */ 915 916 struct pl011_dmarx_data *dmarx = &uap->dmarx; 917 int dmataken = 0; 918 919 if (uap->dmarx.poll_rate) { 920 /* The data can be taken by polling */ 921 dmataken = sgbuf->sg.length - dmarx->last_residue; 922 /* Recalculate the pending size */ 923 if (pending >= dmataken) 924 pending -= dmataken; 925 } 926 927 /* Pick the remain data from the DMA */ 928 if (pending) { 929 930 /* 931 * First take all chars in the DMA pipe, then look in the FIFO. 932 * Note that tty_insert_flip_buf() tries to take as many chars 933 * as it can. 934 */ 935 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 936 pending); 937 938 uap->port.icount.rx += dma_count; 939 if (dma_count < pending) 940 dev_warn(uap->port.dev, 941 "couldn't insert all characters (TTY is full?)\n"); 942 } 943 944 /* Reset the last_residue for Rx DMA poll */ 945 if (uap->dmarx.poll_rate) 946 dmarx->last_residue = sgbuf->sg.length; 947 948 /* 949 * Only continue with trying to read the FIFO if all DMA chars have 950 * been taken first. 951 */ 952 if (dma_count == pending && readfifo) { 953 /* Clear any error flags */ 954 pl011_writew(uap, 955 UART011_OEIS | UART011_BEIS | UART011_PEIS 956 | UART011_FEIS, REG_ICR); 957 958 /* 959 * If we read all the DMA'd characters, and we had an 960 * incomplete buffer, that could be due to an rx error, or 961 * maybe we just timed out. Read any pending chars and check 962 * the error status. 963 * 964 * Error conditions will only occur in the FIFO, these will 965 * trigger an immediate interrupt and stop the DMA job, so we 966 * will always find the error in the FIFO, never in the DMA 967 * buffer. 968 */ 969 fifotaken = pl011_fifo_to_tty(uap); 970 } 971 972 spin_unlock(&uap->port.lock); 973 dev_vdbg(uap->port.dev, 974 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 975 dma_count, fifotaken); 976 tty_flip_buffer_push(port); 977 spin_lock(&uap->port.lock); 978 } 979 980 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 981 { 982 struct pl011_dmarx_data *dmarx = &uap->dmarx; 983 struct dma_chan *rxchan = dmarx->chan; 984 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 985 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 986 size_t pending; 987 struct dma_tx_state state; 988 enum dma_status dmastat; 989 990 /* 991 * Pause the transfer so we can trust the current counter, 992 * do this before we pause the PL011 block, else we may 993 * overflow the FIFO. 994 */ 995 if (dmaengine_pause(rxchan)) 996 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 997 dmastat = rxchan->device->device_tx_status(rxchan, 998 dmarx->cookie, &state); 999 if (dmastat != DMA_PAUSED) 1000 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 1001 1002 /* Disable RX DMA - incoming data will wait in the FIFO */ 1003 uap->dmacr &= ~UART011_RXDMAE; 1004 pl011_writew(uap, uap->dmacr, REG_DMACR); 1005 uap->dmarx.running = false; 1006 1007 pending = sgbuf->sg.length - state.residue; 1008 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1009 /* Then we terminate the transfer - we now know our residue */ 1010 dmaengine_terminate_all(rxchan); 1011 1012 /* 1013 * This will take the chars we have so far and insert 1014 * into the framework. 1015 */ 1016 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 1017 1018 /* Switch buffer & re-trigger DMA job */ 1019 dmarx->use_buf_b = !dmarx->use_buf_b; 1020 if (pl011_dma_rx_trigger_dma(uap)) { 1021 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1022 "fall back to interrupt mode\n"); 1023 uap->im |= UART011_RXIM; 1024 pl011_writew(uap, uap->im, REG_IMSC); 1025 } 1026 } 1027 1028 static void pl011_dma_rx_callback(void *data) 1029 { 1030 struct uart_amba_port *uap = data; 1031 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1032 struct dma_chan *rxchan = dmarx->chan; 1033 bool lastbuf = dmarx->use_buf_b; 1034 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 1035 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 1036 size_t pending; 1037 struct dma_tx_state state; 1038 int ret; 1039 1040 /* 1041 * This completion interrupt occurs typically when the 1042 * RX buffer is totally stuffed but no timeout has yet 1043 * occurred. When that happens, we just want the RX 1044 * routine to flush out the secondary DMA buffer while 1045 * we immediately trigger the next DMA job. 1046 */ 1047 spin_lock_irq(&uap->port.lock); 1048 /* 1049 * Rx data can be taken by the UART interrupts during 1050 * the DMA irq handler. So we check the residue here. 1051 */ 1052 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1053 pending = sgbuf->sg.length - state.residue; 1054 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1055 /* Then we terminate the transfer - we now know our residue */ 1056 dmaengine_terminate_all(rxchan); 1057 1058 uap->dmarx.running = false; 1059 dmarx->use_buf_b = !lastbuf; 1060 ret = pl011_dma_rx_trigger_dma(uap); 1061 1062 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1063 spin_unlock_irq(&uap->port.lock); 1064 /* 1065 * Do this check after we picked the DMA chars so we don't 1066 * get some IRQ immediately from RX. 1067 */ 1068 if (ret) { 1069 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1070 "fall back to interrupt mode\n"); 1071 uap->im |= UART011_RXIM; 1072 pl011_writew(uap, uap->im, REG_IMSC); 1073 } 1074 } 1075 1076 /* 1077 * Stop accepting received characters, when we're shutting down or 1078 * suspending this port. 1079 * Locking: called with port lock held and IRQs disabled. 1080 */ 1081 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1082 { 1083 /* FIXME. Just disable the DMA enable */ 1084 uap->dmacr &= ~UART011_RXDMAE; 1085 pl011_writew(uap, uap->dmacr, REG_DMACR); 1086 } 1087 1088 /* 1089 * Timer handler for Rx DMA polling. 1090 * Every polling, It checks the residue in the dma buffer and transfer 1091 * data to the tty. Also, last_residue is updated for the next polling. 1092 */ 1093 static void pl011_dma_rx_poll(unsigned long args) 1094 { 1095 struct uart_amba_port *uap = (struct uart_amba_port *)args; 1096 struct tty_port *port = &uap->port.state->port; 1097 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1098 struct dma_chan *rxchan = uap->dmarx.chan; 1099 unsigned long flags = 0; 1100 unsigned int dmataken = 0; 1101 unsigned int size = 0; 1102 struct pl011_sgbuf *sgbuf; 1103 int dma_count; 1104 struct dma_tx_state state; 1105 1106 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1107 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1108 if (likely(state.residue < dmarx->last_residue)) { 1109 dmataken = sgbuf->sg.length - dmarx->last_residue; 1110 size = dmarx->last_residue - state.residue; 1111 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1112 size); 1113 if (dma_count == size) 1114 dmarx->last_residue = state.residue; 1115 dmarx->last_jiffies = jiffies; 1116 } 1117 tty_flip_buffer_push(port); 1118 1119 /* 1120 * If no data is received in poll_timeout, the driver will fall back 1121 * to interrupt mode. We will retrigger DMA at the first interrupt. 1122 */ 1123 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1124 > uap->dmarx.poll_timeout) { 1125 1126 spin_lock_irqsave(&uap->port.lock, flags); 1127 pl011_dma_rx_stop(uap); 1128 uap->im |= UART011_RXIM; 1129 pl011_writew(uap, uap->im, REG_IMSC); 1130 spin_unlock_irqrestore(&uap->port.lock, flags); 1131 1132 uap->dmarx.running = false; 1133 dmaengine_terminate_all(rxchan); 1134 del_timer(&uap->dmarx.timer); 1135 } else { 1136 mod_timer(&uap->dmarx.timer, 1137 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1138 } 1139 } 1140 1141 static void pl011_dma_startup(struct uart_amba_port *uap) 1142 { 1143 int ret; 1144 1145 if (!uap->dma_probed) 1146 pl011_dma_probe(uap); 1147 1148 if (!uap->dmatx.chan) 1149 return; 1150 1151 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1152 if (!uap->dmatx.buf) { 1153 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1154 uap->port.fifosize = uap->fifosize; 1155 return; 1156 } 1157 1158 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1159 1160 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1161 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1162 uap->using_tx_dma = true; 1163 1164 if (!uap->dmarx.chan) 1165 goto skip_rx; 1166 1167 /* Allocate and map DMA RX buffers */ 1168 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1169 DMA_FROM_DEVICE); 1170 if (ret) { 1171 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1172 "RX buffer A", ret); 1173 goto skip_rx; 1174 } 1175 1176 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1177 DMA_FROM_DEVICE); 1178 if (ret) { 1179 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1180 "RX buffer B", ret); 1181 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1182 DMA_FROM_DEVICE); 1183 goto skip_rx; 1184 } 1185 1186 uap->using_rx_dma = true; 1187 1188 skip_rx: 1189 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1190 uap->dmacr |= UART011_DMAONERR; 1191 pl011_writew(uap, uap->dmacr, REG_DMACR); 1192 1193 /* 1194 * ST Micro variants has some specific dma burst threshold 1195 * compensation. Set this to 16 bytes, so burst will only 1196 * be issued above/below 16 bytes. 1197 */ 1198 if (uap->vendor->dma_threshold) 1199 pl011_writew(uap, 1200 ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1201 REG_ST_DMAWM); 1202 1203 if (uap->using_rx_dma) { 1204 if (pl011_dma_rx_trigger_dma(uap)) 1205 dev_dbg(uap->port.dev, "could not trigger initial " 1206 "RX DMA job, fall back to interrupt mode\n"); 1207 if (uap->dmarx.poll_rate) { 1208 init_timer(&(uap->dmarx.timer)); 1209 uap->dmarx.timer.function = pl011_dma_rx_poll; 1210 uap->dmarx.timer.data = (unsigned long)uap; 1211 mod_timer(&uap->dmarx.timer, 1212 jiffies + 1213 msecs_to_jiffies(uap->dmarx.poll_rate)); 1214 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1215 uap->dmarx.last_jiffies = jiffies; 1216 } 1217 } 1218 } 1219 1220 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1221 { 1222 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1223 return; 1224 1225 /* Disable RX and TX DMA */ 1226 while (pl011_readw(uap, REG_FR) & uap->fr_busy) 1227 barrier(); 1228 1229 spin_lock_irq(&uap->port.lock); 1230 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1231 pl011_writew(uap, uap->dmacr, REG_DMACR); 1232 spin_unlock_irq(&uap->port.lock); 1233 1234 if (uap->using_tx_dma) { 1235 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1236 dmaengine_terminate_all(uap->dmatx.chan); 1237 if (uap->dmatx.queued) { 1238 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1239 DMA_TO_DEVICE); 1240 uap->dmatx.queued = false; 1241 } 1242 1243 kfree(uap->dmatx.buf); 1244 uap->using_tx_dma = false; 1245 } 1246 1247 if (uap->using_rx_dma) { 1248 dmaengine_terminate_all(uap->dmarx.chan); 1249 /* Clean up the RX DMA */ 1250 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1251 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1252 if (uap->dmarx.poll_rate) 1253 del_timer_sync(&uap->dmarx.timer); 1254 uap->using_rx_dma = false; 1255 } 1256 } 1257 1258 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1259 { 1260 return uap->using_rx_dma; 1261 } 1262 1263 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1264 { 1265 return uap->using_rx_dma && uap->dmarx.running; 1266 } 1267 1268 #else 1269 /* Blank functions if the DMA engine is not available */ 1270 static inline void pl011_dma_probe(struct uart_amba_port *uap) 1271 { 1272 } 1273 1274 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1275 { 1276 } 1277 1278 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1279 { 1280 } 1281 1282 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1283 { 1284 } 1285 1286 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1287 { 1288 return false; 1289 } 1290 1291 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1292 { 1293 } 1294 1295 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1296 { 1297 return false; 1298 } 1299 1300 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1301 { 1302 } 1303 1304 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1305 { 1306 } 1307 1308 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1309 { 1310 return -EIO; 1311 } 1312 1313 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1314 { 1315 return false; 1316 } 1317 1318 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1319 { 1320 return false; 1321 } 1322 1323 #define pl011_dma_flush_buffer NULL 1324 #endif 1325 1326 static void pl011_stop_tx(struct uart_port *port) 1327 { 1328 struct uart_amba_port *uap = 1329 container_of(port, struct uart_amba_port, port); 1330 1331 uap->im &= ~UART011_TXIM; 1332 pl011_writew(uap, uap->im, REG_IMSC); 1333 pl011_dma_tx_stop(uap); 1334 } 1335 1336 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1337 1338 /* Start TX with programmed I/O only (no DMA) */ 1339 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1340 { 1341 uap->im |= UART011_TXIM; 1342 pl011_writew(uap, uap->im, REG_IMSC); 1343 pl011_tx_chars(uap, false); 1344 } 1345 1346 static void pl011_start_tx(struct uart_port *port) 1347 { 1348 struct uart_amba_port *uap = 1349 container_of(port, struct uart_amba_port, port); 1350 1351 if (!pl011_dma_tx_start(uap)) 1352 pl011_start_tx_pio(uap); 1353 } 1354 1355 static void pl011_stop_rx(struct uart_port *port) 1356 { 1357 struct uart_amba_port *uap = 1358 container_of(port, struct uart_amba_port, port); 1359 1360 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1361 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1362 pl011_writew(uap, uap->im, REG_IMSC); 1363 1364 pl011_dma_rx_stop(uap); 1365 } 1366 1367 static void pl011_enable_ms(struct uart_port *port) 1368 { 1369 struct uart_amba_port *uap = 1370 container_of(port, struct uart_amba_port, port); 1371 1372 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1373 pl011_writew(uap, uap->im, REG_IMSC); 1374 } 1375 1376 static void pl011_rx_chars(struct uart_amba_port *uap) 1377 __releases(&uap->port.lock) 1378 __acquires(&uap->port.lock) 1379 { 1380 pl011_fifo_to_tty(uap); 1381 1382 spin_unlock(&uap->port.lock); 1383 tty_flip_buffer_push(&uap->port.state->port); 1384 /* 1385 * If we were temporarily out of DMA mode for a while, 1386 * attempt to switch back to DMA mode again. 1387 */ 1388 if (pl011_dma_rx_available(uap)) { 1389 if (pl011_dma_rx_trigger_dma(uap)) { 1390 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1391 "fall back to interrupt mode again\n"); 1392 uap->im |= UART011_RXIM; 1393 pl011_writew(uap, uap->im, REG_IMSC); 1394 } else { 1395 #ifdef CONFIG_DMA_ENGINE 1396 /* Start Rx DMA poll */ 1397 if (uap->dmarx.poll_rate) { 1398 uap->dmarx.last_jiffies = jiffies; 1399 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1400 mod_timer(&uap->dmarx.timer, 1401 jiffies + 1402 msecs_to_jiffies(uap->dmarx.poll_rate)); 1403 } 1404 #endif 1405 } 1406 } 1407 spin_lock(&uap->port.lock); 1408 } 1409 1410 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1411 bool from_irq) 1412 { 1413 if (unlikely(!from_irq) && 1414 pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 1415 return false; /* unable to transmit character */ 1416 1417 pl011_writew(uap, c, REG_DR); 1418 uap->port.icount.tx++; 1419 1420 return true; 1421 } 1422 1423 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1424 { 1425 struct circ_buf *xmit = &uap->port.state->xmit; 1426 int count = uap->fifosize >> 1; 1427 1428 if (uap->port.x_char) { 1429 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1430 return; 1431 uap->port.x_char = 0; 1432 --count; 1433 } 1434 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1435 pl011_stop_tx(&uap->port); 1436 return; 1437 } 1438 1439 /* If we are using DMA mode, try to send some characters. */ 1440 if (pl011_dma_tx_irq(uap)) 1441 return; 1442 1443 do { 1444 if (likely(from_irq) && count-- == 0) 1445 break; 1446 1447 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1448 break; 1449 1450 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1451 } while (!uart_circ_empty(xmit)); 1452 1453 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1454 uart_write_wakeup(&uap->port); 1455 1456 if (uart_circ_empty(xmit)) 1457 pl011_stop_tx(&uap->port); 1458 } 1459 1460 static void pl011_modem_status(struct uart_amba_port *uap) 1461 { 1462 unsigned int status, delta; 1463 1464 status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1465 1466 delta = status ^ uap->old_status; 1467 uap->old_status = status; 1468 1469 if (!delta) 1470 return; 1471 1472 if (delta & UART01x_FR_DCD) 1473 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1474 1475 if (delta & uap->fr_dsr) 1476 uap->port.icount.dsr++; 1477 1478 if (delta & uap->fr_cts) 1479 uart_handle_cts_change(&uap->port, status & uap->fr_cts); 1480 1481 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1482 } 1483 1484 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1485 { 1486 unsigned int dummy_read; 1487 1488 if (!uap->vendor->cts_event_workaround) 1489 return; 1490 1491 /* workaround to make sure that all bits are unlocked.. */ 1492 pl011_writew(uap, 0x00, REG_ICR); 1493 1494 /* 1495 * WA: introduce 26ns(1 uart clk) delay before W1C; 1496 * single apb access will incur 2 pclk(133.12Mhz) delay, 1497 * so add 2 dummy reads 1498 */ 1499 dummy_read = pl011_readw(uap, REG_ICR); 1500 dummy_read = pl011_readw(uap, REG_ICR); 1501 } 1502 1503 static irqreturn_t pl011_int(int irq, void *dev_id) 1504 { 1505 struct uart_amba_port *uap = dev_id; 1506 unsigned long flags; 1507 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1508 u16 imsc; 1509 int handled = 0; 1510 1511 spin_lock_irqsave(&uap->port.lock, flags); 1512 imsc = pl011_readw(uap, REG_IMSC); 1513 status = pl011_readw(uap, REG_RIS) & imsc; 1514 if (status) { 1515 do { 1516 check_apply_cts_event_workaround(uap); 1517 pl011_writew(uap, status & ~(UART011_TXIS|UART011_RTIS| 1518 UART011_RXIS), REG_ICR); 1519 1520 if (status & (UART011_RTIS|UART011_RXIS)) { 1521 if (pl011_dma_rx_running(uap)) 1522 pl011_dma_rx_irq(uap); 1523 else 1524 pl011_rx_chars(uap); 1525 } 1526 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1527 UART011_CTSMIS|UART011_RIMIS)) 1528 pl011_modem_status(uap); 1529 if (status & UART011_TXIS) 1530 pl011_tx_chars(uap, true); 1531 1532 if (pass_counter-- == 0) 1533 break; 1534 1535 status = pl011_readw(uap, REG_RIS) & imsc; 1536 } while (status != 0); 1537 handled = 1; 1538 } 1539 1540 spin_unlock_irqrestore(&uap->port.lock, flags); 1541 1542 return IRQ_RETVAL(handled); 1543 } 1544 1545 static unsigned int pl011_tx_empty(struct uart_port *port) 1546 { 1547 struct uart_amba_port *uap = 1548 container_of(port, struct uart_amba_port, port); 1549 unsigned int status = pl011_readw(uap, REG_FR); 1550 return status & (uap->fr_busy|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; 1551 } 1552 1553 static unsigned int pl011_get_mctrl(struct uart_port *port) 1554 { 1555 struct uart_amba_port *uap = 1556 container_of(port, struct uart_amba_port, port); 1557 unsigned int result = 0; 1558 unsigned int status = pl011_readw(uap, REG_FR); 1559 1560 #define TIOCMBIT(uartbit, tiocmbit) \ 1561 if (status & uartbit) \ 1562 result |= tiocmbit 1563 1564 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1565 TIOCMBIT(uap->fr_dsr, TIOCM_DSR); 1566 TIOCMBIT(uap->fr_cts, TIOCM_CTS); 1567 TIOCMBIT(uap->fr_ri, TIOCM_RNG); 1568 #undef TIOCMBIT 1569 return result; 1570 } 1571 1572 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1573 { 1574 struct uart_amba_port *uap = 1575 container_of(port, struct uart_amba_port, port); 1576 unsigned int cr; 1577 1578 cr = pl011_readw(uap, REG_CR); 1579 1580 #define TIOCMBIT(tiocmbit, uartbit) \ 1581 if (mctrl & tiocmbit) \ 1582 cr |= uartbit; \ 1583 else \ 1584 cr &= ~uartbit 1585 1586 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1587 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1588 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1589 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1590 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1591 1592 if (uap->autorts) { 1593 /* We need to disable auto-RTS if we want to turn RTS off */ 1594 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1595 } 1596 #undef TIOCMBIT 1597 1598 pl011_writew(uap, cr, REG_CR); 1599 } 1600 1601 static void pl011_break_ctl(struct uart_port *port, int break_state) 1602 { 1603 struct uart_amba_port *uap = 1604 container_of(port, struct uart_amba_port, port); 1605 unsigned long flags; 1606 unsigned int lcr_h; 1607 1608 spin_lock_irqsave(&uap->port.lock, flags); 1609 lcr_h = pl011_readw(uap, uap->lcrh_tx); 1610 if (break_state == -1) 1611 lcr_h |= UART01x_LCRH_BRK; 1612 else 1613 lcr_h &= ~UART01x_LCRH_BRK; 1614 pl011_writew(uap, lcr_h, uap->lcrh_tx); 1615 spin_unlock_irqrestore(&uap->port.lock, flags); 1616 } 1617 1618 #ifdef CONFIG_CONSOLE_POLL 1619 1620 static void pl011_quiesce_irqs(struct uart_port *port) 1621 { 1622 struct uart_amba_port *uap = 1623 container_of(port, struct uart_amba_port, port); 1624 1625 pl011_writew(uap, pl011_readw(uap, REG_MIS), REG_ICR); 1626 /* 1627 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1628 * we simply mask it. start_tx() will unmask it. 1629 * 1630 * Note we can race with start_tx(), and if the race happens, the 1631 * polling user might get another interrupt just after we clear it. 1632 * But it should be OK and can happen even w/o the race, e.g. 1633 * controller immediately got some new data and raised the IRQ. 1634 * 1635 * And whoever uses polling routines assumes that it manages the device 1636 * (including tx queue), so we're also fine with start_tx()'s caller 1637 * side. 1638 */ 1639 pl011_writew(uap, pl011_readw(uap, REG_IMSC) & ~UART011_TXIM, REG_IMSC); 1640 } 1641 1642 static int pl011_get_poll_char(struct uart_port *port) 1643 { 1644 struct uart_amba_port *uap = 1645 container_of(port, struct uart_amba_port, port); 1646 unsigned int status; 1647 1648 /* 1649 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1650 * debugger. 1651 */ 1652 pl011_quiesce_irqs(port); 1653 1654 status = pl011_readw(uap, REG_FR); 1655 if (status & UART01x_FR_RXFE) 1656 return NO_POLL_CHAR; 1657 1658 return pl011_readw(uap, REG_DR); 1659 } 1660 1661 static void pl011_put_poll_char(struct uart_port *port, 1662 unsigned char ch) 1663 { 1664 struct uart_amba_port *uap = 1665 container_of(port, struct uart_amba_port, port); 1666 1667 while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 1668 barrier(); 1669 1670 pl011_writew(uap, ch, REG_DR); 1671 } 1672 1673 #endif /* CONFIG_CONSOLE_POLL */ 1674 1675 static int pl011_hwinit(struct uart_port *port) 1676 { 1677 struct uart_amba_port *uap = 1678 container_of(port, struct uart_amba_port, port); 1679 int retval; 1680 1681 /* Optionaly enable pins to be muxed in and configured */ 1682 pinctrl_pm_select_default_state(port->dev); 1683 1684 /* 1685 * Try to enable the clock producer. 1686 */ 1687 retval = clk_prepare_enable(uap->clk); 1688 if (retval) 1689 return retval; 1690 1691 uap->port.uartclk = clk_get_rate(uap->clk); 1692 1693 /* Clear pending error and receive interrupts */ 1694 pl011_writew(uap, UART011_OEIS | UART011_BEIS | UART011_PEIS | 1695 UART011_FEIS | UART011_RTIS | UART011_RXIS, REG_ICR); 1696 1697 /* 1698 * Save interrupts enable mask, and enable RX interrupts in case if 1699 * the interrupt is used for NMI entry. 1700 */ 1701 uap->im = pl011_readw(uap, REG_IMSC); 1702 pl011_writew(uap, UART011_RTIM | UART011_RXIM, REG_IMSC); 1703 1704 if (dev_get_platdata(uap->port.dev)) { 1705 struct amba_pl011_data *plat; 1706 1707 plat = dev_get_platdata(uap->port.dev); 1708 if (plat->init) 1709 plat->init(); 1710 } 1711 return 0; 1712 } 1713 1714 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1715 { 1716 pl011_writew(uap, lcr_h, uap->lcrh_rx); 1717 if (is_implemented(uap, REG_ST_LCRH_RX)) { 1718 int i; 1719 /* 1720 * Wait 10 PCLKs before writing LCRH_TX register, 1721 * to get this delay write read only register 10 times 1722 */ 1723 for (i = 0; i < 10; ++i) 1724 pl011_writew(uap, 0xff, REG_MIS); 1725 pl011_writew(uap, lcr_h, uap->lcrh_tx); 1726 } 1727 } 1728 1729 static int pl011_allocate_irq(struct uart_amba_port *uap) 1730 { 1731 pl011_writew(uap, uap->im, REG_IMSC); 1732 1733 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); 1734 } 1735 1736 /* 1737 * Enable interrupts, only timeouts when using DMA 1738 * if initial RX DMA job failed, start in interrupt mode 1739 * as well. 1740 */ 1741 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1742 { 1743 spin_lock_irq(&uap->port.lock); 1744 1745 /* Clear out any spuriously appearing RX interrupts */ 1746 pl011_writew(uap, UART011_RTIS | UART011_RXIS, REG_ICR); 1747 uap->im = UART011_RTIM; 1748 if (!pl011_dma_rx_running(uap)) 1749 uap->im |= UART011_RXIM; 1750 pl011_writew(uap, uap->im, REG_IMSC); 1751 spin_unlock_irq(&uap->port.lock); 1752 } 1753 1754 static int pl011_startup(struct uart_port *port) 1755 { 1756 struct uart_amba_port *uap = 1757 container_of(port, struct uart_amba_port, port); 1758 unsigned int cr; 1759 int retval; 1760 1761 retval = pl011_hwinit(port); 1762 if (retval) 1763 goto clk_dis; 1764 1765 retval = pl011_allocate_irq(uap); 1766 if (retval) 1767 goto clk_dis; 1768 1769 pl011_writew(uap, uap->vendor->ifls, REG_IFLS); 1770 1771 spin_lock_irq(&uap->port.lock); 1772 1773 /* restore RTS and DTR */ 1774 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); 1775 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 1776 pl011_writew(uap, cr, REG_CR); 1777 1778 spin_unlock_irq(&uap->port.lock); 1779 1780 /* 1781 * initialise the old status of the modem signals 1782 */ 1783 uap->old_status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1784 1785 /* Startup DMA */ 1786 pl011_dma_startup(uap); 1787 1788 pl011_enable_interrupts(uap); 1789 1790 return 0; 1791 1792 clk_dis: 1793 clk_disable_unprepare(uap->clk); 1794 return retval; 1795 } 1796 1797 static int sbsa_uart_startup(struct uart_port *port) 1798 { 1799 struct uart_amba_port *uap = 1800 container_of(port, struct uart_amba_port, port); 1801 int retval; 1802 1803 retval = pl011_hwinit(port); 1804 if (retval) 1805 return retval; 1806 1807 retval = pl011_allocate_irq(uap); 1808 if (retval) 1809 return retval; 1810 1811 /* The SBSA UART does not support any modem status lines. */ 1812 uap->old_status = 0; 1813 1814 pl011_enable_interrupts(uap); 1815 1816 return 0; 1817 } 1818 1819 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1820 unsigned int lcrh) 1821 { 1822 unsigned long val; 1823 1824 val = pl011_readw(uap, lcrh); 1825 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1826 pl011_writew(uap, val, lcrh); 1827 } 1828 1829 /* 1830 * disable the port. It should not disable RTS and DTR. 1831 * Also RTS and DTR state should be preserved to restore 1832 * it during startup(). 1833 */ 1834 static void pl011_disable_uart(struct uart_amba_port *uap) 1835 { 1836 unsigned int cr; 1837 1838 uap->autorts = false; 1839 spin_lock_irq(&uap->port.lock); 1840 cr = pl011_readw(uap, REG_CR); 1841 uap->old_cr = cr; 1842 cr &= UART011_CR_RTS | UART011_CR_DTR; 1843 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1844 pl011_writew(uap, cr, REG_CR); 1845 spin_unlock_irq(&uap->port.lock); 1846 1847 /* 1848 * disable break condition and fifos 1849 */ 1850 pl011_shutdown_channel(uap, uap->lcrh_rx); 1851 if (is_implemented(uap, REG_ST_LCRH_RX)) 1852 pl011_shutdown_channel(uap, uap->lcrh_tx); 1853 } 1854 1855 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1856 { 1857 spin_lock_irq(&uap->port.lock); 1858 1859 /* mask all interrupts and clear all pending ones */ 1860 uap->im = 0; 1861 pl011_writew(uap, uap->im, REG_IMSC); 1862 pl011_writew(uap, 0xffff, REG_ICR); 1863 1864 spin_unlock_irq(&uap->port.lock); 1865 } 1866 1867 static void pl011_shutdown(struct uart_port *port) 1868 { 1869 struct uart_amba_port *uap = 1870 container_of(port, struct uart_amba_port, port); 1871 1872 pl011_disable_interrupts(uap); 1873 1874 pl011_dma_shutdown(uap); 1875 1876 free_irq(uap->port.irq, uap); 1877 1878 pl011_disable_uart(uap); 1879 1880 /* 1881 * Shut down the clock producer 1882 */ 1883 clk_disable_unprepare(uap->clk); 1884 /* Optionally let pins go into sleep states */ 1885 pinctrl_pm_select_sleep_state(port->dev); 1886 1887 if (dev_get_platdata(uap->port.dev)) { 1888 struct amba_pl011_data *plat; 1889 1890 plat = dev_get_platdata(uap->port.dev); 1891 if (plat->exit) 1892 plat->exit(); 1893 } 1894 1895 if (uap->port.ops->flush_buffer) 1896 uap->port.ops->flush_buffer(port); 1897 } 1898 1899 static void sbsa_uart_shutdown(struct uart_port *port) 1900 { 1901 struct uart_amba_port *uap = 1902 container_of(port, struct uart_amba_port, port); 1903 1904 pl011_disable_interrupts(uap); 1905 1906 free_irq(uap->port.irq, uap); 1907 1908 if (uap->port.ops->flush_buffer) 1909 uap->port.ops->flush_buffer(port); 1910 } 1911 1912 static void 1913 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 1914 { 1915 port->read_status_mask = UART011_DR_OE | 255; 1916 if (termios->c_iflag & INPCK) 1917 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 1918 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1919 port->read_status_mask |= UART011_DR_BE; 1920 1921 /* 1922 * Characters to ignore 1923 */ 1924 port->ignore_status_mask = 0; 1925 if (termios->c_iflag & IGNPAR) 1926 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 1927 if (termios->c_iflag & IGNBRK) { 1928 port->ignore_status_mask |= UART011_DR_BE; 1929 /* 1930 * If we're ignoring parity and break indicators, 1931 * ignore overruns too (for real raw support). 1932 */ 1933 if (termios->c_iflag & IGNPAR) 1934 port->ignore_status_mask |= UART011_DR_OE; 1935 } 1936 1937 /* 1938 * Ignore all characters if CREAD is not set. 1939 */ 1940 if ((termios->c_cflag & CREAD) == 0) 1941 port->ignore_status_mask |= UART_DUMMY_DR_RX; 1942 } 1943 1944 static void 1945 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 1946 struct ktermios *old) 1947 { 1948 struct uart_amba_port *uap = 1949 container_of(port, struct uart_amba_port, port); 1950 unsigned int lcr_h, old_cr; 1951 unsigned long flags; 1952 unsigned int baud, quot, clkdiv; 1953 1954 if (uap->vendor->oversampling) 1955 clkdiv = 8; 1956 else 1957 clkdiv = 16; 1958 1959 /* 1960 * Ask the core to calculate the divisor for us. 1961 */ 1962 baud = uart_get_baud_rate(port, termios, old, 0, 1963 port->uartclk / clkdiv); 1964 #ifdef CONFIG_DMA_ENGINE 1965 /* 1966 * Adjust RX DMA polling rate with baud rate if not specified. 1967 */ 1968 if (uap->dmarx.auto_poll_rate) 1969 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 1970 #endif 1971 1972 if (baud > port->uartclk/16) 1973 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 1974 else 1975 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 1976 1977 switch (termios->c_cflag & CSIZE) { 1978 case CS5: 1979 lcr_h = UART01x_LCRH_WLEN_5; 1980 break; 1981 case CS6: 1982 lcr_h = UART01x_LCRH_WLEN_6; 1983 break; 1984 case CS7: 1985 lcr_h = UART01x_LCRH_WLEN_7; 1986 break; 1987 default: // CS8 1988 lcr_h = UART01x_LCRH_WLEN_8; 1989 break; 1990 } 1991 if (termios->c_cflag & CSTOPB) 1992 lcr_h |= UART01x_LCRH_STP2; 1993 if (termios->c_cflag & PARENB) { 1994 lcr_h |= UART01x_LCRH_PEN; 1995 if (!(termios->c_cflag & PARODD)) 1996 lcr_h |= UART01x_LCRH_EPS; 1997 } 1998 if (uap->fifosize > 1) 1999 lcr_h |= UART01x_LCRH_FEN; 2000 2001 spin_lock_irqsave(&port->lock, flags); 2002 2003 /* 2004 * Update the per-port timeout. 2005 */ 2006 uart_update_timeout(port, termios->c_cflag, baud); 2007 2008 pl011_setup_status_masks(port, termios); 2009 2010 if (UART_ENABLE_MS(port, termios->c_cflag)) 2011 pl011_enable_ms(port); 2012 2013 /* first, disable everything */ 2014 old_cr = pl011_readw(uap, REG_CR); 2015 pl011_writew(uap, 0, REG_CR); 2016 2017 if (termios->c_cflag & CRTSCTS) { 2018 if (old_cr & UART011_CR_RTS) 2019 old_cr |= UART011_CR_RTSEN; 2020 2021 old_cr |= UART011_CR_CTSEN; 2022 uap->autorts = true; 2023 } else { 2024 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2025 uap->autorts = false; 2026 } 2027 2028 if (uap->vendor->oversampling) { 2029 if (baud > port->uartclk / 16) 2030 old_cr |= ST_UART011_CR_OVSFACT; 2031 else 2032 old_cr &= ~ST_UART011_CR_OVSFACT; 2033 } 2034 2035 /* 2036 * Workaround for the ST Micro oversampling variants to 2037 * increase the bitrate slightly, by lowering the divisor, 2038 * to avoid delayed sampling of start bit at high speeds, 2039 * else we see data corruption. 2040 */ 2041 if (uap->vendor->oversampling) { 2042 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 2043 quot -= 1; 2044 else if ((baud > 3250000) && (quot > 2)) 2045 quot -= 2; 2046 } 2047 /* Set baud rate */ 2048 pl011_writew(uap, quot & 0x3f, REG_FBRD); 2049 pl011_writew(uap, quot >> 6, REG_IBRD); 2050 2051 /* 2052 * ----------v----------v----------v----------v----- 2053 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER 2054 * REG_FBRD & REG_IBRD. 2055 * ----------^----------^----------^----------^----- 2056 */ 2057 pl011_write_lcr_h(uap, lcr_h); 2058 pl011_writew(uap, old_cr, REG_CR); 2059 2060 spin_unlock_irqrestore(&port->lock, flags); 2061 } 2062 2063 static void 2064 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2065 struct ktermios *old) 2066 { 2067 struct uart_amba_port *uap = 2068 container_of(port, struct uart_amba_port, port); 2069 unsigned long flags; 2070 2071 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2072 2073 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2074 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2075 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2076 termios->c_cflag |= CS8 | CLOCAL; 2077 2078 spin_lock_irqsave(&port->lock, flags); 2079 uart_update_timeout(port, CS8, uap->fixed_baud); 2080 pl011_setup_status_masks(port, termios); 2081 spin_unlock_irqrestore(&port->lock, flags); 2082 } 2083 2084 static const char *pl011_type(struct uart_port *port) 2085 { 2086 struct uart_amba_port *uap = 2087 container_of(port, struct uart_amba_port, port); 2088 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2089 } 2090 2091 /* 2092 * Release the memory region(s) being used by 'port' 2093 */ 2094 static void pl011_release_port(struct uart_port *port) 2095 { 2096 release_mem_region(port->mapbase, SZ_4K); 2097 } 2098 2099 /* 2100 * Request the memory region(s) being used by 'port' 2101 */ 2102 static int pl011_request_port(struct uart_port *port) 2103 { 2104 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") 2105 != NULL ? 0 : -EBUSY; 2106 } 2107 2108 /* 2109 * Configure/autoconfigure the port. 2110 */ 2111 static void pl011_config_port(struct uart_port *port, int flags) 2112 { 2113 if (flags & UART_CONFIG_TYPE) { 2114 port->type = PORT_AMBA; 2115 pl011_request_port(port); 2116 } 2117 } 2118 2119 /* 2120 * verify the new serial_struct (for TIOCSSERIAL). 2121 */ 2122 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2123 { 2124 int ret = 0; 2125 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2126 ret = -EINVAL; 2127 if (ser->irq < 0 || ser->irq >= nr_irqs) 2128 ret = -EINVAL; 2129 if (ser->baud_base < 9600) 2130 ret = -EINVAL; 2131 return ret; 2132 } 2133 2134 static struct uart_ops amba_pl011_pops = { 2135 .tx_empty = pl011_tx_empty, 2136 .set_mctrl = pl011_set_mctrl, 2137 .get_mctrl = pl011_get_mctrl, 2138 .stop_tx = pl011_stop_tx, 2139 .start_tx = pl011_start_tx, 2140 .stop_rx = pl011_stop_rx, 2141 .enable_ms = pl011_enable_ms, 2142 .break_ctl = pl011_break_ctl, 2143 .startup = pl011_startup, 2144 .shutdown = pl011_shutdown, 2145 .flush_buffer = pl011_dma_flush_buffer, 2146 .set_termios = pl011_set_termios, 2147 .type = pl011_type, 2148 .release_port = pl011_release_port, 2149 .request_port = pl011_request_port, 2150 .config_port = pl011_config_port, 2151 .verify_port = pl011_verify_port, 2152 #ifdef CONFIG_CONSOLE_POLL 2153 .poll_init = pl011_hwinit, 2154 .poll_get_char = pl011_get_poll_char, 2155 .poll_put_char = pl011_put_poll_char, 2156 #endif 2157 }; 2158 2159 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2160 { 2161 } 2162 2163 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2164 { 2165 return 0; 2166 } 2167 2168 static const struct uart_ops sbsa_uart_pops = { 2169 .tx_empty = pl011_tx_empty, 2170 .set_mctrl = sbsa_uart_set_mctrl, 2171 .get_mctrl = sbsa_uart_get_mctrl, 2172 .stop_tx = pl011_stop_tx, 2173 .start_tx = pl011_start_tx, 2174 .stop_rx = pl011_stop_rx, 2175 .startup = sbsa_uart_startup, 2176 .shutdown = sbsa_uart_shutdown, 2177 .set_termios = sbsa_uart_set_termios, 2178 .type = pl011_type, 2179 .release_port = pl011_release_port, 2180 .request_port = pl011_request_port, 2181 .config_port = pl011_config_port, 2182 .verify_port = pl011_verify_port, 2183 #ifdef CONFIG_CONSOLE_POLL 2184 .poll_init = pl011_hwinit, 2185 .poll_get_char = pl011_get_poll_char, 2186 .poll_put_char = pl011_put_poll_char, 2187 #endif 2188 }; 2189 2190 static struct uart_amba_port *amba_ports[UART_NR]; 2191 2192 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2193 2194 static void pl011_console_putchar(struct uart_port *port, int ch) 2195 { 2196 struct uart_amba_port *uap = 2197 container_of(port, struct uart_amba_port, port); 2198 2199 while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 2200 barrier(); 2201 pl011_writew(uap, ch, REG_DR); 2202 } 2203 2204 static void 2205 pl011_console_write(struct console *co, const char *s, unsigned int count) 2206 { 2207 struct uart_amba_port *uap = amba_ports[co->index]; 2208 unsigned int status, old_cr = 0, new_cr; 2209 unsigned long flags; 2210 int locked = 1; 2211 2212 clk_enable(uap->clk); 2213 2214 local_irq_save(flags); 2215 if (uap->port.sysrq) 2216 locked = 0; 2217 else if (oops_in_progress) 2218 locked = spin_trylock(&uap->port.lock); 2219 else 2220 spin_lock(&uap->port.lock); 2221 2222 /* 2223 * First save the CR then disable the interrupts 2224 */ 2225 if (!uap->vendor->always_enabled) { 2226 old_cr = pl011_readw(uap, REG_CR); 2227 new_cr = old_cr & ~UART011_CR_CTSEN; 2228 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2229 pl011_writew(uap, new_cr, REG_CR); 2230 } 2231 2232 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2233 2234 /* 2235 * Finally, wait for transmitter to become empty 2236 * and restore the TCR 2237 */ 2238 do { 2239 status = pl011_readw(uap, REG_FR); 2240 } while (status & uap->fr_busy); 2241 if (!uap->vendor->always_enabled) 2242 pl011_writew(uap, old_cr, REG_CR); 2243 2244 if (locked) 2245 spin_unlock(&uap->port.lock); 2246 local_irq_restore(flags); 2247 2248 clk_disable(uap->clk); 2249 } 2250 2251 static void __init 2252 pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2253 int *parity, int *bits) 2254 { 2255 if (pl011_readw(uap, REG_CR) & UART01x_CR_UARTEN) { 2256 unsigned int lcr_h, ibrd, fbrd; 2257 2258 lcr_h = pl011_readw(uap, uap->lcrh_tx); 2259 2260 *parity = 'n'; 2261 if (lcr_h & UART01x_LCRH_PEN) { 2262 if (lcr_h & UART01x_LCRH_EPS) 2263 *parity = 'e'; 2264 else 2265 *parity = 'o'; 2266 } 2267 2268 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2269 *bits = 7; 2270 else 2271 *bits = 8; 2272 2273 ibrd = pl011_readw(uap, REG_IBRD); 2274 fbrd = pl011_readw(uap, REG_FBRD); 2275 2276 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2277 2278 if (uap->vendor->oversampling) { 2279 if (pl011_readw(uap, REG_CR) 2280 & ST_UART011_CR_OVSFACT) 2281 *baud *= 2; 2282 } 2283 } 2284 } 2285 2286 static int __init pl011_console_setup(struct console *co, char *options) 2287 { 2288 struct uart_amba_port *uap; 2289 int baud = 38400; 2290 int bits = 8; 2291 int parity = 'n'; 2292 int flow = 'n'; 2293 int ret; 2294 2295 /* 2296 * Check whether an invalid uart number has been specified, and 2297 * if so, search for the first available port that does have 2298 * console support. 2299 */ 2300 if (co->index >= UART_NR) 2301 co->index = 0; 2302 uap = amba_ports[co->index]; 2303 if (!uap) 2304 return -ENODEV; 2305 2306 /* Allow pins to be muxed in and configured */ 2307 pinctrl_pm_select_default_state(uap->port.dev); 2308 2309 ret = clk_prepare(uap->clk); 2310 if (ret) 2311 return ret; 2312 2313 if (dev_get_platdata(uap->port.dev)) { 2314 struct amba_pl011_data *plat; 2315 2316 plat = dev_get_platdata(uap->port.dev); 2317 if (plat->init) 2318 plat->init(); 2319 } 2320 2321 uap->port.uartclk = clk_get_rate(uap->clk); 2322 2323 if (uap->vendor->fixed_options) { 2324 baud = uap->fixed_baud; 2325 } else { 2326 if (options) 2327 uart_parse_options(options, 2328 &baud, &parity, &bits, &flow); 2329 else 2330 pl011_console_get_options(uap, &baud, &parity, &bits); 2331 } 2332 2333 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2334 } 2335 2336 static struct uart_driver amba_reg; 2337 static struct console amba_console = { 2338 .name = "ttyAMA", 2339 .write = pl011_console_write, 2340 .device = uart_console_device, 2341 .setup = pl011_console_setup, 2342 .flags = CON_PRINTBUFFER, 2343 .index = -1, 2344 .data = &amba_reg, 2345 }; 2346 2347 #define AMBA_CONSOLE (&amba_console) 2348 2349 static void pl011_putc(struct uart_port *port, int c) 2350 { 2351 struct uart_amba_port *uap = 2352 container_of(port, struct uart_amba_port, port); 2353 2354 while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) 2355 ; 2356 pl011_writeb(uap, c, REG_DR); 2357 while (pl011_readw(uap, REG_FR) & uap->fr_busy) 2358 ; 2359 } 2360 2361 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2362 { 2363 struct earlycon_device *dev = con->data; 2364 2365 uart_console_write(&dev->port, s, n, pl011_putc); 2366 } 2367 2368 static int __init pl011_early_console_setup(struct earlycon_device *device, 2369 const char *opt) 2370 { 2371 if (!device->port.membase) 2372 return -ENODEV; 2373 2374 device->con->write = pl011_early_write; 2375 return 0; 2376 } 2377 EARLYCON_DECLARE(pl011, pl011_early_console_setup); 2378 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2379 2380 #else 2381 #define AMBA_CONSOLE NULL 2382 #endif 2383 2384 static struct uart_driver amba_reg = { 2385 .owner = THIS_MODULE, 2386 .driver_name = "ttyAMA", 2387 .dev_name = "ttyAMA", 2388 .major = SERIAL_AMBA_MAJOR, 2389 .minor = SERIAL_AMBA_MINOR, 2390 .nr = UART_NR, 2391 .cons = AMBA_CONSOLE, 2392 }; 2393 2394 static int pl011_probe_dt_alias(int index, struct device *dev) 2395 { 2396 struct device_node *np; 2397 static bool seen_dev_with_alias = false; 2398 static bool seen_dev_without_alias = false; 2399 int ret = index; 2400 2401 if (!IS_ENABLED(CONFIG_OF)) 2402 return ret; 2403 2404 np = dev->of_node; 2405 if (!np) 2406 return ret; 2407 2408 ret = of_alias_get_id(np, "serial"); 2409 if (IS_ERR_VALUE(ret)) { 2410 seen_dev_without_alias = true; 2411 ret = index; 2412 } else { 2413 seen_dev_with_alias = true; 2414 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2415 dev_warn(dev, "requested serial port %d not available.\n", ret); 2416 ret = index; 2417 } 2418 } 2419 2420 if (seen_dev_with_alias && seen_dev_without_alias) 2421 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2422 2423 return ret; 2424 } 2425 2426 /* unregisters the driver also if no more ports are left */ 2427 static void pl011_unregister_port(struct uart_amba_port *uap) 2428 { 2429 int i; 2430 bool busy = false; 2431 2432 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2433 if (amba_ports[i] == uap) 2434 amba_ports[i] = NULL; 2435 else if (amba_ports[i]) 2436 busy = true; 2437 } 2438 pl011_dma_remove(uap); 2439 if (!busy) 2440 uart_unregister_driver(&amba_reg); 2441 } 2442 2443 static int pl011_find_free_port(void) 2444 { 2445 int i; 2446 2447 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2448 if (amba_ports[i] == NULL) 2449 return i; 2450 2451 return -EBUSY; 2452 } 2453 2454 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2455 struct resource *mmiobase, int index) 2456 { 2457 void __iomem *base; 2458 2459 base = devm_ioremap_resource(dev, mmiobase); 2460 if (IS_ERR(base)) 2461 return PTR_ERR(base); 2462 2463 index = pl011_probe_dt_alias(index, dev); 2464 2465 uap->old_cr = 0; 2466 uap->port.dev = dev; 2467 uap->port.mapbase = mmiobase->start; 2468 uap->port.membase = base; 2469 uap->port.iotype = UPIO_MEM; 2470 uap->port.fifosize = uap->fifosize; 2471 uap->port.flags = UPF_BOOT_AUTOCONF; 2472 uap->port.line = index; 2473 2474 amba_ports[index] = uap; 2475 2476 return 0; 2477 } 2478 2479 static int pl011_register_port(struct uart_amba_port *uap) 2480 { 2481 int ret; 2482 2483 /* Ensure interrupts from this UART are masked and cleared */ 2484 pl011_writew(uap, 0, REG_IMSC); 2485 pl011_writew(uap, 0xffff, REG_ICR); 2486 2487 if (!amba_reg.state) { 2488 ret = uart_register_driver(&amba_reg); 2489 if (ret < 0) { 2490 dev_err(uap->port.dev, 2491 "Failed to register AMBA-PL011 driver\n"); 2492 return ret; 2493 } 2494 } 2495 2496 ret = uart_add_one_port(&amba_reg, &uap->port); 2497 if (ret) 2498 pl011_unregister_port(uap); 2499 2500 return ret; 2501 } 2502 2503 #ifdef CONFIG_ARM_AMBA 2504 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2505 { 2506 struct uart_amba_port *uap; 2507 struct vendor_data *vendor = id->data; 2508 int portnr, ret; 2509 2510 portnr = pl011_find_free_port(); 2511 if (portnr < 0) 2512 return portnr; 2513 2514 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2515 GFP_KERNEL); 2516 if (!uap) 2517 return -ENOMEM; 2518 2519 uap->clk = devm_clk_get(&dev->dev, NULL); 2520 if (IS_ERR(uap->clk)) 2521 return PTR_ERR(uap->clk); 2522 2523 uap->vendor = vendor; 2524 uap->reg_lut = vendor->reg_lut; 2525 uap->lcrh_rx = vendor->lcrh_rx; 2526 uap->lcrh_tx = vendor->lcrh_tx; 2527 uap->fr_busy = vendor->fr_busy; 2528 uap->fr_dsr = vendor->fr_dsr; 2529 uap->fr_cts = vendor->fr_cts; 2530 uap->fr_ri = vendor->fr_ri; 2531 uap->fifosize = vendor->get_fifosize(dev); 2532 uap->port.irq = dev->irq[0]; 2533 uap->port.ops = &amba_pl011_pops; 2534 2535 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2536 2537 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2538 if (ret) 2539 return ret; 2540 2541 amba_set_drvdata(dev, uap); 2542 2543 return pl011_register_port(uap); 2544 } 2545 2546 static int pl011_remove(struct amba_device *dev) 2547 { 2548 struct uart_amba_port *uap = amba_get_drvdata(dev); 2549 2550 uart_remove_one_port(&amba_reg, &uap->port); 2551 pl011_unregister_port(uap); 2552 return 0; 2553 } 2554 #endif 2555 2556 #ifdef CONFIG_SOC_ZX296702 2557 static int zx_uart_probe(struct platform_device *pdev) 2558 { 2559 struct uart_amba_port *uap; 2560 struct vendor_data *vendor = &vendor_zte; 2561 struct resource *res; 2562 int portnr, ret; 2563 2564 portnr = pl011_find_free_port(); 2565 if (portnr < 0) 2566 return portnr; 2567 2568 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2569 GFP_KERNEL); 2570 if (!uap) { 2571 ret = -ENOMEM; 2572 goto out; 2573 } 2574 2575 uap->clk = devm_clk_get(&pdev->dev, NULL); 2576 if (IS_ERR(uap->clk)) { 2577 ret = PTR_ERR(uap->clk); 2578 goto out; 2579 } 2580 2581 uap->vendor = vendor; 2582 uap->reg_lut = vendor->reg_lut; 2583 uap->lcrh_rx = vendor->lcrh_rx; 2584 uap->lcrh_tx = vendor->lcrh_tx; 2585 uap->fr_busy = vendor->fr_busy; 2586 uap->fr_dsr = vendor->fr_dsr; 2587 uap->fr_cts = vendor->fr_cts; 2588 uap->fr_ri = vendor->fr_ri; 2589 uap->fifosize = 16; 2590 uap->port.irq = platform_get_irq(pdev, 0); 2591 uap->port.ops = &amba_pl011_pops; 2592 2593 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2594 2595 ret = pl011_setup_port(&pdev->dev, uap, res, portnr); 2596 if (ret) 2597 return ret; 2598 2599 platform_set_drvdata(pdev, uap); 2600 2601 return pl011_register_port(uap); 2602 out: 2603 return ret; 2604 } 2605 2606 static int zx_uart_remove(struct platform_device *pdev) 2607 { 2608 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2609 2610 uart_remove_one_port(&amba_reg, &uap->port); 2611 pl011_unregister_port(uap); 2612 return 0; 2613 } 2614 #endif 2615 2616 #ifdef CONFIG_PM_SLEEP 2617 static int pl011_suspend(struct device *dev) 2618 { 2619 struct uart_amba_port *uap = dev_get_drvdata(dev); 2620 2621 if (!uap) 2622 return -EINVAL; 2623 2624 return uart_suspend_port(&amba_reg, &uap->port); 2625 } 2626 2627 static int pl011_resume(struct device *dev) 2628 { 2629 struct uart_amba_port *uap = dev_get_drvdata(dev); 2630 2631 if (!uap) 2632 return -EINVAL; 2633 2634 return uart_resume_port(&amba_reg, &uap->port); 2635 } 2636 #endif 2637 2638 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2639 2640 static int sbsa_uart_probe(struct platform_device *pdev) 2641 { 2642 struct uart_amba_port *uap; 2643 struct resource *r; 2644 int portnr, ret; 2645 int baudrate; 2646 2647 /* 2648 * Check the mandatory baud rate parameter in the DT node early 2649 * so that we can easily exit with the error. 2650 */ 2651 if (pdev->dev.of_node) { 2652 struct device_node *np = pdev->dev.of_node; 2653 2654 ret = of_property_read_u32(np, "current-speed", &baudrate); 2655 if (ret) 2656 return ret; 2657 } else { 2658 baudrate = 115200; 2659 } 2660 2661 portnr = pl011_find_free_port(); 2662 if (portnr < 0) 2663 return portnr; 2664 2665 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2666 GFP_KERNEL); 2667 if (!uap) 2668 return -ENOMEM; 2669 2670 uap->vendor = &vendor_sbsa; 2671 uap->reg_lut = vendor_sbsa.reg_lut; 2672 uap->fr_busy = vendor_sbsa.fr_busy; 2673 uap->fr_dsr = vendor_sbsa.fr_dsr; 2674 uap->fr_cts = vendor_sbsa.fr_cts; 2675 uap->fr_ri = vendor_sbsa.fr_ri; 2676 uap->fifosize = 32; 2677 uap->port.irq = platform_get_irq(pdev, 0); 2678 uap->port.ops = &sbsa_uart_pops; 2679 uap->fixed_baud = baudrate; 2680 2681 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2682 2683 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2684 2685 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2686 if (ret) 2687 return ret; 2688 2689 platform_set_drvdata(pdev, uap); 2690 2691 return pl011_register_port(uap); 2692 } 2693 2694 static int sbsa_uart_remove(struct platform_device *pdev) 2695 { 2696 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2697 2698 uart_remove_one_port(&amba_reg, &uap->port); 2699 pl011_unregister_port(uap); 2700 return 0; 2701 } 2702 2703 static const struct of_device_id sbsa_uart_of_match[] = { 2704 { .compatible = "arm,sbsa-uart", }, 2705 {}, 2706 }; 2707 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2708 2709 static const struct acpi_device_id sbsa_uart_acpi_match[] = { 2710 { "ARMH0011", 0 }, 2711 {}, 2712 }; 2713 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2714 2715 static struct platform_driver arm_sbsa_uart_platform_driver = { 2716 .probe = sbsa_uart_probe, 2717 .remove = sbsa_uart_remove, 2718 .driver = { 2719 .name = "sbsa-uart", 2720 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2721 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2722 }, 2723 }; 2724 2725 #ifdef CONFIG_ARM_AMBA 2726 static struct amba_id pl011_ids[] = { 2727 { 2728 .id = 0x00041011, 2729 .mask = 0x000fffff, 2730 .data = &vendor_arm, 2731 }, 2732 { 2733 .id = 0x00380802, 2734 .mask = 0x00ffffff, 2735 .data = &vendor_st, 2736 }, 2737 { 0, 0 }, 2738 }; 2739 2740 MODULE_DEVICE_TABLE(amba, pl011_ids); 2741 2742 static struct amba_driver pl011_driver = { 2743 .drv = { 2744 .name = "uart-pl011", 2745 .pm = &pl011_dev_pm_ops, 2746 }, 2747 .id_table = pl011_ids, 2748 .probe = pl011_probe, 2749 .remove = pl011_remove, 2750 }; 2751 #endif 2752 2753 #ifdef CONFIG_SOC_ZX296702 2754 static const struct of_device_id zx_uart_dt_ids[] = { 2755 { .compatible = "zte,zx296702-uart", }, 2756 { /* sentinel */ } 2757 }; 2758 MODULE_DEVICE_TABLE(of, zx_uart_dt_ids); 2759 2760 static struct platform_driver zx_uart_driver = { 2761 .driver = { 2762 .name = "zx-uart", 2763 .owner = THIS_MODULE, 2764 .pm = &pl011_dev_pm_ops, 2765 .of_match_table = zx_uart_dt_ids, 2766 }, 2767 .probe = zx_uart_probe, 2768 .remove = zx_uart_remove, 2769 }; 2770 #endif 2771 2772 2773 static int __init pl011_init(void) 2774 { 2775 int ret; 2776 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2777 2778 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2779 pr_warn("could not register SBSA UART platform driver\n"); 2780 2781 #ifdef CONFIG_SOC_ZX296702 2782 ret = platform_driver_register(&zx_uart_driver); 2783 if (ret) 2784 pr_warn("could not register ZX UART platform driver\n"); 2785 #endif 2786 2787 #ifdef CONFIG_ARM_AMBA 2788 ret = amba_driver_register(&pl011_driver); 2789 #endif 2790 return ret; 2791 } 2792 2793 static void __exit pl011_exit(void) 2794 { 2795 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2796 #ifdef CONFIG_SOC_ZX296702 2797 platform_driver_unregister(&zx_uart_driver); 2798 #endif 2799 #ifdef CONFIG_ARM_AMBA 2800 amba_driver_unregister(&pl011_driver); 2801 #endif 2802 } 2803 2804 /* 2805 * While this can be a module, if builtin it's most likely the console 2806 * So let's leave module_exit but move module_init to an earlier place 2807 */ 2808 arch_initcall(pl011_init); 2809 module_exit(pl011_exit); 2810 2811 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 2812 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 2813 MODULE_LICENSE("GPL"); 2814