1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for AMBA serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright 1999 ARM Limited 8 * Copyright (C) 2000 Deep Blue Solutions Ltd. 9 * Copyright (C) 2010 ST-Ericsson SA 10 * 11 * This is a generic driver for ARM AMBA-type serial ports. They 12 * have a lot of 16550-like features, but are not register compatible. 13 * Note that although they do have CTS, DCD and DSR inputs, they do 14 * not have an RI input, nor do they have DTR or RTS outputs. If 15 * required, these have to be supplied via some other means (eg, GPIO) 16 * and hooked into this driver. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/ioport.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/platform_device.h> 24 #include <linux/sysrq.h> 25 #include <linux/device.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/serial_core.h> 29 #include <linux/serial.h> 30 #include <linux/amba/bus.h> 31 #include <linux/amba/serial.h> 32 #include <linux/clk.h> 33 #include <linux/slab.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/scatterlist.h> 37 #include <linux/delay.h> 38 #include <linux/types.h> 39 #include <linux/of.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/sizes.h> 42 #include <linux/io.h> 43 #include <linux/acpi.h> 44 45 #define UART_NR 14 46 47 #define SERIAL_AMBA_MAJOR 204 48 #define SERIAL_AMBA_MINOR 64 49 #define SERIAL_AMBA_NR UART_NR 50 51 #define AMBA_ISR_PASS_LIMIT 256 52 53 #define UART_DR_ERROR (UART011_DR_OE | UART011_DR_BE | UART011_DR_PE | UART011_DR_FE) 54 #define UART_DUMMY_DR_RX BIT(16) 55 56 enum { 57 REG_DR, 58 REG_ST_DMAWM, 59 REG_ST_TIMEOUT, 60 REG_FR, 61 REG_LCRH_RX, 62 REG_LCRH_TX, 63 REG_IBRD, 64 REG_FBRD, 65 REG_CR, 66 REG_IFLS, 67 REG_IMSC, 68 REG_RIS, 69 REG_MIS, 70 REG_ICR, 71 REG_DMACR, 72 REG_ST_XFCR, 73 REG_ST_XON1, 74 REG_ST_XON2, 75 REG_ST_XOFF1, 76 REG_ST_XOFF2, 77 REG_ST_ITCR, 78 REG_ST_ITIP, 79 REG_ST_ABCR, 80 REG_ST_ABIMSC, 81 82 /* The size of the array - must be last */ 83 REG_ARRAY_SIZE, 84 }; 85 86 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 87 [REG_DR] = UART01x_DR, 88 [REG_FR] = UART01x_FR, 89 [REG_LCRH_RX] = UART011_LCRH, 90 [REG_LCRH_TX] = UART011_LCRH, 91 [REG_IBRD] = UART011_IBRD, 92 [REG_FBRD] = UART011_FBRD, 93 [REG_CR] = UART011_CR, 94 [REG_IFLS] = UART011_IFLS, 95 [REG_IMSC] = UART011_IMSC, 96 [REG_RIS] = UART011_RIS, 97 [REG_MIS] = UART011_MIS, 98 [REG_ICR] = UART011_ICR, 99 [REG_DMACR] = UART011_DMACR, 100 }; 101 102 /* There is by now at least one vendor with differing details, so handle it */ 103 struct vendor_data { 104 const u16 *reg_offset; 105 unsigned int ifls; 106 unsigned int fr_busy; 107 unsigned int fr_dsr; 108 unsigned int fr_cts; 109 unsigned int fr_ri; 110 unsigned int inv_fr; 111 bool access_32b; 112 bool oversampling; 113 bool dma_threshold; 114 bool cts_event_workaround; 115 bool always_enabled; 116 bool fixed_options; 117 bool skip_ibrd_fbrd; 118 bool set_uartclk_rate; 119 120 unsigned int (*get_fifosize)(struct amba_device *dev); 121 }; 122 123 static unsigned int get_fifosize_arm(struct amba_device *dev) 124 { 125 return amba_rev(dev) < 3 ? 16 : 32; 126 } 127 128 static struct vendor_data vendor_arm = { 129 .reg_offset = pl011_std_offsets, 130 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, 131 .fr_busy = UART01x_FR_BUSY, 132 .fr_dsr = UART01x_FR_DSR, 133 .fr_cts = UART01x_FR_CTS, 134 .fr_ri = UART011_FR_RI, 135 .oversampling = false, 136 .dma_threshold = false, 137 .cts_event_workaround = false, 138 .always_enabled = false, 139 .fixed_options = false, 140 .get_fifosize = get_fifosize_arm, 141 }; 142 143 static const struct vendor_data vendor_sbsa = { 144 .reg_offset = pl011_std_offsets, 145 .fr_busy = UART01x_FR_BUSY, 146 .fr_dsr = UART01x_FR_DSR, 147 .fr_cts = UART01x_FR_CTS, 148 .fr_ri = UART011_FR_RI, 149 .access_32b = true, 150 .oversampling = false, 151 .dma_threshold = false, 152 .cts_event_workaround = false, 153 .always_enabled = true, 154 .fixed_options = true, 155 }; 156 157 #ifdef CONFIG_ACPI_SPCR_TABLE 158 static const struct vendor_data vendor_qdt_qdf2400_e44 = { 159 .reg_offset = pl011_std_offsets, 160 .fr_busy = UART011_FR_TXFE, 161 .fr_dsr = UART01x_FR_DSR, 162 .fr_cts = UART01x_FR_CTS, 163 .fr_ri = UART011_FR_RI, 164 .inv_fr = UART011_FR_TXFE, 165 .access_32b = true, 166 .oversampling = false, 167 .dma_threshold = false, 168 .cts_event_workaround = false, 169 .always_enabled = true, 170 .fixed_options = true, 171 }; 172 #endif 173 174 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 175 [REG_DR] = UART01x_DR, 176 [REG_ST_DMAWM] = ST_UART011_DMAWM, 177 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 178 [REG_FR] = UART01x_FR, 179 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 180 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 181 [REG_IBRD] = UART011_IBRD, 182 [REG_FBRD] = UART011_FBRD, 183 [REG_CR] = UART011_CR, 184 [REG_IFLS] = UART011_IFLS, 185 [REG_IMSC] = UART011_IMSC, 186 [REG_RIS] = UART011_RIS, 187 [REG_MIS] = UART011_MIS, 188 [REG_ICR] = UART011_ICR, 189 [REG_DMACR] = UART011_DMACR, 190 [REG_ST_XFCR] = ST_UART011_XFCR, 191 [REG_ST_XON1] = ST_UART011_XON1, 192 [REG_ST_XON2] = ST_UART011_XON2, 193 [REG_ST_XOFF1] = ST_UART011_XOFF1, 194 [REG_ST_XOFF2] = ST_UART011_XOFF2, 195 [REG_ST_ITCR] = ST_UART011_ITCR, 196 [REG_ST_ITIP] = ST_UART011_ITIP, 197 [REG_ST_ABCR] = ST_UART011_ABCR, 198 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 199 }; 200 201 static unsigned int get_fifosize_st(struct amba_device *dev) 202 { 203 return 64; 204 } 205 206 static struct vendor_data vendor_st = { 207 .reg_offset = pl011_st_offsets, 208 .ifls = UART011_IFLS_RX_HALF | UART011_IFLS_TX_HALF, 209 .fr_busy = UART01x_FR_BUSY, 210 .fr_dsr = UART01x_FR_DSR, 211 .fr_cts = UART01x_FR_CTS, 212 .fr_ri = UART011_FR_RI, 213 .oversampling = true, 214 .dma_threshold = true, 215 .cts_event_workaround = true, 216 .always_enabled = false, 217 .fixed_options = false, 218 .get_fifosize = get_fifosize_st, 219 }; 220 221 static unsigned int get_fifosize_nvidia(struct amba_device *dev) 222 { 223 return 32; 224 } 225 226 static struct vendor_data vendor_nvidia = { 227 .reg_offset = pl011_std_offsets, 228 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, 229 .fr_busy = UART01x_FR_BUSY, 230 .fr_dsr = UART01x_FR_DSR, 231 .fr_cts = UART01x_FR_CTS, 232 .fr_ri = UART011_FR_RI, 233 .oversampling = false, 234 .dma_threshold = false, 235 .cts_event_workaround = false, 236 .always_enabled = false, 237 .fixed_options = false, 238 .skip_ibrd_fbrd = true, 239 .set_uartclk_rate = true, 240 .get_fifosize = get_fifosize_nvidia, 241 }; 242 243 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { 244 [REG_DR] = ZX_UART011_DR, 245 [REG_FR] = ZX_UART011_FR, 246 [REG_LCRH_RX] = ZX_UART011_LCRH, 247 [REG_LCRH_TX] = ZX_UART011_LCRH, 248 [REG_IBRD] = ZX_UART011_IBRD, 249 [REG_FBRD] = ZX_UART011_FBRD, 250 [REG_CR] = ZX_UART011_CR, 251 [REG_IFLS] = ZX_UART011_IFLS, 252 [REG_IMSC] = ZX_UART011_IMSC, 253 [REG_RIS] = ZX_UART011_RIS, 254 [REG_MIS] = ZX_UART011_MIS, 255 [REG_ICR] = ZX_UART011_ICR, 256 [REG_DMACR] = ZX_UART011_DMACR, 257 }; 258 259 static unsigned int get_fifosize_zte(struct amba_device *dev) 260 { 261 return 16; 262 } 263 264 static struct vendor_data vendor_zte = { 265 .reg_offset = pl011_zte_offsets, 266 .access_32b = true, 267 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, 268 .fr_busy = ZX_UART01x_FR_BUSY, 269 .fr_dsr = ZX_UART01x_FR_DSR, 270 .fr_cts = ZX_UART01x_FR_CTS, 271 .fr_ri = ZX_UART011_FR_RI, 272 .get_fifosize = get_fifosize_zte, 273 }; 274 275 /* Deals with DMA transactions */ 276 277 struct pl011_dmabuf { 278 dma_addr_t dma; 279 size_t len; 280 char *buf; 281 }; 282 283 struct pl011_dmarx_data { 284 struct dma_chan *chan; 285 struct completion complete; 286 bool use_buf_b; 287 struct pl011_dmabuf dbuf_a; 288 struct pl011_dmabuf dbuf_b; 289 dma_cookie_t cookie; 290 bool running; 291 struct timer_list timer; 292 unsigned int last_residue; 293 unsigned long last_jiffies; 294 bool auto_poll_rate; 295 unsigned int poll_rate; 296 unsigned int poll_timeout; 297 }; 298 299 struct pl011_dmatx_data { 300 struct dma_chan *chan; 301 dma_addr_t dma; 302 size_t len; 303 char *buf; 304 bool queued; 305 }; 306 307 enum pl011_rs485_tx_state { 308 OFF, 309 WAIT_AFTER_RTS, 310 SEND, 311 WAIT_AFTER_SEND, 312 WAIT_AFTER_SEND_DELAY, 313 }; 314 315 /* 316 * We wrap our port structure around the generic uart_port. 317 */ 318 struct uart_amba_port { 319 struct uart_port port; 320 const u16 *reg_offset; 321 struct clk *clk; 322 const struct vendor_data *vendor; 323 unsigned int im; /* interrupt mask */ 324 unsigned int old_status; 325 unsigned int fifosize; /* vendor-specific */ 326 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 327 char type[12]; 328 ktime_t rs485_tx_drain_interval; /* nano */ 329 enum pl011_rs485_tx_state rs485_tx_state; 330 struct hrtimer trigger_start_tx; 331 struct hrtimer trigger_stop_tx; 332 bool console_line_ended; 333 #ifdef CONFIG_DMA_ENGINE 334 /* DMA stuff */ 335 unsigned int dmacr; /* dma control reg */ 336 bool using_tx_dma; 337 bool using_rx_dma; 338 struct pl011_dmarx_data dmarx; 339 struct pl011_dmatx_data dmatx; 340 bool dma_probed; 341 #endif 342 }; 343 344 static unsigned int pl011_tx_empty(struct uart_port *port); 345 346 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 347 unsigned int reg) 348 { 349 return uap->reg_offset[reg]; 350 } 351 352 static unsigned int pl011_read(const struct uart_amba_port *uap, 353 unsigned int reg) 354 { 355 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 356 357 return (uap->port.iotype == UPIO_MEM32) ? 358 readl_relaxed(addr) : readw_relaxed(addr); 359 } 360 361 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 362 unsigned int reg) 363 { 364 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 365 366 if (uap->port.iotype == UPIO_MEM32) 367 writel_relaxed(val, addr); 368 else 369 writew_relaxed(val, addr); 370 } 371 372 /* 373 * Reads up to 256 characters from the FIFO or until it's empty and 374 * inserts them into the TTY layer. Returns the number of characters 375 * read from the FIFO. 376 */ 377 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 378 { 379 unsigned int ch, fifotaken; 380 int sysrq; 381 u16 status; 382 u8 flag; 383 384 for (fifotaken = 0; fifotaken != 256; fifotaken++) { 385 status = pl011_read(uap, REG_FR); 386 if (status & UART01x_FR_RXFE) 387 break; 388 389 /* Take chars from the FIFO and update status */ 390 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 391 flag = TTY_NORMAL; 392 uap->port.icount.rx++; 393 394 if (unlikely(ch & UART_DR_ERROR)) { 395 if (ch & UART011_DR_BE) { 396 ch &= ~(UART011_DR_FE | UART011_DR_PE); 397 uap->port.icount.brk++; 398 if (uart_handle_break(&uap->port)) 399 continue; 400 } else if (ch & UART011_DR_PE) { 401 uap->port.icount.parity++; 402 } else if (ch & UART011_DR_FE) { 403 uap->port.icount.frame++; 404 } 405 if (ch & UART011_DR_OE) 406 uap->port.icount.overrun++; 407 408 ch &= uap->port.read_status_mask; 409 410 if (ch & UART011_DR_BE) 411 flag = TTY_BREAK; 412 else if (ch & UART011_DR_PE) 413 flag = TTY_PARITY; 414 else if (ch & UART011_DR_FE) 415 flag = TTY_FRAME; 416 } 417 418 sysrq = uart_prepare_sysrq_char(&uap->port, ch & 255); 419 if (!sysrq) 420 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 421 } 422 423 return fifotaken; 424 } 425 426 /* 427 * All the DMA operation mode stuff goes inside this ifdef. 428 * This assumes that you have a generic DMA device interface, 429 * no custom DMA interfaces are supported. 430 */ 431 #ifdef CONFIG_DMA_ENGINE 432 433 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 434 435 static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db, 436 enum dma_data_direction dir) 437 { 438 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE, 439 &db->dma, GFP_KERNEL); 440 if (!db->buf) 441 return -ENOMEM; 442 db->len = PL011_DMA_BUFFER_SIZE; 443 444 return 0; 445 } 446 447 static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db, 448 enum dma_data_direction dir) 449 { 450 if (db->buf) { 451 dma_free_coherent(chan->device->dev, 452 PL011_DMA_BUFFER_SIZE, db->buf, db->dma); 453 } 454 } 455 456 static void pl011_dma_probe(struct uart_amba_port *uap) 457 { 458 /* DMA is the sole user of the platform data right now */ 459 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 460 struct device *dev = uap->port.dev; 461 struct dma_slave_config tx_conf = { 462 .dst_addr = uap->port.mapbase + 463 pl011_reg_to_offset(uap, REG_DR), 464 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 465 .direction = DMA_MEM_TO_DEV, 466 .dst_maxburst = uap->fifosize >> 1, 467 .device_fc = false, 468 }; 469 struct dma_chan *chan; 470 dma_cap_mask_t mask; 471 472 uap->dma_probed = true; 473 chan = dma_request_chan(dev, "tx"); 474 if (IS_ERR(chan)) { 475 if (PTR_ERR(chan) == -EPROBE_DEFER) { 476 uap->dma_probed = false; 477 return; 478 } 479 480 /* We need platform data */ 481 if (!plat || !plat->dma_filter) { 482 dev_dbg(uap->port.dev, "no DMA platform data\n"); 483 return; 484 } 485 486 /* Try to acquire a generic DMA engine slave TX channel */ 487 dma_cap_zero(mask); 488 dma_cap_set(DMA_SLAVE, mask); 489 490 chan = dma_request_channel(mask, plat->dma_filter, 491 plat->dma_tx_param); 492 if (!chan) { 493 dev_err(uap->port.dev, "no TX DMA channel!\n"); 494 return; 495 } 496 } 497 498 dmaengine_slave_config(chan, &tx_conf); 499 uap->dmatx.chan = chan; 500 501 dev_info(uap->port.dev, "DMA channel TX %s\n", 502 dma_chan_name(uap->dmatx.chan)); 503 504 /* Optionally make use of an RX channel as well */ 505 chan = dma_request_chan(dev, "rx"); 506 507 if (IS_ERR(chan) && plat && plat->dma_rx_param) { 508 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 509 510 if (!chan) { 511 dev_err(uap->port.dev, "no RX DMA channel!\n"); 512 return; 513 } 514 } 515 516 if (!IS_ERR(chan)) { 517 struct dma_slave_config rx_conf = { 518 .src_addr = uap->port.mapbase + 519 pl011_reg_to_offset(uap, REG_DR), 520 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 521 .direction = DMA_DEV_TO_MEM, 522 .src_maxburst = uap->fifosize >> 2, 523 .device_fc = false, 524 }; 525 struct dma_slave_caps caps; 526 527 /* 528 * Some DMA controllers provide information on their capabilities. 529 * If the controller does, check for suitable residue processing 530 * otherwise assime all is well. 531 */ 532 if (dma_get_slave_caps(chan, &caps) == 0) { 533 if (caps.residue_granularity == 534 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 535 dma_release_channel(chan); 536 dev_info(uap->port.dev, 537 "RX DMA disabled - no residue processing\n"); 538 return; 539 } 540 } 541 dmaengine_slave_config(chan, &rx_conf); 542 uap->dmarx.chan = chan; 543 544 uap->dmarx.auto_poll_rate = false; 545 if (plat && plat->dma_rx_poll_enable) { 546 /* Set poll rate if specified. */ 547 if (plat->dma_rx_poll_rate) { 548 uap->dmarx.auto_poll_rate = false; 549 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 550 } else { 551 /* 552 * 100 ms defaults to poll rate if not 553 * specified. This will be adjusted with 554 * the baud rate at set_termios. 555 */ 556 uap->dmarx.auto_poll_rate = true; 557 uap->dmarx.poll_rate = 100; 558 } 559 /* 3 secs defaults poll_timeout if not specified. */ 560 if (plat->dma_rx_poll_timeout) 561 uap->dmarx.poll_timeout = 562 plat->dma_rx_poll_timeout; 563 else 564 uap->dmarx.poll_timeout = 3000; 565 } else if (!plat && dev->of_node) { 566 uap->dmarx.auto_poll_rate = 567 of_property_read_bool(dev->of_node, "auto-poll"); 568 if (uap->dmarx.auto_poll_rate) { 569 u32 x; 570 571 if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0) 572 uap->dmarx.poll_rate = x; 573 else 574 uap->dmarx.poll_rate = 100; 575 if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0) 576 uap->dmarx.poll_timeout = x; 577 else 578 uap->dmarx.poll_timeout = 3000; 579 } 580 } 581 dev_info(uap->port.dev, "DMA channel RX %s\n", 582 dma_chan_name(uap->dmarx.chan)); 583 } 584 } 585 586 static void pl011_dma_remove(struct uart_amba_port *uap) 587 { 588 if (uap->dmatx.chan) 589 dma_release_channel(uap->dmatx.chan); 590 if (uap->dmarx.chan) 591 dma_release_channel(uap->dmarx.chan); 592 } 593 594 /* Forward declare these for the refill routine */ 595 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 596 static void pl011_start_tx_pio(struct uart_amba_port *uap); 597 598 /* 599 * The current DMA TX buffer has been sent. 600 * Try to queue up another DMA buffer. 601 */ 602 static void pl011_dma_tx_callback(void *data) 603 { 604 struct uart_amba_port *uap = data; 605 struct tty_port *tport = &uap->port.state->port; 606 struct pl011_dmatx_data *dmatx = &uap->dmatx; 607 unsigned long flags; 608 u16 dmacr; 609 610 uart_port_lock_irqsave(&uap->port, &flags); 611 if (uap->dmatx.queued) 612 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma, 613 dmatx->len, DMA_TO_DEVICE); 614 615 dmacr = uap->dmacr; 616 uap->dmacr = dmacr & ~UART011_TXDMAE; 617 pl011_write(uap->dmacr, uap, REG_DMACR); 618 619 /* 620 * If TX DMA was disabled, it means that we've stopped the DMA for 621 * some reason (eg, XOFF received, or we want to send an X-char.) 622 * 623 * Note: we need to be careful here of a potential race between DMA 624 * and the rest of the driver - if the driver disables TX DMA while 625 * a TX buffer completing, we must update the tx queued status to 626 * get further refills (hence we check dmacr). 627 */ 628 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 629 kfifo_is_empty(&tport->xmit_fifo)) { 630 uap->dmatx.queued = false; 631 uart_port_unlock_irqrestore(&uap->port, flags); 632 return; 633 } 634 635 if (pl011_dma_tx_refill(uap) <= 0) 636 /* 637 * We didn't queue a DMA buffer for some reason, but we 638 * have data pending to be sent. Re-enable the TX IRQ. 639 */ 640 pl011_start_tx_pio(uap); 641 642 uart_port_unlock_irqrestore(&uap->port, flags); 643 } 644 645 /* 646 * Try to refill the TX DMA buffer. 647 * Locking: called with port lock held and IRQs disabled. 648 * Returns: 649 * 1 if we queued up a TX DMA buffer. 650 * 0 if we didn't want to handle this by DMA 651 * <0 on error 652 */ 653 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 654 { 655 struct pl011_dmatx_data *dmatx = &uap->dmatx; 656 struct dma_chan *chan = dmatx->chan; 657 struct dma_device *dma_dev = chan->device; 658 struct dma_async_tx_descriptor *desc; 659 struct tty_port *tport = &uap->port.state->port; 660 unsigned int count; 661 662 /* 663 * Try to avoid the overhead involved in using DMA if the 664 * transaction fits in the first half of the FIFO, by using 665 * the standard interrupt handling. This ensures that we 666 * issue a uart_write_wakeup() at the appropriate time. 667 */ 668 count = kfifo_len(&tport->xmit_fifo); 669 if (count < (uap->fifosize >> 1)) { 670 uap->dmatx.queued = false; 671 return 0; 672 } 673 674 /* 675 * Bodge: don't send the last character by DMA, as this 676 * will prevent XON from notifying us to restart DMA. 677 */ 678 count -= 1; 679 680 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 681 if (count > PL011_DMA_BUFFER_SIZE) 682 count = PL011_DMA_BUFFER_SIZE; 683 684 count = kfifo_out_peek(&tport->xmit_fifo, dmatx->buf, count); 685 686 /* 687 * Align the TX buffer length to the DMA controller's copy_align 688 * requirements. Some DMA controllers (e.g., Tegra GPC DMA) require 689 * word-aligned transfers. Unaligned bytes will be sent via PIO. 690 */ 691 if (chan->device->copy_align) 692 count = ALIGN_DOWN(count, 1 << chan->device->copy_align); 693 694 dmatx->len = count; 695 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, 696 DMA_TO_DEVICE); 697 if (dma_mapping_error(dma_dev->dev, dmatx->dma)) { 698 uap->dmatx.queued = false; 699 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 700 return -EBUSY; 701 } 702 703 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV, 704 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 705 if (!desc) { 706 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE); 707 uap->dmatx.queued = false; 708 /* 709 * If DMA cannot be used right now, we complete this 710 * transaction via IRQ and let the TTY layer retry. 711 */ 712 dev_dbg(uap->port.dev, "TX DMA busy\n"); 713 return -EBUSY; 714 } 715 716 /* Some data to go along to the callback */ 717 desc->callback = pl011_dma_tx_callback; 718 desc->callback_param = uap; 719 720 /* All errors should happen at prepare time */ 721 dmaengine_submit(desc); 722 723 /* Fire the DMA transaction */ 724 dma_dev->device_issue_pending(chan); 725 726 uap->dmacr |= UART011_TXDMAE; 727 pl011_write(uap->dmacr, uap, REG_DMACR); 728 uap->dmatx.queued = true; 729 730 /* 731 * Now we know that DMA will fire, so advance the ring buffer 732 * with the stuff we just dispatched. 733 */ 734 uart_xmit_advance(&uap->port, count); 735 736 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 737 uart_write_wakeup(&uap->port); 738 739 return 1; 740 } 741 742 /* 743 * We received a transmit interrupt without a pending X-char but with 744 * pending characters. 745 * Locking: called with port lock held and IRQs disabled. 746 * Returns: 747 * false if we want to use PIO to transmit 748 * true if we queued a DMA buffer 749 */ 750 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 751 { 752 if (!uap->using_tx_dma) 753 return false; 754 755 /* 756 * If we already have a TX buffer queued, but received a 757 * TX interrupt, it will be because we've just sent an X-char. 758 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 759 */ 760 if (uap->dmatx.queued) { 761 uap->dmacr |= UART011_TXDMAE; 762 pl011_write(uap->dmacr, uap, REG_DMACR); 763 uap->im &= ~UART011_TXIM; 764 pl011_write(uap->im, uap, REG_IMSC); 765 return true; 766 } 767 768 /* 769 * We don't have a TX buffer queued, so try to queue one. 770 * If we successfully queued a buffer, mask the TX IRQ. 771 */ 772 if (pl011_dma_tx_refill(uap) > 0) { 773 uap->im &= ~UART011_TXIM; 774 pl011_write(uap->im, uap, REG_IMSC); 775 return true; 776 } 777 return false; 778 } 779 780 /* 781 * Stop the DMA transmit (eg, due to received XOFF). 782 * Locking: called with port lock held and IRQs disabled. 783 */ 784 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 785 { 786 if (uap->dmatx.queued) { 787 uap->dmacr &= ~UART011_TXDMAE; 788 pl011_write(uap->dmacr, uap, REG_DMACR); 789 } 790 } 791 792 /* 793 * Try to start a DMA transmit, or in the case of an XON/OFF 794 * character queued for send, try to get that character out ASAP. 795 * Locking: called with port lock held and IRQs disabled. 796 * Returns: 797 * false if we want the TX IRQ to be enabled 798 * true if we have a buffer queued 799 */ 800 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 801 { 802 u16 dmacr; 803 804 if (!uap->using_tx_dma) 805 return false; 806 807 if (!uap->port.x_char) { 808 /* no X-char, try to push chars out in DMA mode */ 809 bool ret = true; 810 811 if (!uap->dmatx.queued) { 812 if (pl011_dma_tx_refill(uap) > 0) { 813 uap->im &= ~UART011_TXIM; 814 pl011_write(uap->im, uap, REG_IMSC); 815 } else { 816 ret = false; 817 } 818 } else if (!(uap->dmacr & UART011_TXDMAE)) { 819 uap->dmacr |= UART011_TXDMAE; 820 pl011_write(uap->dmacr, uap, REG_DMACR); 821 } 822 return ret; 823 } 824 825 /* 826 * We have an X-char to send. Disable DMA to prevent it loading 827 * the TX fifo, and then see if we can stuff it into the FIFO. 828 */ 829 dmacr = uap->dmacr; 830 uap->dmacr &= ~UART011_TXDMAE; 831 pl011_write(uap->dmacr, uap, REG_DMACR); 832 833 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 834 /* 835 * No space in the FIFO, so enable the transmit interrupt 836 * so we know when there is space. Note that once we've 837 * loaded the character, we should just re-enable DMA. 838 */ 839 return false; 840 } 841 842 pl011_write(uap->port.x_char, uap, REG_DR); 843 uap->port.icount.tx++; 844 uap->port.x_char = 0; 845 846 /* Success - restore the DMA state */ 847 uap->dmacr = dmacr; 848 pl011_write(dmacr, uap, REG_DMACR); 849 850 return true; 851 } 852 853 /* 854 * Flush the transmit buffer. 855 * Locking: called with port lock held and IRQs disabled. 856 */ 857 static void pl011_dma_flush_buffer(struct uart_port *port) 858 __releases(&uap->port.lock) 859 __acquires(&uap->port.lock) 860 { 861 struct uart_amba_port *uap = 862 container_of(port, struct uart_amba_port, port); 863 864 if (!uap->using_tx_dma) 865 return; 866 867 dmaengine_terminate_async(uap->dmatx.chan); 868 869 if (uap->dmatx.queued) { 870 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, 871 uap->dmatx.len, DMA_TO_DEVICE); 872 uap->dmatx.queued = false; 873 uap->dmacr &= ~UART011_TXDMAE; 874 pl011_write(uap->dmacr, uap, REG_DMACR); 875 } 876 } 877 878 static void pl011_dma_rx_callback(void *data); 879 880 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 881 { 882 struct dma_chan *rxchan = uap->dmarx.chan; 883 struct pl011_dmarx_data *dmarx = &uap->dmarx; 884 struct dma_async_tx_descriptor *desc; 885 struct pl011_dmabuf *dbuf; 886 887 if (!rxchan) 888 return -EIO; 889 890 /* Start the RX DMA job */ 891 dbuf = uap->dmarx.use_buf_b ? 892 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 893 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len, 894 DMA_DEV_TO_MEM, 895 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 896 /* 897 * If the DMA engine is busy and cannot prepare a 898 * channel, no big deal, the driver will fall back 899 * to interrupt mode as a result of this error code. 900 */ 901 if (!desc) { 902 uap->dmarx.running = false; 903 dmaengine_terminate_all(rxchan); 904 return -EBUSY; 905 } 906 907 /* Some data to go along to the callback */ 908 desc->callback = pl011_dma_rx_callback; 909 desc->callback_param = uap; 910 dmarx->cookie = dmaengine_submit(desc); 911 dma_async_issue_pending(rxchan); 912 913 uap->dmacr |= UART011_RXDMAE; 914 pl011_write(uap->dmacr, uap, REG_DMACR); 915 uap->dmarx.running = true; 916 917 uap->im &= ~UART011_RXIM; 918 pl011_write(uap->im, uap, REG_IMSC); 919 920 return 0; 921 } 922 923 /* 924 * This is called when either the DMA job is complete, or 925 * the FIFO timeout interrupt occurred. This must be called 926 * with the port spinlock uap->port.lock held. 927 */ 928 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 929 u32 pending, bool use_buf_b, 930 bool readfifo) 931 { 932 struct tty_port *port = &uap->port.state->port; 933 struct pl011_dmabuf *dbuf = use_buf_b ? 934 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 935 int dma_count = 0; 936 u32 fifotaken = 0; /* only used for vdbg() */ 937 938 struct pl011_dmarx_data *dmarx = &uap->dmarx; 939 int dmataken = 0; 940 941 if (uap->dmarx.poll_rate) { 942 /* The data can be taken by polling */ 943 dmataken = dbuf->len - dmarx->last_residue; 944 /* Recalculate the pending size */ 945 if (pending >= dmataken) 946 pending -= dmataken; 947 } 948 949 /* Pick the remain data from the DMA */ 950 if (pending) { 951 /* 952 * First take all chars in the DMA pipe, then look in the FIFO. 953 * Note that tty_insert_flip_buf() tries to take as many chars 954 * as it can. 955 */ 956 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending); 957 958 uap->port.icount.rx += dma_count; 959 if (dma_count < pending) 960 dev_warn(uap->port.dev, 961 "couldn't insert all characters (TTY is full?)\n"); 962 } 963 964 /* Reset the last_residue for Rx DMA poll */ 965 if (uap->dmarx.poll_rate) 966 dmarx->last_residue = dbuf->len; 967 968 /* 969 * Only continue with trying to read the FIFO if all DMA chars have 970 * been taken first. 971 */ 972 if (dma_count == pending && readfifo) { 973 /* Clear any error flags */ 974 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 975 UART011_FEIS, uap, REG_ICR); 976 977 /* 978 * If we read all the DMA'd characters, and we had an 979 * incomplete buffer, that could be due to an rx error, or 980 * maybe we just timed out. Read any pending chars and check 981 * the error status. 982 * 983 * Error conditions will only occur in the FIFO, these will 984 * trigger an immediate interrupt and stop the DMA job, so we 985 * will always find the error in the FIFO, never in the DMA 986 * buffer. 987 */ 988 fifotaken = pl011_fifo_to_tty(uap); 989 } 990 991 dev_vdbg(uap->port.dev, 992 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 993 dma_count, fifotaken); 994 tty_flip_buffer_push(port); 995 } 996 997 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 998 { 999 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1000 struct dma_chan *rxchan = dmarx->chan; 1001 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? 1002 &dmarx->dbuf_b : &dmarx->dbuf_a; 1003 size_t pending; 1004 struct dma_tx_state state; 1005 enum dma_status dmastat; 1006 1007 /* 1008 * Pause the transfer so we can trust the current counter, 1009 * do this before we pause the PL011 block, else we may 1010 * overflow the FIFO. 1011 */ 1012 if (dmaengine_pause(rxchan)) 1013 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 1014 dmastat = rxchan->device->device_tx_status(rxchan, 1015 dmarx->cookie, &state); 1016 if (dmastat != DMA_PAUSED) 1017 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 1018 1019 /* Disable RX DMA - incoming data will wait in the FIFO */ 1020 uap->dmacr &= ~UART011_RXDMAE; 1021 pl011_write(uap->dmacr, uap, REG_DMACR); 1022 uap->dmarx.running = false; 1023 1024 pending = dbuf->len - state.residue; 1025 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1026 /* Then we terminate the transfer - we now know our residue */ 1027 dmaengine_terminate_all(rxchan); 1028 1029 /* 1030 * This will take the chars we have so far and insert 1031 * into the framework. 1032 */ 1033 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 1034 1035 /* Switch buffer & re-trigger DMA job */ 1036 dmarx->use_buf_b = !dmarx->use_buf_b; 1037 if (pl011_dma_rx_trigger_dma(uap)) { 1038 dev_dbg(uap->port.dev, 1039 "could not retrigger RX DMA job fall back to interrupt mode\n"); 1040 uap->im |= UART011_RXIM; 1041 pl011_write(uap->im, uap, REG_IMSC); 1042 } 1043 } 1044 1045 static void pl011_dma_rx_callback(void *data) 1046 { 1047 struct uart_amba_port *uap = data; 1048 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1049 struct dma_chan *rxchan = dmarx->chan; 1050 bool lastbuf = dmarx->use_buf_b; 1051 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? 1052 &dmarx->dbuf_b : &dmarx->dbuf_a; 1053 size_t pending; 1054 struct dma_tx_state state; 1055 int ret; 1056 1057 /* 1058 * This completion interrupt occurs typically when the 1059 * RX buffer is totally stuffed but no timeout has yet 1060 * occurred. When that happens, we just want the RX 1061 * routine to flush out the secondary DMA buffer while 1062 * we immediately trigger the next DMA job. 1063 */ 1064 uart_port_lock_irq(&uap->port); 1065 /* 1066 * Rx data can be taken by the UART interrupts during 1067 * the DMA irq handler. So we check the residue here. 1068 */ 1069 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1070 pending = dbuf->len - state.residue; 1071 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 1072 /* Then we terminate the transfer - we now know our residue */ 1073 dmaengine_terminate_all(rxchan); 1074 1075 uap->dmarx.running = false; 1076 dmarx->use_buf_b = !lastbuf; 1077 ret = pl011_dma_rx_trigger_dma(uap); 1078 1079 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1080 uart_unlock_and_check_sysrq(&uap->port); 1081 /* 1082 * Do this check after we picked the DMA chars so we don't 1083 * get some IRQ immediately from RX. 1084 */ 1085 if (ret) { 1086 dev_dbg(uap->port.dev, 1087 "could not retrigger RX DMA job fall back to interrupt mode\n"); 1088 uap->im |= UART011_RXIM; 1089 pl011_write(uap->im, uap, REG_IMSC); 1090 } 1091 } 1092 1093 /* 1094 * Stop accepting received characters, when we're shutting down or 1095 * suspending this port. 1096 * Locking: called with port lock held and IRQs disabled. 1097 */ 1098 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1099 { 1100 if (!uap->using_rx_dma) 1101 return; 1102 1103 /* FIXME. Just disable the DMA enable */ 1104 uap->dmacr &= ~UART011_RXDMAE; 1105 pl011_write(uap->dmacr, uap, REG_DMACR); 1106 } 1107 1108 /* 1109 * Timer handler for Rx DMA polling. 1110 * Every polling, It checks the residue in the dma buffer and transfer 1111 * data to the tty. Also, last_residue is updated for the next polling. 1112 */ 1113 static void pl011_dma_rx_poll(struct timer_list *t) 1114 { 1115 struct uart_amba_port *uap = timer_container_of(uap, t, dmarx.timer); 1116 struct tty_port *port = &uap->port.state->port; 1117 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1118 struct dma_chan *rxchan = uap->dmarx.chan; 1119 unsigned long flags; 1120 unsigned int dmataken = 0; 1121 unsigned int size = 0; 1122 struct pl011_dmabuf *dbuf; 1123 int dma_count; 1124 struct dma_tx_state state; 1125 1126 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; 1127 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1128 if (likely(state.residue < dmarx->last_residue)) { 1129 dmataken = dbuf->len - dmarx->last_residue; 1130 size = dmarx->last_residue - state.residue; 1131 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, 1132 size); 1133 if (dma_count == size) 1134 dmarx->last_residue = state.residue; 1135 dmarx->last_jiffies = jiffies; 1136 } 1137 tty_flip_buffer_push(port); 1138 1139 /* 1140 * If no data is received in poll_timeout, the driver will fall back 1141 * to interrupt mode. We will retrigger DMA at the first interrupt. 1142 */ 1143 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1144 > uap->dmarx.poll_timeout) { 1145 uart_port_lock_irqsave(&uap->port, &flags); 1146 pl011_dma_rx_stop(uap); 1147 uap->im |= UART011_RXIM; 1148 pl011_write(uap->im, uap, REG_IMSC); 1149 uart_port_unlock_irqrestore(&uap->port, flags); 1150 1151 uap->dmarx.running = false; 1152 dmaengine_terminate_all(rxchan); 1153 timer_delete(&uap->dmarx.timer); 1154 } else { 1155 mod_timer(&uap->dmarx.timer, 1156 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1157 } 1158 } 1159 1160 static void pl011_dma_startup(struct uart_amba_port *uap) 1161 { 1162 int ret; 1163 1164 if (!uap->dma_probed) 1165 pl011_dma_probe(uap); 1166 1167 if (!uap->dmatx.chan) 1168 return; 1169 1170 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1171 if (!uap->dmatx.buf) { 1172 uap->port.fifosize = uap->fifosize; 1173 return; 1174 } 1175 1176 uap->dmatx.len = PL011_DMA_BUFFER_SIZE; 1177 1178 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1179 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1180 uap->using_tx_dma = true; 1181 1182 if (!uap->dmarx.chan) 1183 goto skip_rx; 1184 1185 /* Allocate and map DMA RX buffers */ 1186 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, 1187 DMA_FROM_DEVICE); 1188 if (ret) { 1189 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1190 "RX buffer A", ret); 1191 goto skip_rx; 1192 } 1193 1194 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, 1195 DMA_FROM_DEVICE); 1196 if (ret) { 1197 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1198 "RX buffer B", ret); 1199 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, 1200 DMA_FROM_DEVICE); 1201 goto skip_rx; 1202 } 1203 1204 uap->using_rx_dma = true; 1205 1206 skip_rx: 1207 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1208 uap->dmacr |= UART011_DMAONERR; 1209 pl011_write(uap->dmacr, uap, REG_DMACR); 1210 1211 /* 1212 * ST Micro variants has some specific dma burst threshold 1213 * compensation. Set this to 16 bytes, so burst will only 1214 * be issued above/below 16 bytes. 1215 */ 1216 if (uap->vendor->dma_threshold) 1217 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1218 uap, REG_ST_DMAWM); 1219 1220 if (uap->using_rx_dma) { 1221 if (pl011_dma_rx_trigger_dma(uap)) 1222 dev_dbg(uap->port.dev, 1223 "could not trigger initial RX DMA job, fall back to interrupt mode\n"); 1224 if (uap->dmarx.poll_rate) { 1225 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); 1226 mod_timer(&uap->dmarx.timer, 1227 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1228 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1229 uap->dmarx.last_jiffies = jiffies; 1230 } 1231 } 1232 } 1233 1234 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1235 { 1236 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1237 return; 1238 1239 /* Disable RX and TX DMA */ 1240 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1241 cpu_relax(); 1242 1243 uart_port_lock_irq(&uap->port); 1244 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1245 pl011_write(uap->dmacr, uap, REG_DMACR); 1246 uart_port_unlock_irq(&uap->port); 1247 1248 if (uap->using_tx_dma) { 1249 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1250 dmaengine_terminate_sync(uap->dmatx.chan); 1251 if (uap->dmatx.queued) { 1252 dma_unmap_single(uap->dmatx.chan->device->dev, 1253 uap->dmatx.dma, uap->dmatx.len, 1254 DMA_TO_DEVICE); 1255 uap->dmatx.queued = false; 1256 } 1257 1258 kfree(uap->dmatx.buf); 1259 uap->using_tx_dma = false; 1260 } 1261 1262 if (uap->using_rx_dma) { 1263 if (uap->dmarx.poll_rate) 1264 timer_delete_sync(&uap->dmarx.timer); 1265 dmaengine_terminate_sync(uap->dmarx.chan); 1266 /* Clean up the RX DMA */ 1267 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); 1268 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); 1269 uap->using_rx_dma = false; 1270 } 1271 } 1272 1273 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1274 { 1275 return uap->using_rx_dma; 1276 } 1277 1278 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1279 { 1280 return uap->using_rx_dma && uap->dmarx.running; 1281 } 1282 1283 #else 1284 /* Blank functions if the DMA engine is not available */ 1285 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1286 { 1287 } 1288 1289 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1290 { 1291 } 1292 1293 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1294 { 1295 } 1296 1297 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1298 { 1299 return false; 1300 } 1301 1302 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1303 { 1304 } 1305 1306 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1307 { 1308 return false; 1309 } 1310 1311 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1312 { 1313 } 1314 1315 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1316 { 1317 } 1318 1319 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1320 { 1321 return -EIO; 1322 } 1323 1324 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1325 { 1326 return false; 1327 } 1328 1329 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1330 { 1331 return false; 1332 } 1333 1334 #define pl011_dma_flush_buffer NULL 1335 #endif 1336 1337 static void pl011_rs485_tx_stop_now(struct uart_amba_port *uap) 1338 { 1339 struct uart_port *port = &uap->port; 1340 u32 cr; 1341 1342 cr = pl011_read(uap, REG_CR); 1343 1344 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) 1345 cr &= ~UART011_CR_RTS; 1346 else 1347 cr |= UART011_CR_RTS; 1348 1349 /* Disable the transmitter and reenable the transceiver */ 1350 cr &= ~UART011_CR_TXE; 1351 cr |= UART011_CR_RXE; 1352 pl011_write(cr, uap, REG_CR); 1353 1354 uap->rs485_tx_state = OFF; 1355 } 1356 1357 static void pl011_rs485_tx_stop(struct uart_amba_port *uap) 1358 { 1359 struct uart_port *port = &uap->port; 1360 1361 if (uap->rs485_tx_state == SEND) 1362 uap->rs485_tx_state = WAIT_AFTER_SEND; 1363 1364 if (uap->rs485_tx_state == WAIT_AFTER_SEND) { 1365 /* Schedule hrtimer if tx queue not empty */ 1366 if (!pl011_tx_empty(port)) { 1367 hrtimer_start(&uap->trigger_stop_tx, 1368 uap->rs485_tx_drain_interval, 1369 HRTIMER_MODE_REL); 1370 return; 1371 } 1372 if (port->rs485.delay_rts_after_send > 0) { 1373 uap->rs485_tx_state = WAIT_AFTER_SEND_DELAY; 1374 hrtimer_start(&uap->trigger_stop_tx, 1375 ms_to_ktime(port->rs485.delay_rts_after_send), 1376 HRTIMER_MODE_REL); 1377 return; 1378 } 1379 /* Continue without any delay */ 1380 } else if (uap->rs485_tx_state == WAIT_AFTER_RTS) { 1381 hrtimer_try_to_cancel(&uap->trigger_start_tx); 1382 } 1383 1384 pl011_rs485_tx_stop_now(uap); 1385 } 1386 1387 static void pl011_stop_tx(struct uart_port *port) 1388 { 1389 struct uart_amba_port *uap = 1390 container_of(port, struct uart_amba_port, port); 1391 1392 if (port->rs485.flags & SER_RS485_ENABLED && 1393 uap->rs485_tx_state == WAIT_AFTER_RTS) { 1394 pl011_rs485_tx_stop(uap); 1395 return; 1396 } 1397 1398 uap->im &= ~UART011_TXIM; 1399 pl011_write(uap->im, uap, REG_IMSC); 1400 pl011_dma_tx_stop(uap); 1401 1402 if (port->rs485.flags & SER_RS485_ENABLED && 1403 uap->rs485_tx_state != OFF) 1404 pl011_rs485_tx_stop(uap); 1405 } 1406 1407 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1408 1409 /* Start TX with programmed I/O only (no DMA) */ 1410 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1411 { 1412 if (pl011_tx_chars(uap, false)) { 1413 uap->im |= UART011_TXIM; 1414 pl011_write(uap->im, uap, REG_IMSC); 1415 } 1416 } 1417 1418 static void pl011_rs485_tx_start(struct uart_amba_port *uap) 1419 { 1420 struct uart_port *port = &uap->port; 1421 u32 cr; 1422 1423 if (uap->rs485_tx_state == WAIT_AFTER_RTS) { 1424 uap->rs485_tx_state = SEND; 1425 return; 1426 } 1427 if (uap->rs485_tx_state == WAIT_AFTER_SEND || 1428 uap->rs485_tx_state == WAIT_AFTER_SEND_DELAY) { 1429 hrtimer_try_to_cancel(&uap->trigger_stop_tx); 1430 uap->rs485_tx_state = SEND; 1431 return; 1432 } 1433 /* uap->rs485_tx_state == OFF */ 1434 /* Enable transmitter */ 1435 cr = pl011_read(uap, REG_CR); 1436 cr |= UART011_CR_TXE; 1437 /* Disable receiver if half-duplex */ 1438 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1439 cr &= ~UART011_CR_RXE; 1440 1441 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) 1442 cr &= ~UART011_CR_RTS; 1443 else 1444 cr |= UART011_CR_RTS; 1445 1446 pl011_write(cr, uap, REG_CR); 1447 1448 if (port->rs485.delay_rts_before_send > 0) { 1449 uap->rs485_tx_state = WAIT_AFTER_RTS; 1450 hrtimer_start(&uap->trigger_start_tx, 1451 ms_to_ktime(port->rs485.delay_rts_before_send), 1452 HRTIMER_MODE_REL); 1453 } else { 1454 uap->rs485_tx_state = SEND; 1455 } 1456 } 1457 1458 static void pl011_start_tx(struct uart_port *port) 1459 { 1460 struct uart_amba_port *uap = 1461 container_of(port, struct uart_amba_port, port); 1462 1463 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && 1464 uap->rs485_tx_state != SEND) { 1465 pl011_rs485_tx_start(uap); 1466 if (uap->rs485_tx_state == WAIT_AFTER_RTS) 1467 return; 1468 } 1469 1470 if (!pl011_dma_tx_start(uap)) 1471 pl011_start_tx_pio(uap); 1472 } 1473 1474 static enum hrtimer_restart pl011_trigger_start_tx(struct hrtimer *t) 1475 { 1476 struct uart_amba_port *uap = 1477 container_of(t, struct uart_amba_port, trigger_start_tx); 1478 unsigned long flags; 1479 1480 uart_port_lock_irqsave(&uap->port, &flags); 1481 if (uap->rs485_tx_state == WAIT_AFTER_RTS) 1482 pl011_start_tx(&uap->port); 1483 uart_port_unlock_irqrestore(&uap->port, flags); 1484 1485 return HRTIMER_NORESTART; 1486 } 1487 1488 static enum hrtimer_restart pl011_trigger_stop_tx(struct hrtimer *t) 1489 { 1490 struct uart_amba_port *uap = 1491 container_of(t, struct uart_amba_port, trigger_stop_tx); 1492 unsigned long flags; 1493 1494 uart_port_lock_irqsave(&uap->port, &flags); 1495 if (uap->rs485_tx_state == WAIT_AFTER_SEND || 1496 uap->rs485_tx_state == WAIT_AFTER_SEND_DELAY) 1497 pl011_rs485_tx_stop(uap); 1498 uart_port_unlock_irqrestore(&uap->port, flags); 1499 1500 return HRTIMER_NORESTART; 1501 } 1502 1503 static void pl011_stop_rx(struct uart_port *port) 1504 { 1505 struct uart_amba_port *uap = 1506 container_of(port, struct uart_amba_port, port); 1507 1508 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM | 1509 UART011_PEIM | UART011_BEIM | UART011_OEIM); 1510 pl011_write(uap->im, uap, REG_IMSC); 1511 1512 pl011_dma_rx_stop(uap); 1513 } 1514 1515 static void pl011_throttle_rx(struct uart_port *port) 1516 { 1517 unsigned long flags; 1518 1519 uart_port_lock_irqsave(port, &flags); 1520 pl011_stop_rx(port); 1521 uart_port_unlock_irqrestore(port, flags); 1522 } 1523 1524 static void pl011_enable_ms(struct uart_port *port) 1525 { 1526 struct uart_amba_port *uap = 1527 container_of(port, struct uart_amba_port, port); 1528 1529 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM; 1530 pl011_write(uap->im, uap, REG_IMSC); 1531 } 1532 1533 static void pl011_rx_chars(struct uart_amba_port *uap) 1534 __releases(&uap->port.lock) 1535 __acquires(&uap->port.lock) 1536 { 1537 pl011_fifo_to_tty(uap); 1538 1539 uart_port_unlock(&uap->port); 1540 tty_flip_buffer_push(&uap->port.state->port); 1541 /* 1542 * If we were temporarily out of DMA mode for a while, 1543 * attempt to switch back to DMA mode again. 1544 */ 1545 if (pl011_dma_rx_available(uap)) { 1546 if (pl011_dma_rx_trigger_dma(uap)) { 1547 dev_dbg(uap->port.dev, 1548 "could not trigger RX DMA job fall back to interrupt mode again\n"); 1549 uap->im |= UART011_RXIM; 1550 pl011_write(uap->im, uap, REG_IMSC); 1551 } else { 1552 #ifdef CONFIG_DMA_ENGINE 1553 /* Start Rx DMA poll */ 1554 if (uap->dmarx.poll_rate) { 1555 uap->dmarx.last_jiffies = jiffies; 1556 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1557 mod_timer(&uap->dmarx.timer, 1558 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1559 } 1560 #endif 1561 } 1562 } 1563 uart_port_lock(&uap->port); 1564 } 1565 1566 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1567 bool from_irq) 1568 { 1569 if (unlikely(!from_irq) && 1570 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1571 return false; /* unable to transmit character */ 1572 1573 pl011_write(c, uap, REG_DR); 1574 uap->port.icount.tx++; 1575 1576 return true; 1577 } 1578 1579 /* Returns true if tx interrupts have to be (kept) enabled */ 1580 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1581 { 1582 struct tty_port *tport = &uap->port.state->port; 1583 int count = uap->fifosize >> 1; 1584 1585 if (uap->port.x_char) { 1586 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1587 return true; 1588 uap->port.x_char = 0; 1589 --count; 1590 } 1591 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(&uap->port)) { 1592 pl011_stop_tx(&uap->port); 1593 return false; 1594 } 1595 1596 /* If we are using DMA mode, try to send some characters. */ 1597 if (pl011_dma_tx_irq(uap)) 1598 return true; 1599 1600 while (1) { 1601 unsigned char c; 1602 1603 if (likely(from_irq) && count-- == 0) 1604 break; 1605 1606 if (!kfifo_peek(&tport->xmit_fifo, &c)) 1607 break; 1608 1609 if (!pl011_tx_char(uap, c, from_irq)) 1610 break; 1611 1612 kfifo_skip(&tport->xmit_fifo); 1613 } 1614 1615 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1616 uart_write_wakeup(&uap->port); 1617 1618 if (kfifo_is_empty(&tport->xmit_fifo)) { 1619 pl011_stop_tx(&uap->port); 1620 return false; 1621 } 1622 return true; 1623 } 1624 1625 static void pl011_modem_status(struct uart_amba_port *uap) 1626 { 1627 unsigned int status, delta; 1628 1629 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1630 1631 delta = status ^ uap->old_status; 1632 uap->old_status = status; 1633 1634 if (!delta) 1635 return; 1636 1637 if (delta & UART01x_FR_DCD) 1638 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1639 1640 if (delta & uap->vendor->fr_dsr) 1641 uap->port.icount.dsr++; 1642 1643 if (delta & uap->vendor->fr_cts) 1644 uart_handle_cts_change(&uap->port, 1645 status & uap->vendor->fr_cts); 1646 1647 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1648 } 1649 1650 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1651 { 1652 if (!uap->vendor->cts_event_workaround) 1653 return; 1654 1655 /* workaround to make sure that all bits are unlocked.. */ 1656 pl011_write(0x00, uap, REG_ICR); 1657 1658 /* 1659 * WA: introduce 26ns(1 uart clk) delay before W1C; 1660 * single apb access will incur 2 pclk(133.12Mhz) delay, 1661 * so add 2 dummy reads 1662 */ 1663 pl011_read(uap, REG_ICR); 1664 pl011_read(uap, REG_ICR); 1665 } 1666 1667 static irqreturn_t pl011_int(int irq, void *dev_id) 1668 { 1669 struct uart_amba_port *uap = dev_id; 1670 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1671 int handled = 0; 1672 1673 uart_port_lock(&uap->port); 1674 status = pl011_read(uap, REG_RIS) & uap->im; 1675 if (status) { 1676 do { 1677 check_apply_cts_event_workaround(uap); 1678 1679 pl011_write(status & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS), 1680 uap, REG_ICR); 1681 1682 if (status & (UART011_RTIS | UART011_RXIS)) { 1683 if (pl011_dma_rx_running(uap)) 1684 pl011_dma_rx_irq(uap); 1685 else 1686 pl011_rx_chars(uap); 1687 } 1688 if (status & (UART011_DSRMIS | UART011_DCDMIS | 1689 UART011_CTSMIS | UART011_RIMIS)) 1690 pl011_modem_status(uap); 1691 if (status & UART011_TXIS) 1692 pl011_tx_chars(uap, true); 1693 1694 if (pass_counter-- == 0) 1695 break; 1696 1697 status = pl011_read(uap, REG_RIS) & uap->im; 1698 } while (status != 0); 1699 handled = 1; 1700 } 1701 1702 uart_unlock_and_check_sysrq(&uap->port); 1703 1704 return IRQ_RETVAL(handled); 1705 } 1706 1707 static unsigned int pl011_tx_empty(struct uart_port *port) 1708 { 1709 struct uart_amba_port *uap = 1710 container_of(port, struct uart_amba_port, port); 1711 1712 /* Allow feature register bits to be inverted to work around errata */ 1713 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; 1714 1715 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 1716 0 : TIOCSER_TEMT; 1717 } 1718 1719 static void pl011_maybe_set_bit(bool cond, unsigned int *ptr, unsigned int mask) 1720 { 1721 if (cond) 1722 *ptr |= mask; 1723 } 1724 1725 static unsigned int pl011_get_mctrl(struct uart_port *port) 1726 { 1727 struct uart_amba_port *uap = 1728 container_of(port, struct uart_amba_port, port); 1729 unsigned int result = 0; 1730 unsigned int status = pl011_read(uap, REG_FR); 1731 1732 pl011_maybe_set_bit(status & UART01x_FR_DCD, &result, TIOCM_CAR); 1733 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR); 1734 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS); 1735 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG); 1736 1737 return result; 1738 } 1739 1740 static void pl011_assign_bit(bool cond, unsigned int *ptr, unsigned int mask) 1741 { 1742 if (cond) 1743 *ptr |= mask; 1744 else 1745 *ptr &= ~mask; 1746 } 1747 1748 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1749 { 1750 struct uart_amba_port *uap = 1751 container_of(port, struct uart_amba_port, port); 1752 unsigned int cr; 1753 1754 cr = pl011_read(uap, REG_CR); 1755 1756 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTS); 1757 pl011_assign_bit(mctrl & TIOCM_DTR, &cr, UART011_CR_DTR); 1758 pl011_assign_bit(mctrl & TIOCM_OUT1, &cr, UART011_CR_OUT1); 1759 pl011_assign_bit(mctrl & TIOCM_OUT2, &cr, UART011_CR_OUT2); 1760 pl011_assign_bit(mctrl & TIOCM_LOOP, &cr, UART011_CR_LBE); 1761 1762 if (port->status & UPSTAT_AUTORTS) { 1763 /* We need to disable auto-RTS if we want to turn RTS off */ 1764 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTSEN); 1765 } 1766 1767 pl011_write(cr, uap, REG_CR); 1768 } 1769 1770 static void pl011_break_ctl(struct uart_port *port, int break_state) 1771 { 1772 struct uart_amba_port *uap = 1773 container_of(port, struct uart_amba_port, port); 1774 unsigned long flags; 1775 unsigned int lcr_h; 1776 1777 uart_port_lock_irqsave(&uap->port, &flags); 1778 lcr_h = pl011_read(uap, REG_LCRH_TX); 1779 if (break_state == -1) 1780 lcr_h |= UART01x_LCRH_BRK; 1781 else 1782 lcr_h &= ~UART01x_LCRH_BRK; 1783 pl011_write(lcr_h, uap, REG_LCRH_TX); 1784 uart_port_unlock_irqrestore(&uap->port, flags); 1785 } 1786 1787 #ifdef CONFIG_CONSOLE_POLL 1788 1789 static void pl011_quiesce_irqs(struct uart_port *port) 1790 { 1791 struct uart_amba_port *uap = 1792 container_of(port, struct uart_amba_port, port); 1793 1794 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1795 /* 1796 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1797 * we simply mask it. start_tx() will unmask it. 1798 * 1799 * Note we can race with start_tx(), and if the race happens, the 1800 * polling user might get another interrupt just after we clear it. 1801 * But it should be OK and can happen even w/o the race, e.g. 1802 * controller immediately got some new data and raised the IRQ. 1803 * 1804 * And whoever uses polling routines assumes that it manages the device 1805 * (including tx queue), so we're also fine with start_tx()'s caller 1806 * side. 1807 */ 1808 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1809 REG_IMSC); 1810 } 1811 1812 static int pl011_get_poll_char(struct uart_port *port) 1813 { 1814 struct uart_amba_port *uap = 1815 container_of(port, struct uart_amba_port, port); 1816 unsigned int status; 1817 1818 /* 1819 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1820 * debugger. 1821 */ 1822 pl011_quiesce_irqs(port); 1823 1824 status = pl011_read(uap, REG_FR); 1825 if (status & UART01x_FR_RXFE) 1826 return NO_POLL_CHAR; 1827 1828 return pl011_read(uap, REG_DR); 1829 } 1830 1831 static void pl011_put_poll_char(struct uart_port *port, unsigned char ch) 1832 { 1833 struct uart_amba_port *uap = 1834 container_of(port, struct uart_amba_port, port); 1835 1836 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1837 cpu_relax(); 1838 1839 pl011_write(ch, uap, REG_DR); 1840 } 1841 1842 #endif /* CONFIG_CONSOLE_POLL */ 1843 1844 static int pl011_hwinit(struct uart_port *port) 1845 { 1846 struct uart_amba_port *uap = 1847 container_of(port, struct uart_amba_port, port); 1848 int retval; 1849 1850 /* Optionaly enable pins to be muxed in and configured */ 1851 pinctrl_pm_select_default_state(port->dev); 1852 1853 /* 1854 * Try to enable the clock producer. 1855 */ 1856 retval = clk_prepare_enable(uap->clk); 1857 if (retval) 1858 return retval; 1859 1860 uap->port.uartclk = clk_get_rate(uap->clk); 1861 1862 /* Clear pending error and receive interrupts */ 1863 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1864 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1865 uap, REG_ICR); 1866 1867 /* 1868 * Save interrupts enable mask, and enable RX interrupts in case if 1869 * the interrupt is used for NMI entry. 1870 */ 1871 uap->im = pl011_read(uap, REG_IMSC); 1872 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1873 1874 if (dev_get_platdata(uap->port.dev)) { 1875 struct amba_pl011_data *plat; 1876 1877 plat = dev_get_platdata(uap->port.dev); 1878 if (plat->init) 1879 plat->init(); 1880 } 1881 return 0; 1882 } 1883 1884 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1885 { 1886 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1887 pl011_reg_to_offset(uap, REG_LCRH_TX); 1888 } 1889 1890 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1891 { 1892 pl011_write(lcr_h, uap, REG_LCRH_RX); 1893 if (pl011_split_lcrh(uap)) { 1894 int i; 1895 /* 1896 * Wait 10 PCLKs before writing LCRH_TX register, 1897 * to get this delay write read only register 10 times 1898 */ 1899 for (i = 0; i < 10; ++i) 1900 pl011_write(0xff, uap, REG_MIS); 1901 pl011_write(lcr_h, uap, REG_LCRH_TX); 1902 } 1903 } 1904 1905 static int pl011_allocate_irq(struct uart_amba_port *uap) 1906 { 1907 pl011_write(uap->im, uap, REG_IMSC); 1908 1909 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); 1910 } 1911 1912 /* 1913 * Enable interrupts, only timeouts when using DMA 1914 * if initial RX DMA job failed, start in interrupt mode 1915 * as well. 1916 */ 1917 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1918 { 1919 unsigned long flags; 1920 unsigned int i; 1921 1922 uart_port_lock_irqsave(&uap->port, &flags); 1923 1924 /* Clear out any spuriously appearing RX interrupts */ 1925 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1926 1927 /* 1928 * RXIS is asserted only when the RX FIFO transitions from below 1929 * to above the trigger threshold. If the RX FIFO is already 1930 * full to the threshold this can't happen and RXIS will now be 1931 * stuck off. Drain the RX FIFO explicitly to fix this: 1932 */ 1933 for (i = 0; i < uap->fifosize * 2; ++i) { 1934 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE) 1935 break; 1936 1937 pl011_read(uap, REG_DR); 1938 } 1939 1940 uap->im = UART011_RTIM; 1941 if (!pl011_dma_rx_running(uap)) 1942 uap->im |= UART011_RXIM; 1943 pl011_write(uap->im, uap, REG_IMSC); 1944 uart_port_unlock_irqrestore(&uap->port, flags); 1945 } 1946 1947 static void pl011_unthrottle_rx(struct uart_port *port) 1948 { 1949 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); 1950 unsigned long flags; 1951 1952 uart_port_lock_irqsave(&uap->port, &flags); 1953 1954 uap->im = UART011_RTIM; 1955 if (!pl011_dma_rx_running(uap)) 1956 uap->im |= UART011_RXIM; 1957 1958 pl011_write(uap->im, uap, REG_IMSC); 1959 1960 #ifdef CONFIG_DMA_ENGINE 1961 if (uap->using_rx_dma) { 1962 uap->dmacr |= UART011_RXDMAE; 1963 pl011_write(uap->dmacr, uap, REG_DMACR); 1964 } 1965 #endif 1966 1967 uart_port_unlock_irqrestore(&uap->port, flags); 1968 } 1969 1970 static int pl011_startup(struct uart_port *port) 1971 { 1972 struct uart_amba_port *uap = 1973 container_of(port, struct uart_amba_port, port); 1974 unsigned int cr; 1975 int retval; 1976 1977 retval = pl011_hwinit(port); 1978 if (retval) 1979 goto clk_dis; 1980 1981 retval = pl011_allocate_irq(uap); 1982 if (retval) 1983 goto clk_dis; 1984 1985 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1986 1987 uart_port_lock_irq(&uap->port); 1988 1989 cr = pl011_read(uap, REG_CR); 1990 cr &= UART011_CR_RTS | UART011_CR_DTR; 1991 cr |= UART01x_CR_UARTEN | UART011_CR_RXE; 1992 1993 if (!(port->rs485.flags & SER_RS485_ENABLED)) 1994 cr |= UART011_CR_TXE; 1995 1996 pl011_write(cr, uap, REG_CR); 1997 1998 uart_port_unlock_irq(&uap->port); 1999 2000 /* 2001 * initialise the old status of the modem signals 2002 */ 2003 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 2004 2005 /* Startup DMA */ 2006 pl011_dma_startup(uap); 2007 2008 pl011_enable_interrupts(uap); 2009 2010 return 0; 2011 2012 clk_dis: 2013 clk_disable_unprepare(uap->clk); 2014 return retval; 2015 } 2016 2017 static int sbsa_uart_startup(struct uart_port *port) 2018 { 2019 struct uart_amba_port *uap = 2020 container_of(port, struct uart_amba_port, port); 2021 int retval; 2022 2023 retval = pl011_hwinit(port); 2024 if (retval) 2025 return retval; 2026 2027 retval = pl011_allocate_irq(uap); 2028 if (retval) 2029 return retval; 2030 2031 /* The SBSA UART does not support any modem status lines. */ 2032 uap->old_status = 0; 2033 2034 pl011_enable_interrupts(uap); 2035 2036 return 0; 2037 } 2038 2039 static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh) 2040 { 2041 unsigned long val; 2042 2043 val = pl011_read(uap, lcrh); 2044 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 2045 pl011_write(val, uap, lcrh); 2046 } 2047 2048 /* 2049 * disable the port. It should not disable RTS and DTR. 2050 * Also RTS and DTR state should be preserved to restore 2051 * it during startup(). 2052 */ 2053 static void pl011_disable_uart(struct uart_amba_port *uap) 2054 { 2055 unsigned int cr; 2056 2057 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2058 uart_port_lock_irq(&uap->port); 2059 cr = pl011_read(uap, REG_CR); 2060 cr &= UART011_CR_RTS | UART011_CR_DTR; 2061 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2062 pl011_write(cr, uap, REG_CR); 2063 uart_port_unlock_irq(&uap->port); 2064 2065 /* 2066 * disable break condition and fifos 2067 */ 2068 pl011_shutdown_channel(uap, REG_LCRH_RX); 2069 if (pl011_split_lcrh(uap)) 2070 pl011_shutdown_channel(uap, REG_LCRH_TX); 2071 } 2072 2073 static void pl011_disable_interrupts(struct uart_amba_port *uap) 2074 { 2075 uart_port_lock_irq(&uap->port); 2076 2077 /* mask all interrupts and clear all pending ones */ 2078 uap->im = 0; 2079 pl011_write(uap->im, uap, REG_IMSC); 2080 pl011_write(0xffff, uap, REG_ICR); 2081 2082 uart_port_unlock_irq(&uap->port); 2083 } 2084 2085 static void pl011_shutdown(struct uart_port *port) 2086 { 2087 struct uart_amba_port *uap = 2088 container_of(port, struct uart_amba_port, port); 2089 2090 pl011_disable_interrupts(uap); 2091 2092 pl011_dma_shutdown(uap); 2093 2094 free_irq(uap->port.irq, uap); 2095 2096 /* 2097 * free_irq() drains the UART interrupt handler, which can arm either 2098 * timer. Cancel the timers afterwards to drain their callbacks too. 2099 */ 2100 hrtimer_cancel(&uap->trigger_start_tx); 2101 hrtimer_cancel(&uap->trigger_stop_tx); 2102 2103 uart_port_lock_irq(port); 2104 if (uap->rs485_tx_state != OFF) 2105 pl011_rs485_tx_stop_now(uap); 2106 uart_port_unlock_irq(port); 2107 2108 pl011_disable_uart(uap); 2109 2110 /* 2111 * Shut down the clock producer 2112 */ 2113 clk_disable_unprepare(uap->clk); 2114 /* Optionally let pins go into sleep states */ 2115 pinctrl_pm_select_sleep_state(port->dev); 2116 2117 if (dev_get_platdata(uap->port.dev)) { 2118 struct amba_pl011_data *plat; 2119 2120 plat = dev_get_platdata(uap->port.dev); 2121 if (plat->exit) 2122 plat->exit(); 2123 } 2124 2125 if (uap->port.ops->flush_buffer) 2126 uap->port.ops->flush_buffer(port); 2127 } 2128 2129 static void sbsa_uart_shutdown(struct uart_port *port) 2130 { 2131 struct uart_amba_port *uap = 2132 container_of(port, struct uart_amba_port, port); 2133 2134 pl011_disable_interrupts(uap); 2135 2136 free_irq(uap->port.irq, uap); 2137 2138 if (uap->port.ops->flush_buffer) 2139 uap->port.ops->flush_buffer(port); 2140 } 2141 2142 static void 2143 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 2144 { 2145 port->read_status_mask = UART011_DR_OE | 255; 2146 if (termios->c_iflag & INPCK) 2147 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 2148 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2149 port->read_status_mask |= UART011_DR_BE; 2150 2151 /* 2152 * Characters to ignore 2153 */ 2154 port->ignore_status_mask = 0; 2155 if (termios->c_iflag & IGNPAR) 2156 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 2157 if (termios->c_iflag & IGNBRK) { 2158 port->ignore_status_mask |= UART011_DR_BE; 2159 /* 2160 * If we're ignoring parity and break indicators, 2161 * ignore overruns too (for real raw support). 2162 */ 2163 if (termios->c_iflag & IGNPAR) 2164 port->ignore_status_mask |= UART011_DR_OE; 2165 } 2166 2167 /* 2168 * Ignore all characters if CREAD is not set. 2169 */ 2170 if ((termios->c_cflag & CREAD) == 0) 2171 port->ignore_status_mask |= UART_DUMMY_DR_RX; 2172 } 2173 2174 static void 2175 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 2176 const struct ktermios *old) 2177 { 2178 struct uart_amba_port *uap = 2179 container_of(port, struct uart_amba_port, port); 2180 unsigned int lcr_h, old_cr; 2181 unsigned long flags; 2182 unsigned int baud, quot, clkdiv; 2183 unsigned int max_baud; 2184 unsigned int bits; 2185 2186 if (uap->vendor->oversampling) 2187 clkdiv = 8; 2188 else 2189 clkdiv = 16; 2190 2191 max_baud = port->uartclk / clkdiv; 2192 2193 if (uap->vendor->set_uartclk_rate) { 2194 long max_clkrate = clk_round_rate(uap->clk, UINT_MAX); 2195 2196 /* 2197 * Clock is reprogrammable - determine max baud from the clock's 2198 * maximum rate, not the current uartclk. 2199 */ 2200 if (max_clkrate > 0) 2201 max_baud = max_clkrate / clkdiv; 2202 } 2203 2204 /* 2205 * Ask the core to calculate the divisor for us. 2206 */ 2207 baud = uart_get_baud_rate(port, termios, old, 0, max_baud); 2208 2209 if (uap->vendor->set_uartclk_rate) { 2210 int err; 2211 2212 err = clk_set_rate(uap->clk, baud * clkdiv); 2213 if (err) { 2214 dev_err(port->dev, "Failed to set clock rate: %d\n", err); 2215 return; 2216 } 2217 } 2218 2219 #ifdef CONFIG_DMA_ENGINE 2220 /* 2221 * Adjust RX DMA polling rate with baud rate if not specified. 2222 */ 2223 if (uap->dmarx.auto_poll_rate) 2224 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 2225 #endif 2226 2227 switch (termios->c_cflag & CSIZE) { 2228 case CS5: 2229 lcr_h = UART01x_LCRH_WLEN_5; 2230 break; 2231 case CS6: 2232 lcr_h = UART01x_LCRH_WLEN_6; 2233 break; 2234 case CS7: 2235 lcr_h = UART01x_LCRH_WLEN_7; 2236 break; 2237 default: // CS8 2238 lcr_h = UART01x_LCRH_WLEN_8; 2239 break; 2240 } 2241 if (termios->c_cflag & CSTOPB) 2242 lcr_h |= UART01x_LCRH_STP2; 2243 if (termios->c_cflag & PARENB) { 2244 lcr_h |= UART01x_LCRH_PEN; 2245 if (!(termios->c_cflag & PARODD)) 2246 lcr_h |= UART01x_LCRH_EPS; 2247 if (termios->c_cflag & CMSPAR) 2248 lcr_h |= UART011_LCRH_SPS; 2249 } 2250 if (uap->fifosize > 1) 2251 lcr_h |= UART01x_LCRH_FEN; 2252 2253 bits = tty_get_frame_size(termios->c_cflag); 2254 2255 uart_port_lock_irqsave(port, &flags); 2256 2257 /* 2258 * Update the per-port timeout. 2259 */ 2260 uart_update_timeout(port, termios->c_cflag, baud); 2261 2262 /* 2263 * Calculate the approximated time it takes to transmit one character 2264 * with the given baud rate. We use this as the poll interval when we 2265 * wait for the tx queue to empty. 2266 */ 2267 uap->rs485_tx_drain_interval = ns_to_ktime(DIV_ROUND_UP(bits * NSEC_PER_SEC, baud)); 2268 2269 pl011_setup_status_masks(port, termios); 2270 2271 if (UART_ENABLE_MS(port, termios->c_cflag)) 2272 pl011_enable_ms(port); 2273 2274 if (port->rs485.flags & SER_RS485_ENABLED) 2275 termios->c_cflag &= ~CRTSCTS; 2276 2277 old_cr = pl011_read(uap, REG_CR); 2278 2279 if (termios->c_cflag & CRTSCTS) { 2280 if (old_cr & UART011_CR_RTS) 2281 old_cr |= UART011_CR_RTSEN; 2282 2283 old_cr |= UART011_CR_CTSEN; 2284 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 2285 } else { 2286 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 2287 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 2288 } 2289 2290 if (uap->vendor->oversampling) { 2291 if (baud > port->uartclk / 16) 2292 old_cr |= ST_UART011_CR_OVSFACT; 2293 else 2294 old_cr &= ~ST_UART011_CR_OVSFACT; 2295 } 2296 2297 if (!uap->vendor->skip_ibrd_fbrd) { 2298 if (baud > port->uartclk / 16) 2299 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 2300 else 2301 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 2302 2303 /* 2304 * Workaround for the ST Micro oversampling variants to 2305 * increase the bitrate slightly, by lowering the divisor, 2306 * to avoid delayed sampling of start bit at high speeds, 2307 * else we see data corruption. 2308 */ 2309 if (uap->vendor->oversampling) { 2310 if (baud >= 3000000 && baud < 3250000 && quot > 1) 2311 quot -= 1; 2312 else if (baud > 3250000 && quot > 2) 2313 quot -= 2; 2314 } 2315 /* Set baud rate */ 2316 pl011_write(quot & 0x3f, uap, REG_FBRD); 2317 pl011_write(quot >> 6, uap, REG_IBRD); 2318 } 2319 2320 /* 2321 * ----------v----------v----------v----------v----- 2322 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2323 * REG_FBRD & REG_IBRD. 2324 * ----------^----------^----------^----------^----- 2325 */ 2326 pl011_write_lcr_h(uap, lcr_h); 2327 2328 /* 2329 * Receive was disabled by pl011_disable_uart during shutdown. 2330 * Need to reenable receive if you need to use a tty_driver 2331 * returns from tty_find_polling_driver() after a port shutdown. 2332 */ 2333 old_cr |= UART011_CR_RXE; 2334 pl011_write(old_cr, uap, REG_CR); 2335 2336 uart_port_unlock_irqrestore(port, flags); 2337 } 2338 2339 static void 2340 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2341 const struct ktermios *old) 2342 { 2343 struct uart_amba_port *uap = 2344 container_of(port, struct uart_amba_port, port); 2345 unsigned long flags; 2346 2347 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2348 2349 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2350 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2351 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2352 termios->c_cflag |= CS8 | CLOCAL; 2353 2354 uart_port_lock_irqsave(port, &flags); 2355 uart_update_timeout(port, CS8, uap->fixed_baud); 2356 pl011_setup_status_masks(port, termios); 2357 uart_port_unlock_irqrestore(port, flags); 2358 } 2359 2360 static const char *pl011_type(struct uart_port *port) 2361 { 2362 struct uart_amba_port *uap = 2363 container_of(port, struct uart_amba_port, port); 2364 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2365 } 2366 2367 /* 2368 * Configure/autoconfigure the port. 2369 */ 2370 static void pl011_config_port(struct uart_port *port, int flags) 2371 { 2372 if (flags & UART_CONFIG_TYPE) 2373 port->type = PORT_AMBA; 2374 } 2375 2376 /* 2377 * verify the new serial_struct (for TIOCSSERIAL). 2378 */ 2379 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2380 { 2381 int ret = 0; 2382 2383 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2384 ret = -EINVAL; 2385 if (ser->irq < 0 || ser->irq >= irq_get_nr_irqs()) 2386 ret = -EINVAL; 2387 if (ser->baud_base < 9600) 2388 ret = -EINVAL; 2389 if (port->mapbase != (unsigned long)ser->iomem_base) 2390 ret = -EINVAL; 2391 return ret; 2392 } 2393 2394 static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios, 2395 struct serial_rs485 *rs485) 2396 { 2397 struct uart_amba_port *uap = 2398 container_of(port, struct uart_amba_port, port); 2399 2400 if (port->rs485.flags & SER_RS485_ENABLED) 2401 pl011_rs485_tx_stop(uap); 2402 2403 /* Make sure auto RTS is disabled */ 2404 if (rs485->flags & SER_RS485_ENABLED) { 2405 u32 cr = pl011_read(uap, REG_CR); 2406 2407 cr &= ~UART011_CR_RTSEN; 2408 pl011_write(cr, uap, REG_CR); 2409 port->status &= ~UPSTAT_AUTORTS; 2410 } 2411 2412 return 0; 2413 } 2414 2415 static const struct uart_ops amba_pl011_pops = { 2416 .tx_empty = pl011_tx_empty, 2417 .set_mctrl = pl011_set_mctrl, 2418 .get_mctrl = pl011_get_mctrl, 2419 .stop_tx = pl011_stop_tx, 2420 .start_tx = pl011_start_tx, 2421 .stop_rx = pl011_stop_rx, 2422 .throttle = pl011_throttle_rx, 2423 .unthrottle = pl011_unthrottle_rx, 2424 .enable_ms = pl011_enable_ms, 2425 .break_ctl = pl011_break_ctl, 2426 .startup = pl011_startup, 2427 .shutdown = pl011_shutdown, 2428 .flush_buffer = pl011_dma_flush_buffer, 2429 .set_termios = pl011_set_termios, 2430 .type = pl011_type, 2431 .config_port = pl011_config_port, 2432 .verify_port = pl011_verify_port, 2433 #ifdef CONFIG_CONSOLE_POLL 2434 .poll_init = pl011_hwinit, 2435 .poll_get_char = pl011_get_poll_char, 2436 .poll_put_char = pl011_put_poll_char, 2437 #endif 2438 }; 2439 2440 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2441 { 2442 } 2443 2444 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2445 { 2446 return 0; 2447 } 2448 2449 static const struct uart_ops sbsa_uart_pops = { 2450 .tx_empty = pl011_tx_empty, 2451 .set_mctrl = sbsa_uart_set_mctrl, 2452 .get_mctrl = sbsa_uart_get_mctrl, 2453 .stop_tx = pl011_stop_tx, 2454 .start_tx = pl011_start_tx, 2455 .stop_rx = pl011_stop_rx, 2456 .startup = sbsa_uart_startup, 2457 .shutdown = sbsa_uart_shutdown, 2458 .set_termios = sbsa_uart_set_termios, 2459 .type = pl011_type, 2460 .config_port = pl011_config_port, 2461 .verify_port = pl011_verify_port, 2462 #ifdef CONFIG_CONSOLE_POLL 2463 .poll_init = pl011_hwinit, 2464 .poll_get_char = pl011_get_poll_char, 2465 .poll_put_char = pl011_put_poll_char, 2466 #endif 2467 }; 2468 2469 static struct uart_amba_port *amba_ports[UART_NR]; 2470 2471 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2472 2473 static void pl011_console_putchar(struct uart_port *port, unsigned char ch) 2474 { 2475 struct uart_amba_port *uap = 2476 container_of(port, struct uart_amba_port, port); 2477 2478 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2479 cpu_relax(); 2480 pl011_write(ch, uap, REG_DR); 2481 uap->console_line_ended = (ch == '\n'); 2482 } 2483 2484 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2485 int *parity, int *bits) 2486 { 2487 unsigned int lcr_h, ibrd, fbrd; 2488 unsigned int clkdiv; 2489 2490 if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN)) 2491 return; 2492 2493 lcr_h = pl011_read(uap, REG_LCRH_TX); 2494 2495 *parity = 'n'; 2496 if (lcr_h & UART01x_LCRH_PEN) { 2497 if (lcr_h & UART01x_LCRH_EPS) 2498 *parity = 'e'; 2499 else 2500 *parity = 'o'; 2501 } 2502 2503 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2504 *bits = 7; 2505 else 2506 *bits = 8; 2507 2508 if (uap->vendor->skip_ibrd_fbrd) { 2509 clkdiv = 64; 2510 } else { 2511 ibrd = pl011_read(uap, REG_IBRD); 2512 fbrd = pl011_read(uap, REG_FBRD); 2513 clkdiv = 64 * ibrd + fbrd; 2514 } 2515 2516 *baud = uap->port.uartclk * 4 / clkdiv; 2517 2518 if (uap->vendor->oversampling && 2519 (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT)) 2520 *baud *= 2; 2521 } 2522 2523 static int pl011_console_setup(struct console *co, char *options) 2524 { 2525 struct uart_amba_port *uap; 2526 int baud = 38400; 2527 int bits = 8; 2528 int parity = 'n'; 2529 int flow = 'n'; 2530 int ret; 2531 2532 /* 2533 * Check whether an invalid uart number has been specified, and 2534 * if so, search for the first available port that does have 2535 * console support. 2536 */ 2537 if (co->index >= UART_NR) 2538 co->index = 0; 2539 uap = amba_ports[co->index]; 2540 if (!uap) 2541 return -ENODEV; 2542 2543 /* Allow pins to be muxed in and configured */ 2544 pinctrl_pm_select_default_state(uap->port.dev); 2545 2546 ret = clk_prepare(uap->clk); 2547 if (ret) 2548 return ret; 2549 2550 uap->console_line_ended = true; 2551 2552 if (dev_get_platdata(uap->port.dev)) { 2553 struct amba_pl011_data *plat; 2554 2555 plat = dev_get_platdata(uap->port.dev); 2556 if (plat->init) 2557 plat->init(); 2558 } 2559 2560 uap->port.uartclk = clk_get_rate(uap->clk); 2561 2562 if (uap->vendor->fixed_options) { 2563 baud = uap->fixed_baud; 2564 } else { 2565 if (options) 2566 uart_parse_options(options, 2567 &baud, &parity, &bits, &flow); 2568 else 2569 pl011_console_get_options(uap, &baud, &parity, &bits); 2570 } 2571 2572 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2573 } 2574 2575 /** 2576 * pl011_console_match - non-standard console matching 2577 * @co: registering console 2578 * @name: name from console command line 2579 * @idx: index from console command line 2580 * @options: ptr to option string from console command line 2581 * 2582 * Only attempts to match console command lines of the form: 2583 * console=pl011,mmio|mmio32,<addr>[,<options>] 2584 * console=pl011,0x<addr>[,<options>] 2585 * This form is used to register an initial earlycon boot console and 2586 * replace it with the amba_console at pl011 driver init. 2587 * 2588 * Performs console setup for a match (as required by interface) 2589 * If no <options> are specified, then assume the h/w is already setup. 2590 * 2591 * Returns 0 if console matches; otherwise non-zero to use default matching 2592 */ 2593 static int pl011_console_match(struct console *co, char *name, int idx, 2594 char *options) 2595 { 2596 enum uart_iotype iotype; 2597 resource_size_t addr; 2598 int i; 2599 2600 /* 2601 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum 2602 * have a distinct console name, so make sure we check for that. 2603 * The actual implementation of the erratum occurs in the probe 2604 * function. 2605 */ 2606 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0)) 2607 return -ENODEV; 2608 2609 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 2610 return -ENODEV; 2611 2612 if (iotype != UPIO_MEM && iotype != UPIO_MEM32) 2613 return -ENODEV; 2614 2615 /* try to match the port specified on the command line */ 2616 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2617 struct uart_port *port; 2618 2619 if (!amba_ports[i]) 2620 continue; 2621 2622 port = &amba_ports[i]->port; 2623 2624 if (port->mapbase != addr) 2625 continue; 2626 2627 co->index = i; 2628 uart_port_set_cons(port, co); 2629 return pl011_console_setup(co, options); 2630 } 2631 2632 return -ENODEV; 2633 } 2634 2635 static void 2636 pl011_console_write_atomic(struct console *co, struct nbcon_write_context *wctxt) 2637 { 2638 struct uart_amba_port *uap = amba_ports[co->index]; 2639 unsigned int old_cr = 0; 2640 2641 if (!nbcon_enter_unsafe(wctxt)) 2642 return; 2643 2644 clk_enable(uap->clk); 2645 2646 if (!uap->vendor->always_enabled) { 2647 old_cr = pl011_read(uap, REG_CR); 2648 pl011_write((old_cr & ~UART011_CR_CTSEN) | (UART01x_CR_UARTEN | UART011_CR_TXE), 2649 uap, REG_CR); 2650 } 2651 2652 if (!uap->console_line_ended) 2653 uart_console_write(&uap->port, "\n", 1, pl011_console_putchar); 2654 uart_console_write(&uap->port, wctxt->outbuf, wctxt->len, pl011_console_putchar); 2655 2656 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) & uap->vendor->fr_busy) 2657 cpu_relax(); 2658 2659 if (!uap->vendor->always_enabled) 2660 pl011_write(old_cr, uap, REG_CR); 2661 2662 clk_disable(uap->clk); 2663 2664 nbcon_exit_unsafe(wctxt); 2665 } 2666 2667 static void 2668 pl011_console_write_thread(struct console *co, struct nbcon_write_context *wctxt) 2669 { 2670 struct uart_amba_port *uap = amba_ports[co->index]; 2671 unsigned int old_cr = 0; 2672 2673 if (!nbcon_enter_unsafe(wctxt)) 2674 return; 2675 2676 clk_enable(uap->clk); 2677 2678 if (!uap->vendor->always_enabled) { 2679 old_cr = pl011_read(uap, REG_CR); 2680 pl011_write((old_cr & ~UART011_CR_CTSEN) | (UART01x_CR_UARTEN | UART011_CR_TXE), 2681 uap, REG_CR); 2682 } 2683 2684 if (nbcon_exit_unsafe(wctxt)) { 2685 int i; 2686 unsigned int len = READ_ONCE(wctxt->len); 2687 2688 for (i = 0; i < len; i++) { 2689 if (!nbcon_enter_unsafe(wctxt)) 2690 break; 2691 uart_console_write(&uap->port, wctxt->outbuf + i, 1, pl011_console_putchar); 2692 if (!nbcon_exit_unsafe(wctxt)) 2693 break; 2694 } 2695 } 2696 2697 while (!nbcon_enter_unsafe(wctxt)) 2698 nbcon_reacquire_nobuf(wctxt); 2699 2700 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) & uap->vendor->fr_busy) 2701 cpu_relax(); 2702 2703 if (!uap->vendor->always_enabled) 2704 pl011_write(old_cr, uap, REG_CR); 2705 2706 clk_disable(uap->clk); 2707 2708 nbcon_exit_unsafe(wctxt); 2709 } 2710 2711 static void 2712 pl011_console_device_lock(struct console *co, unsigned long *flags) 2713 { 2714 __uart_port_lock_irqsave(&amba_ports[co->index]->port, flags); 2715 } 2716 2717 static void 2718 pl011_console_device_unlock(struct console *co, unsigned long flags) 2719 { 2720 __uart_port_unlock_irqrestore(&amba_ports[co->index]->port, flags); 2721 } 2722 2723 static struct uart_driver amba_reg; 2724 static struct console amba_console = { 2725 .name = "ttyAMA", 2726 .device = uart_console_device, 2727 .setup = pl011_console_setup, 2728 .match = pl011_console_match, 2729 .write_atomic = pl011_console_write_atomic, 2730 .write_thread = pl011_console_write_thread, 2731 .device_lock = pl011_console_device_lock, 2732 .device_unlock = pl011_console_device_unlock, 2733 .flags = CON_PRINTBUFFER | CON_ANYTIME | CON_NBCON, 2734 .index = -1, 2735 .data = &amba_reg, 2736 }; 2737 2738 #define AMBA_CONSOLE (&amba_console) 2739 2740 static void qdf2400_e44_putc(struct uart_port *port, unsigned char c) 2741 { 2742 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2743 cpu_relax(); 2744 writel(c, port->membase + UART01x_DR); 2745 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) 2746 cpu_relax(); 2747 } 2748 2749 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned int n) 2750 { 2751 struct earlycon_device *dev = con->data; 2752 2753 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); 2754 } 2755 2756 static void pl011_putc(struct uart_port *port, unsigned char c) 2757 { 2758 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) 2759 cpu_relax(); 2760 if (port->iotype == UPIO_MEM32) 2761 writel(c, port->membase + UART01x_DR); 2762 else 2763 writeb(c, port->membase + UART01x_DR); 2764 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) 2765 cpu_relax(); 2766 } 2767 2768 static void pl011_early_write(struct console *con, const char *s, unsigned int n) 2769 { 2770 struct earlycon_device *dev = con->data; 2771 2772 uart_console_write(&dev->port, s, n, pl011_putc); 2773 } 2774 2775 #ifdef CONFIG_CONSOLE_POLL 2776 static int pl011_getc(struct uart_port *port) 2777 { 2778 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) 2779 return NO_POLL_CHAR; 2780 2781 if (port->iotype == UPIO_MEM32) 2782 return readl(port->membase + UART01x_DR); 2783 else 2784 return readb(port->membase + UART01x_DR); 2785 } 2786 2787 static int pl011_early_read(struct console *con, char *s, unsigned int n) 2788 { 2789 struct earlycon_device *dev = con->data; 2790 int ch, num_read = 0; 2791 2792 while (num_read < n) { 2793 ch = pl011_getc(&dev->port); 2794 if (ch == NO_POLL_CHAR) 2795 break; 2796 2797 s[num_read++] = ch; 2798 } 2799 2800 return num_read; 2801 } 2802 #else 2803 #define pl011_early_read NULL 2804 #endif 2805 2806 /* 2807 * On non-ACPI systems, earlycon is enabled by specifying 2808 * "earlycon=pl011,<address>" on the kernel command line. 2809 * 2810 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table, 2811 * by specifying only "earlycon" on the command line. Because it requires 2812 * SPCR, the console starts after ACPI is parsed, which is later than a 2813 * traditional early console. 2814 * 2815 * To get the traditional early console that starts before ACPI is parsed, 2816 * specify the full "earlycon=pl011,<address>" option. 2817 */ 2818 static int __init pl011_early_console_setup(struct earlycon_device *device, 2819 const char *opt) 2820 { 2821 unsigned int cr; 2822 2823 if (!device->port.membase) 2824 return -ENODEV; 2825 2826 device->con->write = pl011_early_write; 2827 device->con->read = pl011_early_read; 2828 2829 if (device->port.iotype == UPIO_MEM32) 2830 cr = readl(device->port.membase + UART011_CR); 2831 else 2832 cr = readw(device->port.membase + UART011_CR); 2833 cr &= UART011_CR_RTS | UART011_CR_DTR; 2834 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 2835 if (device->port.iotype == UPIO_MEM32) 2836 writel(cr, device->port.membase + UART011_CR); 2837 else 2838 writew(cr, device->port.membase + UART011_CR); 2839 2840 return 0; 2841 } 2842 2843 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2844 2845 /* 2846 * The SBSA UART has no defined control register and is assumed to 2847 * be pre-enabled by firmware, so we do not write to UART011_CR. 2848 */ 2849 static int __init sbsa_uart_early_console_setup(struct earlycon_device *device, 2850 const char *opt) 2851 { 2852 if (!device->port.membase) 2853 return -ENODEV; 2854 2855 device->con->write = pl011_early_write; 2856 device->con->read = pl011_early_read; 2857 2858 return 0; 2859 } 2860 2861 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", sbsa_uart_early_console_setup); 2862 2863 /* 2864 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by 2865 * Erratum 44, traditional earlycon can be enabled by specifying 2866 * "earlycon=qdf2400_e44,<address>". Any options are ignored. 2867 * 2868 * Alternatively, you can just specify "earlycon", and the early console 2869 * will be enabled with the information from the SPCR table. In this 2870 * case, the SPCR code will detect the need for the E44 work-around, 2871 * and set the console name to "qdf2400_e44". 2872 */ 2873 static int __init 2874 qdf2400_e44_early_console_setup(struct earlycon_device *device, 2875 const char *opt) 2876 { 2877 if (!device->port.membase) 2878 return -ENODEV; 2879 2880 device->con->write = qdf2400_e44_early_write; 2881 return 0; 2882 } 2883 2884 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup); 2885 2886 #else 2887 #define AMBA_CONSOLE NULL 2888 #endif 2889 2890 static struct uart_driver amba_reg = { 2891 .owner = THIS_MODULE, 2892 .driver_name = "ttyAMA", 2893 .dev_name = "ttyAMA", 2894 .major = SERIAL_AMBA_MAJOR, 2895 .minor = SERIAL_AMBA_MINOR, 2896 .nr = UART_NR, 2897 .cons = AMBA_CONSOLE, 2898 }; 2899 2900 static int pl011_probe_dt_alias(int index, struct device *dev) 2901 { 2902 struct device_node *np; 2903 static bool seen_dev_with_alias; 2904 static bool seen_dev_without_alias; 2905 int ret = index; 2906 2907 if (!IS_ENABLED(CONFIG_OF)) 2908 return ret; 2909 2910 np = dev->of_node; 2911 if (!np) 2912 return ret; 2913 2914 ret = of_alias_get_id(np, "serial"); 2915 if (ret < 0) { 2916 seen_dev_without_alias = true; 2917 ret = index; 2918 } else { 2919 seen_dev_with_alias = true; 2920 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret]) { 2921 dev_warn(dev, "requested serial port %d not available.\n", ret); 2922 ret = index; 2923 } 2924 } 2925 2926 if (seen_dev_with_alias && seen_dev_without_alias) 2927 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2928 2929 return ret; 2930 } 2931 2932 /* unregisters the driver also if no more ports are left */ 2933 static void pl011_unregister_port(struct uart_amba_port *uap) 2934 { 2935 int i; 2936 bool busy = false; 2937 2938 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2939 if (amba_ports[i] == uap) 2940 amba_ports[i] = NULL; 2941 else if (amba_ports[i]) 2942 busy = true; 2943 } 2944 pl011_dma_remove(uap); 2945 if (!busy) 2946 uart_unregister_driver(&amba_reg); 2947 } 2948 2949 static int pl011_find_free_port(void) 2950 { 2951 int i; 2952 2953 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2954 if (!amba_ports[i]) 2955 return i; 2956 2957 return -EBUSY; 2958 } 2959 2960 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2961 struct resource *mmiobase, int index) 2962 { 2963 void __iomem *base; 2964 int ret; 2965 2966 base = devm_ioremap_resource(dev, mmiobase); 2967 if (IS_ERR(base)) 2968 return PTR_ERR(base); 2969 2970 index = pl011_probe_dt_alias(index, dev); 2971 2972 uap->port.dev = dev; 2973 uap->port.mapbase = mmiobase->start; 2974 uap->port.membase = base; 2975 uap->port.fifosize = uap->fifosize; 2976 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); 2977 uap->port.flags = UPF_BOOT_AUTOCONF; 2978 uap->port.line = index; 2979 2980 ret = uart_get_rs485_mode(&uap->port); 2981 if (ret) 2982 return ret; 2983 2984 amba_ports[index] = uap; 2985 2986 return 0; 2987 } 2988 2989 static int pl011_register_port(struct uart_amba_port *uap) 2990 { 2991 int ret, i; 2992 2993 /* Ensure interrupts from this UART are masked and cleared */ 2994 pl011_write(0, uap, REG_IMSC); 2995 pl011_write(0xffff, uap, REG_ICR); 2996 2997 if (!amba_reg.state) { 2998 ret = uart_register_driver(&amba_reg); 2999 if (ret < 0) { 3000 dev_err(uap->port.dev, 3001 "Failed to register AMBA-PL011 driver\n"); 3002 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 3003 if (amba_ports[i] == uap) 3004 amba_ports[i] = NULL; 3005 return ret; 3006 } 3007 } 3008 3009 ret = uart_add_one_port(&amba_reg, &uap->port); 3010 if (ret) 3011 pl011_unregister_port(uap); 3012 3013 return ret; 3014 } 3015 3016 static const struct serial_rs485 pl011_rs485_supported = { 3017 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 3018 SER_RS485_RX_DURING_TX, 3019 .delay_rts_before_send = 1, 3020 .delay_rts_after_send = 1, 3021 }; 3022 3023 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 3024 { 3025 struct uart_amba_port *uap; 3026 struct vendor_data *vendor = id->data; 3027 int portnr, ret; 3028 u32 val; 3029 3030 portnr = pl011_find_free_port(); 3031 if (portnr < 0) 3032 return portnr; 3033 3034 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 3035 GFP_KERNEL); 3036 if (!uap) 3037 return -ENOMEM; 3038 3039 uap->clk = devm_clk_get(&dev->dev, NULL); 3040 if (IS_ERR(uap->clk)) 3041 return PTR_ERR(uap->clk); 3042 3043 uap->reg_offset = vendor->reg_offset; 3044 uap->vendor = vendor; 3045 uap->fifosize = vendor->get_fifosize(dev); 3046 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 3047 uap->port.irq = dev->irq[0]; 3048 uap->port.ops = &amba_pl011_pops; 3049 uap->port.rs485_config = pl011_rs485_config; 3050 uap->port.rs485_supported = pl011_rs485_supported; 3051 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 3052 3053 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { 3054 switch (val) { 3055 case 1: 3056 uap->port.iotype = UPIO_MEM; 3057 break; 3058 case 4: 3059 uap->port.iotype = UPIO_MEM32; 3060 break; 3061 default: 3062 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n", 3063 val); 3064 return -EINVAL; 3065 } 3066 } 3067 hrtimer_setup(&uap->trigger_start_tx, pl011_trigger_start_tx, CLOCK_MONOTONIC, 3068 HRTIMER_MODE_REL); 3069 hrtimer_setup(&uap->trigger_stop_tx, pl011_trigger_stop_tx, CLOCK_MONOTONIC, 3070 HRTIMER_MODE_REL); 3071 3072 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 3073 if (ret) 3074 return ret; 3075 3076 amba_set_drvdata(dev, uap); 3077 3078 return pl011_register_port(uap); 3079 } 3080 3081 static void pl011_remove(struct amba_device *dev) 3082 { 3083 struct uart_amba_port *uap = amba_get_drvdata(dev); 3084 3085 uart_remove_one_port(&amba_reg, &uap->port); 3086 hrtimer_cancel(&uap->trigger_start_tx); 3087 hrtimer_cancel(&uap->trigger_stop_tx); 3088 pl011_unregister_port(uap); 3089 } 3090 3091 #ifdef CONFIG_PM_SLEEP 3092 static int pl011_suspend(struct device *dev) 3093 { 3094 struct uart_amba_port *uap = dev_get_drvdata(dev); 3095 3096 if (!uap) 3097 return -EINVAL; 3098 3099 return uart_suspend_port(&amba_reg, &uap->port); 3100 } 3101 3102 static int pl011_resume(struct device *dev) 3103 { 3104 struct uart_amba_port *uap = dev_get_drvdata(dev); 3105 3106 if (!uap) 3107 return -EINVAL; 3108 3109 return uart_resume_port(&amba_reg, &uap->port); 3110 } 3111 #endif 3112 3113 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 3114 3115 #ifdef CONFIG_ACPI_SPCR_TABLE 3116 static void qpdf2400_erratum44_workaround(struct device *dev, 3117 struct uart_amba_port *uap) 3118 { 3119 if (!qdf2400_e44_present) 3120 return; 3121 3122 dev_info(dev, "working around QDF2400 SoC erratum 44\n"); 3123 uap->vendor = &vendor_qdt_qdf2400_e44; 3124 } 3125 #else 3126 static void qpdf2400_erratum44_workaround(struct device *dev, 3127 struct uart_amba_port *uap) 3128 { /* empty */ } 3129 #endif 3130 3131 static int sbsa_uart_probe(struct platform_device *pdev) 3132 { 3133 struct uart_amba_port *uap; 3134 struct resource *r; 3135 int portnr, ret; 3136 int baudrate; 3137 3138 /* 3139 * Check the mandatory baud rate parameter in the DT node early 3140 * so that we can easily exit with the error. 3141 */ 3142 if (pdev->dev.of_node) { 3143 struct device_node *np = pdev->dev.of_node; 3144 3145 ret = of_property_read_u32(np, "current-speed", &baudrate); 3146 if (ret) 3147 return ret; 3148 } else { 3149 baudrate = 115200; 3150 } 3151 3152 portnr = pl011_find_free_port(); 3153 if (portnr < 0) 3154 return portnr; 3155 3156 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 3157 GFP_KERNEL); 3158 if (!uap) 3159 return -ENOMEM; 3160 3161 ret = platform_get_irq(pdev, 0); 3162 if (ret < 0) 3163 return ret; 3164 uap->port.irq = ret; 3165 3166 uap->vendor = &vendor_sbsa; 3167 qpdf2400_erratum44_workaround(&pdev->dev, uap); 3168 3169 uap->reg_offset = uap->vendor->reg_offset; 3170 uap->fifosize = 32; 3171 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; 3172 uap->port.ops = &sbsa_uart_pops; 3173 uap->fixed_baud = baudrate; 3174 3175 snprintf(uap->type, sizeof(uap->type), "SBSA"); 3176 3177 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3178 3179 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 3180 if (ret) 3181 return ret; 3182 3183 platform_set_drvdata(pdev, uap); 3184 3185 return pl011_register_port(uap); 3186 } 3187 3188 static void sbsa_uart_remove(struct platform_device *pdev) 3189 { 3190 struct uart_amba_port *uap = platform_get_drvdata(pdev); 3191 3192 uart_remove_one_port(&amba_reg, &uap->port); 3193 pl011_unregister_port(uap); 3194 } 3195 3196 static const struct of_device_id sbsa_uart_of_match[] = { 3197 { .compatible = "arm,sbsa-uart", }, 3198 {}, 3199 }; 3200 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 3201 3202 static const struct acpi_device_id sbsa_uart_acpi_match[] = { 3203 { "ARMH0011", 0 }, 3204 { "ARMHB000", 0 }, 3205 {}, 3206 }; 3207 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 3208 3209 static struct platform_driver arm_sbsa_uart_platform_driver = { 3210 .probe = sbsa_uart_probe, 3211 .remove = sbsa_uart_remove, 3212 .driver = { 3213 .name = "sbsa-uart", 3214 .pm = &pl011_dev_pm_ops, 3215 .of_match_table = sbsa_uart_of_match, 3216 .acpi_match_table = sbsa_uart_acpi_match, 3217 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 3218 }, 3219 }; 3220 3221 static const struct amba_id pl011_ids[] = { 3222 { 3223 .id = 0x00041011, 3224 .mask = 0x000fffff, 3225 .data = &vendor_arm, 3226 }, 3227 { 3228 .id = 0x00380802, 3229 .mask = 0x00ffffff, 3230 .data = &vendor_st, 3231 }, 3232 { 3233 .id = 0x0006b011, 3234 .mask = 0x000fffff, 3235 .data = &vendor_nvidia, 3236 }, 3237 { 3238 /* This is an invented ID. The actual hardware that contains 3239 * these ZTE UARTs (zx29 boards) has no AMBA PIDs stored. ZTE 3240 * JEDEC ID (ignoring banks) and the "011" part number as used 3241 * by ARM. 3242 */ 3243 .id = 0x0008c011, 3244 .mask = 0x000fffff, 3245 .data = &vendor_zte, 3246 }, 3247 { 0, 0 }, 3248 }; 3249 3250 MODULE_DEVICE_TABLE(amba, pl011_ids); 3251 3252 static struct amba_driver pl011_driver = { 3253 .drv = { 3254 .name = "uart-pl011", 3255 .pm = &pl011_dev_pm_ops, 3256 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011), 3257 }, 3258 .id_table = pl011_ids, 3259 .probe = pl011_probe, 3260 .remove = pl011_remove, 3261 }; 3262 3263 static int __init pl011_init(void) 3264 { 3265 pr_info("Serial: AMBA PL011 UART driver\n"); 3266 3267 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 3268 pr_warn("could not register SBSA UART platform driver\n"); 3269 return amba_driver_register(&pl011_driver); 3270 } 3271 3272 static void __exit pl011_exit(void) 3273 { 3274 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 3275 amba_driver_unregister(&pl011_driver); 3276 } 3277 3278 /* 3279 * While this can be a module, if builtin it's most likely the console 3280 * So let's leave module_exit but move module_init to an earlier place 3281 */ 3282 arch_initcall(pl011_init); 3283 module_exit(pl011_exit); 3284 3285 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 3286 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 3287 MODULE_LICENSE("GPL"); 3288