1 /* 2 * Driver for AMBA serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * Copyright (C) 2010 ST-Ericsson SA 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 * This is a generic driver for ARM AMBA-type serial ports. They 25 * have a lot of 16550-like features, but are not register compatible. 26 * Note that although they do have CTS, DCD and DSR inputs, they do 27 * not have an RI input, nor do they have DTR or RTS outputs. If 28 * required, these have to be supplied via some other means (eg, GPIO) 29 * and hooked into this driver. 30 */ 31 32 33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 34 #define SUPPORT_SYSRQ 35 #endif 36 37 #include <linux/module.h> 38 #include <linux/ioport.h> 39 #include <linux/init.h> 40 #include <linux/console.h> 41 #include <linux/sysrq.h> 42 #include <linux/device.h> 43 #include <linux/tty.h> 44 #include <linux/tty_flip.h> 45 #include <linux/serial_core.h> 46 #include <linux/serial.h> 47 #include <linux/amba/bus.h> 48 #include <linux/amba/serial.h> 49 #include <linux/clk.h> 50 #include <linux/slab.h> 51 #include <linux/dmaengine.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/scatterlist.h> 54 #include <linux/delay.h> 55 #include <linux/types.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/pinctrl/consumer.h> 59 #include <linux/sizes.h> 60 #include <linux/io.h> 61 #include <linux/acpi.h> 62 63 #include "amba-pl011.h" 64 65 #define UART_NR 14 66 67 #define SERIAL_AMBA_MAJOR 204 68 #define SERIAL_AMBA_MINOR 64 69 #define SERIAL_AMBA_NR UART_NR 70 71 #define AMBA_ISR_PASS_LIMIT 256 72 73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 74 #define UART_DUMMY_DR_RX (1 << 16) 75 76 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 77 [REG_DR] = UART01x_DR, 78 [REG_FR] = UART01x_FR, 79 [REG_LCRH_RX] = UART011_LCRH, 80 [REG_LCRH_TX] = UART011_LCRH, 81 [REG_IBRD] = UART011_IBRD, 82 [REG_FBRD] = UART011_FBRD, 83 [REG_CR] = UART011_CR, 84 [REG_IFLS] = UART011_IFLS, 85 [REG_IMSC] = UART011_IMSC, 86 [REG_RIS] = UART011_RIS, 87 [REG_MIS] = UART011_MIS, 88 [REG_ICR] = UART011_ICR, 89 [REG_DMACR] = UART011_DMACR, 90 }; 91 92 /* There is by now at least one vendor with differing details, so handle it */ 93 struct vendor_data { 94 const u16 *reg_offset; 95 unsigned int ifls; 96 bool access_32b; 97 bool oversampling; 98 bool dma_threshold; 99 bool cts_event_workaround; 100 bool always_enabled; 101 bool fixed_options; 102 103 unsigned int (*get_fifosize)(struct amba_device *dev); 104 }; 105 106 static unsigned int get_fifosize_arm(struct amba_device *dev) 107 { 108 return amba_rev(dev) < 3 ? 16 : 32; 109 } 110 111 static struct vendor_data vendor_arm = { 112 .reg_offset = pl011_std_offsets, 113 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 114 .oversampling = false, 115 .dma_threshold = false, 116 .cts_event_workaround = false, 117 .always_enabled = false, 118 .fixed_options = false, 119 .get_fifosize = get_fifosize_arm, 120 }; 121 122 static struct vendor_data vendor_sbsa = { 123 .reg_offset = pl011_std_offsets, 124 .oversampling = false, 125 .dma_threshold = false, 126 .cts_event_workaround = false, 127 .always_enabled = true, 128 .fixed_options = true, 129 }; 130 131 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 132 [REG_DR] = UART01x_DR, 133 [REG_ST_DMAWM] = ST_UART011_DMAWM, 134 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 135 [REG_FR] = UART01x_FR, 136 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 137 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 138 [REG_IBRD] = UART011_IBRD, 139 [REG_FBRD] = UART011_FBRD, 140 [REG_CR] = UART011_CR, 141 [REG_IFLS] = UART011_IFLS, 142 [REG_IMSC] = UART011_IMSC, 143 [REG_RIS] = UART011_RIS, 144 [REG_MIS] = UART011_MIS, 145 [REG_ICR] = UART011_ICR, 146 [REG_DMACR] = UART011_DMACR, 147 [REG_ST_XFCR] = ST_UART011_XFCR, 148 [REG_ST_XON1] = ST_UART011_XON1, 149 [REG_ST_XON2] = ST_UART011_XON2, 150 [REG_ST_XOFF1] = ST_UART011_XOFF1, 151 [REG_ST_XOFF2] = ST_UART011_XOFF2, 152 [REG_ST_ITCR] = ST_UART011_ITCR, 153 [REG_ST_ITIP] = ST_UART011_ITIP, 154 [REG_ST_ABCR] = ST_UART011_ABCR, 155 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 156 }; 157 158 static unsigned int get_fifosize_st(struct amba_device *dev) 159 { 160 return 64; 161 } 162 163 static struct vendor_data vendor_st = { 164 .reg_offset = pl011_st_offsets, 165 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 166 .oversampling = true, 167 .dma_threshold = true, 168 .cts_event_workaround = true, 169 .always_enabled = false, 170 .fixed_options = false, 171 .get_fifosize = get_fifosize_st, 172 }; 173 174 /* Deals with DMA transactions */ 175 176 struct pl011_sgbuf { 177 struct scatterlist sg; 178 char *buf; 179 }; 180 181 struct pl011_dmarx_data { 182 struct dma_chan *chan; 183 struct completion complete; 184 bool use_buf_b; 185 struct pl011_sgbuf sgbuf_a; 186 struct pl011_sgbuf sgbuf_b; 187 dma_cookie_t cookie; 188 bool running; 189 struct timer_list timer; 190 unsigned int last_residue; 191 unsigned long last_jiffies; 192 bool auto_poll_rate; 193 unsigned int poll_rate; 194 unsigned int poll_timeout; 195 }; 196 197 struct pl011_dmatx_data { 198 struct dma_chan *chan; 199 struct scatterlist sg; 200 char *buf; 201 bool queued; 202 }; 203 204 /* 205 * We wrap our port structure around the generic uart_port. 206 */ 207 struct uart_amba_port { 208 struct uart_port port; 209 const u16 *reg_offset; 210 struct clk *clk; 211 const struct vendor_data *vendor; 212 unsigned int dmacr; /* dma control reg */ 213 unsigned int im; /* interrupt mask */ 214 unsigned int old_status; 215 unsigned int fifosize; /* vendor-specific */ 216 unsigned int old_cr; /* state during shutdown */ 217 bool autorts; 218 bool access_32b; 219 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 220 char type[12]; 221 #ifdef CONFIG_DMA_ENGINE 222 /* DMA stuff */ 223 bool using_tx_dma; 224 bool using_rx_dma; 225 struct pl011_dmarx_data dmarx; 226 struct pl011_dmatx_data dmatx; 227 bool dma_probed; 228 #endif 229 }; 230 231 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 232 unsigned int reg) 233 { 234 return uap->reg_offset[reg]; 235 } 236 237 static unsigned int pl011_read(const struct uart_amba_port *uap, 238 unsigned int reg) 239 { 240 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 241 242 return uap->access_32b ? readl(addr) : readw(addr); 243 } 244 245 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 246 unsigned int reg) 247 { 248 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 249 250 if (uap->access_32b) 251 writel(val, addr); 252 else 253 writew(val, addr); 254 } 255 256 /* 257 * Reads up to 256 characters from the FIFO or until it's empty and 258 * inserts them into the TTY layer. Returns the number of characters 259 * read from the FIFO. 260 */ 261 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 262 { 263 u16 status; 264 unsigned int ch, flag, max_count = 256; 265 int fifotaken = 0; 266 267 while (max_count--) { 268 status = pl011_read(uap, REG_FR); 269 if (status & UART01x_FR_RXFE) 270 break; 271 272 /* Take chars from the FIFO and update status */ 273 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 274 flag = TTY_NORMAL; 275 uap->port.icount.rx++; 276 fifotaken++; 277 278 if (unlikely(ch & UART_DR_ERROR)) { 279 if (ch & UART011_DR_BE) { 280 ch &= ~(UART011_DR_FE | UART011_DR_PE); 281 uap->port.icount.brk++; 282 if (uart_handle_break(&uap->port)) 283 continue; 284 } else if (ch & UART011_DR_PE) 285 uap->port.icount.parity++; 286 else if (ch & UART011_DR_FE) 287 uap->port.icount.frame++; 288 if (ch & UART011_DR_OE) 289 uap->port.icount.overrun++; 290 291 ch &= uap->port.read_status_mask; 292 293 if (ch & UART011_DR_BE) 294 flag = TTY_BREAK; 295 else if (ch & UART011_DR_PE) 296 flag = TTY_PARITY; 297 else if (ch & UART011_DR_FE) 298 flag = TTY_FRAME; 299 } 300 301 if (uart_handle_sysrq_char(&uap->port, ch & 255)) 302 continue; 303 304 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 305 } 306 307 return fifotaken; 308 } 309 310 311 /* 312 * All the DMA operation mode stuff goes inside this ifdef. 313 * This assumes that you have a generic DMA device interface, 314 * no custom DMA interfaces are supported. 315 */ 316 #ifdef CONFIG_DMA_ENGINE 317 318 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 319 320 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 321 enum dma_data_direction dir) 322 { 323 dma_addr_t dma_addr; 324 325 sg->buf = dma_alloc_coherent(chan->device->dev, 326 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 327 if (!sg->buf) 328 return -ENOMEM; 329 330 sg_init_table(&sg->sg, 1); 331 sg_set_page(&sg->sg, phys_to_page(dma_addr), 332 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 333 sg_dma_address(&sg->sg) = dma_addr; 334 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 335 336 return 0; 337 } 338 339 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 340 enum dma_data_direction dir) 341 { 342 if (sg->buf) { 343 dma_free_coherent(chan->device->dev, 344 PL011_DMA_BUFFER_SIZE, sg->buf, 345 sg_dma_address(&sg->sg)); 346 } 347 } 348 349 static void pl011_dma_probe(struct uart_amba_port *uap) 350 { 351 /* DMA is the sole user of the platform data right now */ 352 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 353 struct device *dev = uap->port.dev; 354 struct dma_slave_config tx_conf = { 355 .dst_addr = uap->port.mapbase + 356 pl011_reg_to_offset(uap, REG_DR), 357 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 358 .direction = DMA_MEM_TO_DEV, 359 .dst_maxburst = uap->fifosize >> 1, 360 .device_fc = false, 361 }; 362 struct dma_chan *chan; 363 dma_cap_mask_t mask; 364 365 uap->dma_probed = true; 366 chan = dma_request_slave_channel_reason(dev, "tx"); 367 if (IS_ERR(chan)) { 368 if (PTR_ERR(chan) == -EPROBE_DEFER) { 369 uap->dma_probed = false; 370 return; 371 } 372 373 /* We need platform data */ 374 if (!plat || !plat->dma_filter) { 375 dev_info(uap->port.dev, "no DMA platform data\n"); 376 return; 377 } 378 379 /* Try to acquire a generic DMA engine slave TX channel */ 380 dma_cap_zero(mask); 381 dma_cap_set(DMA_SLAVE, mask); 382 383 chan = dma_request_channel(mask, plat->dma_filter, 384 plat->dma_tx_param); 385 if (!chan) { 386 dev_err(uap->port.dev, "no TX DMA channel!\n"); 387 return; 388 } 389 } 390 391 dmaengine_slave_config(chan, &tx_conf); 392 uap->dmatx.chan = chan; 393 394 dev_info(uap->port.dev, "DMA channel TX %s\n", 395 dma_chan_name(uap->dmatx.chan)); 396 397 /* Optionally make use of an RX channel as well */ 398 chan = dma_request_slave_channel(dev, "rx"); 399 400 if (!chan && plat->dma_rx_param) { 401 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 402 403 if (!chan) { 404 dev_err(uap->port.dev, "no RX DMA channel!\n"); 405 return; 406 } 407 } 408 409 if (chan) { 410 struct dma_slave_config rx_conf = { 411 .src_addr = uap->port.mapbase + 412 pl011_reg_to_offset(uap, REG_DR), 413 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 414 .direction = DMA_DEV_TO_MEM, 415 .src_maxburst = uap->fifosize >> 2, 416 .device_fc = false, 417 }; 418 struct dma_slave_caps caps; 419 420 /* 421 * Some DMA controllers provide information on their capabilities. 422 * If the controller does, check for suitable residue processing 423 * otherwise assime all is well. 424 */ 425 if (0 == dma_get_slave_caps(chan, &caps)) { 426 if (caps.residue_granularity == 427 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 428 dma_release_channel(chan); 429 dev_info(uap->port.dev, 430 "RX DMA disabled - no residue processing\n"); 431 return; 432 } 433 } 434 dmaengine_slave_config(chan, &rx_conf); 435 uap->dmarx.chan = chan; 436 437 uap->dmarx.auto_poll_rate = false; 438 if (plat && plat->dma_rx_poll_enable) { 439 /* Set poll rate if specified. */ 440 if (plat->dma_rx_poll_rate) { 441 uap->dmarx.auto_poll_rate = false; 442 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 443 } else { 444 /* 445 * 100 ms defaults to poll rate if not 446 * specified. This will be adjusted with 447 * the baud rate at set_termios. 448 */ 449 uap->dmarx.auto_poll_rate = true; 450 uap->dmarx.poll_rate = 100; 451 } 452 /* 3 secs defaults poll_timeout if not specified. */ 453 if (plat->dma_rx_poll_timeout) 454 uap->dmarx.poll_timeout = 455 plat->dma_rx_poll_timeout; 456 else 457 uap->dmarx.poll_timeout = 3000; 458 } else if (!plat && dev->of_node) { 459 uap->dmarx.auto_poll_rate = of_property_read_bool( 460 dev->of_node, "auto-poll"); 461 if (uap->dmarx.auto_poll_rate) { 462 u32 x; 463 464 if (0 == of_property_read_u32(dev->of_node, 465 "poll-rate-ms", &x)) 466 uap->dmarx.poll_rate = x; 467 else 468 uap->dmarx.poll_rate = 100; 469 if (0 == of_property_read_u32(dev->of_node, 470 "poll-timeout-ms", &x)) 471 uap->dmarx.poll_timeout = x; 472 else 473 uap->dmarx.poll_timeout = 3000; 474 } 475 } 476 dev_info(uap->port.dev, "DMA channel RX %s\n", 477 dma_chan_name(uap->dmarx.chan)); 478 } 479 } 480 481 static void pl011_dma_remove(struct uart_amba_port *uap) 482 { 483 if (uap->dmatx.chan) 484 dma_release_channel(uap->dmatx.chan); 485 if (uap->dmarx.chan) 486 dma_release_channel(uap->dmarx.chan); 487 } 488 489 /* Forward declare these for the refill routine */ 490 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 491 static void pl011_start_tx_pio(struct uart_amba_port *uap); 492 493 /* 494 * The current DMA TX buffer has been sent. 495 * Try to queue up another DMA buffer. 496 */ 497 static void pl011_dma_tx_callback(void *data) 498 { 499 struct uart_amba_port *uap = data; 500 struct pl011_dmatx_data *dmatx = &uap->dmatx; 501 unsigned long flags; 502 u16 dmacr; 503 504 spin_lock_irqsave(&uap->port.lock, flags); 505 if (uap->dmatx.queued) 506 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 507 DMA_TO_DEVICE); 508 509 dmacr = uap->dmacr; 510 uap->dmacr = dmacr & ~UART011_TXDMAE; 511 pl011_write(uap->dmacr, uap, REG_DMACR); 512 513 /* 514 * If TX DMA was disabled, it means that we've stopped the DMA for 515 * some reason (eg, XOFF received, or we want to send an X-char.) 516 * 517 * Note: we need to be careful here of a potential race between DMA 518 * and the rest of the driver - if the driver disables TX DMA while 519 * a TX buffer completing, we must update the tx queued status to 520 * get further refills (hence we check dmacr). 521 */ 522 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 523 uart_circ_empty(&uap->port.state->xmit)) { 524 uap->dmatx.queued = false; 525 spin_unlock_irqrestore(&uap->port.lock, flags); 526 return; 527 } 528 529 if (pl011_dma_tx_refill(uap) <= 0) 530 /* 531 * We didn't queue a DMA buffer for some reason, but we 532 * have data pending to be sent. Re-enable the TX IRQ. 533 */ 534 pl011_start_tx_pio(uap); 535 536 spin_unlock_irqrestore(&uap->port.lock, flags); 537 } 538 539 /* 540 * Try to refill the TX DMA buffer. 541 * Locking: called with port lock held and IRQs disabled. 542 * Returns: 543 * 1 if we queued up a TX DMA buffer. 544 * 0 if we didn't want to handle this by DMA 545 * <0 on error 546 */ 547 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 548 { 549 struct pl011_dmatx_data *dmatx = &uap->dmatx; 550 struct dma_chan *chan = dmatx->chan; 551 struct dma_device *dma_dev = chan->device; 552 struct dma_async_tx_descriptor *desc; 553 struct circ_buf *xmit = &uap->port.state->xmit; 554 unsigned int count; 555 556 /* 557 * Try to avoid the overhead involved in using DMA if the 558 * transaction fits in the first half of the FIFO, by using 559 * the standard interrupt handling. This ensures that we 560 * issue a uart_write_wakeup() at the appropriate time. 561 */ 562 count = uart_circ_chars_pending(xmit); 563 if (count < (uap->fifosize >> 1)) { 564 uap->dmatx.queued = false; 565 return 0; 566 } 567 568 /* 569 * Bodge: don't send the last character by DMA, as this 570 * will prevent XON from notifying us to restart DMA. 571 */ 572 count -= 1; 573 574 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 575 if (count > PL011_DMA_BUFFER_SIZE) 576 count = PL011_DMA_BUFFER_SIZE; 577 578 if (xmit->tail < xmit->head) 579 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 580 else { 581 size_t first = UART_XMIT_SIZE - xmit->tail; 582 size_t second; 583 584 if (first > count) 585 first = count; 586 second = count - first; 587 588 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 589 if (second) 590 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 591 } 592 593 dmatx->sg.length = count; 594 595 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 596 uap->dmatx.queued = false; 597 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 598 return -EBUSY; 599 } 600 601 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 602 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 603 if (!desc) { 604 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 605 uap->dmatx.queued = false; 606 /* 607 * If DMA cannot be used right now, we complete this 608 * transaction via IRQ and let the TTY layer retry. 609 */ 610 dev_dbg(uap->port.dev, "TX DMA busy\n"); 611 return -EBUSY; 612 } 613 614 /* Some data to go along to the callback */ 615 desc->callback = pl011_dma_tx_callback; 616 desc->callback_param = uap; 617 618 /* All errors should happen at prepare time */ 619 dmaengine_submit(desc); 620 621 /* Fire the DMA transaction */ 622 dma_dev->device_issue_pending(chan); 623 624 uap->dmacr |= UART011_TXDMAE; 625 pl011_write(uap->dmacr, uap, REG_DMACR); 626 uap->dmatx.queued = true; 627 628 /* 629 * Now we know that DMA will fire, so advance the ring buffer 630 * with the stuff we just dispatched. 631 */ 632 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 633 uap->port.icount.tx += count; 634 635 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 636 uart_write_wakeup(&uap->port); 637 638 return 1; 639 } 640 641 /* 642 * We received a transmit interrupt without a pending X-char but with 643 * pending characters. 644 * Locking: called with port lock held and IRQs disabled. 645 * Returns: 646 * false if we want to use PIO to transmit 647 * true if we queued a DMA buffer 648 */ 649 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 650 { 651 if (!uap->using_tx_dma) 652 return false; 653 654 /* 655 * If we already have a TX buffer queued, but received a 656 * TX interrupt, it will be because we've just sent an X-char. 657 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 658 */ 659 if (uap->dmatx.queued) { 660 uap->dmacr |= UART011_TXDMAE; 661 pl011_write(uap->dmacr, uap, REG_DMACR); 662 uap->im &= ~UART011_TXIM; 663 pl011_write(uap->im, uap, REG_IMSC); 664 return true; 665 } 666 667 /* 668 * We don't have a TX buffer queued, so try to queue one. 669 * If we successfully queued a buffer, mask the TX IRQ. 670 */ 671 if (pl011_dma_tx_refill(uap) > 0) { 672 uap->im &= ~UART011_TXIM; 673 pl011_write(uap->im, uap, REG_IMSC); 674 return true; 675 } 676 return false; 677 } 678 679 /* 680 * Stop the DMA transmit (eg, due to received XOFF). 681 * Locking: called with port lock held and IRQs disabled. 682 */ 683 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 684 { 685 if (uap->dmatx.queued) { 686 uap->dmacr &= ~UART011_TXDMAE; 687 pl011_write(uap->dmacr, uap, REG_DMACR); 688 } 689 } 690 691 /* 692 * Try to start a DMA transmit, or in the case of an XON/OFF 693 * character queued for send, try to get that character out ASAP. 694 * Locking: called with port lock held and IRQs disabled. 695 * Returns: 696 * false if we want the TX IRQ to be enabled 697 * true if we have a buffer queued 698 */ 699 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 700 { 701 u16 dmacr; 702 703 if (!uap->using_tx_dma) 704 return false; 705 706 if (!uap->port.x_char) { 707 /* no X-char, try to push chars out in DMA mode */ 708 bool ret = true; 709 710 if (!uap->dmatx.queued) { 711 if (pl011_dma_tx_refill(uap) > 0) { 712 uap->im &= ~UART011_TXIM; 713 pl011_write(uap->im, uap, REG_IMSC); 714 } else 715 ret = false; 716 } else if (!(uap->dmacr & UART011_TXDMAE)) { 717 uap->dmacr |= UART011_TXDMAE; 718 pl011_write(uap->dmacr, uap, REG_DMACR); 719 } 720 return ret; 721 } 722 723 /* 724 * We have an X-char to send. Disable DMA to prevent it loading 725 * the TX fifo, and then see if we can stuff it into the FIFO. 726 */ 727 dmacr = uap->dmacr; 728 uap->dmacr &= ~UART011_TXDMAE; 729 pl011_write(uap->dmacr, uap, REG_DMACR); 730 731 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 732 /* 733 * No space in the FIFO, so enable the transmit interrupt 734 * so we know when there is space. Note that once we've 735 * loaded the character, we should just re-enable DMA. 736 */ 737 return false; 738 } 739 740 pl011_write(uap->port.x_char, uap, REG_DR); 741 uap->port.icount.tx++; 742 uap->port.x_char = 0; 743 744 /* Success - restore the DMA state */ 745 uap->dmacr = dmacr; 746 pl011_write(dmacr, uap, REG_DMACR); 747 748 return true; 749 } 750 751 /* 752 * Flush the transmit buffer. 753 * Locking: called with port lock held and IRQs disabled. 754 */ 755 static void pl011_dma_flush_buffer(struct uart_port *port) 756 __releases(&uap->port.lock) 757 __acquires(&uap->port.lock) 758 { 759 struct uart_amba_port *uap = 760 container_of(port, struct uart_amba_port, port); 761 762 if (!uap->using_tx_dma) 763 return; 764 765 /* Avoid deadlock with the DMA engine callback */ 766 spin_unlock(&uap->port.lock); 767 dmaengine_terminate_all(uap->dmatx.chan); 768 spin_lock(&uap->port.lock); 769 if (uap->dmatx.queued) { 770 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 771 DMA_TO_DEVICE); 772 uap->dmatx.queued = false; 773 uap->dmacr &= ~UART011_TXDMAE; 774 pl011_write(uap->dmacr, uap, REG_DMACR); 775 } 776 } 777 778 static void pl011_dma_rx_callback(void *data); 779 780 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 781 { 782 struct dma_chan *rxchan = uap->dmarx.chan; 783 struct pl011_dmarx_data *dmarx = &uap->dmarx; 784 struct dma_async_tx_descriptor *desc; 785 struct pl011_sgbuf *sgbuf; 786 787 if (!rxchan) 788 return -EIO; 789 790 /* Start the RX DMA job */ 791 sgbuf = uap->dmarx.use_buf_b ? 792 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 793 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 794 DMA_DEV_TO_MEM, 795 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 796 /* 797 * If the DMA engine is busy and cannot prepare a 798 * channel, no big deal, the driver will fall back 799 * to interrupt mode as a result of this error code. 800 */ 801 if (!desc) { 802 uap->dmarx.running = false; 803 dmaengine_terminate_all(rxchan); 804 return -EBUSY; 805 } 806 807 /* Some data to go along to the callback */ 808 desc->callback = pl011_dma_rx_callback; 809 desc->callback_param = uap; 810 dmarx->cookie = dmaengine_submit(desc); 811 dma_async_issue_pending(rxchan); 812 813 uap->dmacr |= UART011_RXDMAE; 814 pl011_write(uap->dmacr, uap, REG_DMACR); 815 uap->dmarx.running = true; 816 817 uap->im &= ~UART011_RXIM; 818 pl011_write(uap->im, uap, REG_IMSC); 819 820 return 0; 821 } 822 823 /* 824 * This is called when either the DMA job is complete, or 825 * the FIFO timeout interrupt occurred. This must be called 826 * with the port spinlock uap->port.lock held. 827 */ 828 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 829 u32 pending, bool use_buf_b, 830 bool readfifo) 831 { 832 struct tty_port *port = &uap->port.state->port; 833 struct pl011_sgbuf *sgbuf = use_buf_b ? 834 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 835 int dma_count = 0; 836 u32 fifotaken = 0; /* only used for vdbg() */ 837 838 struct pl011_dmarx_data *dmarx = &uap->dmarx; 839 int dmataken = 0; 840 841 if (uap->dmarx.poll_rate) { 842 /* The data can be taken by polling */ 843 dmataken = sgbuf->sg.length - dmarx->last_residue; 844 /* Recalculate the pending size */ 845 if (pending >= dmataken) 846 pending -= dmataken; 847 } 848 849 /* Pick the remain data from the DMA */ 850 if (pending) { 851 852 /* 853 * First take all chars in the DMA pipe, then look in the FIFO. 854 * Note that tty_insert_flip_buf() tries to take as many chars 855 * as it can. 856 */ 857 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 858 pending); 859 860 uap->port.icount.rx += dma_count; 861 if (dma_count < pending) 862 dev_warn(uap->port.dev, 863 "couldn't insert all characters (TTY is full?)\n"); 864 } 865 866 /* Reset the last_residue for Rx DMA poll */ 867 if (uap->dmarx.poll_rate) 868 dmarx->last_residue = sgbuf->sg.length; 869 870 /* 871 * Only continue with trying to read the FIFO if all DMA chars have 872 * been taken first. 873 */ 874 if (dma_count == pending && readfifo) { 875 /* Clear any error flags */ 876 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 877 UART011_FEIS, uap, REG_ICR); 878 879 /* 880 * If we read all the DMA'd characters, and we had an 881 * incomplete buffer, that could be due to an rx error, or 882 * maybe we just timed out. Read any pending chars and check 883 * the error status. 884 * 885 * Error conditions will only occur in the FIFO, these will 886 * trigger an immediate interrupt and stop the DMA job, so we 887 * will always find the error in the FIFO, never in the DMA 888 * buffer. 889 */ 890 fifotaken = pl011_fifo_to_tty(uap); 891 } 892 893 spin_unlock(&uap->port.lock); 894 dev_vdbg(uap->port.dev, 895 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 896 dma_count, fifotaken); 897 tty_flip_buffer_push(port); 898 spin_lock(&uap->port.lock); 899 } 900 901 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 902 { 903 struct pl011_dmarx_data *dmarx = &uap->dmarx; 904 struct dma_chan *rxchan = dmarx->chan; 905 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 906 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 907 size_t pending; 908 struct dma_tx_state state; 909 enum dma_status dmastat; 910 911 /* 912 * Pause the transfer so we can trust the current counter, 913 * do this before we pause the PL011 block, else we may 914 * overflow the FIFO. 915 */ 916 if (dmaengine_pause(rxchan)) 917 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 918 dmastat = rxchan->device->device_tx_status(rxchan, 919 dmarx->cookie, &state); 920 if (dmastat != DMA_PAUSED) 921 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 922 923 /* Disable RX DMA - incoming data will wait in the FIFO */ 924 uap->dmacr &= ~UART011_RXDMAE; 925 pl011_write(uap->dmacr, uap, REG_DMACR); 926 uap->dmarx.running = false; 927 928 pending = sgbuf->sg.length - state.residue; 929 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 930 /* Then we terminate the transfer - we now know our residue */ 931 dmaengine_terminate_all(rxchan); 932 933 /* 934 * This will take the chars we have so far and insert 935 * into the framework. 936 */ 937 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 938 939 /* Switch buffer & re-trigger DMA job */ 940 dmarx->use_buf_b = !dmarx->use_buf_b; 941 if (pl011_dma_rx_trigger_dma(uap)) { 942 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 943 "fall back to interrupt mode\n"); 944 uap->im |= UART011_RXIM; 945 pl011_write(uap->im, uap, REG_IMSC); 946 } 947 } 948 949 static void pl011_dma_rx_callback(void *data) 950 { 951 struct uart_amba_port *uap = data; 952 struct pl011_dmarx_data *dmarx = &uap->dmarx; 953 struct dma_chan *rxchan = dmarx->chan; 954 bool lastbuf = dmarx->use_buf_b; 955 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 956 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 957 size_t pending; 958 struct dma_tx_state state; 959 int ret; 960 961 /* 962 * This completion interrupt occurs typically when the 963 * RX buffer is totally stuffed but no timeout has yet 964 * occurred. When that happens, we just want the RX 965 * routine to flush out the secondary DMA buffer while 966 * we immediately trigger the next DMA job. 967 */ 968 spin_lock_irq(&uap->port.lock); 969 /* 970 * Rx data can be taken by the UART interrupts during 971 * the DMA irq handler. So we check the residue here. 972 */ 973 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 974 pending = sgbuf->sg.length - state.residue; 975 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 976 /* Then we terminate the transfer - we now know our residue */ 977 dmaengine_terminate_all(rxchan); 978 979 uap->dmarx.running = false; 980 dmarx->use_buf_b = !lastbuf; 981 ret = pl011_dma_rx_trigger_dma(uap); 982 983 pl011_dma_rx_chars(uap, pending, lastbuf, false); 984 spin_unlock_irq(&uap->port.lock); 985 /* 986 * Do this check after we picked the DMA chars so we don't 987 * get some IRQ immediately from RX. 988 */ 989 if (ret) { 990 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 991 "fall back to interrupt mode\n"); 992 uap->im |= UART011_RXIM; 993 pl011_write(uap->im, uap, REG_IMSC); 994 } 995 } 996 997 /* 998 * Stop accepting received characters, when we're shutting down or 999 * suspending this port. 1000 * Locking: called with port lock held and IRQs disabled. 1001 */ 1002 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1003 { 1004 /* FIXME. Just disable the DMA enable */ 1005 uap->dmacr &= ~UART011_RXDMAE; 1006 pl011_write(uap->dmacr, uap, REG_DMACR); 1007 } 1008 1009 /* 1010 * Timer handler for Rx DMA polling. 1011 * Every polling, It checks the residue in the dma buffer and transfer 1012 * data to the tty. Also, last_residue is updated for the next polling. 1013 */ 1014 static void pl011_dma_rx_poll(unsigned long args) 1015 { 1016 struct uart_amba_port *uap = (struct uart_amba_port *)args; 1017 struct tty_port *port = &uap->port.state->port; 1018 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1019 struct dma_chan *rxchan = uap->dmarx.chan; 1020 unsigned long flags = 0; 1021 unsigned int dmataken = 0; 1022 unsigned int size = 0; 1023 struct pl011_sgbuf *sgbuf; 1024 int dma_count; 1025 struct dma_tx_state state; 1026 1027 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1028 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1029 if (likely(state.residue < dmarx->last_residue)) { 1030 dmataken = sgbuf->sg.length - dmarx->last_residue; 1031 size = dmarx->last_residue - state.residue; 1032 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1033 size); 1034 if (dma_count == size) 1035 dmarx->last_residue = state.residue; 1036 dmarx->last_jiffies = jiffies; 1037 } 1038 tty_flip_buffer_push(port); 1039 1040 /* 1041 * If no data is received in poll_timeout, the driver will fall back 1042 * to interrupt mode. We will retrigger DMA at the first interrupt. 1043 */ 1044 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1045 > uap->dmarx.poll_timeout) { 1046 1047 spin_lock_irqsave(&uap->port.lock, flags); 1048 pl011_dma_rx_stop(uap); 1049 uap->im |= UART011_RXIM; 1050 pl011_write(uap->im, uap, REG_IMSC); 1051 spin_unlock_irqrestore(&uap->port.lock, flags); 1052 1053 uap->dmarx.running = false; 1054 dmaengine_terminate_all(rxchan); 1055 del_timer(&uap->dmarx.timer); 1056 } else { 1057 mod_timer(&uap->dmarx.timer, 1058 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1059 } 1060 } 1061 1062 static void pl011_dma_startup(struct uart_amba_port *uap) 1063 { 1064 int ret; 1065 1066 if (!uap->dma_probed) 1067 pl011_dma_probe(uap); 1068 1069 if (!uap->dmatx.chan) 1070 return; 1071 1072 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1073 if (!uap->dmatx.buf) { 1074 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1075 uap->port.fifosize = uap->fifosize; 1076 return; 1077 } 1078 1079 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1080 1081 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1082 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1083 uap->using_tx_dma = true; 1084 1085 if (!uap->dmarx.chan) 1086 goto skip_rx; 1087 1088 /* Allocate and map DMA RX buffers */ 1089 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1090 DMA_FROM_DEVICE); 1091 if (ret) { 1092 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1093 "RX buffer A", ret); 1094 goto skip_rx; 1095 } 1096 1097 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1098 DMA_FROM_DEVICE); 1099 if (ret) { 1100 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1101 "RX buffer B", ret); 1102 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1103 DMA_FROM_DEVICE); 1104 goto skip_rx; 1105 } 1106 1107 uap->using_rx_dma = true; 1108 1109 skip_rx: 1110 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1111 uap->dmacr |= UART011_DMAONERR; 1112 pl011_write(uap->dmacr, uap, REG_DMACR); 1113 1114 /* 1115 * ST Micro variants has some specific dma burst threshold 1116 * compensation. Set this to 16 bytes, so burst will only 1117 * be issued above/below 16 bytes. 1118 */ 1119 if (uap->vendor->dma_threshold) 1120 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1121 uap, REG_ST_DMAWM); 1122 1123 if (uap->using_rx_dma) { 1124 if (pl011_dma_rx_trigger_dma(uap)) 1125 dev_dbg(uap->port.dev, "could not trigger initial " 1126 "RX DMA job, fall back to interrupt mode\n"); 1127 if (uap->dmarx.poll_rate) { 1128 init_timer(&(uap->dmarx.timer)); 1129 uap->dmarx.timer.function = pl011_dma_rx_poll; 1130 uap->dmarx.timer.data = (unsigned long)uap; 1131 mod_timer(&uap->dmarx.timer, 1132 jiffies + 1133 msecs_to_jiffies(uap->dmarx.poll_rate)); 1134 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1135 uap->dmarx.last_jiffies = jiffies; 1136 } 1137 } 1138 } 1139 1140 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1141 { 1142 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1143 return; 1144 1145 /* Disable RX and TX DMA */ 1146 while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY) 1147 barrier(); 1148 1149 spin_lock_irq(&uap->port.lock); 1150 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1151 pl011_write(uap->dmacr, uap, REG_DMACR); 1152 spin_unlock_irq(&uap->port.lock); 1153 1154 if (uap->using_tx_dma) { 1155 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1156 dmaengine_terminate_all(uap->dmatx.chan); 1157 if (uap->dmatx.queued) { 1158 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1159 DMA_TO_DEVICE); 1160 uap->dmatx.queued = false; 1161 } 1162 1163 kfree(uap->dmatx.buf); 1164 uap->using_tx_dma = false; 1165 } 1166 1167 if (uap->using_rx_dma) { 1168 dmaengine_terminate_all(uap->dmarx.chan); 1169 /* Clean up the RX DMA */ 1170 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1171 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1172 if (uap->dmarx.poll_rate) 1173 del_timer_sync(&uap->dmarx.timer); 1174 uap->using_rx_dma = false; 1175 } 1176 } 1177 1178 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1179 { 1180 return uap->using_rx_dma; 1181 } 1182 1183 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1184 { 1185 return uap->using_rx_dma && uap->dmarx.running; 1186 } 1187 1188 #else 1189 /* Blank functions if the DMA engine is not available */ 1190 static inline void pl011_dma_probe(struct uart_amba_port *uap) 1191 { 1192 } 1193 1194 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1195 { 1196 } 1197 1198 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1199 { 1200 } 1201 1202 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1203 { 1204 } 1205 1206 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1207 { 1208 return false; 1209 } 1210 1211 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1212 { 1213 } 1214 1215 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1216 { 1217 return false; 1218 } 1219 1220 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1221 { 1222 } 1223 1224 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1225 { 1226 } 1227 1228 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1229 { 1230 return -EIO; 1231 } 1232 1233 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1234 { 1235 return false; 1236 } 1237 1238 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1239 { 1240 return false; 1241 } 1242 1243 #define pl011_dma_flush_buffer NULL 1244 #endif 1245 1246 static void pl011_stop_tx(struct uart_port *port) 1247 { 1248 struct uart_amba_port *uap = 1249 container_of(port, struct uart_amba_port, port); 1250 1251 uap->im &= ~UART011_TXIM; 1252 pl011_write(uap->im, uap, REG_IMSC); 1253 pl011_dma_tx_stop(uap); 1254 } 1255 1256 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1257 1258 /* Start TX with programmed I/O only (no DMA) */ 1259 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1260 { 1261 uap->im |= UART011_TXIM; 1262 pl011_write(uap->im, uap, REG_IMSC); 1263 pl011_tx_chars(uap, false); 1264 } 1265 1266 static void pl011_start_tx(struct uart_port *port) 1267 { 1268 struct uart_amba_port *uap = 1269 container_of(port, struct uart_amba_port, port); 1270 1271 if (!pl011_dma_tx_start(uap)) 1272 pl011_start_tx_pio(uap); 1273 } 1274 1275 static void pl011_stop_rx(struct uart_port *port) 1276 { 1277 struct uart_amba_port *uap = 1278 container_of(port, struct uart_amba_port, port); 1279 1280 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1281 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1282 pl011_write(uap->im, uap, REG_IMSC); 1283 1284 pl011_dma_rx_stop(uap); 1285 } 1286 1287 static void pl011_enable_ms(struct uart_port *port) 1288 { 1289 struct uart_amba_port *uap = 1290 container_of(port, struct uart_amba_port, port); 1291 1292 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1293 pl011_write(uap->im, uap, REG_IMSC); 1294 } 1295 1296 static void pl011_rx_chars(struct uart_amba_port *uap) 1297 __releases(&uap->port.lock) 1298 __acquires(&uap->port.lock) 1299 { 1300 pl011_fifo_to_tty(uap); 1301 1302 spin_unlock(&uap->port.lock); 1303 tty_flip_buffer_push(&uap->port.state->port); 1304 /* 1305 * If we were temporarily out of DMA mode for a while, 1306 * attempt to switch back to DMA mode again. 1307 */ 1308 if (pl011_dma_rx_available(uap)) { 1309 if (pl011_dma_rx_trigger_dma(uap)) { 1310 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1311 "fall back to interrupt mode again\n"); 1312 uap->im |= UART011_RXIM; 1313 pl011_write(uap->im, uap, REG_IMSC); 1314 } else { 1315 #ifdef CONFIG_DMA_ENGINE 1316 /* Start Rx DMA poll */ 1317 if (uap->dmarx.poll_rate) { 1318 uap->dmarx.last_jiffies = jiffies; 1319 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1320 mod_timer(&uap->dmarx.timer, 1321 jiffies + 1322 msecs_to_jiffies(uap->dmarx.poll_rate)); 1323 } 1324 #endif 1325 } 1326 } 1327 spin_lock(&uap->port.lock); 1328 } 1329 1330 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1331 bool from_irq) 1332 { 1333 if (unlikely(!from_irq) && 1334 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1335 return false; /* unable to transmit character */ 1336 1337 pl011_write(c, uap, REG_DR); 1338 uap->port.icount.tx++; 1339 1340 return true; 1341 } 1342 1343 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1344 { 1345 struct circ_buf *xmit = &uap->port.state->xmit; 1346 int count = uap->fifosize >> 1; 1347 1348 if (uap->port.x_char) { 1349 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1350 return; 1351 uap->port.x_char = 0; 1352 --count; 1353 } 1354 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1355 pl011_stop_tx(&uap->port); 1356 return; 1357 } 1358 1359 /* If we are using DMA mode, try to send some characters. */ 1360 if (pl011_dma_tx_irq(uap)) 1361 return; 1362 1363 do { 1364 if (likely(from_irq) && count-- == 0) 1365 break; 1366 1367 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1368 break; 1369 1370 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1371 } while (!uart_circ_empty(xmit)); 1372 1373 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1374 uart_write_wakeup(&uap->port); 1375 1376 if (uart_circ_empty(xmit)) 1377 pl011_stop_tx(&uap->port); 1378 } 1379 1380 static void pl011_modem_status(struct uart_amba_port *uap) 1381 { 1382 unsigned int status, delta; 1383 1384 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1385 1386 delta = status ^ uap->old_status; 1387 uap->old_status = status; 1388 1389 if (!delta) 1390 return; 1391 1392 if (delta & UART01x_FR_DCD) 1393 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1394 1395 if (delta & UART01x_FR_DSR) 1396 uap->port.icount.dsr++; 1397 1398 if (delta & UART01x_FR_CTS) 1399 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 1400 1401 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1402 } 1403 1404 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1405 { 1406 unsigned int dummy_read; 1407 1408 if (!uap->vendor->cts_event_workaround) 1409 return; 1410 1411 /* workaround to make sure that all bits are unlocked.. */ 1412 pl011_write(0x00, uap, REG_ICR); 1413 1414 /* 1415 * WA: introduce 26ns(1 uart clk) delay before W1C; 1416 * single apb access will incur 2 pclk(133.12Mhz) delay, 1417 * so add 2 dummy reads 1418 */ 1419 dummy_read = pl011_read(uap, REG_ICR); 1420 dummy_read = pl011_read(uap, REG_ICR); 1421 } 1422 1423 static irqreturn_t pl011_int(int irq, void *dev_id) 1424 { 1425 struct uart_amba_port *uap = dev_id; 1426 unsigned long flags; 1427 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1428 u16 imsc; 1429 int handled = 0; 1430 1431 spin_lock_irqsave(&uap->port.lock, flags); 1432 imsc = pl011_read(uap, REG_IMSC); 1433 status = pl011_read(uap, REG_RIS) & imsc; 1434 if (status) { 1435 do { 1436 check_apply_cts_event_workaround(uap); 1437 1438 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1439 UART011_RXIS), 1440 uap, REG_ICR); 1441 1442 if (status & (UART011_RTIS|UART011_RXIS)) { 1443 if (pl011_dma_rx_running(uap)) 1444 pl011_dma_rx_irq(uap); 1445 else 1446 pl011_rx_chars(uap); 1447 } 1448 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1449 UART011_CTSMIS|UART011_RIMIS)) 1450 pl011_modem_status(uap); 1451 if (status & UART011_TXIS) 1452 pl011_tx_chars(uap, true); 1453 1454 if (pass_counter-- == 0) 1455 break; 1456 1457 status = pl011_read(uap, REG_RIS) & imsc; 1458 } while (status != 0); 1459 handled = 1; 1460 } 1461 1462 spin_unlock_irqrestore(&uap->port.lock, flags); 1463 1464 return IRQ_RETVAL(handled); 1465 } 1466 1467 static unsigned int pl011_tx_empty(struct uart_port *port) 1468 { 1469 struct uart_amba_port *uap = 1470 container_of(port, struct uart_amba_port, port); 1471 unsigned int status = pl011_read(uap, REG_FR); 1472 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; 1473 } 1474 1475 static unsigned int pl011_get_mctrl(struct uart_port *port) 1476 { 1477 struct uart_amba_port *uap = 1478 container_of(port, struct uart_amba_port, port); 1479 unsigned int result = 0; 1480 unsigned int status = pl011_read(uap, REG_FR); 1481 1482 #define TIOCMBIT(uartbit, tiocmbit) \ 1483 if (status & uartbit) \ 1484 result |= tiocmbit 1485 1486 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1487 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); 1488 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); 1489 TIOCMBIT(UART011_FR_RI, TIOCM_RNG); 1490 #undef TIOCMBIT 1491 return result; 1492 } 1493 1494 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1495 { 1496 struct uart_amba_port *uap = 1497 container_of(port, struct uart_amba_port, port); 1498 unsigned int cr; 1499 1500 cr = pl011_read(uap, REG_CR); 1501 1502 #define TIOCMBIT(tiocmbit, uartbit) \ 1503 if (mctrl & tiocmbit) \ 1504 cr |= uartbit; \ 1505 else \ 1506 cr &= ~uartbit 1507 1508 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1509 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1510 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1511 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1512 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1513 1514 if (uap->autorts) { 1515 /* We need to disable auto-RTS if we want to turn RTS off */ 1516 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1517 } 1518 #undef TIOCMBIT 1519 1520 pl011_write(cr, uap, REG_CR); 1521 } 1522 1523 static void pl011_break_ctl(struct uart_port *port, int break_state) 1524 { 1525 struct uart_amba_port *uap = 1526 container_of(port, struct uart_amba_port, port); 1527 unsigned long flags; 1528 unsigned int lcr_h; 1529 1530 spin_lock_irqsave(&uap->port.lock, flags); 1531 lcr_h = pl011_read(uap, REG_LCRH_TX); 1532 if (break_state == -1) 1533 lcr_h |= UART01x_LCRH_BRK; 1534 else 1535 lcr_h &= ~UART01x_LCRH_BRK; 1536 pl011_write(lcr_h, uap, REG_LCRH_TX); 1537 spin_unlock_irqrestore(&uap->port.lock, flags); 1538 } 1539 1540 #ifdef CONFIG_CONSOLE_POLL 1541 1542 static void pl011_quiesce_irqs(struct uart_port *port) 1543 { 1544 struct uart_amba_port *uap = 1545 container_of(port, struct uart_amba_port, port); 1546 1547 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1548 /* 1549 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1550 * we simply mask it. start_tx() will unmask it. 1551 * 1552 * Note we can race with start_tx(), and if the race happens, the 1553 * polling user might get another interrupt just after we clear it. 1554 * But it should be OK and can happen even w/o the race, e.g. 1555 * controller immediately got some new data and raised the IRQ. 1556 * 1557 * And whoever uses polling routines assumes that it manages the device 1558 * (including tx queue), so we're also fine with start_tx()'s caller 1559 * side. 1560 */ 1561 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1562 REG_IMSC); 1563 } 1564 1565 static int pl011_get_poll_char(struct uart_port *port) 1566 { 1567 struct uart_amba_port *uap = 1568 container_of(port, struct uart_amba_port, port); 1569 unsigned int status; 1570 1571 /* 1572 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1573 * debugger. 1574 */ 1575 pl011_quiesce_irqs(port); 1576 1577 status = pl011_read(uap, REG_FR); 1578 if (status & UART01x_FR_RXFE) 1579 return NO_POLL_CHAR; 1580 1581 return pl011_read(uap, REG_DR); 1582 } 1583 1584 static void pl011_put_poll_char(struct uart_port *port, 1585 unsigned char ch) 1586 { 1587 struct uart_amba_port *uap = 1588 container_of(port, struct uart_amba_port, port); 1589 1590 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1591 barrier(); 1592 1593 pl011_write(ch, uap, REG_DR); 1594 } 1595 1596 #endif /* CONFIG_CONSOLE_POLL */ 1597 1598 static int pl011_hwinit(struct uart_port *port) 1599 { 1600 struct uart_amba_port *uap = 1601 container_of(port, struct uart_amba_port, port); 1602 int retval; 1603 1604 /* Optionaly enable pins to be muxed in and configured */ 1605 pinctrl_pm_select_default_state(port->dev); 1606 1607 /* 1608 * Try to enable the clock producer. 1609 */ 1610 retval = clk_prepare_enable(uap->clk); 1611 if (retval) 1612 return retval; 1613 1614 uap->port.uartclk = clk_get_rate(uap->clk); 1615 1616 /* Clear pending error and receive interrupts */ 1617 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1618 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1619 uap, REG_ICR); 1620 1621 /* 1622 * Save interrupts enable mask, and enable RX interrupts in case if 1623 * the interrupt is used for NMI entry. 1624 */ 1625 uap->im = pl011_read(uap, REG_IMSC); 1626 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1627 1628 if (dev_get_platdata(uap->port.dev)) { 1629 struct amba_pl011_data *plat; 1630 1631 plat = dev_get_platdata(uap->port.dev); 1632 if (plat->init) 1633 plat->init(); 1634 } 1635 return 0; 1636 } 1637 1638 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1639 { 1640 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1641 pl011_reg_to_offset(uap, REG_LCRH_TX); 1642 } 1643 1644 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1645 { 1646 pl011_write(lcr_h, uap, REG_LCRH_RX); 1647 if (pl011_split_lcrh(uap)) { 1648 int i; 1649 /* 1650 * Wait 10 PCLKs before writing LCRH_TX register, 1651 * to get this delay write read only register 10 times 1652 */ 1653 for (i = 0; i < 10; ++i) 1654 pl011_write(0xff, uap, REG_MIS); 1655 pl011_write(lcr_h, uap, REG_LCRH_TX); 1656 } 1657 } 1658 1659 static int pl011_allocate_irq(struct uart_amba_port *uap) 1660 { 1661 pl011_write(uap->im, uap, REG_IMSC); 1662 1663 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); 1664 } 1665 1666 /* 1667 * Enable interrupts, only timeouts when using DMA 1668 * if initial RX DMA job failed, start in interrupt mode 1669 * as well. 1670 */ 1671 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1672 { 1673 spin_lock_irq(&uap->port.lock); 1674 1675 /* Clear out any spuriously appearing RX interrupts */ 1676 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1677 uap->im = UART011_RTIM; 1678 if (!pl011_dma_rx_running(uap)) 1679 uap->im |= UART011_RXIM; 1680 pl011_write(uap->im, uap, REG_IMSC); 1681 spin_unlock_irq(&uap->port.lock); 1682 } 1683 1684 static int pl011_startup(struct uart_port *port) 1685 { 1686 struct uart_amba_port *uap = 1687 container_of(port, struct uart_amba_port, port); 1688 unsigned int cr; 1689 int retval; 1690 1691 retval = pl011_hwinit(port); 1692 if (retval) 1693 goto clk_dis; 1694 1695 retval = pl011_allocate_irq(uap); 1696 if (retval) 1697 goto clk_dis; 1698 1699 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1700 1701 spin_lock_irq(&uap->port.lock); 1702 1703 /* restore RTS and DTR */ 1704 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); 1705 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 1706 pl011_write(cr, uap, REG_CR); 1707 1708 spin_unlock_irq(&uap->port.lock); 1709 1710 /* 1711 * initialise the old status of the modem signals 1712 */ 1713 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1714 1715 /* Startup DMA */ 1716 pl011_dma_startup(uap); 1717 1718 pl011_enable_interrupts(uap); 1719 1720 return 0; 1721 1722 clk_dis: 1723 clk_disable_unprepare(uap->clk); 1724 return retval; 1725 } 1726 1727 static int sbsa_uart_startup(struct uart_port *port) 1728 { 1729 struct uart_amba_port *uap = 1730 container_of(port, struct uart_amba_port, port); 1731 int retval; 1732 1733 retval = pl011_hwinit(port); 1734 if (retval) 1735 return retval; 1736 1737 retval = pl011_allocate_irq(uap); 1738 if (retval) 1739 return retval; 1740 1741 /* The SBSA UART does not support any modem status lines. */ 1742 uap->old_status = 0; 1743 1744 pl011_enable_interrupts(uap); 1745 1746 return 0; 1747 } 1748 1749 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1750 unsigned int lcrh) 1751 { 1752 unsigned long val; 1753 1754 val = pl011_read(uap, lcrh); 1755 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1756 pl011_write(val, uap, lcrh); 1757 } 1758 1759 /* 1760 * disable the port. It should not disable RTS and DTR. 1761 * Also RTS and DTR state should be preserved to restore 1762 * it during startup(). 1763 */ 1764 static void pl011_disable_uart(struct uart_amba_port *uap) 1765 { 1766 unsigned int cr; 1767 1768 uap->autorts = false; 1769 spin_lock_irq(&uap->port.lock); 1770 cr = pl011_read(uap, REG_CR); 1771 uap->old_cr = cr; 1772 cr &= UART011_CR_RTS | UART011_CR_DTR; 1773 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1774 pl011_write(cr, uap, REG_CR); 1775 spin_unlock_irq(&uap->port.lock); 1776 1777 /* 1778 * disable break condition and fifos 1779 */ 1780 pl011_shutdown_channel(uap, REG_LCRH_RX); 1781 if (pl011_split_lcrh(uap)) 1782 pl011_shutdown_channel(uap, REG_LCRH_TX); 1783 } 1784 1785 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1786 { 1787 spin_lock_irq(&uap->port.lock); 1788 1789 /* mask all interrupts and clear all pending ones */ 1790 uap->im = 0; 1791 pl011_write(uap->im, uap, REG_IMSC); 1792 pl011_write(0xffff, uap, REG_ICR); 1793 1794 spin_unlock_irq(&uap->port.lock); 1795 } 1796 1797 static void pl011_shutdown(struct uart_port *port) 1798 { 1799 struct uart_amba_port *uap = 1800 container_of(port, struct uart_amba_port, port); 1801 1802 pl011_disable_interrupts(uap); 1803 1804 pl011_dma_shutdown(uap); 1805 1806 free_irq(uap->port.irq, uap); 1807 1808 pl011_disable_uart(uap); 1809 1810 /* 1811 * Shut down the clock producer 1812 */ 1813 clk_disable_unprepare(uap->clk); 1814 /* Optionally let pins go into sleep states */ 1815 pinctrl_pm_select_sleep_state(port->dev); 1816 1817 if (dev_get_platdata(uap->port.dev)) { 1818 struct amba_pl011_data *plat; 1819 1820 plat = dev_get_platdata(uap->port.dev); 1821 if (plat->exit) 1822 plat->exit(); 1823 } 1824 1825 if (uap->port.ops->flush_buffer) 1826 uap->port.ops->flush_buffer(port); 1827 } 1828 1829 static void sbsa_uart_shutdown(struct uart_port *port) 1830 { 1831 struct uart_amba_port *uap = 1832 container_of(port, struct uart_amba_port, port); 1833 1834 pl011_disable_interrupts(uap); 1835 1836 free_irq(uap->port.irq, uap); 1837 1838 if (uap->port.ops->flush_buffer) 1839 uap->port.ops->flush_buffer(port); 1840 } 1841 1842 static void 1843 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 1844 { 1845 port->read_status_mask = UART011_DR_OE | 255; 1846 if (termios->c_iflag & INPCK) 1847 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 1848 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1849 port->read_status_mask |= UART011_DR_BE; 1850 1851 /* 1852 * Characters to ignore 1853 */ 1854 port->ignore_status_mask = 0; 1855 if (termios->c_iflag & IGNPAR) 1856 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 1857 if (termios->c_iflag & IGNBRK) { 1858 port->ignore_status_mask |= UART011_DR_BE; 1859 /* 1860 * If we're ignoring parity and break indicators, 1861 * ignore overruns too (for real raw support). 1862 */ 1863 if (termios->c_iflag & IGNPAR) 1864 port->ignore_status_mask |= UART011_DR_OE; 1865 } 1866 1867 /* 1868 * Ignore all characters if CREAD is not set. 1869 */ 1870 if ((termios->c_cflag & CREAD) == 0) 1871 port->ignore_status_mask |= UART_DUMMY_DR_RX; 1872 } 1873 1874 static void 1875 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 1876 struct ktermios *old) 1877 { 1878 struct uart_amba_port *uap = 1879 container_of(port, struct uart_amba_port, port); 1880 unsigned int lcr_h, old_cr; 1881 unsigned long flags; 1882 unsigned int baud, quot, clkdiv; 1883 1884 if (uap->vendor->oversampling) 1885 clkdiv = 8; 1886 else 1887 clkdiv = 16; 1888 1889 /* 1890 * Ask the core to calculate the divisor for us. 1891 */ 1892 baud = uart_get_baud_rate(port, termios, old, 0, 1893 port->uartclk / clkdiv); 1894 #ifdef CONFIG_DMA_ENGINE 1895 /* 1896 * Adjust RX DMA polling rate with baud rate if not specified. 1897 */ 1898 if (uap->dmarx.auto_poll_rate) 1899 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 1900 #endif 1901 1902 if (baud > port->uartclk/16) 1903 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 1904 else 1905 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 1906 1907 switch (termios->c_cflag & CSIZE) { 1908 case CS5: 1909 lcr_h = UART01x_LCRH_WLEN_5; 1910 break; 1911 case CS6: 1912 lcr_h = UART01x_LCRH_WLEN_6; 1913 break; 1914 case CS7: 1915 lcr_h = UART01x_LCRH_WLEN_7; 1916 break; 1917 default: // CS8 1918 lcr_h = UART01x_LCRH_WLEN_8; 1919 break; 1920 } 1921 if (termios->c_cflag & CSTOPB) 1922 lcr_h |= UART01x_LCRH_STP2; 1923 if (termios->c_cflag & PARENB) { 1924 lcr_h |= UART01x_LCRH_PEN; 1925 if (!(termios->c_cflag & PARODD)) 1926 lcr_h |= UART01x_LCRH_EPS; 1927 } 1928 if (uap->fifosize > 1) 1929 lcr_h |= UART01x_LCRH_FEN; 1930 1931 spin_lock_irqsave(&port->lock, flags); 1932 1933 /* 1934 * Update the per-port timeout. 1935 */ 1936 uart_update_timeout(port, termios->c_cflag, baud); 1937 1938 pl011_setup_status_masks(port, termios); 1939 1940 if (UART_ENABLE_MS(port, termios->c_cflag)) 1941 pl011_enable_ms(port); 1942 1943 /* first, disable everything */ 1944 old_cr = pl011_read(uap, REG_CR); 1945 pl011_write(0, uap, REG_CR); 1946 1947 if (termios->c_cflag & CRTSCTS) { 1948 if (old_cr & UART011_CR_RTS) 1949 old_cr |= UART011_CR_RTSEN; 1950 1951 old_cr |= UART011_CR_CTSEN; 1952 uap->autorts = true; 1953 } else { 1954 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 1955 uap->autorts = false; 1956 } 1957 1958 if (uap->vendor->oversampling) { 1959 if (baud > port->uartclk / 16) 1960 old_cr |= ST_UART011_CR_OVSFACT; 1961 else 1962 old_cr &= ~ST_UART011_CR_OVSFACT; 1963 } 1964 1965 /* 1966 * Workaround for the ST Micro oversampling variants to 1967 * increase the bitrate slightly, by lowering the divisor, 1968 * to avoid delayed sampling of start bit at high speeds, 1969 * else we see data corruption. 1970 */ 1971 if (uap->vendor->oversampling) { 1972 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 1973 quot -= 1; 1974 else if ((baud > 3250000) && (quot > 2)) 1975 quot -= 2; 1976 } 1977 /* Set baud rate */ 1978 pl011_write(quot & 0x3f, uap, REG_FBRD); 1979 pl011_write(quot >> 6, uap, REG_IBRD); 1980 1981 /* 1982 * ----------v----------v----------v----------v----- 1983 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 1984 * REG_FBRD & REG_IBRD. 1985 * ----------^----------^----------^----------^----- 1986 */ 1987 pl011_write_lcr_h(uap, lcr_h); 1988 pl011_write(old_cr, uap, REG_CR); 1989 1990 spin_unlock_irqrestore(&port->lock, flags); 1991 } 1992 1993 static void 1994 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 1995 struct ktermios *old) 1996 { 1997 struct uart_amba_port *uap = 1998 container_of(port, struct uart_amba_port, port); 1999 unsigned long flags; 2000 2001 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2002 2003 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2004 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2005 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2006 termios->c_cflag |= CS8 | CLOCAL; 2007 2008 spin_lock_irqsave(&port->lock, flags); 2009 uart_update_timeout(port, CS8, uap->fixed_baud); 2010 pl011_setup_status_masks(port, termios); 2011 spin_unlock_irqrestore(&port->lock, flags); 2012 } 2013 2014 static const char *pl011_type(struct uart_port *port) 2015 { 2016 struct uart_amba_port *uap = 2017 container_of(port, struct uart_amba_port, port); 2018 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2019 } 2020 2021 /* 2022 * Release the memory region(s) being used by 'port' 2023 */ 2024 static void pl011_release_port(struct uart_port *port) 2025 { 2026 release_mem_region(port->mapbase, SZ_4K); 2027 } 2028 2029 /* 2030 * Request the memory region(s) being used by 'port' 2031 */ 2032 static int pl011_request_port(struct uart_port *port) 2033 { 2034 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") 2035 != NULL ? 0 : -EBUSY; 2036 } 2037 2038 /* 2039 * Configure/autoconfigure the port. 2040 */ 2041 static void pl011_config_port(struct uart_port *port, int flags) 2042 { 2043 if (flags & UART_CONFIG_TYPE) { 2044 port->type = PORT_AMBA; 2045 pl011_request_port(port); 2046 } 2047 } 2048 2049 /* 2050 * verify the new serial_struct (for TIOCSSERIAL). 2051 */ 2052 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2053 { 2054 int ret = 0; 2055 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2056 ret = -EINVAL; 2057 if (ser->irq < 0 || ser->irq >= nr_irqs) 2058 ret = -EINVAL; 2059 if (ser->baud_base < 9600) 2060 ret = -EINVAL; 2061 return ret; 2062 } 2063 2064 static struct uart_ops amba_pl011_pops = { 2065 .tx_empty = pl011_tx_empty, 2066 .set_mctrl = pl011_set_mctrl, 2067 .get_mctrl = pl011_get_mctrl, 2068 .stop_tx = pl011_stop_tx, 2069 .start_tx = pl011_start_tx, 2070 .stop_rx = pl011_stop_rx, 2071 .enable_ms = pl011_enable_ms, 2072 .break_ctl = pl011_break_ctl, 2073 .startup = pl011_startup, 2074 .shutdown = pl011_shutdown, 2075 .flush_buffer = pl011_dma_flush_buffer, 2076 .set_termios = pl011_set_termios, 2077 .type = pl011_type, 2078 .release_port = pl011_release_port, 2079 .request_port = pl011_request_port, 2080 .config_port = pl011_config_port, 2081 .verify_port = pl011_verify_port, 2082 #ifdef CONFIG_CONSOLE_POLL 2083 .poll_init = pl011_hwinit, 2084 .poll_get_char = pl011_get_poll_char, 2085 .poll_put_char = pl011_put_poll_char, 2086 #endif 2087 }; 2088 2089 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2090 { 2091 } 2092 2093 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2094 { 2095 return 0; 2096 } 2097 2098 static const struct uart_ops sbsa_uart_pops = { 2099 .tx_empty = pl011_tx_empty, 2100 .set_mctrl = sbsa_uart_set_mctrl, 2101 .get_mctrl = sbsa_uart_get_mctrl, 2102 .stop_tx = pl011_stop_tx, 2103 .start_tx = pl011_start_tx, 2104 .stop_rx = pl011_stop_rx, 2105 .startup = sbsa_uart_startup, 2106 .shutdown = sbsa_uart_shutdown, 2107 .set_termios = sbsa_uart_set_termios, 2108 .type = pl011_type, 2109 .release_port = pl011_release_port, 2110 .request_port = pl011_request_port, 2111 .config_port = pl011_config_port, 2112 .verify_port = pl011_verify_port, 2113 #ifdef CONFIG_CONSOLE_POLL 2114 .poll_init = pl011_hwinit, 2115 .poll_get_char = pl011_get_poll_char, 2116 .poll_put_char = pl011_put_poll_char, 2117 #endif 2118 }; 2119 2120 static struct uart_amba_port *amba_ports[UART_NR]; 2121 2122 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2123 2124 static void pl011_console_putchar(struct uart_port *port, int ch) 2125 { 2126 struct uart_amba_port *uap = 2127 container_of(port, struct uart_amba_port, port); 2128 2129 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2130 barrier(); 2131 pl011_write(ch, uap, REG_DR); 2132 } 2133 2134 static void 2135 pl011_console_write(struct console *co, const char *s, unsigned int count) 2136 { 2137 struct uart_amba_port *uap = amba_ports[co->index]; 2138 unsigned int status, old_cr = 0, new_cr; 2139 unsigned long flags; 2140 int locked = 1; 2141 2142 clk_enable(uap->clk); 2143 2144 local_irq_save(flags); 2145 if (uap->port.sysrq) 2146 locked = 0; 2147 else if (oops_in_progress) 2148 locked = spin_trylock(&uap->port.lock); 2149 else 2150 spin_lock(&uap->port.lock); 2151 2152 /* 2153 * First save the CR then disable the interrupts 2154 */ 2155 if (!uap->vendor->always_enabled) { 2156 old_cr = pl011_read(uap, REG_CR); 2157 new_cr = old_cr & ~UART011_CR_CTSEN; 2158 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2159 pl011_write(new_cr, uap, REG_CR); 2160 } 2161 2162 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2163 2164 /* 2165 * Finally, wait for transmitter to become empty 2166 * and restore the TCR 2167 */ 2168 do { 2169 status = pl011_read(uap, REG_FR); 2170 } while (status & UART01x_FR_BUSY); 2171 if (!uap->vendor->always_enabled) 2172 pl011_write(old_cr, uap, REG_CR); 2173 2174 if (locked) 2175 spin_unlock(&uap->port.lock); 2176 local_irq_restore(flags); 2177 2178 clk_disable(uap->clk); 2179 } 2180 2181 static void __init 2182 pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2183 int *parity, int *bits) 2184 { 2185 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2186 unsigned int lcr_h, ibrd, fbrd; 2187 2188 lcr_h = pl011_read(uap, REG_LCRH_TX); 2189 2190 *parity = 'n'; 2191 if (lcr_h & UART01x_LCRH_PEN) { 2192 if (lcr_h & UART01x_LCRH_EPS) 2193 *parity = 'e'; 2194 else 2195 *parity = 'o'; 2196 } 2197 2198 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2199 *bits = 7; 2200 else 2201 *bits = 8; 2202 2203 ibrd = pl011_read(uap, REG_IBRD); 2204 fbrd = pl011_read(uap, REG_FBRD); 2205 2206 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2207 2208 if (uap->vendor->oversampling) { 2209 if (pl011_read(uap, REG_CR) 2210 & ST_UART011_CR_OVSFACT) 2211 *baud *= 2; 2212 } 2213 } 2214 } 2215 2216 static int __init pl011_console_setup(struct console *co, char *options) 2217 { 2218 struct uart_amba_port *uap; 2219 int baud = 38400; 2220 int bits = 8; 2221 int parity = 'n'; 2222 int flow = 'n'; 2223 int ret; 2224 2225 /* 2226 * Check whether an invalid uart number has been specified, and 2227 * if so, search for the first available port that does have 2228 * console support. 2229 */ 2230 if (co->index >= UART_NR) 2231 co->index = 0; 2232 uap = amba_ports[co->index]; 2233 if (!uap) 2234 return -ENODEV; 2235 2236 /* Allow pins to be muxed in and configured */ 2237 pinctrl_pm_select_default_state(uap->port.dev); 2238 2239 ret = clk_prepare(uap->clk); 2240 if (ret) 2241 return ret; 2242 2243 if (dev_get_platdata(uap->port.dev)) { 2244 struct amba_pl011_data *plat; 2245 2246 plat = dev_get_platdata(uap->port.dev); 2247 if (plat->init) 2248 plat->init(); 2249 } 2250 2251 uap->port.uartclk = clk_get_rate(uap->clk); 2252 2253 if (uap->vendor->fixed_options) { 2254 baud = uap->fixed_baud; 2255 } else { 2256 if (options) 2257 uart_parse_options(options, 2258 &baud, &parity, &bits, &flow); 2259 else 2260 pl011_console_get_options(uap, &baud, &parity, &bits); 2261 } 2262 2263 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2264 } 2265 2266 static struct uart_driver amba_reg; 2267 static struct console amba_console = { 2268 .name = "ttyAMA", 2269 .write = pl011_console_write, 2270 .device = uart_console_device, 2271 .setup = pl011_console_setup, 2272 .flags = CON_PRINTBUFFER, 2273 .index = -1, 2274 .data = &amba_reg, 2275 }; 2276 2277 #define AMBA_CONSOLE (&amba_console) 2278 2279 static void pl011_putc(struct uart_port *port, int c) 2280 { 2281 while (readl(port->membase + REG_FR) & UART01x_FR_TXFF) 2282 ; 2283 writeb(c, port->membase + REG_DR); 2284 while (readl(port->membase + REG_FR) & UART01x_FR_BUSY) 2285 ; 2286 } 2287 2288 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2289 { 2290 struct earlycon_device *dev = con->data; 2291 2292 uart_console_write(&dev->port, s, n, pl011_putc); 2293 } 2294 2295 static int __init pl011_early_console_setup(struct earlycon_device *device, 2296 const char *opt) 2297 { 2298 if (!device->port.membase) 2299 return -ENODEV; 2300 2301 device->con->write = pl011_early_write; 2302 return 0; 2303 } 2304 EARLYCON_DECLARE(pl011, pl011_early_console_setup); 2305 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2306 2307 #else 2308 #define AMBA_CONSOLE NULL 2309 #endif 2310 2311 static struct uart_driver amba_reg = { 2312 .owner = THIS_MODULE, 2313 .driver_name = "ttyAMA", 2314 .dev_name = "ttyAMA", 2315 .major = SERIAL_AMBA_MAJOR, 2316 .minor = SERIAL_AMBA_MINOR, 2317 .nr = UART_NR, 2318 .cons = AMBA_CONSOLE, 2319 }; 2320 2321 static int pl011_probe_dt_alias(int index, struct device *dev) 2322 { 2323 struct device_node *np; 2324 static bool seen_dev_with_alias = false; 2325 static bool seen_dev_without_alias = false; 2326 int ret = index; 2327 2328 if (!IS_ENABLED(CONFIG_OF)) 2329 return ret; 2330 2331 np = dev->of_node; 2332 if (!np) 2333 return ret; 2334 2335 ret = of_alias_get_id(np, "serial"); 2336 if (IS_ERR_VALUE(ret)) { 2337 seen_dev_without_alias = true; 2338 ret = index; 2339 } else { 2340 seen_dev_with_alias = true; 2341 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2342 dev_warn(dev, "requested serial port %d not available.\n", ret); 2343 ret = index; 2344 } 2345 } 2346 2347 if (seen_dev_with_alias && seen_dev_without_alias) 2348 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2349 2350 return ret; 2351 } 2352 2353 /* unregisters the driver also if no more ports are left */ 2354 static void pl011_unregister_port(struct uart_amba_port *uap) 2355 { 2356 int i; 2357 bool busy = false; 2358 2359 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2360 if (amba_ports[i] == uap) 2361 amba_ports[i] = NULL; 2362 else if (amba_ports[i]) 2363 busy = true; 2364 } 2365 pl011_dma_remove(uap); 2366 if (!busy) 2367 uart_unregister_driver(&amba_reg); 2368 } 2369 2370 static int pl011_find_free_port(void) 2371 { 2372 int i; 2373 2374 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2375 if (amba_ports[i] == NULL) 2376 return i; 2377 2378 return -EBUSY; 2379 } 2380 2381 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2382 struct resource *mmiobase, int index) 2383 { 2384 void __iomem *base; 2385 2386 base = devm_ioremap_resource(dev, mmiobase); 2387 if (IS_ERR(base)) 2388 return PTR_ERR(base); 2389 2390 index = pl011_probe_dt_alias(index, dev); 2391 2392 uap->old_cr = 0; 2393 uap->port.dev = dev; 2394 uap->port.mapbase = mmiobase->start; 2395 uap->port.membase = base; 2396 uap->port.iotype = UPIO_MEM; 2397 uap->port.fifosize = uap->fifosize; 2398 uap->port.flags = UPF_BOOT_AUTOCONF; 2399 uap->port.line = index; 2400 2401 amba_ports[index] = uap; 2402 2403 return 0; 2404 } 2405 2406 static int pl011_register_port(struct uart_amba_port *uap) 2407 { 2408 int ret; 2409 2410 /* Ensure interrupts from this UART are masked and cleared */ 2411 pl011_write(0, uap, REG_IMSC); 2412 pl011_write(0xffff, uap, REG_ICR); 2413 2414 if (!amba_reg.state) { 2415 ret = uart_register_driver(&amba_reg); 2416 if (ret < 0) { 2417 dev_err(uap->port.dev, 2418 "Failed to register AMBA-PL011 driver\n"); 2419 return ret; 2420 } 2421 } 2422 2423 ret = uart_add_one_port(&amba_reg, &uap->port); 2424 if (ret) 2425 pl011_unregister_port(uap); 2426 2427 return ret; 2428 } 2429 2430 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2431 { 2432 struct uart_amba_port *uap; 2433 struct vendor_data *vendor = id->data; 2434 int portnr, ret; 2435 2436 portnr = pl011_find_free_port(); 2437 if (portnr < 0) 2438 return portnr; 2439 2440 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2441 GFP_KERNEL); 2442 if (!uap) 2443 return -ENOMEM; 2444 2445 uap->clk = devm_clk_get(&dev->dev, NULL); 2446 if (IS_ERR(uap->clk)) 2447 return PTR_ERR(uap->clk); 2448 2449 uap->reg_offset = vendor->reg_offset; 2450 uap->access_32b = vendor->access_32b; 2451 uap->vendor = vendor; 2452 uap->fifosize = vendor->get_fifosize(dev); 2453 uap->port.irq = dev->irq[0]; 2454 uap->port.ops = &amba_pl011_pops; 2455 2456 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2457 2458 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2459 if (ret) 2460 return ret; 2461 2462 amba_set_drvdata(dev, uap); 2463 2464 return pl011_register_port(uap); 2465 } 2466 2467 static int pl011_remove(struct amba_device *dev) 2468 { 2469 struct uart_amba_port *uap = amba_get_drvdata(dev); 2470 2471 uart_remove_one_port(&amba_reg, &uap->port); 2472 pl011_unregister_port(uap); 2473 return 0; 2474 } 2475 2476 #ifdef CONFIG_PM_SLEEP 2477 static int pl011_suspend(struct device *dev) 2478 { 2479 struct uart_amba_port *uap = dev_get_drvdata(dev); 2480 2481 if (!uap) 2482 return -EINVAL; 2483 2484 return uart_suspend_port(&amba_reg, &uap->port); 2485 } 2486 2487 static int pl011_resume(struct device *dev) 2488 { 2489 struct uart_amba_port *uap = dev_get_drvdata(dev); 2490 2491 if (!uap) 2492 return -EINVAL; 2493 2494 return uart_resume_port(&amba_reg, &uap->port); 2495 } 2496 #endif 2497 2498 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2499 2500 static int sbsa_uart_probe(struct platform_device *pdev) 2501 { 2502 struct uart_amba_port *uap; 2503 struct resource *r; 2504 int portnr, ret; 2505 int baudrate; 2506 2507 /* 2508 * Check the mandatory baud rate parameter in the DT node early 2509 * so that we can easily exit with the error. 2510 */ 2511 if (pdev->dev.of_node) { 2512 struct device_node *np = pdev->dev.of_node; 2513 2514 ret = of_property_read_u32(np, "current-speed", &baudrate); 2515 if (ret) 2516 return ret; 2517 } else { 2518 baudrate = 115200; 2519 } 2520 2521 portnr = pl011_find_free_port(); 2522 if (portnr < 0) 2523 return portnr; 2524 2525 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2526 GFP_KERNEL); 2527 if (!uap) 2528 return -ENOMEM; 2529 2530 uap->reg_offset = vendor_sbsa.reg_offset; 2531 uap->access_32b = vendor_sbsa.access_32b; 2532 uap->vendor = &vendor_sbsa; 2533 uap->fifosize = 32; 2534 uap->port.irq = platform_get_irq(pdev, 0); 2535 uap->port.ops = &sbsa_uart_pops; 2536 uap->fixed_baud = baudrate; 2537 2538 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2539 2540 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2541 2542 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2543 if (ret) 2544 return ret; 2545 2546 platform_set_drvdata(pdev, uap); 2547 2548 return pl011_register_port(uap); 2549 } 2550 2551 static int sbsa_uart_remove(struct platform_device *pdev) 2552 { 2553 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2554 2555 uart_remove_one_port(&amba_reg, &uap->port); 2556 pl011_unregister_port(uap); 2557 return 0; 2558 } 2559 2560 static const struct of_device_id sbsa_uart_of_match[] = { 2561 { .compatible = "arm,sbsa-uart", }, 2562 {}, 2563 }; 2564 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2565 2566 static const struct acpi_device_id sbsa_uart_acpi_match[] = { 2567 { "ARMH0011", 0 }, 2568 {}, 2569 }; 2570 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2571 2572 static struct platform_driver arm_sbsa_uart_platform_driver = { 2573 .probe = sbsa_uart_probe, 2574 .remove = sbsa_uart_remove, 2575 .driver = { 2576 .name = "sbsa-uart", 2577 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2578 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2579 }, 2580 }; 2581 2582 static struct amba_id pl011_ids[] = { 2583 { 2584 .id = 0x00041011, 2585 .mask = 0x000fffff, 2586 .data = &vendor_arm, 2587 }, 2588 { 2589 .id = 0x00380802, 2590 .mask = 0x00ffffff, 2591 .data = &vendor_st, 2592 }, 2593 { 0, 0 }, 2594 }; 2595 2596 MODULE_DEVICE_TABLE(amba, pl011_ids); 2597 2598 static struct amba_driver pl011_driver = { 2599 .drv = { 2600 .name = "uart-pl011", 2601 .pm = &pl011_dev_pm_ops, 2602 }, 2603 .id_table = pl011_ids, 2604 .probe = pl011_probe, 2605 .remove = pl011_remove, 2606 }; 2607 2608 static int __init pl011_init(void) 2609 { 2610 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2611 2612 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2613 pr_warn("could not register SBSA UART platform driver\n"); 2614 return amba_driver_register(&pl011_driver); 2615 } 2616 2617 static void __exit pl011_exit(void) 2618 { 2619 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2620 amba_driver_unregister(&pl011_driver); 2621 } 2622 2623 /* 2624 * While this can be a module, if builtin it's most likely the console 2625 * So let's leave module_exit but move module_init to an earlier place 2626 */ 2627 arch_initcall(pl011_init); 2628 module_exit(pl011_exit); 2629 2630 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 2631 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 2632 MODULE_LICENSE("GPL"); 2633