1 /* 2 * Driver for AMBA serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright 1999 ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * Copyright (C) 2010 ST-Ericsson SA 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 * This is a generic driver for ARM AMBA-type serial ports. They 25 * have a lot of 16550-like features, but are not register compatible. 26 * Note that although they do have CTS, DCD and DSR inputs, they do 27 * not have an RI input, nor do they have DTR or RTS outputs. If 28 * required, these have to be supplied via some other means (eg, GPIO) 29 * and hooked into this driver. 30 */ 31 32 33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 34 #define SUPPORT_SYSRQ 35 #endif 36 37 #include <linux/module.h> 38 #include <linux/ioport.h> 39 #include <linux/init.h> 40 #include <linux/console.h> 41 #include <linux/sysrq.h> 42 #include <linux/device.h> 43 #include <linux/tty.h> 44 #include <linux/tty_flip.h> 45 #include <linux/serial_core.h> 46 #include <linux/serial.h> 47 #include <linux/amba/bus.h> 48 #include <linux/amba/serial.h> 49 #include <linux/clk.h> 50 #include <linux/slab.h> 51 #include <linux/dmaengine.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/scatterlist.h> 54 #include <linux/delay.h> 55 #include <linux/types.h> 56 #include <linux/of.h> 57 #include <linux/of_device.h> 58 #include <linux/pinctrl/consumer.h> 59 #include <linux/sizes.h> 60 #include <linux/io.h> 61 #include <linux/acpi.h> 62 63 #include "amba-pl011.h" 64 65 #define UART_NR 14 66 67 #define SERIAL_AMBA_MAJOR 204 68 #define SERIAL_AMBA_MINOR 64 69 #define SERIAL_AMBA_NR UART_NR 70 71 #define AMBA_ISR_PASS_LIMIT 256 72 73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) 74 #define UART_DUMMY_DR_RX (1 << 16) 75 76 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { 77 [REG_DR] = UART01x_DR, 78 [REG_FR] = UART01x_FR, 79 [REG_LCRH_RX] = UART011_LCRH, 80 [REG_LCRH_TX] = UART011_LCRH, 81 [REG_IBRD] = UART011_IBRD, 82 [REG_FBRD] = UART011_FBRD, 83 [REG_CR] = UART011_CR, 84 [REG_IFLS] = UART011_IFLS, 85 [REG_IMSC] = UART011_IMSC, 86 [REG_RIS] = UART011_RIS, 87 [REG_MIS] = UART011_MIS, 88 [REG_ICR] = UART011_ICR, 89 [REG_DMACR] = UART011_DMACR, 90 }; 91 92 /* There is by now at least one vendor with differing details, so handle it */ 93 struct vendor_data { 94 const u16 *reg_offset; 95 unsigned int ifls; 96 bool access_32b; 97 bool oversampling; 98 bool dma_threshold; 99 bool cts_event_workaround; 100 bool always_enabled; 101 bool fixed_options; 102 103 unsigned int (*get_fifosize)(struct amba_device *dev); 104 }; 105 106 static unsigned int get_fifosize_arm(struct amba_device *dev) 107 { 108 return amba_rev(dev) < 3 ? 16 : 32; 109 } 110 111 static struct vendor_data vendor_arm = { 112 .reg_offset = pl011_std_offsets, 113 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 114 .oversampling = false, 115 .dma_threshold = false, 116 .cts_event_workaround = false, 117 .always_enabled = false, 118 .fixed_options = false, 119 .get_fifosize = get_fifosize_arm, 120 }; 121 122 static struct vendor_data vendor_sbsa = { 123 .reg_offset = pl011_std_offsets, 124 .oversampling = false, 125 .dma_threshold = false, 126 .cts_event_workaround = false, 127 .always_enabled = true, 128 .fixed_options = true, 129 }; 130 131 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { 132 [REG_DR] = UART01x_DR, 133 [REG_ST_DMAWM] = ST_UART011_DMAWM, 134 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, 135 [REG_FR] = UART01x_FR, 136 [REG_LCRH_RX] = ST_UART011_LCRH_RX, 137 [REG_LCRH_TX] = ST_UART011_LCRH_TX, 138 [REG_IBRD] = UART011_IBRD, 139 [REG_FBRD] = UART011_FBRD, 140 [REG_CR] = UART011_CR, 141 [REG_IFLS] = UART011_IFLS, 142 [REG_IMSC] = UART011_IMSC, 143 [REG_RIS] = UART011_RIS, 144 [REG_MIS] = UART011_MIS, 145 [REG_ICR] = UART011_ICR, 146 [REG_DMACR] = UART011_DMACR, 147 [REG_ST_XFCR] = ST_UART011_XFCR, 148 [REG_ST_XON1] = ST_UART011_XON1, 149 [REG_ST_XON2] = ST_UART011_XON2, 150 [REG_ST_XOFF1] = ST_UART011_XOFF1, 151 [REG_ST_XOFF2] = ST_UART011_XOFF2, 152 [REG_ST_ITCR] = ST_UART011_ITCR, 153 [REG_ST_ITIP] = ST_UART011_ITIP, 154 [REG_ST_ABCR] = ST_UART011_ABCR, 155 [REG_ST_ABIMSC] = ST_UART011_ABIMSC, 156 }; 157 158 static unsigned int get_fifosize_st(struct amba_device *dev) 159 { 160 return 64; 161 } 162 163 static struct vendor_data vendor_st = { 164 .reg_offset = pl011_st_offsets, 165 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, 166 .oversampling = true, 167 .dma_threshold = true, 168 .cts_event_workaround = true, 169 .always_enabled = false, 170 .fixed_options = false, 171 .get_fifosize = get_fifosize_st, 172 }; 173 174 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { 175 [REG_DR] = ZX_UART011_DR, 176 [REG_FR] = ZX_UART011_FR, 177 [REG_LCRH_RX] = ZX_UART011_LCRH, 178 [REG_LCRH_TX] = ZX_UART011_LCRH, 179 [REG_IBRD] = ZX_UART011_IBRD, 180 [REG_FBRD] = ZX_UART011_FBRD, 181 [REG_CR] = ZX_UART011_CR, 182 [REG_IFLS] = ZX_UART011_IFLS, 183 [REG_IMSC] = ZX_UART011_IMSC, 184 [REG_RIS] = ZX_UART011_RIS, 185 [REG_MIS] = ZX_UART011_MIS, 186 [REG_ICR] = ZX_UART011_ICR, 187 [REG_DMACR] = ZX_UART011_DMACR, 188 }; 189 190 static struct vendor_data vendor_zte = { 191 .reg_offset = pl011_zte_offsets, 192 .access_32b = true, 193 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, 194 .get_fifosize = get_fifosize_arm, 195 }; 196 197 /* Deals with DMA transactions */ 198 199 struct pl011_sgbuf { 200 struct scatterlist sg; 201 char *buf; 202 }; 203 204 struct pl011_dmarx_data { 205 struct dma_chan *chan; 206 struct completion complete; 207 bool use_buf_b; 208 struct pl011_sgbuf sgbuf_a; 209 struct pl011_sgbuf sgbuf_b; 210 dma_cookie_t cookie; 211 bool running; 212 struct timer_list timer; 213 unsigned int last_residue; 214 unsigned long last_jiffies; 215 bool auto_poll_rate; 216 unsigned int poll_rate; 217 unsigned int poll_timeout; 218 }; 219 220 struct pl011_dmatx_data { 221 struct dma_chan *chan; 222 struct scatterlist sg; 223 char *buf; 224 bool queued; 225 }; 226 227 /* 228 * We wrap our port structure around the generic uart_port. 229 */ 230 struct uart_amba_port { 231 struct uart_port port; 232 const u16 *reg_offset; 233 struct clk *clk; 234 const struct vendor_data *vendor; 235 unsigned int dmacr; /* dma control reg */ 236 unsigned int im; /* interrupt mask */ 237 unsigned int old_status; 238 unsigned int fifosize; /* vendor-specific */ 239 unsigned int old_cr; /* state during shutdown */ 240 bool autorts; 241 bool access_32b; 242 unsigned int fixed_baud; /* vendor-set fixed baud rate */ 243 char type[12]; 244 #ifdef CONFIG_DMA_ENGINE 245 /* DMA stuff */ 246 bool using_tx_dma; 247 bool using_rx_dma; 248 struct pl011_dmarx_data dmarx; 249 struct pl011_dmatx_data dmatx; 250 bool dma_probed; 251 #endif 252 }; 253 254 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, 255 unsigned int reg) 256 { 257 return uap->reg_offset[reg]; 258 } 259 260 static unsigned int pl011_read(const struct uart_amba_port *uap, 261 unsigned int reg) 262 { 263 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 264 265 return uap->access_32b ? readl(addr) : readw(addr); 266 } 267 268 static void pl011_write(unsigned int val, const struct uart_amba_port *uap, 269 unsigned int reg) 270 { 271 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); 272 273 if (uap->access_32b) 274 writel(val, addr); 275 else 276 writew(val, addr); 277 } 278 279 /* 280 * Reads up to 256 characters from the FIFO or until it's empty and 281 * inserts them into the TTY layer. Returns the number of characters 282 * read from the FIFO. 283 */ 284 static int pl011_fifo_to_tty(struct uart_amba_port *uap) 285 { 286 u16 status; 287 unsigned int ch, flag, max_count = 256; 288 int fifotaken = 0; 289 290 while (max_count--) { 291 status = pl011_read(uap, REG_FR); 292 if (status & UART01x_FR_RXFE) 293 break; 294 295 /* Take chars from the FIFO and update status */ 296 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; 297 flag = TTY_NORMAL; 298 uap->port.icount.rx++; 299 fifotaken++; 300 301 if (unlikely(ch & UART_DR_ERROR)) { 302 if (ch & UART011_DR_BE) { 303 ch &= ~(UART011_DR_FE | UART011_DR_PE); 304 uap->port.icount.brk++; 305 if (uart_handle_break(&uap->port)) 306 continue; 307 } else if (ch & UART011_DR_PE) 308 uap->port.icount.parity++; 309 else if (ch & UART011_DR_FE) 310 uap->port.icount.frame++; 311 if (ch & UART011_DR_OE) 312 uap->port.icount.overrun++; 313 314 ch &= uap->port.read_status_mask; 315 316 if (ch & UART011_DR_BE) 317 flag = TTY_BREAK; 318 else if (ch & UART011_DR_PE) 319 flag = TTY_PARITY; 320 else if (ch & UART011_DR_FE) 321 flag = TTY_FRAME; 322 } 323 324 if (uart_handle_sysrq_char(&uap->port, ch & 255)) 325 continue; 326 327 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); 328 } 329 330 return fifotaken; 331 } 332 333 334 /* 335 * All the DMA operation mode stuff goes inside this ifdef. 336 * This assumes that you have a generic DMA device interface, 337 * no custom DMA interfaces are supported. 338 */ 339 #ifdef CONFIG_DMA_ENGINE 340 341 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE 342 343 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, 344 enum dma_data_direction dir) 345 { 346 dma_addr_t dma_addr; 347 348 sg->buf = dma_alloc_coherent(chan->device->dev, 349 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); 350 if (!sg->buf) 351 return -ENOMEM; 352 353 sg_init_table(&sg->sg, 1); 354 sg_set_page(&sg->sg, phys_to_page(dma_addr), 355 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); 356 sg_dma_address(&sg->sg) = dma_addr; 357 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; 358 359 return 0; 360 } 361 362 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, 363 enum dma_data_direction dir) 364 { 365 if (sg->buf) { 366 dma_free_coherent(chan->device->dev, 367 PL011_DMA_BUFFER_SIZE, sg->buf, 368 sg_dma_address(&sg->sg)); 369 } 370 } 371 372 static void pl011_dma_probe(struct uart_amba_port *uap) 373 { 374 /* DMA is the sole user of the platform data right now */ 375 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); 376 struct device *dev = uap->port.dev; 377 struct dma_slave_config tx_conf = { 378 .dst_addr = uap->port.mapbase + 379 pl011_reg_to_offset(uap, REG_DR), 380 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 381 .direction = DMA_MEM_TO_DEV, 382 .dst_maxburst = uap->fifosize >> 1, 383 .device_fc = false, 384 }; 385 struct dma_chan *chan; 386 dma_cap_mask_t mask; 387 388 uap->dma_probed = true; 389 chan = dma_request_slave_channel_reason(dev, "tx"); 390 if (IS_ERR(chan)) { 391 if (PTR_ERR(chan) == -EPROBE_DEFER) { 392 uap->dma_probed = false; 393 return; 394 } 395 396 /* We need platform data */ 397 if (!plat || !plat->dma_filter) { 398 dev_info(uap->port.dev, "no DMA platform data\n"); 399 return; 400 } 401 402 /* Try to acquire a generic DMA engine slave TX channel */ 403 dma_cap_zero(mask); 404 dma_cap_set(DMA_SLAVE, mask); 405 406 chan = dma_request_channel(mask, plat->dma_filter, 407 plat->dma_tx_param); 408 if (!chan) { 409 dev_err(uap->port.dev, "no TX DMA channel!\n"); 410 return; 411 } 412 } 413 414 dmaengine_slave_config(chan, &tx_conf); 415 uap->dmatx.chan = chan; 416 417 dev_info(uap->port.dev, "DMA channel TX %s\n", 418 dma_chan_name(uap->dmatx.chan)); 419 420 /* Optionally make use of an RX channel as well */ 421 chan = dma_request_slave_channel(dev, "rx"); 422 423 if (!chan && plat->dma_rx_param) { 424 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); 425 426 if (!chan) { 427 dev_err(uap->port.dev, "no RX DMA channel!\n"); 428 return; 429 } 430 } 431 432 if (chan) { 433 struct dma_slave_config rx_conf = { 434 .src_addr = uap->port.mapbase + 435 pl011_reg_to_offset(uap, REG_DR), 436 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, 437 .direction = DMA_DEV_TO_MEM, 438 .src_maxburst = uap->fifosize >> 2, 439 .device_fc = false, 440 }; 441 struct dma_slave_caps caps; 442 443 /* 444 * Some DMA controllers provide information on their capabilities. 445 * If the controller does, check for suitable residue processing 446 * otherwise assime all is well. 447 */ 448 if (0 == dma_get_slave_caps(chan, &caps)) { 449 if (caps.residue_granularity == 450 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 451 dma_release_channel(chan); 452 dev_info(uap->port.dev, 453 "RX DMA disabled - no residue processing\n"); 454 return; 455 } 456 } 457 dmaengine_slave_config(chan, &rx_conf); 458 uap->dmarx.chan = chan; 459 460 uap->dmarx.auto_poll_rate = false; 461 if (plat && plat->dma_rx_poll_enable) { 462 /* Set poll rate if specified. */ 463 if (plat->dma_rx_poll_rate) { 464 uap->dmarx.auto_poll_rate = false; 465 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; 466 } else { 467 /* 468 * 100 ms defaults to poll rate if not 469 * specified. This will be adjusted with 470 * the baud rate at set_termios. 471 */ 472 uap->dmarx.auto_poll_rate = true; 473 uap->dmarx.poll_rate = 100; 474 } 475 /* 3 secs defaults poll_timeout if not specified. */ 476 if (plat->dma_rx_poll_timeout) 477 uap->dmarx.poll_timeout = 478 plat->dma_rx_poll_timeout; 479 else 480 uap->dmarx.poll_timeout = 3000; 481 } else if (!plat && dev->of_node) { 482 uap->dmarx.auto_poll_rate = of_property_read_bool( 483 dev->of_node, "auto-poll"); 484 if (uap->dmarx.auto_poll_rate) { 485 u32 x; 486 487 if (0 == of_property_read_u32(dev->of_node, 488 "poll-rate-ms", &x)) 489 uap->dmarx.poll_rate = x; 490 else 491 uap->dmarx.poll_rate = 100; 492 if (0 == of_property_read_u32(dev->of_node, 493 "poll-timeout-ms", &x)) 494 uap->dmarx.poll_timeout = x; 495 else 496 uap->dmarx.poll_timeout = 3000; 497 } 498 } 499 dev_info(uap->port.dev, "DMA channel RX %s\n", 500 dma_chan_name(uap->dmarx.chan)); 501 } 502 } 503 504 static void pl011_dma_remove(struct uart_amba_port *uap) 505 { 506 if (uap->dmatx.chan) 507 dma_release_channel(uap->dmatx.chan); 508 if (uap->dmarx.chan) 509 dma_release_channel(uap->dmarx.chan); 510 } 511 512 /* Forward declare these for the refill routine */ 513 static int pl011_dma_tx_refill(struct uart_amba_port *uap); 514 static void pl011_start_tx_pio(struct uart_amba_port *uap); 515 516 /* 517 * The current DMA TX buffer has been sent. 518 * Try to queue up another DMA buffer. 519 */ 520 static void pl011_dma_tx_callback(void *data) 521 { 522 struct uart_amba_port *uap = data; 523 struct pl011_dmatx_data *dmatx = &uap->dmatx; 524 unsigned long flags; 525 u16 dmacr; 526 527 spin_lock_irqsave(&uap->port.lock, flags); 528 if (uap->dmatx.queued) 529 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 530 DMA_TO_DEVICE); 531 532 dmacr = uap->dmacr; 533 uap->dmacr = dmacr & ~UART011_TXDMAE; 534 pl011_write(uap->dmacr, uap, REG_DMACR); 535 536 /* 537 * If TX DMA was disabled, it means that we've stopped the DMA for 538 * some reason (eg, XOFF received, or we want to send an X-char.) 539 * 540 * Note: we need to be careful here of a potential race between DMA 541 * and the rest of the driver - if the driver disables TX DMA while 542 * a TX buffer completing, we must update the tx queued status to 543 * get further refills (hence we check dmacr). 544 */ 545 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 546 uart_circ_empty(&uap->port.state->xmit)) { 547 uap->dmatx.queued = false; 548 spin_unlock_irqrestore(&uap->port.lock, flags); 549 return; 550 } 551 552 if (pl011_dma_tx_refill(uap) <= 0) 553 /* 554 * We didn't queue a DMA buffer for some reason, but we 555 * have data pending to be sent. Re-enable the TX IRQ. 556 */ 557 pl011_start_tx_pio(uap); 558 559 spin_unlock_irqrestore(&uap->port.lock, flags); 560 } 561 562 /* 563 * Try to refill the TX DMA buffer. 564 * Locking: called with port lock held and IRQs disabled. 565 * Returns: 566 * 1 if we queued up a TX DMA buffer. 567 * 0 if we didn't want to handle this by DMA 568 * <0 on error 569 */ 570 static int pl011_dma_tx_refill(struct uart_amba_port *uap) 571 { 572 struct pl011_dmatx_data *dmatx = &uap->dmatx; 573 struct dma_chan *chan = dmatx->chan; 574 struct dma_device *dma_dev = chan->device; 575 struct dma_async_tx_descriptor *desc; 576 struct circ_buf *xmit = &uap->port.state->xmit; 577 unsigned int count; 578 579 /* 580 * Try to avoid the overhead involved in using DMA if the 581 * transaction fits in the first half of the FIFO, by using 582 * the standard interrupt handling. This ensures that we 583 * issue a uart_write_wakeup() at the appropriate time. 584 */ 585 count = uart_circ_chars_pending(xmit); 586 if (count < (uap->fifosize >> 1)) { 587 uap->dmatx.queued = false; 588 return 0; 589 } 590 591 /* 592 * Bodge: don't send the last character by DMA, as this 593 * will prevent XON from notifying us to restart DMA. 594 */ 595 count -= 1; 596 597 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ 598 if (count > PL011_DMA_BUFFER_SIZE) 599 count = PL011_DMA_BUFFER_SIZE; 600 601 if (xmit->tail < xmit->head) 602 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); 603 else { 604 size_t first = UART_XMIT_SIZE - xmit->tail; 605 size_t second; 606 607 if (first > count) 608 first = count; 609 second = count - first; 610 611 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); 612 if (second) 613 memcpy(&dmatx->buf[first], &xmit->buf[0], second); 614 } 615 616 dmatx->sg.length = count; 617 618 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { 619 uap->dmatx.queued = false; 620 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); 621 return -EBUSY; 622 } 623 624 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, 625 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 626 if (!desc) { 627 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); 628 uap->dmatx.queued = false; 629 /* 630 * If DMA cannot be used right now, we complete this 631 * transaction via IRQ and let the TTY layer retry. 632 */ 633 dev_dbg(uap->port.dev, "TX DMA busy\n"); 634 return -EBUSY; 635 } 636 637 /* Some data to go along to the callback */ 638 desc->callback = pl011_dma_tx_callback; 639 desc->callback_param = uap; 640 641 /* All errors should happen at prepare time */ 642 dmaengine_submit(desc); 643 644 /* Fire the DMA transaction */ 645 dma_dev->device_issue_pending(chan); 646 647 uap->dmacr |= UART011_TXDMAE; 648 pl011_write(uap->dmacr, uap, REG_DMACR); 649 uap->dmatx.queued = true; 650 651 /* 652 * Now we know that DMA will fire, so advance the ring buffer 653 * with the stuff we just dispatched. 654 */ 655 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); 656 uap->port.icount.tx += count; 657 658 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 659 uart_write_wakeup(&uap->port); 660 661 return 1; 662 } 663 664 /* 665 * We received a transmit interrupt without a pending X-char but with 666 * pending characters. 667 * Locking: called with port lock held and IRQs disabled. 668 * Returns: 669 * false if we want to use PIO to transmit 670 * true if we queued a DMA buffer 671 */ 672 static bool pl011_dma_tx_irq(struct uart_amba_port *uap) 673 { 674 if (!uap->using_tx_dma) 675 return false; 676 677 /* 678 * If we already have a TX buffer queued, but received a 679 * TX interrupt, it will be because we've just sent an X-char. 680 * Ensure the TX DMA is enabled and the TX IRQ is disabled. 681 */ 682 if (uap->dmatx.queued) { 683 uap->dmacr |= UART011_TXDMAE; 684 pl011_write(uap->dmacr, uap, REG_DMACR); 685 uap->im &= ~UART011_TXIM; 686 pl011_write(uap->im, uap, REG_IMSC); 687 return true; 688 } 689 690 /* 691 * We don't have a TX buffer queued, so try to queue one. 692 * If we successfully queued a buffer, mask the TX IRQ. 693 */ 694 if (pl011_dma_tx_refill(uap) > 0) { 695 uap->im &= ~UART011_TXIM; 696 pl011_write(uap->im, uap, REG_IMSC); 697 return true; 698 } 699 return false; 700 } 701 702 /* 703 * Stop the DMA transmit (eg, due to received XOFF). 704 * Locking: called with port lock held and IRQs disabled. 705 */ 706 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 707 { 708 if (uap->dmatx.queued) { 709 uap->dmacr &= ~UART011_TXDMAE; 710 pl011_write(uap->dmacr, uap, REG_DMACR); 711 } 712 } 713 714 /* 715 * Try to start a DMA transmit, or in the case of an XON/OFF 716 * character queued for send, try to get that character out ASAP. 717 * Locking: called with port lock held and IRQs disabled. 718 * Returns: 719 * false if we want the TX IRQ to be enabled 720 * true if we have a buffer queued 721 */ 722 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 723 { 724 u16 dmacr; 725 726 if (!uap->using_tx_dma) 727 return false; 728 729 if (!uap->port.x_char) { 730 /* no X-char, try to push chars out in DMA mode */ 731 bool ret = true; 732 733 if (!uap->dmatx.queued) { 734 if (pl011_dma_tx_refill(uap) > 0) { 735 uap->im &= ~UART011_TXIM; 736 pl011_write(uap->im, uap, REG_IMSC); 737 } else 738 ret = false; 739 } else if (!(uap->dmacr & UART011_TXDMAE)) { 740 uap->dmacr |= UART011_TXDMAE; 741 pl011_write(uap->dmacr, uap, REG_DMACR); 742 } 743 return ret; 744 } 745 746 /* 747 * We have an X-char to send. Disable DMA to prevent it loading 748 * the TX fifo, and then see if we can stuff it into the FIFO. 749 */ 750 dmacr = uap->dmacr; 751 uap->dmacr &= ~UART011_TXDMAE; 752 pl011_write(uap->dmacr, uap, REG_DMACR); 753 754 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { 755 /* 756 * No space in the FIFO, so enable the transmit interrupt 757 * so we know when there is space. Note that once we've 758 * loaded the character, we should just re-enable DMA. 759 */ 760 return false; 761 } 762 763 pl011_write(uap->port.x_char, uap, REG_DR); 764 uap->port.icount.tx++; 765 uap->port.x_char = 0; 766 767 /* Success - restore the DMA state */ 768 uap->dmacr = dmacr; 769 pl011_write(dmacr, uap, REG_DMACR); 770 771 return true; 772 } 773 774 /* 775 * Flush the transmit buffer. 776 * Locking: called with port lock held and IRQs disabled. 777 */ 778 static void pl011_dma_flush_buffer(struct uart_port *port) 779 __releases(&uap->port.lock) 780 __acquires(&uap->port.lock) 781 { 782 struct uart_amba_port *uap = 783 container_of(port, struct uart_amba_port, port); 784 785 if (!uap->using_tx_dma) 786 return; 787 788 /* Avoid deadlock with the DMA engine callback */ 789 spin_unlock(&uap->port.lock); 790 dmaengine_terminate_all(uap->dmatx.chan); 791 spin_lock(&uap->port.lock); 792 if (uap->dmatx.queued) { 793 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 794 DMA_TO_DEVICE); 795 uap->dmatx.queued = false; 796 uap->dmacr &= ~UART011_TXDMAE; 797 pl011_write(uap->dmacr, uap, REG_DMACR); 798 } 799 } 800 801 static void pl011_dma_rx_callback(void *data); 802 803 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 804 { 805 struct dma_chan *rxchan = uap->dmarx.chan; 806 struct pl011_dmarx_data *dmarx = &uap->dmarx; 807 struct dma_async_tx_descriptor *desc; 808 struct pl011_sgbuf *sgbuf; 809 810 if (!rxchan) 811 return -EIO; 812 813 /* Start the RX DMA job */ 814 sgbuf = uap->dmarx.use_buf_b ? 815 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 816 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, 817 DMA_DEV_TO_MEM, 818 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 819 /* 820 * If the DMA engine is busy and cannot prepare a 821 * channel, no big deal, the driver will fall back 822 * to interrupt mode as a result of this error code. 823 */ 824 if (!desc) { 825 uap->dmarx.running = false; 826 dmaengine_terminate_all(rxchan); 827 return -EBUSY; 828 } 829 830 /* Some data to go along to the callback */ 831 desc->callback = pl011_dma_rx_callback; 832 desc->callback_param = uap; 833 dmarx->cookie = dmaengine_submit(desc); 834 dma_async_issue_pending(rxchan); 835 836 uap->dmacr |= UART011_RXDMAE; 837 pl011_write(uap->dmacr, uap, REG_DMACR); 838 uap->dmarx.running = true; 839 840 uap->im &= ~UART011_RXIM; 841 pl011_write(uap->im, uap, REG_IMSC); 842 843 return 0; 844 } 845 846 /* 847 * This is called when either the DMA job is complete, or 848 * the FIFO timeout interrupt occurred. This must be called 849 * with the port spinlock uap->port.lock held. 850 */ 851 static void pl011_dma_rx_chars(struct uart_amba_port *uap, 852 u32 pending, bool use_buf_b, 853 bool readfifo) 854 { 855 struct tty_port *port = &uap->port.state->port; 856 struct pl011_sgbuf *sgbuf = use_buf_b ? 857 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 858 int dma_count = 0; 859 u32 fifotaken = 0; /* only used for vdbg() */ 860 861 struct pl011_dmarx_data *dmarx = &uap->dmarx; 862 int dmataken = 0; 863 864 if (uap->dmarx.poll_rate) { 865 /* The data can be taken by polling */ 866 dmataken = sgbuf->sg.length - dmarx->last_residue; 867 /* Recalculate the pending size */ 868 if (pending >= dmataken) 869 pending -= dmataken; 870 } 871 872 /* Pick the remain data from the DMA */ 873 if (pending) { 874 875 /* 876 * First take all chars in the DMA pipe, then look in the FIFO. 877 * Note that tty_insert_flip_buf() tries to take as many chars 878 * as it can. 879 */ 880 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 881 pending); 882 883 uap->port.icount.rx += dma_count; 884 if (dma_count < pending) 885 dev_warn(uap->port.dev, 886 "couldn't insert all characters (TTY is full?)\n"); 887 } 888 889 /* Reset the last_residue for Rx DMA poll */ 890 if (uap->dmarx.poll_rate) 891 dmarx->last_residue = sgbuf->sg.length; 892 893 /* 894 * Only continue with trying to read the FIFO if all DMA chars have 895 * been taken first. 896 */ 897 if (dma_count == pending && readfifo) { 898 /* Clear any error flags */ 899 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 900 UART011_FEIS, uap, REG_ICR); 901 902 /* 903 * If we read all the DMA'd characters, and we had an 904 * incomplete buffer, that could be due to an rx error, or 905 * maybe we just timed out. Read any pending chars and check 906 * the error status. 907 * 908 * Error conditions will only occur in the FIFO, these will 909 * trigger an immediate interrupt and stop the DMA job, so we 910 * will always find the error in the FIFO, never in the DMA 911 * buffer. 912 */ 913 fifotaken = pl011_fifo_to_tty(uap); 914 } 915 916 spin_unlock(&uap->port.lock); 917 dev_vdbg(uap->port.dev, 918 "Took %d chars from DMA buffer and %d chars from the FIFO\n", 919 dma_count, fifotaken); 920 tty_flip_buffer_push(port); 921 spin_lock(&uap->port.lock); 922 } 923 924 static void pl011_dma_rx_irq(struct uart_amba_port *uap) 925 { 926 struct pl011_dmarx_data *dmarx = &uap->dmarx; 927 struct dma_chan *rxchan = dmarx->chan; 928 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 929 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 930 size_t pending; 931 struct dma_tx_state state; 932 enum dma_status dmastat; 933 934 /* 935 * Pause the transfer so we can trust the current counter, 936 * do this before we pause the PL011 block, else we may 937 * overflow the FIFO. 938 */ 939 if (dmaengine_pause(rxchan)) 940 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 941 dmastat = rxchan->device->device_tx_status(rxchan, 942 dmarx->cookie, &state); 943 if (dmastat != DMA_PAUSED) 944 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); 945 946 /* Disable RX DMA - incoming data will wait in the FIFO */ 947 uap->dmacr &= ~UART011_RXDMAE; 948 pl011_write(uap->dmacr, uap, REG_DMACR); 949 uap->dmarx.running = false; 950 951 pending = sgbuf->sg.length - state.residue; 952 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 953 /* Then we terminate the transfer - we now know our residue */ 954 dmaengine_terminate_all(rxchan); 955 956 /* 957 * This will take the chars we have so far and insert 958 * into the framework. 959 */ 960 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); 961 962 /* Switch buffer & re-trigger DMA job */ 963 dmarx->use_buf_b = !dmarx->use_buf_b; 964 if (pl011_dma_rx_trigger_dma(uap)) { 965 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 966 "fall back to interrupt mode\n"); 967 uap->im |= UART011_RXIM; 968 pl011_write(uap->im, uap, REG_IMSC); 969 } 970 } 971 972 static void pl011_dma_rx_callback(void *data) 973 { 974 struct uart_amba_port *uap = data; 975 struct pl011_dmarx_data *dmarx = &uap->dmarx; 976 struct dma_chan *rxchan = dmarx->chan; 977 bool lastbuf = dmarx->use_buf_b; 978 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? 979 &dmarx->sgbuf_b : &dmarx->sgbuf_a; 980 size_t pending; 981 struct dma_tx_state state; 982 int ret; 983 984 /* 985 * This completion interrupt occurs typically when the 986 * RX buffer is totally stuffed but no timeout has yet 987 * occurred. When that happens, we just want the RX 988 * routine to flush out the secondary DMA buffer while 989 * we immediately trigger the next DMA job. 990 */ 991 spin_lock_irq(&uap->port.lock); 992 /* 993 * Rx data can be taken by the UART interrupts during 994 * the DMA irq handler. So we check the residue here. 995 */ 996 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 997 pending = sgbuf->sg.length - state.residue; 998 BUG_ON(pending > PL011_DMA_BUFFER_SIZE); 999 /* Then we terminate the transfer - we now know our residue */ 1000 dmaengine_terminate_all(rxchan); 1001 1002 uap->dmarx.running = false; 1003 dmarx->use_buf_b = !lastbuf; 1004 ret = pl011_dma_rx_trigger_dma(uap); 1005 1006 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1007 spin_unlock_irq(&uap->port.lock); 1008 /* 1009 * Do this check after we picked the DMA chars so we don't 1010 * get some IRQ immediately from RX. 1011 */ 1012 if (ret) { 1013 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " 1014 "fall back to interrupt mode\n"); 1015 uap->im |= UART011_RXIM; 1016 pl011_write(uap->im, uap, REG_IMSC); 1017 } 1018 } 1019 1020 /* 1021 * Stop accepting received characters, when we're shutting down or 1022 * suspending this port. 1023 * Locking: called with port lock held and IRQs disabled. 1024 */ 1025 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1026 { 1027 /* FIXME. Just disable the DMA enable */ 1028 uap->dmacr &= ~UART011_RXDMAE; 1029 pl011_write(uap->dmacr, uap, REG_DMACR); 1030 } 1031 1032 /* 1033 * Timer handler for Rx DMA polling. 1034 * Every polling, It checks the residue in the dma buffer and transfer 1035 * data to the tty. Also, last_residue is updated for the next polling. 1036 */ 1037 static void pl011_dma_rx_poll(unsigned long args) 1038 { 1039 struct uart_amba_port *uap = (struct uart_amba_port *)args; 1040 struct tty_port *port = &uap->port.state->port; 1041 struct pl011_dmarx_data *dmarx = &uap->dmarx; 1042 struct dma_chan *rxchan = uap->dmarx.chan; 1043 unsigned long flags = 0; 1044 unsigned int dmataken = 0; 1045 unsigned int size = 0; 1046 struct pl011_sgbuf *sgbuf; 1047 int dma_count; 1048 struct dma_tx_state state; 1049 1050 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; 1051 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); 1052 if (likely(state.residue < dmarx->last_residue)) { 1053 dmataken = sgbuf->sg.length - dmarx->last_residue; 1054 size = dmarx->last_residue - state.residue; 1055 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, 1056 size); 1057 if (dma_count == size) 1058 dmarx->last_residue = state.residue; 1059 dmarx->last_jiffies = jiffies; 1060 } 1061 tty_flip_buffer_push(port); 1062 1063 /* 1064 * If no data is received in poll_timeout, the driver will fall back 1065 * to interrupt mode. We will retrigger DMA at the first interrupt. 1066 */ 1067 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1068 > uap->dmarx.poll_timeout) { 1069 1070 spin_lock_irqsave(&uap->port.lock, flags); 1071 pl011_dma_rx_stop(uap); 1072 uap->im |= UART011_RXIM; 1073 pl011_write(uap->im, uap, REG_IMSC); 1074 spin_unlock_irqrestore(&uap->port.lock, flags); 1075 1076 uap->dmarx.running = false; 1077 dmaengine_terminate_all(rxchan); 1078 del_timer(&uap->dmarx.timer); 1079 } else { 1080 mod_timer(&uap->dmarx.timer, 1081 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); 1082 } 1083 } 1084 1085 static void pl011_dma_startup(struct uart_amba_port *uap) 1086 { 1087 int ret; 1088 1089 if (!uap->dma_probed) 1090 pl011_dma_probe(uap); 1091 1092 if (!uap->dmatx.chan) 1093 return; 1094 1095 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); 1096 if (!uap->dmatx.buf) { 1097 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); 1098 uap->port.fifosize = uap->fifosize; 1099 return; 1100 } 1101 1102 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); 1103 1104 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 1105 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; 1106 uap->using_tx_dma = true; 1107 1108 if (!uap->dmarx.chan) 1109 goto skip_rx; 1110 1111 /* Allocate and map DMA RX buffers */ 1112 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1113 DMA_FROM_DEVICE); 1114 if (ret) { 1115 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1116 "RX buffer A", ret); 1117 goto skip_rx; 1118 } 1119 1120 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, 1121 DMA_FROM_DEVICE); 1122 if (ret) { 1123 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", 1124 "RX buffer B", ret); 1125 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, 1126 DMA_FROM_DEVICE); 1127 goto skip_rx; 1128 } 1129 1130 uap->using_rx_dma = true; 1131 1132 skip_rx: 1133 /* Turn on DMA error (RX/TX will be enabled on demand) */ 1134 uap->dmacr |= UART011_DMAONERR; 1135 pl011_write(uap->dmacr, uap, REG_DMACR); 1136 1137 /* 1138 * ST Micro variants has some specific dma burst threshold 1139 * compensation. Set this to 16 bytes, so burst will only 1140 * be issued above/below 16 bytes. 1141 */ 1142 if (uap->vendor->dma_threshold) 1143 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, 1144 uap, REG_ST_DMAWM); 1145 1146 if (uap->using_rx_dma) { 1147 if (pl011_dma_rx_trigger_dma(uap)) 1148 dev_dbg(uap->port.dev, "could not trigger initial " 1149 "RX DMA job, fall back to interrupt mode\n"); 1150 if (uap->dmarx.poll_rate) { 1151 init_timer(&(uap->dmarx.timer)); 1152 uap->dmarx.timer.function = pl011_dma_rx_poll; 1153 uap->dmarx.timer.data = (unsigned long)uap; 1154 mod_timer(&uap->dmarx.timer, 1155 jiffies + 1156 msecs_to_jiffies(uap->dmarx.poll_rate)); 1157 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1158 uap->dmarx.last_jiffies = jiffies; 1159 } 1160 } 1161 } 1162 1163 static void pl011_dma_shutdown(struct uart_amba_port *uap) 1164 { 1165 if (!(uap->using_tx_dma || uap->using_rx_dma)) 1166 return; 1167 1168 /* Disable RX and TX DMA */ 1169 while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY) 1170 barrier(); 1171 1172 spin_lock_irq(&uap->port.lock); 1173 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1174 pl011_write(uap->dmacr, uap, REG_DMACR); 1175 spin_unlock_irq(&uap->port.lock); 1176 1177 if (uap->using_tx_dma) { 1178 /* In theory, this should already be done by pl011_dma_flush_buffer */ 1179 dmaengine_terminate_all(uap->dmatx.chan); 1180 if (uap->dmatx.queued) { 1181 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, 1182 DMA_TO_DEVICE); 1183 uap->dmatx.queued = false; 1184 } 1185 1186 kfree(uap->dmatx.buf); 1187 uap->using_tx_dma = false; 1188 } 1189 1190 if (uap->using_rx_dma) { 1191 dmaengine_terminate_all(uap->dmarx.chan); 1192 /* Clean up the RX DMA */ 1193 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); 1194 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); 1195 if (uap->dmarx.poll_rate) 1196 del_timer_sync(&uap->dmarx.timer); 1197 uap->using_rx_dma = false; 1198 } 1199 } 1200 1201 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1202 { 1203 return uap->using_rx_dma; 1204 } 1205 1206 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1207 { 1208 return uap->using_rx_dma && uap->dmarx.running; 1209 } 1210 1211 #else 1212 /* Blank functions if the DMA engine is not available */ 1213 static inline void pl011_dma_probe(struct uart_amba_port *uap) 1214 { 1215 } 1216 1217 static inline void pl011_dma_remove(struct uart_amba_port *uap) 1218 { 1219 } 1220 1221 static inline void pl011_dma_startup(struct uart_amba_port *uap) 1222 { 1223 } 1224 1225 static inline void pl011_dma_shutdown(struct uart_amba_port *uap) 1226 { 1227 } 1228 1229 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) 1230 { 1231 return false; 1232 } 1233 1234 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) 1235 { 1236 } 1237 1238 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) 1239 { 1240 return false; 1241 } 1242 1243 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) 1244 { 1245 } 1246 1247 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) 1248 { 1249 } 1250 1251 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) 1252 { 1253 return -EIO; 1254 } 1255 1256 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) 1257 { 1258 return false; 1259 } 1260 1261 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) 1262 { 1263 return false; 1264 } 1265 1266 #define pl011_dma_flush_buffer NULL 1267 #endif 1268 1269 static void pl011_stop_tx(struct uart_port *port) 1270 { 1271 struct uart_amba_port *uap = 1272 container_of(port, struct uart_amba_port, port); 1273 1274 uap->im &= ~UART011_TXIM; 1275 pl011_write(uap->im, uap, REG_IMSC); 1276 pl011_dma_tx_stop(uap); 1277 } 1278 1279 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); 1280 1281 /* Start TX with programmed I/O only (no DMA) */ 1282 static void pl011_start_tx_pio(struct uart_amba_port *uap) 1283 { 1284 uap->im |= UART011_TXIM; 1285 pl011_write(uap->im, uap, REG_IMSC); 1286 pl011_tx_chars(uap, false); 1287 } 1288 1289 static void pl011_start_tx(struct uart_port *port) 1290 { 1291 struct uart_amba_port *uap = 1292 container_of(port, struct uart_amba_port, port); 1293 1294 if (!pl011_dma_tx_start(uap)) 1295 pl011_start_tx_pio(uap); 1296 } 1297 1298 static void pl011_stop_rx(struct uart_port *port) 1299 { 1300 struct uart_amba_port *uap = 1301 container_of(port, struct uart_amba_port, port); 1302 1303 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| 1304 UART011_PEIM|UART011_BEIM|UART011_OEIM); 1305 pl011_write(uap->im, uap, REG_IMSC); 1306 1307 pl011_dma_rx_stop(uap); 1308 } 1309 1310 static void pl011_enable_ms(struct uart_port *port) 1311 { 1312 struct uart_amba_port *uap = 1313 container_of(port, struct uart_amba_port, port); 1314 1315 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; 1316 pl011_write(uap->im, uap, REG_IMSC); 1317 } 1318 1319 static void pl011_rx_chars(struct uart_amba_port *uap) 1320 __releases(&uap->port.lock) 1321 __acquires(&uap->port.lock) 1322 { 1323 pl011_fifo_to_tty(uap); 1324 1325 spin_unlock(&uap->port.lock); 1326 tty_flip_buffer_push(&uap->port.state->port); 1327 /* 1328 * If we were temporarily out of DMA mode for a while, 1329 * attempt to switch back to DMA mode again. 1330 */ 1331 if (pl011_dma_rx_available(uap)) { 1332 if (pl011_dma_rx_trigger_dma(uap)) { 1333 dev_dbg(uap->port.dev, "could not trigger RX DMA job " 1334 "fall back to interrupt mode again\n"); 1335 uap->im |= UART011_RXIM; 1336 pl011_write(uap->im, uap, REG_IMSC); 1337 } else { 1338 #ifdef CONFIG_DMA_ENGINE 1339 /* Start Rx DMA poll */ 1340 if (uap->dmarx.poll_rate) { 1341 uap->dmarx.last_jiffies = jiffies; 1342 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; 1343 mod_timer(&uap->dmarx.timer, 1344 jiffies + 1345 msecs_to_jiffies(uap->dmarx.poll_rate)); 1346 } 1347 #endif 1348 } 1349 } 1350 spin_lock(&uap->port.lock); 1351 } 1352 1353 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, 1354 bool from_irq) 1355 { 1356 if (unlikely(!from_irq) && 1357 pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1358 return false; /* unable to transmit character */ 1359 1360 pl011_write(c, uap, REG_DR); 1361 uap->port.icount.tx++; 1362 1363 return true; 1364 } 1365 1366 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) 1367 { 1368 struct circ_buf *xmit = &uap->port.state->xmit; 1369 int count = uap->fifosize >> 1; 1370 1371 if (uap->port.x_char) { 1372 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) 1373 return; 1374 uap->port.x_char = 0; 1375 --count; 1376 } 1377 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 1378 pl011_stop_tx(&uap->port); 1379 return; 1380 } 1381 1382 /* If we are using DMA mode, try to send some characters. */ 1383 if (pl011_dma_tx_irq(uap)) 1384 return; 1385 1386 do { 1387 if (likely(from_irq) && count-- == 0) 1388 break; 1389 1390 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) 1391 break; 1392 1393 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1394 } while (!uart_circ_empty(xmit)); 1395 1396 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1397 uart_write_wakeup(&uap->port); 1398 1399 if (uart_circ_empty(xmit)) 1400 pl011_stop_tx(&uap->port); 1401 } 1402 1403 static void pl011_modem_status(struct uart_amba_port *uap) 1404 { 1405 unsigned int status, delta; 1406 1407 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1408 1409 delta = status ^ uap->old_status; 1410 uap->old_status = status; 1411 1412 if (!delta) 1413 return; 1414 1415 if (delta & UART01x_FR_DCD) 1416 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 1417 1418 if (delta & UART01x_FR_DSR) 1419 uap->port.icount.dsr++; 1420 1421 if (delta & UART01x_FR_CTS) 1422 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 1423 1424 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 1425 } 1426 1427 static void check_apply_cts_event_workaround(struct uart_amba_port *uap) 1428 { 1429 unsigned int dummy_read; 1430 1431 if (!uap->vendor->cts_event_workaround) 1432 return; 1433 1434 /* workaround to make sure that all bits are unlocked.. */ 1435 pl011_write(0x00, uap, REG_ICR); 1436 1437 /* 1438 * WA: introduce 26ns(1 uart clk) delay before W1C; 1439 * single apb access will incur 2 pclk(133.12Mhz) delay, 1440 * so add 2 dummy reads 1441 */ 1442 dummy_read = pl011_read(uap, REG_ICR); 1443 dummy_read = pl011_read(uap, REG_ICR); 1444 } 1445 1446 static irqreturn_t pl011_int(int irq, void *dev_id) 1447 { 1448 struct uart_amba_port *uap = dev_id; 1449 unsigned long flags; 1450 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1451 u16 imsc; 1452 int handled = 0; 1453 1454 spin_lock_irqsave(&uap->port.lock, flags); 1455 imsc = pl011_read(uap, REG_IMSC); 1456 status = pl011_read(uap, REG_RIS) & imsc; 1457 if (status) { 1458 do { 1459 check_apply_cts_event_workaround(uap); 1460 1461 pl011_write(status & ~(UART011_TXIS|UART011_RTIS| 1462 UART011_RXIS), 1463 uap, REG_ICR); 1464 1465 if (status & (UART011_RTIS|UART011_RXIS)) { 1466 if (pl011_dma_rx_running(uap)) 1467 pl011_dma_rx_irq(uap); 1468 else 1469 pl011_rx_chars(uap); 1470 } 1471 if (status & (UART011_DSRMIS|UART011_DCDMIS| 1472 UART011_CTSMIS|UART011_RIMIS)) 1473 pl011_modem_status(uap); 1474 if (status & UART011_TXIS) 1475 pl011_tx_chars(uap, true); 1476 1477 if (pass_counter-- == 0) 1478 break; 1479 1480 status = pl011_read(uap, REG_RIS) & imsc; 1481 } while (status != 0); 1482 handled = 1; 1483 } 1484 1485 spin_unlock_irqrestore(&uap->port.lock, flags); 1486 1487 return IRQ_RETVAL(handled); 1488 } 1489 1490 static unsigned int pl011_tx_empty(struct uart_port *port) 1491 { 1492 struct uart_amba_port *uap = 1493 container_of(port, struct uart_amba_port, port); 1494 unsigned int status = pl011_read(uap, REG_FR); 1495 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; 1496 } 1497 1498 static unsigned int pl011_get_mctrl(struct uart_port *port) 1499 { 1500 struct uart_amba_port *uap = 1501 container_of(port, struct uart_amba_port, port); 1502 unsigned int result = 0; 1503 unsigned int status = pl011_read(uap, REG_FR); 1504 1505 #define TIOCMBIT(uartbit, tiocmbit) \ 1506 if (status & uartbit) \ 1507 result |= tiocmbit 1508 1509 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); 1510 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); 1511 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); 1512 TIOCMBIT(UART011_FR_RI, TIOCM_RNG); 1513 #undef TIOCMBIT 1514 return result; 1515 } 1516 1517 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) 1518 { 1519 struct uart_amba_port *uap = 1520 container_of(port, struct uart_amba_port, port); 1521 unsigned int cr; 1522 1523 cr = pl011_read(uap, REG_CR); 1524 1525 #define TIOCMBIT(tiocmbit, uartbit) \ 1526 if (mctrl & tiocmbit) \ 1527 cr |= uartbit; \ 1528 else \ 1529 cr &= ~uartbit 1530 1531 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); 1532 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); 1533 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); 1534 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); 1535 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); 1536 1537 if (uap->autorts) { 1538 /* We need to disable auto-RTS if we want to turn RTS off */ 1539 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); 1540 } 1541 #undef TIOCMBIT 1542 1543 pl011_write(cr, uap, REG_CR); 1544 } 1545 1546 static void pl011_break_ctl(struct uart_port *port, int break_state) 1547 { 1548 struct uart_amba_port *uap = 1549 container_of(port, struct uart_amba_port, port); 1550 unsigned long flags; 1551 unsigned int lcr_h; 1552 1553 spin_lock_irqsave(&uap->port.lock, flags); 1554 lcr_h = pl011_read(uap, REG_LCRH_TX); 1555 if (break_state == -1) 1556 lcr_h |= UART01x_LCRH_BRK; 1557 else 1558 lcr_h &= ~UART01x_LCRH_BRK; 1559 pl011_write(lcr_h, uap, REG_LCRH_TX); 1560 spin_unlock_irqrestore(&uap->port.lock, flags); 1561 } 1562 1563 #ifdef CONFIG_CONSOLE_POLL 1564 1565 static void pl011_quiesce_irqs(struct uart_port *port) 1566 { 1567 struct uart_amba_port *uap = 1568 container_of(port, struct uart_amba_port, port); 1569 1570 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); 1571 /* 1572 * There is no way to clear TXIM as this is "ready to transmit IRQ", so 1573 * we simply mask it. start_tx() will unmask it. 1574 * 1575 * Note we can race with start_tx(), and if the race happens, the 1576 * polling user might get another interrupt just after we clear it. 1577 * But it should be OK and can happen even w/o the race, e.g. 1578 * controller immediately got some new data and raised the IRQ. 1579 * 1580 * And whoever uses polling routines assumes that it manages the device 1581 * (including tx queue), so we're also fine with start_tx()'s caller 1582 * side. 1583 */ 1584 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, 1585 REG_IMSC); 1586 } 1587 1588 static int pl011_get_poll_char(struct uart_port *port) 1589 { 1590 struct uart_amba_port *uap = 1591 container_of(port, struct uart_amba_port, port); 1592 unsigned int status; 1593 1594 /* 1595 * The caller might need IRQs lowered, e.g. if used with KDB NMI 1596 * debugger. 1597 */ 1598 pl011_quiesce_irqs(port); 1599 1600 status = pl011_read(uap, REG_FR); 1601 if (status & UART01x_FR_RXFE) 1602 return NO_POLL_CHAR; 1603 1604 return pl011_read(uap, REG_DR); 1605 } 1606 1607 static void pl011_put_poll_char(struct uart_port *port, 1608 unsigned char ch) 1609 { 1610 struct uart_amba_port *uap = 1611 container_of(port, struct uart_amba_port, port); 1612 1613 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 1614 barrier(); 1615 1616 pl011_write(ch, uap, REG_DR); 1617 } 1618 1619 #endif /* CONFIG_CONSOLE_POLL */ 1620 1621 static int pl011_hwinit(struct uart_port *port) 1622 { 1623 struct uart_amba_port *uap = 1624 container_of(port, struct uart_amba_port, port); 1625 int retval; 1626 1627 /* Optionaly enable pins to be muxed in and configured */ 1628 pinctrl_pm_select_default_state(port->dev); 1629 1630 /* 1631 * Try to enable the clock producer. 1632 */ 1633 retval = clk_prepare_enable(uap->clk); 1634 if (retval) 1635 return retval; 1636 1637 uap->port.uartclk = clk_get_rate(uap->clk); 1638 1639 /* Clear pending error and receive interrupts */ 1640 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | 1641 UART011_FEIS | UART011_RTIS | UART011_RXIS, 1642 uap, REG_ICR); 1643 1644 /* 1645 * Save interrupts enable mask, and enable RX interrupts in case if 1646 * the interrupt is used for NMI entry. 1647 */ 1648 uap->im = pl011_read(uap, REG_IMSC); 1649 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); 1650 1651 if (dev_get_platdata(uap->port.dev)) { 1652 struct amba_pl011_data *plat; 1653 1654 plat = dev_get_platdata(uap->port.dev); 1655 if (plat->init) 1656 plat->init(); 1657 } 1658 return 0; 1659 } 1660 1661 static bool pl011_split_lcrh(const struct uart_amba_port *uap) 1662 { 1663 return pl011_reg_to_offset(uap, REG_LCRH_RX) != 1664 pl011_reg_to_offset(uap, REG_LCRH_TX); 1665 } 1666 1667 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) 1668 { 1669 pl011_write(lcr_h, uap, REG_LCRH_RX); 1670 if (pl011_split_lcrh(uap)) { 1671 int i; 1672 /* 1673 * Wait 10 PCLKs before writing LCRH_TX register, 1674 * to get this delay write read only register 10 times 1675 */ 1676 for (i = 0; i < 10; ++i) 1677 pl011_write(0xff, uap, REG_MIS); 1678 pl011_write(lcr_h, uap, REG_LCRH_TX); 1679 } 1680 } 1681 1682 static int pl011_allocate_irq(struct uart_amba_port *uap) 1683 { 1684 pl011_write(uap->im, uap, REG_IMSC); 1685 1686 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); 1687 } 1688 1689 /* 1690 * Enable interrupts, only timeouts when using DMA 1691 * if initial RX DMA job failed, start in interrupt mode 1692 * as well. 1693 */ 1694 static void pl011_enable_interrupts(struct uart_amba_port *uap) 1695 { 1696 spin_lock_irq(&uap->port.lock); 1697 1698 /* Clear out any spuriously appearing RX interrupts */ 1699 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); 1700 uap->im = UART011_RTIM; 1701 if (!pl011_dma_rx_running(uap)) 1702 uap->im |= UART011_RXIM; 1703 pl011_write(uap->im, uap, REG_IMSC); 1704 spin_unlock_irq(&uap->port.lock); 1705 } 1706 1707 static int pl011_startup(struct uart_port *port) 1708 { 1709 struct uart_amba_port *uap = 1710 container_of(port, struct uart_amba_port, port); 1711 unsigned int cr; 1712 int retval; 1713 1714 retval = pl011_hwinit(port); 1715 if (retval) 1716 goto clk_dis; 1717 1718 retval = pl011_allocate_irq(uap); 1719 if (retval) 1720 goto clk_dis; 1721 1722 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1723 1724 spin_lock_irq(&uap->port.lock); 1725 1726 /* restore RTS and DTR */ 1727 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); 1728 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; 1729 pl011_write(cr, uap, REG_CR); 1730 1731 spin_unlock_irq(&uap->port.lock); 1732 1733 /* 1734 * initialise the old status of the modem signals 1735 */ 1736 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; 1737 1738 /* Startup DMA */ 1739 pl011_dma_startup(uap); 1740 1741 pl011_enable_interrupts(uap); 1742 1743 return 0; 1744 1745 clk_dis: 1746 clk_disable_unprepare(uap->clk); 1747 return retval; 1748 } 1749 1750 static int sbsa_uart_startup(struct uart_port *port) 1751 { 1752 struct uart_amba_port *uap = 1753 container_of(port, struct uart_amba_port, port); 1754 int retval; 1755 1756 retval = pl011_hwinit(port); 1757 if (retval) 1758 return retval; 1759 1760 retval = pl011_allocate_irq(uap); 1761 if (retval) 1762 return retval; 1763 1764 /* The SBSA UART does not support any modem status lines. */ 1765 uap->old_status = 0; 1766 1767 pl011_enable_interrupts(uap); 1768 1769 return 0; 1770 } 1771 1772 static void pl011_shutdown_channel(struct uart_amba_port *uap, 1773 unsigned int lcrh) 1774 { 1775 unsigned long val; 1776 1777 val = pl011_read(uap, lcrh); 1778 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); 1779 pl011_write(val, uap, lcrh); 1780 } 1781 1782 /* 1783 * disable the port. It should not disable RTS and DTR. 1784 * Also RTS and DTR state should be preserved to restore 1785 * it during startup(). 1786 */ 1787 static void pl011_disable_uart(struct uart_amba_port *uap) 1788 { 1789 unsigned int cr; 1790 1791 uap->autorts = false; 1792 spin_lock_irq(&uap->port.lock); 1793 cr = pl011_read(uap, REG_CR); 1794 uap->old_cr = cr; 1795 cr &= UART011_CR_RTS | UART011_CR_DTR; 1796 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1797 pl011_write(cr, uap, REG_CR); 1798 spin_unlock_irq(&uap->port.lock); 1799 1800 /* 1801 * disable break condition and fifos 1802 */ 1803 pl011_shutdown_channel(uap, REG_LCRH_RX); 1804 if (pl011_split_lcrh(uap)) 1805 pl011_shutdown_channel(uap, REG_LCRH_TX); 1806 } 1807 1808 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1809 { 1810 spin_lock_irq(&uap->port.lock); 1811 1812 /* mask all interrupts and clear all pending ones */ 1813 uap->im = 0; 1814 pl011_write(uap->im, uap, REG_IMSC); 1815 pl011_write(0xffff, uap, REG_ICR); 1816 1817 spin_unlock_irq(&uap->port.lock); 1818 } 1819 1820 static void pl011_shutdown(struct uart_port *port) 1821 { 1822 struct uart_amba_port *uap = 1823 container_of(port, struct uart_amba_port, port); 1824 1825 pl011_disable_interrupts(uap); 1826 1827 pl011_dma_shutdown(uap); 1828 1829 free_irq(uap->port.irq, uap); 1830 1831 pl011_disable_uart(uap); 1832 1833 /* 1834 * Shut down the clock producer 1835 */ 1836 clk_disable_unprepare(uap->clk); 1837 /* Optionally let pins go into sleep states */ 1838 pinctrl_pm_select_sleep_state(port->dev); 1839 1840 if (dev_get_platdata(uap->port.dev)) { 1841 struct amba_pl011_data *plat; 1842 1843 plat = dev_get_platdata(uap->port.dev); 1844 if (plat->exit) 1845 plat->exit(); 1846 } 1847 1848 if (uap->port.ops->flush_buffer) 1849 uap->port.ops->flush_buffer(port); 1850 } 1851 1852 static void sbsa_uart_shutdown(struct uart_port *port) 1853 { 1854 struct uart_amba_port *uap = 1855 container_of(port, struct uart_amba_port, port); 1856 1857 pl011_disable_interrupts(uap); 1858 1859 free_irq(uap->port.irq, uap); 1860 1861 if (uap->port.ops->flush_buffer) 1862 uap->port.ops->flush_buffer(port); 1863 } 1864 1865 static void 1866 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) 1867 { 1868 port->read_status_mask = UART011_DR_OE | 255; 1869 if (termios->c_iflag & INPCK) 1870 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; 1871 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1872 port->read_status_mask |= UART011_DR_BE; 1873 1874 /* 1875 * Characters to ignore 1876 */ 1877 port->ignore_status_mask = 0; 1878 if (termios->c_iflag & IGNPAR) 1879 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; 1880 if (termios->c_iflag & IGNBRK) { 1881 port->ignore_status_mask |= UART011_DR_BE; 1882 /* 1883 * If we're ignoring parity and break indicators, 1884 * ignore overruns too (for real raw support). 1885 */ 1886 if (termios->c_iflag & IGNPAR) 1887 port->ignore_status_mask |= UART011_DR_OE; 1888 } 1889 1890 /* 1891 * Ignore all characters if CREAD is not set. 1892 */ 1893 if ((termios->c_cflag & CREAD) == 0) 1894 port->ignore_status_mask |= UART_DUMMY_DR_RX; 1895 } 1896 1897 static void 1898 pl011_set_termios(struct uart_port *port, struct ktermios *termios, 1899 struct ktermios *old) 1900 { 1901 struct uart_amba_port *uap = 1902 container_of(port, struct uart_amba_port, port); 1903 unsigned int lcr_h, old_cr; 1904 unsigned long flags; 1905 unsigned int baud, quot, clkdiv; 1906 1907 if (uap->vendor->oversampling) 1908 clkdiv = 8; 1909 else 1910 clkdiv = 16; 1911 1912 /* 1913 * Ask the core to calculate the divisor for us. 1914 */ 1915 baud = uart_get_baud_rate(port, termios, old, 0, 1916 port->uartclk / clkdiv); 1917 #ifdef CONFIG_DMA_ENGINE 1918 /* 1919 * Adjust RX DMA polling rate with baud rate if not specified. 1920 */ 1921 if (uap->dmarx.auto_poll_rate) 1922 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); 1923 #endif 1924 1925 if (baud > port->uartclk/16) 1926 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); 1927 else 1928 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); 1929 1930 switch (termios->c_cflag & CSIZE) { 1931 case CS5: 1932 lcr_h = UART01x_LCRH_WLEN_5; 1933 break; 1934 case CS6: 1935 lcr_h = UART01x_LCRH_WLEN_6; 1936 break; 1937 case CS7: 1938 lcr_h = UART01x_LCRH_WLEN_7; 1939 break; 1940 default: // CS8 1941 lcr_h = UART01x_LCRH_WLEN_8; 1942 break; 1943 } 1944 if (termios->c_cflag & CSTOPB) 1945 lcr_h |= UART01x_LCRH_STP2; 1946 if (termios->c_cflag & PARENB) { 1947 lcr_h |= UART01x_LCRH_PEN; 1948 if (!(termios->c_cflag & PARODD)) 1949 lcr_h |= UART01x_LCRH_EPS; 1950 } 1951 if (uap->fifosize > 1) 1952 lcr_h |= UART01x_LCRH_FEN; 1953 1954 spin_lock_irqsave(&port->lock, flags); 1955 1956 /* 1957 * Update the per-port timeout. 1958 */ 1959 uart_update_timeout(port, termios->c_cflag, baud); 1960 1961 pl011_setup_status_masks(port, termios); 1962 1963 if (UART_ENABLE_MS(port, termios->c_cflag)) 1964 pl011_enable_ms(port); 1965 1966 /* first, disable everything */ 1967 old_cr = pl011_read(uap, REG_CR); 1968 pl011_write(0, uap, REG_CR); 1969 1970 if (termios->c_cflag & CRTSCTS) { 1971 if (old_cr & UART011_CR_RTS) 1972 old_cr |= UART011_CR_RTSEN; 1973 1974 old_cr |= UART011_CR_CTSEN; 1975 uap->autorts = true; 1976 } else { 1977 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); 1978 uap->autorts = false; 1979 } 1980 1981 if (uap->vendor->oversampling) { 1982 if (baud > port->uartclk / 16) 1983 old_cr |= ST_UART011_CR_OVSFACT; 1984 else 1985 old_cr &= ~ST_UART011_CR_OVSFACT; 1986 } 1987 1988 /* 1989 * Workaround for the ST Micro oversampling variants to 1990 * increase the bitrate slightly, by lowering the divisor, 1991 * to avoid delayed sampling of start bit at high speeds, 1992 * else we see data corruption. 1993 */ 1994 if (uap->vendor->oversampling) { 1995 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) 1996 quot -= 1; 1997 else if ((baud > 3250000) && (quot > 2)) 1998 quot -= 2; 1999 } 2000 /* Set baud rate */ 2001 pl011_write(quot & 0x3f, uap, REG_FBRD); 2002 pl011_write(quot >> 6, uap, REG_IBRD); 2003 2004 /* 2005 * ----------v----------v----------v----------v----- 2006 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER 2007 * REG_FBRD & REG_IBRD. 2008 * ----------^----------^----------^----------^----- 2009 */ 2010 pl011_write_lcr_h(uap, lcr_h); 2011 pl011_write(old_cr, uap, REG_CR); 2012 2013 spin_unlock_irqrestore(&port->lock, flags); 2014 } 2015 2016 static void 2017 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, 2018 struct ktermios *old) 2019 { 2020 struct uart_amba_port *uap = 2021 container_of(port, struct uart_amba_port, port); 2022 unsigned long flags; 2023 2024 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); 2025 2026 /* The SBSA UART only supports 8n1 without hardware flow control. */ 2027 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 2028 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2029 termios->c_cflag |= CS8 | CLOCAL; 2030 2031 spin_lock_irqsave(&port->lock, flags); 2032 uart_update_timeout(port, CS8, uap->fixed_baud); 2033 pl011_setup_status_masks(port, termios); 2034 spin_unlock_irqrestore(&port->lock, flags); 2035 } 2036 2037 static const char *pl011_type(struct uart_port *port) 2038 { 2039 struct uart_amba_port *uap = 2040 container_of(port, struct uart_amba_port, port); 2041 return uap->port.type == PORT_AMBA ? uap->type : NULL; 2042 } 2043 2044 /* 2045 * Release the memory region(s) being used by 'port' 2046 */ 2047 static void pl011_release_port(struct uart_port *port) 2048 { 2049 release_mem_region(port->mapbase, SZ_4K); 2050 } 2051 2052 /* 2053 * Request the memory region(s) being used by 'port' 2054 */ 2055 static int pl011_request_port(struct uart_port *port) 2056 { 2057 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") 2058 != NULL ? 0 : -EBUSY; 2059 } 2060 2061 /* 2062 * Configure/autoconfigure the port. 2063 */ 2064 static void pl011_config_port(struct uart_port *port, int flags) 2065 { 2066 if (flags & UART_CONFIG_TYPE) { 2067 port->type = PORT_AMBA; 2068 pl011_request_port(port); 2069 } 2070 } 2071 2072 /* 2073 * verify the new serial_struct (for TIOCSSERIAL). 2074 */ 2075 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) 2076 { 2077 int ret = 0; 2078 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 2079 ret = -EINVAL; 2080 if (ser->irq < 0 || ser->irq >= nr_irqs) 2081 ret = -EINVAL; 2082 if (ser->baud_base < 9600) 2083 ret = -EINVAL; 2084 return ret; 2085 } 2086 2087 static struct uart_ops amba_pl011_pops = { 2088 .tx_empty = pl011_tx_empty, 2089 .set_mctrl = pl011_set_mctrl, 2090 .get_mctrl = pl011_get_mctrl, 2091 .stop_tx = pl011_stop_tx, 2092 .start_tx = pl011_start_tx, 2093 .stop_rx = pl011_stop_rx, 2094 .enable_ms = pl011_enable_ms, 2095 .break_ctl = pl011_break_ctl, 2096 .startup = pl011_startup, 2097 .shutdown = pl011_shutdown, 2098 .flush_buffer = pl011_dma_flush_buffer, 2099 .set_termios = pl011_set_termios, 2100 .type = pl011_type, 2101 .release_port = pl011_release_port, 2102 .request_port = pl011_request_port, 2103 .config_port = pl011_config_port, 2104 .verify_port = pl011_verify_port, 2105 #ifdef CONFIG_CONSOLE_POLL 2106 .poll_init = pl011_hwinit, 2107 .poll_get_char = pl011_get_poll_char, 2108 .poll_put_char = pl011_put_poll_char, 2109 #endif 2110 }; 2111 2112 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 2113 { 2114 } 2115 2116 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) 2117 { 2118 return 0; 2119 } 2120 2121 static const struct uart_ops sbsa_uart_pops = { 2122 .tx_empty = pl011_tx_empty, 2123 .set_mctrl = sbsa_uart_set_mctrl, 2124 .get_mctrl = sbsa_uart_get_mctrl, 2125 .stop_tx = pl011_stop_tx, 2126 .start_tx = pl011_start_tx, 2127 .stop_rx = pl011_stop_rx, 2128 .startup = sbsa_uart_startup, 2129 .shutdown = sbsa_uart_shutdown, 2130 .set_termios = sbsa_uart_set_termios, 2131 .type = pl011_type, 2132 .release_port = pl011_release_port, 2133 .request_port = pl011_request_port, 2134 .config_port = pl011_config_port, 2135 .verify_port = pl011_verify_port, 2136 #ifdef CONFIG_CONSOLE_POLL 2137 .poll_init = pl011_hwinit, 2138 .poll_get_char = pl011_get_poll_char, 2139 .poll_put_char = pl011_put_poll_char, 2140 #endif 2141 }; 2142 2143 static struct uart_amba_port *amba_ports[UART_NR]; 2144 2145 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE 2146 2147 static void pl011_console_putchar(struct uart_port *port, int ch) 2148 { 2149 struct uart_amba_port *uap = 2150 container_of(port, struct uart_amba_port, port); 2151 2152 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) 2153 barrier(); 2154 pl011_write(ch, uap, REG_DR); 2155 } 2156 2157 static void 2158 pl011_console_write(struct console *co, const char *s, unsigned int count) 2159 { 2160 struct uart_amba_port *uap = amba_ports[co->index]; 2161 unsigned int status, old_cr = 0, new_cr; 2162 unsigned long flags; 2163 int locked = 1; 2164 2165 clk_enable(uap->clk); 2166 2167 local_irq_save(flags); 2168 if (uap->port.sysrq) 2169 locked = 0; 2170 else if (oops_in_progress) 2171 locked = spin_trylock(&uap->port.lock); 2172 else 2173 spin_lock(&uap->port.lock); 2174 2175 /* 2176 * First save the CR then disable the interrupts 2177 */ 2178 if (!uap->vendor->always_enabled) { 2179 old_cr = pl011_read(uap, REG_CR); 2180 new_cr = old_cr & ~UART011_CR_CTSEN; 2181 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 2182 pl011_write(new_cr, uap, REG_CR); 2183 } 2184 2185 uart_console_write(&uap->port, s, count, pl011_console_putchar); 2186 2187 /* 2188 * Finally, wait for transmitter to become empty 2189 * and restore the TCR 2190 */ 2191 do { 2192 status = pl011_read(uap, REG_FR); 2193 } while (status & UART01x_FR_BUSY); 2194 if (!uap->vendor->always_enabled) 2195 pl011_write(old_cr, uap, REG_CR); 2196 2197 if (locked) 2198 spin_unlock(&uap->port.lock); 2199 local_irq_restore(flags); 2200 2201 clk_disable(uap->clk); 2202 } 2203 2204 static void __init 2205 pl011_console_get_options(struct uart_amba_port *uap, int *baud, 2206 int *parity, int *bits) 2207 { 2208 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { 2209 unsigned int lcr_h, ibrd, fbrd; 2210 2211 lcr_h = pl011_read(uap, REG_LCRH_TX); 2212 2213 *parity = 'n'; 2214 if (lcr_h & UART01x_LCRH_PEN) { 2215 if (lcr_h & UART01x_LCRH_EPS) 2216 *parity = 'e'; 2217 else 2218 *parity = 'o'; 2219 } 2220 2221 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 2222 *bits = 7; 2223 else 2224 *bits = 8; 2225 2226 ibrd = pl011_read(uap, REG_IBRD); 2227 fbrd = pl011_read(uap, REG_FBRD); 2228 2229 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); 2230 2231 if (uap->vendor->oversampling) { 2232 if (pl011_read(uap, REG_CR) 2233 & ST_UART011_CR_OVSFACT) 2234 *baud *= 2; 2235 } 2236 } 2237 } 2238 2239 static int __init pl011_console_setup(struct console *co, char *options) 2240 { 2241 struct uart_amba_port *uap; 2242 int baud = 38400; 2243 int bits = 8; 2244 int parity = 'n'; 2245 int flow = 'n'; 2246 int ret; 2247 2248 /* 2249 * Check whether an invalid uart number has been specified, and 2250 * if so, search for the first available port that does have 2251 * console support. 2252 */ 2253 if (co->index >= UART_NR) 2254 co->index = 0; 2255 uap = amba_ports[co->index]; 2256 if (!uap) 2257 return -ENODEV; 2258 2259 /* Allow pins to be muxed in and configured */ 2260 pinctrl_pm_select_default_state(uap->port.dev); 2261 2262 ret = clk_prepare(uap->clk); 2263 if (ret) 2264 return ret; 2265 2266 if (dev_get_platdata(uap->port.dev)) { 2267 struct amba_pl011_data *plat; 2268 2269 plat = dev_get_platdata(uap->port.dev); 2270 if (plat->init) 2271 plat->init(); 2272 } 2273 2274 uap->port.uartclk = clk_get_rate(uap->clk); 2275 2276 if (uap->vendor->fixed_options) { 2277 baud = uap->fixed_baud; 2278 } else { 2279 if (options) 2280 uart_parse_options(options, 2281 &baud, &parity, &bits, &flow); 2282 else 2283 pl011_console_get_options(uap, &baud, &parity, &bits); 2284 } 2285 2286 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 2287 } 2288 2289 static struct uart_driver amba_reg; 2290 static struct console amba_console = { 2291 .name = "ttyAMA", 2292 .write = pl011_console_write, 2293 .device = uart_console_device, 2294 .setup = pl011_console_setup, 2295 .flags = CON_PRINTBUFFER, 2296 .index = -1, 2297 .data = &amba_reg, 2298 }; 2299 2300 #define AMBA_CONSOLE (&amba_console) 2301 2302 static void pl011_putc(struct uart_port *port, int c) 2303 { 2304 while (readl(port->membase + REG_FR) & UART01x_FR_TXFF) 2305 ; 2306 writeb(c, port->membase + REG_DR); 2307 while (readl(port->membase + REG_FR) & UART01x_FR_BUSY) 2308 ; 2309 } 2310 2311 static void pl011_early_write(struct console *con, const char *s, unsigned n) 2312 { 2313 struct earlycon_device *dev = con->data; 2314 2315 uart_console_write(&dev->port, s, n, pl011_putc); 2316 } 2317 2318 static int __init pl011_early_console_setup(struct earlycon_device *device, 2319 const char *opt) 2320 { 2321 if (!device->port.membase) 2322 return -ENODEV; 2323 2324 device->con->write = pl011_early_write; 2325 return 0; 2326 } 2327 EARLYCON_DECLARE(pl011, pl011_early_console_setup); 2328 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); 2329 2330 #else 2331 #define AMBA_CONSOLE NULL 2332 #endif 2333 2334 static struct uart_driver amba_reg = { 2335 .owner = THIS_MODULE, 2336 .driver_name = "ttyAMA", 2337 .dev_name = "ttyAMA", 2338 .major = SERIAL_AMBA_MAJOR, 2339 .minor = SERIAL_AMBA_MINOR, 2340 .nr = UART_NR, 2341 .cons = AMBA_CONSOLE, 2342 }; 2343 2344 static int pl011_probe_dt_alias(int index, struct device *dev) 2345 { 2346 struct device_node *np; 2347 static bool seen_dev_with_alias = false; 2348 static bool seen_dev_without_alias = false; 2349 int ret = index; 2350 2351 if (!IS_ENABLED(CONFIG_OF)) 2352 return ret; 2353 2354 np = dev->of_node; 2355 if (!np) 2356 return ret; 2357 2358 ret = of_alias_get_id(np, "serial"); 2359 if (IS_ERR_VALUE(ret)) { 2360 seen_dev_without_alias = true; 2361 ret = index; 2362 } else { 2363 seen_dev_with_alias = true; 2364 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { 2365 dev_warn(dev, "requested serial port %d not available.\n", ret); 2366 ret = index; 2367 } 2368 } 2369 2370 if (seen_dev_with_alias && seen_dev_without_alias) 2371 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); 2372 2373 return ret; 2374 } 2375 2376 /* unregisters the driver also if no more ports are left */ 2377 static void pl011_unregister_port(struct uart_amba_port *uap) 2378 { 2379 int i; 2380 bool busy = false; 2381 2382 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { 2383 if (amba_ports[i] == uap) 2384 amba_ports[i] = NULL; 2385 else if (amba_ports[i]) 2386 busy = true; 2387 } 2388 pl011_dma_remove(uap); 2389 if (!busy) 2390 uart_unregister_driver(&amba_reg); 2391 } 2392 2393 static int pl011_find_free_port(void) 2394 { 2395 int i; 2396 2397 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 2398 if (amba_ports[i] == NULL) 2399 return i; 2400 2401 return -EBUSY; 2402 } 2403 2404 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, 2405 struct resource *mmiobase, int index) 2406 { 2407 void __iomem *base; 2408 2409 base = devm_ioremap_resource(dev, mmiobase); 2410 if (IS_ERR(base)) 2411 return PTR_ERR(base); 2412 2413 index = pl011_probe_dt_alias(index, dev); 2414 2415 uap->old_cr = 0; 2416 uap->port.dev = dev; 2417 uap->port.mapbase = mmiobase->start; 2418 uap->port.membase = base; 2419 uap->port.iotype = UPIO_MEM; 2420 uap->port.fifosize = uap->fifosize; 2421 uap->port.flags = UPF_BOOT_AUTOCONF; 2422 uap->port.line = index; 2423 2424 amba_ports[index] = uap; 2425 2426 return 0; 2427 } 2428 2429 static int pl011_register_port(struct uart_amba_port *uap) 2430 { 2431 int ret; 2432 2433 /* Ensure interrupts from this UART are masked and cleared */ 2434 pl011_write(0, uap, REG_IMSC); 2435 pl011_write(0xffff, uap, REG_ICR); 2436 2437 if (!amba_reg.state) { 2438 ret = uart_register_driver(&amba_reg); 2439 if (ret < 0) { 2440 dev_err(uap->port.dev, 2441 "Failed to register AMBA-PL011 driver\n"); 2442 return ret; 2443 } 2444 } 2445 2446 ret = uart_add_one_port(&amba_reg, &uap->port); 2447 if (ret) 2448 pl011_unregister_port(uap); 2449 2450 return ret; 2451 } 2452 2453 static int pl011_probe(struct amba_device *dev, const struct amba_id *id) 2454 { 2455 struct uart_amba_port *uap; 2456 struct vendor_data *vendor = id->data; 2457 int portnr, ret; 2458 2459 portnr = pl011_find_free_port(); 2460 if (portnr < 0) 2461 return portnr; 2462 2463 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), 2464 GFP_KERNEL); 2465 if (!uap) 2466 return -ENOMEM; 2467 2468 uap->clk = devm_clk_get(&dev->dev, NULL); 2469 if (IS_ERR(uap->clk)) 2470 return PTR_ERR(uap->clk); 2471 2472 uap->reg_offset = vendor->reg_offset; 2473 uap->access_32b = vendor->access_32b; 2474 uap->vendor = vendor; 2475 uap->fifosize = vendor->get_fifosize(dev); 2476 uap->port.irq = dev->irq[0]; 2477 uap->port.ops = &amba_pl011_pops; 2478 2479 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); 2480 2481 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); 2482 if (ret) 2483 return ret; 2484 2485 amba_set_drvdata(dev, uap); 2486 2487 return pl011_register_port(uap); 2488 } 2489 2490 static int pl011_remove(struct amba_device *dev) 2491 { 2492 struct uart_amba_port *uap = amba_get_drvdata(dev); 2493 2494 uart_remove_one_port(&amba_reg, &uap->port); 2495 pl011_unregister_port(uap); 2496 return 0; 2497 } 2498 2499 #ifdef CONFIG_PM_SLEEP 2500 static int pl011_suspend(struct device *dev) 2501 { 2502 struct uart_amba_port *uap = dev_get_drvdata(dev); 2503 2504 if (!uap) 2505 return -EINVAL; 2506 2507 return uart_suspend_port(&amba_reg, &uap->port); 2508 } 2509 2510 static int pl011_resume(struct device *dev) 2511 { 2512 struct uart_amba_port *uap = dev_get_drvdata(dev); 2513 2514 if (!uap) 2515 return -EINVAL; 2516 2517 return uart_resume_port(&amba_reg, &uap->port); 2518 } 2519 #endif 2520 2521 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); 2522 2523 static int sbsa_uart_probe(struct platform_device *pdev) 2524 { 2525 struct uart_amba_port *uap; 2526 struct resource *r; 2527 int portnr, ret; 2528 int baudrate; 2529 2530 /* 2531 * Check the mandatory baud rate parameter in the DT node early 2532 * so that we can easily exit with the error. 2533 */ 2534 if (pdev->dev.of_node) { 2535 struct device_node *np = pdev->dev.of_node; 2536 2537 ret = of_property_read_u32(np, "current-speed", &baudrate); 2538 if (ret) 2539 return ret; 2540 } else { 2541 baudrate = 115200; 2542 } 2543 2544 portnr = pl011_find_free_port(); 2545 if (portnr < 0) 2546 return portnr; 2547 2548 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), 2549 GFP_KERNEL); 2550 if (!uap) 2551 return -ENOMEM; 2552 2553 uap->reg_offset = vendor_sbsa.reg_offset; 2554 uap->access_32b = vendor_sbsa.access_32b; 2555 uap->vendor = &vendor_sbsa; 2556 uap->fifosize = 32; 2557 uap->port.irq = platform_get_irq(pdev, 0); 2558 uap->port.ops = &sbsa_uart_pops; 2559 uap->fixed_baud = baudrate; 2560 2561 snprintf(uap->type, sizeof(uap->type), "SBSA"); 2562 2563 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2564 2565 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); 2566 if (ret) 2567 return ret; 2568 2569 platform_set_drvdata(pdev, uap); 2570 2571 return pl011_register_port(uap); 2572 } 2573 2574 static int sbsa_uart_remove(struct platform_device *pdev) 2575 { 2576 struct uart_amba_port *uap = platform_get_drvdata(pdev); 2577 2578 uart_remove_one_port(&amba_reg, &uap->port); 2579 pl011_unregister_port(uap); 2580 return 0; 2581 } 2582 2583 static const struct of_device_id sbsa_uart_of_match[] = { 2584 { .compatible = "arm,sbsa-uart", }, 2585 {}, 2586 }; 2587 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); 2588 2589 static const struct acpi_device_id sbsa_uart_acpi_match[] = { 2590 { "ARMH0011", 0 }, 2591 {}, 2592 }; 2593 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); 2594 2595 static struct platform_driver arm_sbsa_uart_platform_driver = { 2596 .probe = sbsa_uart_probe, 2597 .remove = sbsa_uart_remove, 2598 .driver = { 2599 .name = "sbsa-uart", 2600 .of_match_table = of_match_ptr(sbsa_uart_of_match), 2601 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), 2602 }, 2603 }; 2604 2605 static struct amba_id pl011_ids[] = { 2606 { 2607 .id = 0x00041011, 2608 .mask = 0x000fffff, 2609 .data = &vendor_arm, 2610 }, 2611 { 2612 .id = 0x00380802, 2613 .mask = 0x00ffffff, 2614 .data = &vendor_st, 2615 }, 2616 { 0, 0 }, 2617 }; 2618 2619 MODULE_DEVICE_TABLE(amba, pl011_ids); 2620 2621 static struct amba_driver pl011_driver = { 2622 .drv = { 2623 .name = "uart-pl011", 2624 .pm = &pl011_dev_pm_ops, 2625 }, 2626 .id_table = pl011_ids, 2627 .probe = pl011_probe, 2628 .remove = pl011_remove, 2629 }; 2630 2631 static int __init pl011_init(void) 2632 { 2633 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); 2634 2635 if (platform_driver_register(&arm_sbsa_uart_platform_driver)) 2636 pr_warn("could not register SBSA UART platform driver\n"); 2637 return amba_driver_register(&pl011_driver); 2638 } 2639 2640 static void __exit pl011_exit(void) 2641 { 2642 platform_driver_unregister(&arm_sbsa_uart_platform_driver); 2643 amba_driver_unregister(&pl011_driver); 2644 } 2645 2646 /* 2647 * While this can be a module, if builtin it's most likely the console 2648 * So let's leave module_exit but move module_init to an earlier place 2649 */ 2650 arch_initcall(pl011_init); 2651 module_exit(pl011_exit); 2652 2653 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 2654 MODULE_DESCRIPTION("ARM AMBA serial port driver"); 2655 MODULE_LICENSE("GPL"); 2656