1 /* 2 * Base port operations for 8250/16550-type serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * Split from 8250_core.c, Copyright (C) 2001 Russell King. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * A note about mapbase / membase 13 * 14 * mapbase is the physical address of the IO port. 15 * membase is an 'ioremapped' cookie. 16 */ 17 18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 #define SUPPORT_SYSRQ 20 #endif 21 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/ioport.h> 25 #include <linux/init.h> 26 #include <linux/console.h> 27 #include <linux/sysrq.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/tty.h> 31 #include <linux/ratelimit.h> 32 #include <linux/tty_flip.h> 33 #include <linux/serial.h> 34 #include <linux/serial_8250.h> 35 #include <linux/nmi.h> 36 #include <linux/mutex.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pm_runtime.h> 40 41 #include <asm/io.h> 42 #include <asm/irq.h> 43 44 #include "8250.h" 45 46 /* 47 * Debugging. 48 */ 49 #if 0 50 #define DEBUG_AUTOCONF(fmt...) printk(fmt) 51 #else 52 #define DEBUG_AUTOCONF(fmt...) do { } while (0) 53 #endif 54 55 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 56 57 /* 58 * Here we define the default xmit fifo size used for each type of UART. 59 */ 60 static const struct serial8250_config uart_config[] = { 61 [PORT_UNKNOWN] = { 62 .name = "unknown", 63 .fifo_size = 1, 64 .tx_loadsz = 1, 65 }, 66 [PORT_8250] = { 67 .name = "8250", 68 .fifo_size = 1, 69 .tx_loadsz = 1, 70 }, 71 [PORT_16450] = { 72 .name = "16450", 73 .fifo_size = 1, 74 .tx_loadsz = 1, 75 }, 76 [PORT_16550] = { 77 .name = "16550", 78 .fifo_size = 1, 79 .tx_loadsz = 1, 80 }, 81 [PORT_16550A] = { 82 .name = "16550A", 83 .fifo_size = 16, 84 .tx_loadsz = 16, 85 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 86 .rxtrig_bytes = {1, 4, 8, 14}, 87 .flags = UART_CAP_FIFO, 88 }, 89 [PORT_CIRRUS] = { 90 .name = "Cirrus", 91 .fifo_size = 1, 92 .tx_loadsz = 1, 93 }, 94 [PORT_16650] = { 95 .name = "ST16650", 96 .fifo_size = 1, 97 .tx_loadsz = 1, 98 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 99 }, 100 [PORT_16650V2] = { 101 .name = "ST16650V2", 102 .fifo_size = 32, 103 .tx_loadsz = 16, 104 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 105 UART_FCR_T_TRIG_00, 106 .rxtrig_bytes = {8, 16, 24, 28}, 107 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 108 }, 109 [PORT_16750] = { 110 .name = "TI16750", 111 .fifo_size = 64, 112 .tx_loadsz = 64, 113 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 114 UART_FCR7_64BYTE, 115 .rxtrig_bytes = {1, 16, 32, 56}, 116 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, 117 }, 118 [PORT_STARTECH] = { 119 .name = "Startech", 120 .fifo_size = 1, 121 .tx_loadsz = 1, 122 }, 123 [PORT_16C950] = { 124 .name = "16C950/954", 125 .fifo_size = 128, 126 .tx_loadsz = 128, 127 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 128 /* UART_CAP_EFR breaks billionon CF bluetooth card. */ 129 .flags = UART_CAP_FIFO | UART_CAP_SLEEP, 130 }, 131 [PORT_16654] = { 132 .name = "ST16654", 133 .fifo_size = 64, 134 .tx_loadsz = 32, 135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 136 UART_FCR_T_TRIG_10, 137 .rxtrig_bytes = {8, 16, 56, 60}, 138 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 139 }, 140 [PORT_16850] = { 141 .name = "XR16850", 142 .fifo_size = 128, 143 .tx_loadsz = 128, 144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 145 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 146 }, 147 [PORT_RSA] = { 148 .name = "RSA", 149 .fifo_size = 2048, 150 .tx_loadsz = 2048, 151 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, 152 .flags = UART_CAP_FIFO, 153 }, 154 [PORT_NS16550A] = { 155 .name = "NS16550A", 156 .fifo_size = 16, 157 .tx_loadsz = 16, 158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 159 .flags = UART_CAP_FIFO | UART_NATSEMI, 160 }, 161 [PORT_XSCALE] = { 162 .name = "XScale", 163 .fifo_size = 32, 164 .tx_loadsz = 32, 165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 166 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, 167 }, 168 [PORT_OCTEON] = { 169 .name = "OCTEON", 170 .fifo_size = 64, 171 .tx_loadsz = 64, 172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 173 .flags = UART_CAP_FIFO, 174 }, 175 [PORT_AR7] = { 176 .name = "AR7", 177 .fifo_size = 16, 178 .tx_loadsz = 16, 179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, 180 .flags = UART_CAP_FIFO | UART_CAP_AFE, 181 }, 182 [PORT_U6_16550A] = { 183 .name = "U6_16550A", 184 .fifo_size = 64, 185 .tx_loadsz = 64, 186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 187 .flags = UART_CAP_FIFO | UART_CAP_AFE, 188 }, 189 [PORT_TEGRA] = { 190 .name = "Tegra", 191 .fifo_size = 32, 192 .tx_loadsz = 8, 193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 194 UART_FCR_T_TRIG_01, 195 .rxtrig_bytes = {1, 4, 8, 14}, 196 .flags = UART_CAP_FIFO | UART_CAP_RTOIE, 197 }, 198 [PORT_XR17D15X] = { 199 .name = "XR17D15X", 200 .fifo_size = 64, 201 .tx_loadsz = 64, 202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 203 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | 204 UART_CAP_SLEEP, 205 }, 206 [PORT_XR17V35X] = { 207 .name = "XR17V35X", 208 .fifo_size = 256, 209 .tx_loadsz = 256, 210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 | 211 UART_FCR_T_TRIG_11, 212 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | 213 UART_CAP_SLEEP, 214 }, 215 [PORT_LPC3220] = { 216 .name = "LPC3220", 217 .fifo_size = 64, 218 .tx_loadsz = 32, 219 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | 220 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00, 221 .flags = UART_CAP_FIFO, 222 }, 223 [PORT_BRCM_TRUMANAGE] = { 224 .name = "TruManage", 225 .fifo_size = 1, 226 .tx_loadsz = 1024, 227 .flags = UART_CAP_HFIFO, 228 }, 229 [PORT_8250_CIR] = { 230 .name = "CIR port" 231 }, 232 [PORT_ALTR_16550_F32] = { 233 .name = "Altera 16550 FIFO32", 234 .fifo_size = 32, 235 .tx_loadsz = 32, 236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 237 .flags = UART_CAP_FIFO | UART_CAP_AFE, 238 }, 239 [PORT_ALTR_16550_F64] = { 240 .name = "Altera 16550 FIFO64", 241 .fifo_size = 64, 242 .tx_loadsz = 64, 243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 244 .flags = UART_CAP_FIFO | UART_CAP_AFE, 245 }, 246 [PORT_ALTR_16550_F128] = { 247 .name = "Altera 16550 FIFO128", 248 .fifo_size = 128, 249 .tx_loadsz = 128, 250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 251 .flags = UART_CAP_FIFO | UART_CAP_AFE, 252 }, 253 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement 254 workaround of errata A-008006 which states that tx_loadsz should be 255 configured less than Maximum supported fifo bytes */ 256 [PORT_16550A_FSL64] = { 257 .name = "16550A_FSL64", 258 .fifo_size = 64, 259 .tx_loadsz = 63, 260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 261 UART_FCR7_64BYTE, 262 .flags = UART_CAP_FIFO, 263 }, 264 [PORT_RT2880] = { 265 .name = "Palmchip BK-3103", 266 .fifo_size = 16, 267 .tx_loadsz = 16, 268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 269 .rxtrig_bytes = {1, 4, 8, 14}, 270 .flags = UART_CAP_FIFO, 271 }, 272 }; 273 274 /* Uart divisor latch read */ 275 static int default_serial_dl_read(struct uart_8250_port *up) 276 { 277 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8; 278 } 279 280 /* Uart divisor latch write */ 281 static void default_serial_dl_write(struct uart_8250_port *up, int value) 282 { 283 serial_out(up, UART_DLL, value & 0xff); 284 serial_out(up, UART_DLM, value >> 8 & 0xff); 285 } 286 287 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) 288 289 /* Au1x00/RT288x UART hardware has a weird register layout */ 290 static const s8 au_io_in_map[8] = { 291 0, /* UART_RX */ 292 2, /* UART_IER */ 293 3, /* UART_IIR */ 294 5, /* UART_LCR */ 295 6, /* UART_MCR */ 296 7, /* UART_LSR */ 297 8, /* UART_MSR */ 298 -1, /* UART_SCR (unmapped) */ 299 }; 300 301 static const s8 au_io_out_map[8] = { 302 1, /* UART_TX */ 303 2, /* UART_IER */ 304 4, /* UART_FCR */ 305 5, /* UART_LCR */ 306 6, /* UART_MCR */ 307 -1, /* UART_LSR (unmapped) */ 308 -1, /* UART_MSR (unmapped) */ 309 -1, /* UART_SCR (unmapped) */ 310 }; 311 312 static unsigned int au_serial_in(struct uart_port *p, int offset) 313 { 314 if (offset >= ARRAY_SIZE(au_io_in_map)) 315 return UINT_MAX; 316 offset = au_io_in_map[offset]; 317 if (offset < 0) 318 return UINT_MAX; 319 return __raw_readl(p->membase + (offset << p->regshift)); 320 } 321 322 static void au_serial_out(struct uart_port *p, int offset, int value) 323 { 324 if (offset >= ARRAY_SIZE(au_io_out_map)) 325 return; 326 offset = au_io_out_map[offset]; 327 if (offset < 0) 328 return; 329 __raw_writel(value, p->membase + (offset << p->regshift)); 330 } 331 332 /* Au1x00 haven't got a standard divisor latch */ 333 static int au_serial_dl_read(struct uart_8250_port *up) 334 { 335 return __raw_readl(up->port.membase + 0x28); 336 } 337 338 static void au_serial_dl_write(struct uart_8250_port *up, int value) 339 { 340 __raw_writel(value, up->port.membase + 0x28); 341 } 342 343 #endif 344 345 static unsigned int hub6_serial_in(struct uart_port *p, int offset) 346 { 347 offset = offset << p->regshift; 348 outb(p->hub6 - 1 + offset, p->iobase); 349 return inb(p->iobase + 1); 350 } 351 352 static void hub6_serial_out(struct uart_port *p, int offset, int value) 353 { 354 offset = offset << p->regshift; 355 outb(p->hub6 - 1 + offset, p->iobase); 356 outb(value, p->iobase + 1); 357 } 358 359 static unsigned int mem_serial_in(struct uart_port *p, int offset) 360 { 361 offset = offset << p->regshift; 362 return readb(p->membase + offset); 363 } 364 365 static void mem_serial_out(struct uart_port *p, int offset, int value) 366 { 367 offset = offset << p->regshift; 368 writeb(value, p->membase + offset); 369 } 370 371 static void mem32_serial_out(struct uart_port *p, int offset, int value) 372 { 373 offset = offset << p->regshift; 374 writel(value, p->membase + offset); 375 } 376 377 static unsigned int mem32_serial_in(struct uart_port *p, int offset) 378 { 379 offset = offset << p->regshift; 380 return readl(p->membase + offset); 381 } 382 383 static void mem32be_serial_out(struct uart_port *p, int offset, int value) 384 { 385 offset = offset << p->regshift; 386 iowrite32be(value, p->membase + offset); 387 } 388 389 static unsigned int mem32be_serial_in(struct uart_port *p, int offset) 390 { 391 offset = offset << p->regshift; 392 return ioread32be(p->membase + offset); 393 } 394 395 static unsigned int io_serial_in(struct uart_port *p, int offset) 396 { 397 offset = offset << p->regshift; 398 return inb(p->iobase + offset); 399 } 400 401 static void io_serial_out(struct uart_port *p, int offset, int value) 402 { 403 offset = offset << p->regshift; 404 outb(value, p->iobase + offset); 405 } 406 407 static int serial8250_default_handle_irq(struct uart_port *port); 408 static int exar_handle_irq(struct uart_port *port); 409 410 static void set_io_from_upio(struct uart_port *p) 411 { 412 struct uart_8250_port *up = up_to_u8250p(p); 413 414 up->dl_read = default_serial_dl_read; 415 up->dl_write = default_serial_dl_write; 416 417 switch (p->iotype) { 418 case UPIO_HUB6: 419 p->serial_in = hub6_serial_in; 420 p->serial_out = hub6_serial_out; 421 break; 422 423 case UPIO_MEM: 424 p->serial_in = mem_serial_in; 425 p->serial_out = mem_serial_out; 426 break; 427 428 case UPIO_MEM32: 429 p->serial_in = mem32_serial_in; 430 p->serial_out = mem32_serial_out; 431 break; 432 433 case UPIO_MEM32BE: 434 p->serial_in = mem32be_serial_in; 435 p->serial_out = mem32be_serial_out; 436 break; 437 438 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) 439 case UPIO_AU: 440 p->serial_in = au_serial_in; 441 p->serial_out = au_serial_out; 442 up->dl_read = au_serial_dl_read; 443 up->dl_write = au_serial_dl_write; 444 break; 445 #endif 446 447 default: 448 p->serial_in = io_serial_in; 449 p->serial_out = io_serial_out; 450 break; 451 } 452 /* Remember loaded iotype */ 453 up->cur_iotype = p->iotype; 454 p->handle_irq = serial8250_default_handle_irq; 455 } 456 457 static void 458 serial_port_out_sync(struct uart_port *p, int offset, int value) 459 { 460 switch (p->iotype) { 461 case UPIO_MEM: 462 case UPIO_MEM32: 463 case UPIO_MEM32BE: 464 case UPIO_AU: 465 p->serial_out(p, offset, value); 466 p->serial_in(p, UART_LCR); /* safe, no side-effects */ 467 break; 468 default: 469 p->serial_out(p, offset, value); 470 } 471 } 472 473 /* 474 * For the 16C950 475 */ 476 static void serial_icr_write(struct uart_8250_port *up, int offset, int value) 477 { 478 serial_out(up, UART_SCR, offset); 479 serial_out(up, UART_ICR, value); 480 } 481 482 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) 483 { 484 unsigned int value; 485 486 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); 487 serial_out(up, UART_SCR, offset); 488 value = serial_in(up, UART_ICR); 489 serial_icr_write(up, UART_ACR, up->acr); 490 491 return value; 492 } 493 494 /* 495 * FIFO support. 496 */ 497 static void serial8250_clear_fifos(struct uart_8250_port *p) 498 { 499 if (p->capabilities & UART_CAP_FIFO) { 500 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); 501 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | 502 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 503 serial_out(p, UART_FCR, 0); 504 } 505 } 506 507 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) 508 { 509 serial8250_clear_fifos(p); 510 serial_out(p, UART_FCR, p->fcr); 511 } 512 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); 513 514 void serial8250_rpm_get(struct uart_8250_port *p) 515 { 516 if (!(p->capabilities & UART_CAP_RPM)) 517 return; 518 pm_runtime_get_sync(p->port.dev); 519 } 520 EXPORT_SYMBOL_GPL(serial8250_rpm_get); 521 522 void serial8250_rpm_put(struct uart_8250_port *p) 523 { 524 if (!(p->capabilities & UART_CAP_RPM)) 525 return; 526 pm_runtime_mark_last_busy(p->port.dev); 527 pm_runtime_put_autosuspend(p->port.dev); 528 } 529 EXPORT_SYMBOL_GPL(serial8250_rpm_put); 530 531 /* 532 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than 533 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is 534 * empty and the HW can idle again. 535 */ 536 static void serial8250_rpm_get_tx(struct uart_8250_port *p) 537 { 538 unsigned char rpm_active; 539 540 if (!(p->capabilities & UART_CAP_RPM)) 541 return; 542 543 rpm_active = xchg(&p->rpm_tx_active, 1); 544 if (rpm_active) 545 return; 546 pm_runtime_get_sync(p->port.dev); 547 } 548 549 static void serial8250_rpm_put_tx(struct uart_8250_port *p) 550 { 551 unsigned char rpm_active; 552 553 if (!(p->capabilities & UART_CAP_RPM)) 554 return; 555 556 rpm_active = xchg(&p->rpm_tx_active, 0); 557 if (!rpm_active) 558 return; 559 pm_runtime_mark_last_busy(p->port.dev); 560 pm_runtime_put_autosuspend(p->port.dev); 561 } 562 563 /* 564 * IER sleep support. UARTs which have EFRs need the "extended 565 * capability" bit enabled. Note that on XR16C850s, we need to 566 * reset LCR to write to IER. 567 */ 568 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) 569 { 570 unsigned char lcr = 0, efr = 0; 571 /* 572 * Exar UARTs have a SLEEP register that enables or disables 573 * each UART to enter sleep mode separately. On the XR17V35x the 574 * register is accessible to each UART at the UART_EXAR_SLEEP 575 * offset but the UART channel may only write to the corresponding 576 * bit. 577 */ 578 serial8250_rpm_get(p); 579 if ((p->port.type == PORT_XR17V35X) || 580 (p->port.type == PORT_XR17D15X)) { 581 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0); 582 goto out; 583 } 584 585 if (p->capabilities & UART_CAP_SLEEP) { 586 if (p->capabilities & UART_CAP_EFR) { 587 lcr = serial_in(p, UART_LCR); 588 efr = serial_in(p, UART_EFR); 589 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); 590 serial_out(p, UART_EFR, UART_EFR_ECB); 591 serial_out(p, UART_LCR, 0); 592 } 593 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); 594 if (p->capabilities & UART_CAP_EFR) { 595 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); 596 serial_out(p, UART_EFR, efr); 597 serial_out(p, UART_LCR, lcr); 598 } 599 } 600 out: 601 serial8250_rpm_put(p); 602 } 603 604 #ifdef CONFIG_SERIAL_8250_RSA 605 /* 606 * Attempts to turn on the RSA FIFO. Returns zero on failure. 607 * We set the port uart clock rate if we succeed. 608 */ 609 static int __enable_rsa(struct uart_8250_port *up) 610 { 611 unsigned char mode; 612 int result; 613 614 mode = serial_in(up, UART_RSA_MSR); 615 result = mode & UART_RSA_MSR_FIFO; 616 617 if (!result) { 618 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); 619 mode = serial_in(up, UART_RSA_MSR); 620 result = mode & UART_RSA_MSR_FIFO; 621 } 622 623 if (result) 624 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; 625 626 return result; 627 } 628 629 static void enable_rsa(struct uart_8250_port *up) 630 { 631 if (up->port.type == PORT_RSA) { 632 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 633 spin_lock_irq(&up->port.lock); 634 __enable_rsa(up); 635 spin_unlock_irq(&up->port.lock); 636 } 637 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 638 serial_out(up, UART_RSA_FRR, 0); 639 } 640 } 641 642 /* 643 * Attempts to turn off the RSA FIFO. Returns zero on failure. 644 * It is unknown why interrupts were disabled in here. However, 645 * the caller is expected to preserve this behaviour by grabbing 646 * the spinlock before calling this function. 647 */ 648 static void disable_rsa(struct uart_8250_port *up) 649 { 650 unsigned char mode; 651 int result; 652 653 if (up->port.type == PORT_RSA && 654 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 655 spin_lock_irq(&up->port.lock); 656 657 mode = serial_in(up, UART_RSA_MSR); 658 result = !(mode & UART_RSA_MSR_FIFO); 659 660 if (!result) { 661 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); 662 mode = serial_in(up, UART_RSA_MSR); 663 result = !(mode & UART_RSA_MSR_FIFO); 664 } 665 666 if (result) 667 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 668 spin_unlock_irq(&up->port.lock); 669 } 670 } 671 #endif /* CONFIG_SERIAL_8250_RSA */ 672 673 /* 674 * This is a quickie test to see how big the FIFO is. 675 * It doesn't work at all the time, more's the pity. 676 */ 677 static int size_fifo(struct uart_8250_port *up) 678 { 679 unsigned char old_fcr, old_mcr, old_lcr; 680 unsigned short old_dl; 681 int count; 682 683 old_lcr = serial_in(up, UART_LCR); 684 serial_out(up, UART_LCR, 0); 685 old_fcr = serial_in(up, UART_FCR); 686 old_mcr = serial_in(up, UART_MCR); 687 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 688 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 689 serial_out(up, UART_MCR, UART_MCR_LOOP); 690 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 691 old_dl = serial_dl_read(up); 692 serial_dl_write(up, 0x0001); 693 serial_out(up, UART_LCR, 0x03); 694 for (count = 0; count < 256; count++) 695 serial_out(up, UART_TX, count); 696 mdelay(20);/* FIXME - schedule_timeout */ 697 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && 698 (count < 256); count++) 699 serial_in(up, UART_RX); 700 serial_out(up, UART_FCR, old_fcr); 701 serial_out(up, UART_MCR, old_mcr); 702 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 703 serial_dl_write(up, old_dl); 704 serial_out(up, UART_LCR, old_lcr); 705 706 return count; 707 } 708 709 /* 710 * Read UART ID using the divisor method - set DLL and DLM to zero 711 * and the revision will be in DLL and device type in DLM. We 712 * preserve the device state across this. 713 */ 714 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) 715 { 716 unsigned char old_dll, old_dlm, old_lcr; 717 unsigned int id; 718 719 old_lcr = serial_in(p, UART_LCR); 720 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); 721 722 old_dll = serial_in(p, UART_DLL); 723 old_dlm = serial_in(p, UART_DLM); 724 725 serial_out(p, UART_DLL, 0); 726 serial_out(p, UART_DLM, 0); 727 728 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8; 729 730 serial_out(p, UART_DLL, old_dll); 731 serial_out(p, UART_DLM, old_dlm); 732 serial_out(p, UART_LCR, old_lcr); 733 734 return id; 735 } 736 737 /* 738 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. 739 * When this function is called we know it is at least a StarTech 740 * 16650 V2, but it might be one of several StarTech UARTs, or one of 741 * its clones. (We treat the broken original StarTech 16650 V1 as a 742 * 16550, and why not? Startech doesn't seem to even acknowledge its 743 * existence.) 744 * 745 * What evil have men's minds wrought... 746 */ 747 static void autoconfig_has_efr(struct uart_8250_port *up) 748 { 749 unsigned int id1, id2, id3, rev; 750 751 /* 752 * Everything with an EFR has SLEEP 753 */ 754 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 755 756 /* 757 * First we check to see if it's an Oxford Semiconductor UART. 758 * 759 * If we have to do this here because some non-National 760 * Semiconductor clone chips lock up if you try writing to the 761 * LSR register (which serial_icr_read does) 762 */ 763 764 /* 765 * Check for Oxford Semiconductor 16C950. 766 * 767 * EFR [4] must be set else this test fails. 768 * 769 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) 770 * claims that it's needed for 952 dual UART's (which are not 771 * recommended for new designs). 772 */ 773 up->acr = 0; 774 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 775 serial_out(up, UART_EFR, UART_EFR_ECB); 776 serial_out(up, UART_LCR, 0x00); 777 id1 = serial_icr_read(up, UART_ID1); 778 id2 = serial_icr_read(up, UART_ID2); 779 id3 = serial_icr_read(up, UART_ID3); 780 rev = serial_icr_read(up, UART_REV); 781 782 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); 783 784 if (id1 == 0x16 && id2 == 0xC9 && 785 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { 786 up->port.type = PORT_16C950; 787 788 /* 789 * Enable work around for the Oxford Semiconductor 952 rev B 790 * chip which causes it to seriously miscalculate baud rates 791 * when DLL is 0. 792 */ 793 if (id3 == 0x52 && rev == 0x01) 794 up->bugs |= UART_BUG_QUOT; 795 return; 796 } 797 798 /* 799 * We check for a XR16C850 by setting DLL and DLM to 0, and then 800 * reading back DLL and DLM. The chip type depends on the DLM 801 * value read back: 802 * 0x10 - XR16C850 and the DLL contains the chip revision. 803 * 0x12 - XR16C2850. 804 * 0x14 - XR16C854. 805 */ 806 id1 = autoconfig_read_divisor_id(up); 807 DEBUG_AUTOCONF("850id=%04x ", id1); 808 809 id2 = id1 >> 8; 810 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { 811 up->port.type = PORT_16850; 812 return; 813 } 814 815 /* 816 * It wasn't an XR16C850. 817 * 818 * We distinguish between the '654 and the '650 by counting 819 * how many bytes are in the FIFO. I'm using this for now, 820 * since that's the technique that was sent to me in the 821 * serial driver update, but I'm not convinced this works. 822 * I've had problems doing this in the past. -TYT 823 */ 824 if (size_fifo(up) == 64) 825 up->port.type = PORT_16654; 826 else 827 up->port.type = PORT_16650V2; 828 } 829 830 /* 831 * We detected a chip without a FIFO. Only two fall into 832 * this category - the original 8250 and the 16450. The 833 * 16450 has a scratch register (accessible with LCR=0) 834 */ 835 static void autoconfig_8250(struct uart_8250_port *up) 836 { 837 unsigned char scratch, status1, status2; 838 839 up->port.type = PORT_8250; 840 841 scratch = serial_in(up, UART_SCR); 842 serial_out(up, UART_SCR, 0xa5); 843 status1 = serial_in(up, UART_SCR); 844 serial_out(up, UART_SCR, 0x5a); 845 status2 = serial_in(up, UART_SCR); 846 serial_out(up, UART_SCR, scratch); 847 848 if (status1 == 0xa5 && status2 == 0x5a) 849 up->port.type = PORT_16450; 850 } 851 852 static int broken_efr(struct uart_8250_port *up) 853 { 854 /* 855 * Exar ST16C2550 "A2" devices incorrectly detect as 856 * having an EFR, and report an ID of 0x0201. See 857 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html 858 */ 859 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) 860 return 1; 861 862 return 0; 863 } 864 865 /* 866 * We know that the chip has FIFOs. Does it have an EFR? The 867 * EFR is located in the same register position as the IIR and 868 * we know the top two bits of the IIR are currently set. The 869 * EFR should contain zero. Try to read the EFR. 870 */ 871 static void autoconfig_16550a(struct uart_8250_port *up) 872 { 873 unsigned char status1, status2; 874 unsigned int iersave; 875 876 up->port.type = PORT_16550A; 877 up->capabilities |= UART_CAP_FIFO; 878 879 /* 880 * XR17V35x UARTs have an extra divisor register, DLD 881 * that gets enabled with when DLAB is set which will 882 * cause the device to incorrectly match and assign 883 * port type to PORT_16650. The EFR for this UART is 884 * found at offset 0x09. Instead check the Deice ID (DVID) 885 * register for a 2, 4 or 8 port UART. 886 */ 887 if (up->port.flags & UPF_EXAR_EFR) { 888 status1 = serial_in(up, UART_EXAR_DVID); 889 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) { 890 DEBUG_AUTOCONF("Exar XR17V35x "); 891 up->port.type = PORT_XR17V35X; 892 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | 893 UART_CAP_SLEEP; 894 895 return; 896 } 897 898 } 899 900 /* 901 * Check for presence of the EFR when DLAB is set. 902 * Only ST16C650V1 UARTs pass this test. 903 */ 904 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 905 if (serial_in(up, UART_EFR) == 0) { 906 serial_out(up, UART_EFR, 0xA8); 907 if (serial_in(up, UART_EFR) != 0) { 908 DEBUG_AUTOCONF("EFRv1 "); 909 up->port.type = PORT_16650; 910 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 911 } else { 912 serial_out(up, UART_LCR, 0); 913 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 914 UART_FCR7_64BYTE); 915 status1 = serial_in(up, UART_IIR) >> 5; 916 serial_out(up, UART_FCR, 0); 917 serial_out(up, UART_LCR, 0); 918 919 if (status1 == 7) 920 up->port.type = PORT_16550A_FSL64; 921 else 922 DEBUG_AUTOCONF("Motorola 8xxx DUART "); 923 } 924 serial_out(up, UART_EFR, 0); 925 return; 926 } 927 928 /* 929 * Maybe it requires 0xbf to be written to the LCR. 930 * (other ST16C650V2 UARTs, TI16C752A, etc) 931 */ 932 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 933 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { 934 DEBUG_AUTOCONF("EFRv2 "); 935 autoconfig_has_efr(up); 936 return; 937 } 938 939 /* 940 * Check for a National Semiconductor SuperIO chip. 941 * Attempt to switch to bank 2, read the value of the LOOP bit 942 * from EXCR1. Switch back to bank 0, change it in MCR. Then 943 * switch back to bank 2, read it from EXCR1 again and check 944 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 945 */ 946 serial_out(up, UART_LCR, 0); 947 status1 = serial_in(up, UART_MCR); 948 serial_out(up, UART_LCR, 0xE0); 949 status2 = serial_in(up, 0x02); /* EXCR1 */ 950 951 if (!((status2 ^ status1) & UART_MCR_LOOP)) { 952 serial_out(up, UART_LCR, 0); 953 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP); 954 serial_out(up, UART_LCR, 0xE0); 955 status2 = serial_in(up, 0x02); /* EXCR1 */ 956 serial_out(up, UART_LCR, 0); 957 serial_out(up, UART_MCR, status1); 958 959 if ((status2 ^ status1) & UART_MCR_LOOP) { 960 unsigned short quot; 961 962 serial_out(up, UART_LCR, 0xE0); 963 964 quot = serial_dl_read(up); 965 quot <<= 3; 966 967 if (ns16550a_goto_highspeed(up)) 968 serial_dl_write(up, quot); 969 970 serial_out(up, UART_LCR, 0); 971 972 up->port.uartclk = 921600*16; 973 up->port.type = PORT_NS16550A; 974 up->capabilities |= UART_NATSEMI; 975 return; 976 } 977 } 978 979 /* 980 * No EFR. Try to detect a TI16750, which only sets bit 5 of 981 * the IIR when 64 byte FIFO mode is enabled when DLAB is set. 982 * Try setting it with and without DLAB set. Cheap clones 983 * set bit 5 without DLAB set. 984 */ 985 serial_out(up, UART_LCR, 0); 986 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 987 status1 = serial_in(up, UART_IIR) >> 5; 988 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 989 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 990 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 991 status2 = serial_in(up, UART_IIR) >> 5; 992 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 993 serial_out(up, UART_LCR, 0); 994 995 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); 996 997 if (status1 == 6 && status2 == 7) { 998 up->port.type = PORT_16750; 999 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; 1000 return; 1001 } 1002 1003 /* 1004 * Try writing and reading the UART_IER_UUE bit (b6). 1005 * If it works, this is probably one of the Xscale platform's 1006 * internal UARTs. 1007 * We're going to explicitly set the UUE bit to 0 before 1008 * trying to write and read a 1 just to make sure it's not 1009 * already a 1 and maybe locked there before we even start start. 1010 */ 1011 iersave = serial_in(up, UART_IER); 1012 serial_out(up, UART_IER, iersave & ~UART_IER_UUE); 1013 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { 1014 /* 1015 * OK it's in a known zero state, try writing and reading 1016 * without disturbing the current state of the other bits. 1017 */ 1018 serial_out(up, UART_IER, iersave | UART_IER_UUE); 1019 if (serial_in(up, UART_IER) & UART_IER_UUE) { 1020 /* 1021 * It's an Xscale. 1022 * We'll leave the UART_IER_UUE bit set to 1 (enabled). 1023 */ 1024 DEBUG_AUTOCONF("Xscale "); 1025 up->port.type = PORT_XSCALE; 1026 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; 1027 return; 1028 } 1029 } else { 1030 /* 1031 * If we got here we couldn't force the IER_UUE bit to 0. 1032 * Log it and continue. 1033 */ 1034 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); 1035 } 1036 serial_out(up, UART_IER, iersave); 1037 1038 /* 1039 * Exar uarts have EFR in a weird location 1040 */ 1041 if (up->port.flags & UPF_EXAR_EFR) { 1042 DEBUG_AUTOCONF("Exar XR17D15x "); 1043 up->port.type = PORT_XR17D15X; 1044 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | 1045 UART_CAP_SLEEP; 1046 1047 return; 1048 } 1049 1050 /* 1051 * We distinguish between 16550A and U6 16550A by counting 1052 * how many bytes are in the FIFO. 1053 */ 1054 if (up->port.type == PORT_16550A && size_fifo(up) == 64) { 1055 up->port.type = PORT_U6_16550A; 1056 up->capabilities |= UART_CAP_AFE; 1057 } 1058 } 1059 1060 /* 1061 * This routine is called by rs_init() to initialize a specific serial 1062 * port. It determines what type of UART chip this serial port is 1063 * using: 8250, 16450, 16550, 16550A. The important question is 1064 * whether or not this UART is a 16550A or not, since this will 1065 * determine whether or not we can use its FIFO features or not. 1066 */ 1067 static void autoconfig(struct uart_8250_port *up) 1068 { 1069 unsigned char status1, scratch, scratch2, scratch3; 1070 unsigned char save_lcr, save_mcr; 1071 struct uart_port *port = &up->port; 1072 unsigned long flags; 1073 unsigned int old_capabilities; 1074 1075 if (!port->iobase && !port->mapbase && !port->membase) 1076 return; 1077 1078 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", 1079 serial_index(port), port->iobase, port->membase); 1080 1081 /* 1082 * We really do need global IRQs disabled here - we're going to 1083 * be frobbing the chips IRQ enable register to see if it exists. 1084 */ 1085 spin_lock_irqsave(&port->lock, flags); 1086 1087 up->capabilities = 0; 1088 up->bugs = 0; 1089 1090 if (!(port->flags & UPF_BUGGY_UART)) { 1091 /* 1092 * Do a simple existence test first; if we fail this, 1093 * there's no point trying anything else. 1094 * 1095 * 0x80 is used as a nonsense port to prevent against 1096 * false positives due to ISA bus float. The 1097 * assumption is that 0x80 is a non-existent port; 1098 * which should be safe since include/asm/io.h also 1099 * makes this assumption. 1100 * 1101 * Note: this is safe as long as MCR bit 4 is clear 1102 * and the device is in "PC" mode. 1103 */ 1104 scratch = serial_in(up, UART_IER); 1105 serial_out(up, UART_IER, 0); 1106 #ifdef __i386__ 1107 outb(0xff, 0x080); 1108 #endif 1109 /* 1110 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL 1111 * 16C754B) allow only to modify them if an EFR bit is set. 1112 */ 1113 scratch2 = serial_in(up, UART_IER) & 0x0f; 1114 serial_out(up, UART_IER, 0x0F); 1115 #ifdef __i386__ 1116 outb(0, 0x080); 1117 #endif 1118 scratch3 = serial_in(up, UART_IER) & 0x0f; 1119 serial_out(up, UART_IER, scratch); 1120 if (scratch2 != 0 || scratch3 != 0x0F) { 1121 /* 1122 * We failed; there's nothing here 1123 */ 1124 spin_unlock_irqrestore(&port->lock, flags); 1125 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", 1126 scratch2, scratch3); 1127 goto out; 1128 } 1129 } 1130 1131 save_mcr = serial_in(up, UART_MCR); 1132 save_lcr = serial_in(up, UART_LCR); 1133 1134 /* 1135 * Check to see if a UART is really there. Certain broken 1136 * internal modems based on the Rockwell chipset fail this 1137 * test, because they apparently don't implement the loopback 1138 * test mode. So this test is skipped on the COM 1 through 1139 * COM 4 ports. This *should* be safe, since no board 1140 * manufacturer would be stupid enough to design a board 1141 * that conflicts with COM 1-4 --- we hope! 1142 */ 1143 if (!(port->flags & UPF_SKIP_TEST)) { 1144 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A); 1145 status1 = serial_in(up, UART_MSR) & 0xF0; 1146 serial_out(up, UART_MCR, save_mcr); 1147 if (status1 != 0x90) { 1148 spin_unlock_irqrestore(&port->lock, flags); 1149 DEBUG_AUTOCONF("LOOP test failed (%02x) ", 1150 status1); 1151 goto out; 1152 } 1153 } 1154 1155 /* 1156 * We're pretty sure there's a port here. Lets find out what 1157 * type of port it is. The IIR top two bits allows us to find 1158 * out if it's 8250 or 16450, 16550, 16550A or later. This 1159 * determines what we test for next. 1160 * 1161 * We also initialise the EFR (if any) to zero for later. The 1162 * EFR occupies the same register location as the FCR and IIR. 1163 */ 1164 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1165 serial_out(up, UART_EFR, 0); 1166 serial_out(up, UART_LCR, 0); 1167 1168 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1169 scratch = serial_in(up, UART_IIR) >> 6; 1170 1171 switch (scratch) { 1172 case 0: 1173 autoconfig_8250(up); 1174 break; 1175 case 1: 1176 port->type = PORT_UNKNOWN; 1177 break; 1178 case 2: 1179 port->type = PORT_16550; 1180 break; 1181 case 3: 1182 autoconfig_16550a(up); 1183 break; 1184 } 1185 1186 #ifdef CONFIG_SERIAL_8250_RSA 1187 /* 1188 * Only probe for RSA ports if we got the region. 1189 */ 1190 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA && 1191 __enable_rsa(up)) 1192 port->type = PORT_RSA; 1193 #endif 1194 1195 serial_out(up, UART_LCR, save_lcr); 1196 1197 port->fifosize = uart_config[up->port.type].fifo_size; 1198 old_capabilities = up->capabilities; 1199 up->capabilities = uart_config[port->type].flags; 1200 up->tx_loadsz = uart_config[port->type].tx_loadsz; 1201 1202 if (port->type == PORT_UNKNOWN) 1203 goto out_lock; 1204 1205 /* 1206 * Reset the UART. 1207 */ 1208 #ifdef CONFIG_SERIAL_8250_RSA 1209 if (port->type == PORT_RSA) 1210 serial_out(up, UART_RSA_FRR, 0); 1211 #endif 1212 serial_out(up, UART_MCR, save_mcr); 1213 serial8250_clear_fifos(up); 1214 serial_in(up, UART_RX); 1215 if (up->capabilities & UART_CAP_UUE) 1216 serial_out(up, UART_IER, UART_IER_UUE); 1217 else 1218 serial_out(up, UART_IER, 0); 1219 1220 out_lock: 1221 spin_unlock_irqrestore(&port->lock, flags); 1222 if (up->capabilities != old_capabilities) { 1223 printk(KERN_WARNING 1224 "ttyS%d: detected caps %08x should be %08x\n", 1225 serial_index(port), old_capabilities, 1226 up->capabilities); 1227 } 1228 out: 1229 DEBUG_AUTOCONF("iir=%d ", scratch); 1230 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name); 1231 } 1232 1233 static void autoconfig_irq(struct uart_8250_port *up) 1234 { 1235 struct uart_port *port = &up->port; 1236 unsigned char save_mcr, save_ier; 1237 unsigned char save_ICP = 0; 1238 unsigned int ICP = 0; 1239 unsigned long irqs; 1240 int irq; 1241 1242 if (port->flags & UPF_FOURPORT) { 1243 ICP = (port->iobase & 0xfe0) | 0x1f; 1244 save_ICP = inb_p(ICP); 1245 outb_p(0x80, ICP); 1246 inb_p(ICP); 1247 } 1248 1249 /* forget possible initially masked and pending IRQ */ 1250 probe_irq_off(probe_irq_on()); 1251 save_mcr = serial_in(up, UART_MCR); 1252 save_ier = serial_in(up, UART_IER); 1253 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); 1254 1255 irqs = probe_irq_on(); 1256 serial_out(up, UART_MCR, 0); 1257 udelay(10); 1258 if (port->flags & UPF_FOURPORT) { 1259 serial_out(up, UART_MCR, 1260 UART_MCR_DTR | UART_MCR_RTS); 1261 } else { 1262 serial_out(up, UART_MCR, 1263 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); 1264 } 1265 serial_out(up, UART_IER, 0x0f); /* enable all intrs */ 1266 serial_in(up, UART_LSR); 1267 serial_in(up, UART_RX); 1268 serial_in(up, UART_IIR); 1269 serial_in(up, UART_MSR); 1270 serial_out(up, UART_TX, 0xFF); 1271 udelay(20); 1272 irq = probe_irq_off(irqs); 1273 1274 serial_out(up, UART_MCR, save_mcr); 1275 serial_out(up, UART_IER, save_ier); 1276 1277 if (port->flags & UPF_FOURPORT) 1278 outb_p(save_ICP, ICP); 1279 1280 port->irq = (irq > 0) ? irq : 0; 1281 } 1282 1283 static inline void __stop_tx(struct uart_8250_port *p) 1284 { 1285 if (p->ier & UART_IER_THRI) { 1286 p->ier &= ~UART_IER_THRI; 1287 serial_out(p, UART_IER, p->ier); 1288 serial8250_rpm_put_tx(p); 1289 } 1290 } 1291 1292 static void serial8250_stop_tx(struct uart_port *port) 1293 { 1294 struct uart_8250_port *up = up_to_u8250p(port); 1295 1296 serial8250_rpm_get(up); 1297 __stop_tx(up); 1298 1299 /* 1300 * We really want to stop the transmitter from sending. 1301 */ 1302 if (port->type == PORT_16C950) { 1303 up->acr |= UART_ACR_TXDIS; 1304 serial_icr_write(up, UART_ACR, up->acr); 1305 } 1306 serial8250_rpm_put(up); 1307 } 1308 1309 static void serial8250_start_tx(struct uart_port *port) 1310 { 1311 struct uart_8250_port *up = up_to_u8250p(port); 1312 1313 serial8250_rpm_get_tx(up); 1314 1315 if (up->dma && !up->dma->tx_dma(up)) 1316 return; 1317 1318 if (!(up->ier & UART_IER_THRI)) { 1319 up->ier |= UART_IER_THRI; 1320 serial_port_out(port, UART_IER, up->ier); 1321 1322 if (up->bugs & UART_BUG_TXEN) { 1323 unsigned char lsr; 1324 lsr = serial_in(up, UART_LSR); 1325 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 1326 if (lsr & UART_LSR_THRE) 1327 serial8250_tx_chars(up); 1328 } 1329 } 1330 1331 /* 1332 * Re-enable the transmitter if we disabled it. 1333 */ 1334 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 1335 up->acr &= ~UART_ACR_TXDIS; 1336 serial_icr_write(up, UART_ACR, up->acr); 1337 } 1338 } 1339 1340 static void serial8250_throttle(struct uart_port *port) 1341 { 1342 port->throttle(port); 1343 } 1344 1345 static void serial8250_unthrottle(struct uart_port *port) 1346 { 1347 port->unthrottle(port); 1348 } 1349 1350 static void serial8250_stop_rx(struct uart_port *port) 1351 { 1352 struct uart_8250_port *up = up_to_u8250p(port); 1353 1354 serial8250_rpm_get(up); 1355 1356 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1357 up->port.read_status_mask &= ~UART_LSR_DR; 1358 serial_port_out(port, UART_IER, up->ier); 1359 1360 serial8250_rpm_put(up); 1361 } 1362 1363 static void serial8250_disable_ms(struct uart_port *port) 1364 { 1365 struct uart_8250_port *up = 1366 container_of(port, struct uart_8250_port, port); 1367 1368 /* no MSR capabilities */ 1369 if (up->bugs & UART_BUG_NOMSR) 1370 return; 1371 1372 up->ier &= ~UART_IER_MSI; 1373 serial_port_out(port, UART_IER, up->ier); 1374 } 1375 1376 static void serial8250_enable_ms(struct uart_port *port) 1377 { 1378 struct uart_8250_port *up = up_to_u8250p(port); 1379 1380 /* no MSR capabilities */ 1381 if (up->bugs & UART_BUG_NOMSR) 1382 return; 1383 1384 up->ier |= UART_IER_MSI; 1385 1386 serial8250_rpm_get(up); 1387 serial_port_out(port, UART_IER, up->ier); 1388 serial8250_rpm_put(up); 1389 } 1390 1391 /* 1392 * serial8250_rx_chars: processes according to the passed in LSR 1393 * value, and returns the remaining LSR bits not handled 1394 * by this Rx routine. 1395 */ 1396 unsigned char 1397 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr) 1398 { 1399 struct uart_port *port = &up->port; 1400 unsigned char ch; 1401 int max_count = 256; 1402 char flag; 1403 1404 do { 1405 if (likely(lsr & UART_LSR_DR)) 1406 ch = serial_in(up, UART_RX); 1407 else 1408 /* 1409 * Intel 82571 has a Serial Over Lan device that will 1410 * set UART_LSR_BI without setting UART_LSR_DR when 1411 * it receives a break. To avoid reading from the 1412 * receive buffer without UART_LSR_DR bit set, we 1413 * just force the read character to be 0 1414 */ 1415 ch = 0; 1416 1417 flag = TTY_NORMAL; 1418 port->icount.rx++; 1419 1420 lsr |= up->lsr_saved_flags; 1421 up->lsr_saved_flags = 0; 1422 1423 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { 1424 if (lsr & UART_LSR_BI) { 1425 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 1426 port->icount.brk++; 1427 /* 1428 * We do the SysRQ and SAK checking 1429 * here because otherwise the break 1430 * may get masked by ignore_status_mask 1431 * or read_status_mask. 1432 */ 1433 if (uart_handle_break(port)) 1434 goto ignore_char; 1435 } else if (lsr & UART_LSR_PE) 1436 port->icount.parity++; 1437 else if (lsr & UART_LSR_FE) 1438 port->icount.frame++; 1439 if (lsr & UART_LSR_OE) 1440 port->icount.overrun++; 1441 1442 /* 1443 * Mask off conditions which should be ignored. 1444 */ 1445 lsr &= port->read_status_mask; 1446 1447 if (lsr & UART_LSR_BI) { 1448 DEBUG_INTR("handling break...."); 1449 flag = TTY_BREAK; 1450 } else if (lsr & UART_LSR_PE) 1451 flag = TTY_PARITY; 1452 else if (lsr & UART_LSR_FE) 1453 flag = TTY_FRAME; 1454 } 1455 if (uart_handle_sysrq_char(port, ch)) 1456 goto ignore_char; 1457 1458 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); 1459 1460 ignore_char: 1461 lsr = serial_in(up, UART_LSR); 1462 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0)); 1463 spin_unlock(&port->lock); 1464 tty_flip_buffer_push(&port->state->port); 1465 spin_lock(&port->lock); 1466 return lsr; 1467 } 1468 EXPORT_SYMBOL_GPL(serial8250_rx_chars); 1469 1470 void serial8250_tx_chars(struct uart_8250_port *up) 1471 { 1472 struct uart_port *port = &up->port; 1473 struct circ_buf *xmit = &port->state->xmit; 1474 int count; 1475 1476 if (port->x_char) { 1477 serial_out(up, UART_TX, port->x_char); 1478 port->icount.tx++; 1479 port->x_char = 0; 1480 return; 1481 } 1482 if (uart_tx_stopped(port)) { 1483 serial8250_stop_tx(port); 1484 return; 1485 } 1486 if (uart_circ_empty(xmit)) { 1487 __stop_tx(up); 1488 return; 1489 } 1490 1491 count = up->tx_loadsz; 1492 do { 1493 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 1494 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1495 port->icount.tx++; 1496 if (uart_circ_empty(xmit)) 1497 break; 1498 if (up->capabilities & UART_CAP_HFIFO) { 1499 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) != 1500 BOTH_EMPTY) 1501 break; 1502 } 1503 } while (--count > 0); 1504 1505 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1506 uart_write_wakeup(port); 1507 1508 DEBUG_INTR("THRE..."); 1509 1510 /* 1511 * With RPM enabled, we have to wait until the FIFO is empty before the 1512 * HW can go idle. So we get here once again with empty FIFO and disable 1513 * the interrupt and RPM in __stop_tx() 1514 */ 1515 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM)) 1516 __stop_tx(up); 1517 } 1518 EXPORT_SYMBOL_GPL(serial8250_tx_chars); 1519 1520 /* Caller holds uart port lock */ 1521 unsigned int serial8250_modem_status(struct uart_8250_port *up) 1522 { 1523 struct uart_port *port = &up->port; 1524 unsigned int status = serial_in(up, UART_MSR); 1525 1526 status |= up->msr_saved_flags; 1527 up->msr_saved_flags = 0; 1528 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 1529 port->state != NULL) { 1530 if (status & UART_MSR_TERI) 1531 port->icount.rng++; 1532 if (status & UART_MSR_DDSR) 1533 port->icount.dsr++; 1534 if (status & UART_MSR_DDCD) 1535 uart_handle_dcd_change(port, status & UART_MSR_DCD); 1536 if (status & UART_MSR_DCTS) 1537 uart_handle_cts_change(port, status & UART_MSR_CTS); 1538 1539 wake_up_interruptible(&port->state->port.delta_msr_wait); 1540 } 1541 1542 return status; 1543 } 1544 EXPORT_SYMBOL_GPL(serial8250_modem_status); 1545 1546 /* 1547 * This handles the interrupt from one port. 1548 */ 1549 int serial8250_handle_irq(struct uart_port *port, unsigned int iir) 1550 { 1551 unsigned char status; 1552 unsigned long flags; 1553 struct uart_8250_port *up = up_to_u8250p(port); 1554 int dma_err = 0; 1555 1556 if (iir & UART_IIR_NO_INT) 1557 return 0; 1558 1559 spin_lock_irqsave(&port->lock, flags); 1560 1561 status = serial_port_in(port, UART_LSR); 1562 1563 DEBUG_INTR("status = %x...", status); 1564 1565 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1566 if (up->dma) 1567 dma_err = up->dma->rx_dma(up, iir); 1568 1569 if (!up->dma || dma_err) 1570 status = serial8250_rx_chars(up, status); 1571 } 1572 serial8250_modem_status(up); 1573 if ((!up->dma || (up->dma && up->dma->tx_err)) && 1574 (status & UART_LSR_THRE)) 1575 serial8250_tx_chars(up); 1576 1577 spin_unlock_irqrestore(&port->lock, flags); 1578 return 1; 1579 } 1580 EXPORT_SYMBOL_GPL(serial8250_handle_irq); 1581 1582 static int serial8250_default_handle_irq(struct uart_port *port) 1583 { 1584 struct uart_8250_port *up = up_to_u8250p(port); 1585 unsigned int iir; 1586 int ret; 1587 1588 serial8250_rpm_get(up); 1589 1590 iir = serial_port_in(port, UART_IIR); 1591 ret = serial8250_handle_irq(port, iir); 1592 1593 serial8250_rpm_put(up); 1594 return ret; 1595 } 1596 1597 /* 1598 * These Exar UARTs have an extra interrupt indicator that could 1599 * fire for a few unimplemented interrupts. One of which is a 1600 * wakeup event when coming out of sleep. Put this here just 1601 * to be on the safe side that these interrupts don't go unhandled. 1602 */ 1603 static int exar_handle_irq(struct uart_port *port) 1604 { 1605 unsigned char int0, int1, int2, int3; 1606 unsigned int iir = serial_port_in(port, UART_IIR); 1607 int ret; 1608 1609 ret = serial8250_handle_irq(port, iir); 1610 1611 if ((port->type == PORT_XR17V35X) || 1612 (port->type == PORT_XR17D15X)) { 1613 int0 = serial_port_in(port, 0x80); 1614 int1 = serial_port_in(port, 0x81); 1615 int2 = serial_port_in(port, 0x82); 1616 int3 = serial_port_in(port, 0x83); 1617 } 1618 1619 return ret; 1620 } 1621 1622 static unsigned int serial8250_tx_empty(struct uart_port *port) 1623 { 1624 struct uart_8250_port *up = up_to_u8250p(port); 1625 unsigned long flags; 1626 unsigned int lsr; 1627 1628 serial8250_rpm_get(up); 1629 1630 spin_lock_irqsave(&port->lock, flags); 1631 lsr = serial_port_in(port, UART_LSR); 1632 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 1633 spin_unlock_irqrestore(&port->lock, flags); 1634 1635 serial8250_rpm_put(up); 1636 1637 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; 1638 } 1639 1640 static unsigned int serial8250_get_mctrl(struct uart_port *port) 1641 { 1642 struct uart_8250_port *up = up_to_u8250p(port); 1643 unsigned int status; 1644 unsigned int ret; 1645 1646 serial8250_rpm_get(up); 1647 status = serial8250_modem_status(up); 1648 serial8250_rpm_put(up); 1649 1650 ret = 0; 1651 if (status & UART_MSR_DCD) 1652 ret |= TIOCM_CAR; 1653 if (status & UART_MSR_RI) 1654 ret |= TIOCM_RNG; 1655 if (status & UART_MSR_DSR) 1656 ret |= TIOCM_DSR; 1657 if (status & UART_MSR_CTS) 1658 ret |= TIOCM_CTS; 1659 return ret; 1660 } 1661 1662 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl) 1663 { 1664 struct uart_8250_port *up = up_to_u8250p(port); 1665 unsigned char mcr = 0; 1666 1667 if (mctrl & TIOCM_RTS) 1668 mcr |= UART_MCR_RTS; 1669 if (mctrl & TIOCM_DTR) 1670 mcr |= UART_MCR_DTR; 1671 if (mctrl & TIOCM_OUT1) 1672 mcr |= UART_MCR_OUT1; 1673 if (mctrl & TIOCM_OUT2) 1674 mcr |= UART_MCR_OUT2; 1675 if (mctrl & TIOCM_LOOP) 1676 mcr |= UART_MCR_LOOP; 1677 1678 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; 1679 1680 serial_port_out(port, UART_MCR, mcr); 1681 } 1682 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl); 1683 1684 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 1685 { 1686 if (port->set_mctrl) 1687 port->set_mctrl(port, mctrl); 1688 else 1689 serial8250_do_set_mctrl(port, mctrl); 1690 } 1691 1692 static void serial8250_break_ctl(struct uart_port *port, int break_state) 1693 { 1694 struct uart_8250_port *up = up_to_u8250p(port); 1695 unsigned long flags; 1696 1697 serial8250_rpm_get(up); 1698 spin_lock_irqsave(&port->lock, flags); 1699 if (break_state == -1) 1700 up->lcr |= UART_LCR_SBC; 1701 else 1702 up->lcr &= ~UART_LCR_SBC; 1703 serial_port_out(port, UART_LCR, up->lcr); 1704 spin_unlock_irqrestore(&port->lock, flags); 1705 serial8250_rpm_put(up); 1706 } 1707 1708 /* 1709 * Wait for transmitter & holding register to empty 1710 */ 1711 static void wait_for_xmitr(struct uart_8250_port *up, int bits) 1712 { 1713 unsigned int status, tmout = 10000; 1714 1715 /* Wait up to 10ms for the character(s) to be sent. */ 1716 for (;;) { 1717 status = serial_in(up, UART_LSR); 1718 1719 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; 1720 1721 if ((status & bits) == bits) 1722 break; 1723 if (--tmout == 0) 1724 break; 1725 udelay(1); 1726 } 1727 1728 /* Wait up to 1s for flow control if necessary */ 1729 if (up->port.flags & UPF_CONS_FLOW) { 1730 unsigned int tmout; 1731 for (tmout = 1000000; tmout; tmout--) { 1732 unsigned int msr = serial_in(up, UART_MSR); 1733 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1734 if (msr & UART_MSR_CTS) 1735 break; 1736 udelay(1); 1737 touch_nmi_watchdog(); 1738 } 1739 } 1740 } 1741 1742 #ifdef CONFIG_CONSOLE_POLL 1743 /* 1744 * Console polling routines for writing and reading from the uart while 1745 * in an interrupt or debug context. 1746 */ 1747 1748 static int serial8250_get_poll_char(struct uart_port *port) 1749 { 1750 struct uart_8250_port *up = up_to_u8250p(port); 1751 unsigned char lsr; 1752 int status; 1753 1754 serial8250_rpm_get(up); 1755 1756 lsr = serial_port_in(port, UART_LSR); 1757 1758 if (!(lsr & UART_LSR_DR)) { 1759 status = NO_POLL_CHAR; 1760 goto out; 1761 } 1762 1763 status = serial_port_in(port, UART_RX); 1764 out: 1765 serial8250_rpm_put(up); 1766 return status; 1767 } 1768 1769 1770 static void serial8250_put_poll_char(struct uart_port *port, 1771 unsigned char c) 1772 { 1773 unsigned int ier; 1774 struct uart_8250_port *up = up_to_u8250p(port); 1775 1776 serial8250_rpm_get(up); 1777 /* 1778 * First save the IER then disable the interrupts 1779 */ 1780 ier = serial_port_in(port, UART_IER); 1781 if (up->capabilities & UART_CAP_UUE) 1782 serial_port_out(port, UART_IER, UART_IER_UUE); 1783 else 1784 serial_port_out(port, UART_IER, 0); 1785 1786 wait_for_xmitr(up, BOTH_EMPTY); 1787 /* 1788 * Send the character out. 1789 */ 1790 serial_port_out(port, UART_TX, c); 1791 1792 /* 1793 * Finally, wait for transmitter to become empty 1794 * and restore the IER 1795 */ 1796 wait_for_xmitr(up, BOTH_EMPTY); 1797 serial_port_out(port, UART_IER, ier); 1798 serial8250_rpm_put(up); 1799 } 1800 1801 #endif /* CONFIG_CONSOLE_POLL */ 1802 1803 int serial8250_do_startup(struct uart_port *port) 1804 { 1805 struct uart_8250_port *up = up_to_u8250p(port); 1806 unsigned long flags; 1807 unsigned char lsr, iir; 1808 int retval; 1809 1810 if (port->type == PORT_8250_CIR) 1811 return -ENODEV; 1812 1813 if (!port->fifosize) 1814 port->fifosize = uart_config[port->type].fifo_size; 1815 if (!up->tx_loadsz) 1816 up->tx_loadsz = uart_config[port->type].tx_loadsz; 1817 if (!up->capabilities) 1818 up->capabilities = uart_config[port->type].flags; 1819 up->mcr = 0; 1820 1821 if (port->iotype != up->cur_iotype) 1822 set_io_from_upio(port); 1823 1824 serial8250_rpm_get(up); 1825 if (port->type == PORT_16C950) { 1826 /* Wake up and initialize UART */ 1827 up->acr = 0; 1828 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 1829 serial_port_out(port, UART_EFR, UART_EFR_ECB); 1830 serial_port_out(port, UART_IER, 0); 1831 serial_port_out(port, UART_LCR, 0); 1832 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 1833 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 1834 serial_port_out(port, UART_EFR, UART_EFR_ECB); 1835 serial_port_out(port, UART_LCR, 0); 1836 } 1837 1838 #ifdef CONFIG_SERIAL_8250_RSA 1839 /* 1840 * If this is an RSA port, see if we can kick it up to the 1841 * higher speed clock. 1842 */ 1843 enable_rsa(up); 1844 #endif 1845 1846 if (port->type == PORT_XR17V35X) { 1847 /* 1848 * First enable access to IER [7:5], ISR [5:4], FCR [5:4], 1849 * MCR [7:5] and MSR [7:0] 1850 */ 1851 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB); 1852 1853 /* 1854 * Make sure all interrups are masked until initialization is 1855 * complete and the FIFOs are cleared 1856 */ 1857 serial_port_out(port, UART_IER, 0); 1858 } 1859 1860 /* 1861 * Clear the FIFO buffers and disable them. 1862 * (they will be reenabled in set_termios()) 1863 */ 1864 serial8250_clear_fifos(up); 1865 1866 /* 1867 * Clear the interrupt registers. 1868 */ 1869 serial_port_in(port, UART_LSR); 1870 serial_port_in(port, UART_RX); 1871 serial_port_in(port, UART_IIR); 1872 serial_port_in(port, UART_MSR); 1873 1874 /* 1875 * At this point, there's no way the LSR could still be 0xff; 1876 * if it is, then bail out, because there's likely no UART 1877 * here. 1878 */ 1879 if (!(port->flags & UPF_BUGGY_UART) && 1880 (serial_port_in(port, UART_LSR) == 0xff)) { 1881 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n", 1882 serial_index(port)); 1883 retval = -ENODEV; 1884 goto out; 1885 } 1886 1887 /* 1888 * For a XR16C850, we need to set the trigger levels 1889 */ 1890 if (port->type == PORT_16850) { 1891 unsigned char fctr; 1892 1893 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1894 1895 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); 1896 serial_port_out(port, UART_FCTR, 1897 fctr | UART_FCTR_TRGD | UART_FCTR_RX); 1898 serial_port_out(port, UART_TRG, UART_TRG_96); 1899 serial_port_out(port, UART_FCTR, 1900 fctr | UART_FCTR_TRGD | UART_FCTR_TX); 1901 serial_port_out(port, UART_TRG, UART_TRG_96); 1902 1903 serial_port_out(port, UART_LCR, 0); 1904 } 1905 1906 if (port->irq) { 1907 unsigned char iir1; 1908 /* 1909 * Test for UARTs that do not reassert THRE when the 1910 * transmitter is idle and the interrupt has already 1911 * been cleared. Real 16550s should always reassert 1912 * this interrupt whenever the transmitter is idle and 1913 * the interrupt is enabled. Delays are necessary to 1914 * allow register changes to become visible. 1915 */ 1916 spin_lock_irqsave(&port->lock, flags); 1917 if (up->port.irqflags & IRQF_SHARED) 1918 disable_irq_nosync(port->irq); 1919 1920 wait_for_xmitr(up, UART_LSR_THRE); 1921 serial_port_out_sync(port, UART_IER, UART_IER_THRI); 1922 udelay(1); /* allow THRE to set */ 1923 iir1 = serial_port_in(port, UART_IIR); 1924 serial_port_out(port, UART_IER, 0); 1925 serial_port_out_sync(port, UART_IER, UART_IER_THRI); 1926 udelay(1); /* allow a working UART time to re-assert THRE */ 1927 iir = serial_port_in(port, UART_IIR); 1928 serial_port_out(port, UART_IER, 0); 1929 1930 if (port->irqflags & IRQF_SHARED) 1931 enable_irq(port->irq); 1932 spin_unlock_irqrestore(&port->lock, flags); 1933 1934 /* 1935 * If the interrupt is not reasserted, or we otherwise 1936 * don't trust the iir, setup a timer to kick the UART 1937 * on a regular basis. 1938 */ 1939 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || 1940 up->port.flags & UPF_BUG_THRE) { 1941 up->bugs |= UART_BUG_THRE; 1942 } 1943 } 1944 1945 retval = up->ops->setup_irq(up); 1946 if (retval) 1947 goto out; 1948 1949 /* 1950 * Now, initialize the UART 1951 */ 1952 serial_port_out(port, UART_LCR, UART_LCR_WLEN8); 1953 1954 spin_lock_irqsave(&port->lock, flags); 1955 if (up->port.flags & UPF_FOURPORT) { 1956 if (!up->port.irq) 1957 up->port.mctrl |= TIOCM_OUT1; 1958 } else 1959 /* 1960 * Most PC uarts need OUT2 raised to enable interrupts. 1961 */ 1962 if (port->irq) 1963 up->port.mctrl |= TIOCM_OUT2; 1964 1965 serial8250_set_mctrl(port, port->mctrl); 1966 1967 /* Serial over Lan (SoL) hack: 1968 Intel 8257x Gigabit ethernet chips have a 1969 16550 emulation, to be used for Serial Over Lan. 1970 Those chips take a longer time than a normal 1971 serial device to signalize that a transmission 1972 data was queued. Due to that, the above test generally 1973 fails. One solution would be to delay the reading of 1974 iir. However, this is not reliable, since the timeout 1975 is variable. So, let's just don't test if we receive 1976 TX irq. This way, we'll never enable UART_BUG_TXEN. 1977 */ 1978 if (up->port.flags & UPF_NO_TXEN_TEST) 1979 goto dont_test_tx_en; 1980 1981 /* 1982 * Do a quick test to see if we receive an 1983 * interrupt when we enable the TX irq. 1984 */ 1985 serial_port_out(port, UART_IER, UART_IER_THRI); 1986 lsr = serial_port_in(port, UART_LSR); 1987 iir = serial_port_in(port, UART_IIR); 1988 serial_port_out(port, UART_IER, 0); 1989 1990 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { 1991 if (!(up->bugs & UART_BUG_TXEN)) { 1992 up->bugs |= UART_BUG_TXEN; 1993 pr_debug("ttyS%d - enabling bad tx status workarounds\n", 1994 serial_index(port)); 1995 } 1996 } else { 1997 up->bugs &= ~UART_BUG_TXEN; 1998 } 1999 2000 dont_test_tx_en: 2001 spin_unlock_irqrestore(&port->lock, flags); 2002 2003 /* 2004 * Clear the interrupt registers again for luck, and clear the 2005 * saved flags to avoid getting false values from polling 2006 * routines or the previous session. 2007 */ 2008 serial_port_in(port, UART_LSR); 2009 serial_port_in(port, UART_RX); 2010 serial_port_in(port, UART_IIR); 2011 serial_port_in(port, UART_MSR); 2012 up->lsr_saved_flags = 0; 2013 up->msr_saved_flags = 0; 2014 2015 /* 2016 * Request DMA channels for both RX and TX. 2017 */ 2018 if (up->dma) { 2019 retval = serial8250_request_dma(up); 2020 if (retval) { 2021 pr_warn_ratelimited("ttyS%d - failed to request DMA\n", 2022 serial_index(port)); 2023 up->dma = NULL; 2024 } 2025 } 2026 2027 /* 2028 * Set the IER shadow for rx interrupts but defer actual interrupt 2029 * enable until after the FIFOs are enabled; otherwise, an already- 2030 * active sender can swamp the interrupt handler with "too much work". 2031 */ 2032 up->ier = UART_IER_RLSI | UART_IER_RDI; 2033 2034 if (port->flags & UPF_FOURPORT) { 2035 unsigned int icp; 2036 /* 2037 * Enable interrupts on the AST Fourport board 2038 */ 2039 icp = (port->iobase & 0xfe0) | 0x01f; 2040 outb_p(0x80, icp); 2041 inb_p(icp); 2042 } 2043 retval = 0; 2044 out: 2045 serial8250_rpm_put(up); 2046 return retval; 2047 } 2048 EXPORT_SYMBOL_GPL(serial8250_do_startup); 2049 2050 static int serial8250_startup(struct uart_port *port) 2051 { 2052 if (port->startup) 2053 return port->startup(port); 2054 return serial8250_do_startup(port); 2055 } 2056 2057 void serial8250_do_shutdown(struct uart_port *port) 2058 { 2059 struct uart_8250_port *up = up_to_u8250p(port); 2060 unsigned long flags; 2061 2062 serial8250_rpm_get(up); 2063 /* 2064 * Disable interrupts from this port 2065 */ 2066 up->ier = 0; 2067 serial_port_out(port, UART_IER, 0); 2068 2069 if (up->dma) 2070 serial8250_release_dma(up); 2071 2072 spin_lock_irqsave(&port->lock, flags); 2073 if (port->flags & UPF_FOURPORT) { 2074 /* reset interrupts on the AST Fourport board */ 2075 inb((port->iobase & 0xfe0) | 0x1f); 2076 port->mctrl |= TIOCM_OUT1; 2077 } else 2078 port->mctrl &= ~TIOCM_OUT2; 2079 2080 serial8250_set_mctrl(port, port->mctrl); 2081 spin_unlock_irqrestore(&port->lock, flags); 2082 2083 /* 2084 * Disable break condition and FIFOs 2085 */ 2086 serial_port_out(port, UART_LCR, 2087 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); 2088 serial8250_clear_fifos(up); 2089 2090 #ifdef CONFIG_SERIAL_8250_RSA 2091 /* 2092 * Reset the RSA board back to 115kbps compat mode. 2093 */ 2094 disable_rsa(up); 2095 #endif 2096 2097 /* 2098 * Read data port to reset things, and then unlink from 2099 * the IRQ chain. 2100 */ 2101 serial_port_in(port, UART_RX); 2102 serial8250_rpm_put(up); 2103 2104 up->ops->release_irq(up); 2105 } 2106 EXPORT_SYMBOL_GPL(serial8250_do_shutdown); 2107 2108 static void serial8250_shutdown(struct uart_port *port) 2109 { 2110 if (port->shutdown) 2111 port->shutdown(port); 2112 else 2113 serial8250_do_shutdown(port); 2114 } 2115 2116 /* 2117 * XR17V35x UARTs have an extra fractional divisor register (DLD) 2118 * Calculate divisor with extra 4-bit fractional portion 2119 */ 2120 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up, 2121 unsigned int baud, 2122 unsigned int *frac) 2123 { 2124 struct uart_port *port = &up->port; 2125 unsigned int quot_16; 2126 2127 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud); 2128 *frac = quot_16 & 0x0f; 2129 2130 return quot_16 >> 4; 2131 } 2132 2133 static unsigned int serial8250_get_divisor(struct uart_8250_port *up, 2134 unsigned int baud, 2135 unsigned int *frac) 2136 { 2137 struct uart_port *port = &up->port; 2138 unsigned int quot; 2139 2140 /* 2141 * Handle magic divisors for baud rates above baud_base on 2142 * SMSC SuperIO chips. 2143 * 2144 */ 2145 if ((port->flags & UPF_MAGIC_MULTIPLIER) && 2146 baud == (port->uartclk/4)) 2147 quot = 0x8001; 2148 else if ((port->flags & UPF_MAGIC_MULTIPLIER) && 2149 baud == (port->uartclk/8)) 2150 quot = 0x8002; 2151 else if (up->port.type == PORT_XR17V35X) 2152 quot = xr17v35x_get_divisor(up, baud, frac); 2153 else 2154 quot = uart_get_divisor(port, baud); 2155 2156 /* 2157 * Oxford Semi 952 rev B workaround 2158 */ 2159 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) 2160 quot++; 2161 2162 return quot; 2163 } 2164 2165 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, 2166 tcflag_t c_cflag) 2167 { 2168 unsigned char cval; 2169 2170 switch (c_cflag & CSIZE) { 2171 case CS5: 2172 cval = UART_LCR_WLEN5; 2173 break; 2174 case CS6: 2175 cval = UART_LCR_WLEN6; 2176 break; 2177 case CS7: 2178 cval = UART_LCR_WLEN7; 2179 break; 2180 default: 2181 case CS8: 2182 cval = UART_LCR_WLEN8; 2183 break; 2184 } 2185 2186 if (c_cflag & CSTOPB) 2187 cval |= UART_LCR_STOP; 2188 if (c_cflag & PARENB) { 2189 cval |= UART_LCR_PARITY; 2190 if (up->bugs & UART_BUG_PARITY) 2191 up->fifo_bug = true; 2192 } 2193 if (!(c_cflag & PARODD)) 2194 cval |= UART_LCR_EPAR; 2195 #ifdef CMSPAR 2196 if (c_cflag & CMSPAR) 2197 cval |= UART_LCR_SPAR; 2198 #endif 2199 2200 return cval; 2201 } 2202 2203 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud, 2204 unsigned int quot, unsigned int quot_frac) 2205 { 2206 struct uart_8250_port *up = up_to_u8250p(port); 2207 2208 /* Workaround to enable 115200 baud on OMAP1510 internal ports */ 2209 if (is_omap1510_8250(up)) { 2210 if (baud == 115200) { 2211 quot = 1; 2212 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); 2213 } else 2214 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); 2215 } 2216 2217 /* 2218 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, 2219 * otherwise just set DLAB 2220 */ 2221 if (up->capabilities & UART_NATSEMI) 2222 serial_port_out(port, UART_LCR, 0xe0); 2223 else 2224 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB); 2225 2226 serial_dl_write(up, quot); 2227 2228 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */ 2229 if (up->port.type == PORT_XR17V35X) 2230 serial_port_out(port, 0x2, quot_frac); 2231 } 2232 2233 void 2234 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, 2235 struct ktermios *old) 2236 { 2237 struct uart_8250_port *up = up_to_u8250p(port); 2238 unsigned char cval; 2239 unsigned long flags; 2240 unsigned int baud, quot, frac = 0; 2241 2242 cval = serial8250_compute_lcr(up, termios->c_cflag); 2243 2244 /* 2245 * Ask the core to calculate the divisor for us. 2246 */ 2247 baud = uart_get_baud_rate(port, termios, old, 2248 port->uartclk / 16 / 0xffff, 2249 port->uartclk / 16); 2250 quot = serial8250_get_divisor(up, baud, &frac); 2251 2252 /* 2253 * Ok, we're now changing the port state. Do it with 2254 * interrupts disabled. 2255 */ 2256 serial8250_rpm_get(up); 2257 spin_lock_irqsave(&port->lock, flags); 2258 2259 up->lcr = cval; /* Save computed LCR */ 2260 2261 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { 2262 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */ 2263 if ((baud < 2400 && !up->dma) || up->fifo_bug) { 2264 up->fcr &= ~UART_FCR_TRIGGER_MASK; 2265 up->fcr |= UART_FCR_TRIGGER_1; 2266 } 2267 } 2268 2269 /* 2270 * MCR-based auto flow control. When AFE is enabled, RTS will be 2271 * deasserted when the receive FIFO contains more characters than 2272 * the trigger, or the MCR RTS bit is cleared. In the case where 2273 * the remote UART is not using CTS auto flow control, we must 2274 * have sufficient FIFO entries for the latency of the remote 2275 * UART to respond. IOW, at least 32 bytes of FIFO. 2276 */ 2277 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) { 2278 up->mcr &= ~UART_MCR_AFE; 2279 if (termios->c_cflag & CRTSCTS) 2280 up->mcr |= UART_MCR_AFE; 2281 } 2282 2283 /* 2284 * Update the per-port timeout. 2285 */ 2286 uart_update_timeout(port, termios->c_cflag, baud); 2287 2288 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 2289 if (termios->c_iflag & INPCK) 2290 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 2291 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2292 port->read_status_mask |= UART_LSR_BI; 2293 2294 /* 2295 * Characteres to ignore 2296 */ 2297 port->ignore_status_mask = 0; 2298 if (termios->c_iflag & IGNPAR) 2299 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 2300 if (termios->c_iflag & IGNBRK) { 2301 port->ignore_status_mask |= UART_LSR_BI; 2302 /* 2303 * If we're ignoring parity and break indicators, 2304 * ignore overruns too (for real raw support). 2305 */ 2306 if (termios->c_iflag & IGNPAR) 2307 port->ignore_status_mask |= UART_LSR_OE; 2308 } 2309 2310 /* 2311 * ignore all characters if CREAD is not set 2312 */ 2313 if ((termios->c_cflag & CREAD) == 0) 2314 port->ignore_status_mask |= UART_LSR_DR; 2315 2316 /* 2317 * CTS flow control flag and modem status interrupts 2318 */ 2319 up->ier &= ~UART_IER_MSI; 2320 if (!(up->bugs & UART_BUG_NOMSR) && 2321 UART_ENABLE_MS(&up->port, termios->c_cflag)) 2322 up->ier |= UART_IER_MSI; 2323 if (up->capabilities & UART_CAP_UUE) 2324 up->ier |= UART_IER_UUE; 2325 if (up->capabilities & UART_CAP_RTOIE) 2326 up->ier |= UART_IER_RTOIE; 2327 2328 serial_port_out(port, UART_IER, up->ier); 2329 2330 if (up->capabilities & UART_CAP_EFR) { 2331 unsigned char efr = 0; 2332 /* 2333 * TI16C752/Startech hardware flow control. FIXME: 2334 * - TI16C752 requires control thresholds to be set. 2335 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. 2336 */ 2337 if (termios->c_cflag & CRTSCTS) 2338 efr |= UART_EFR_CTS; 2339 2340 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2341 if (port->flags & UPF_EXAR_EFR) 2342 serial_port_out(port, UART_XR_EFR, efr); 2343 else 2344 serial_port_out(port, UART_EFR, efr); 2345 } 2346 2347 serial8250_set_divisor(port, baud, quot, frac); 2348 2349 /* 2350 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR 2351 * is written without DLAB set, this mode will be disabled. 2352 */ 2353 if (port->type == PORT_16750) 2354 serial_port_out(port, UART_FCR, up->fcr); 2355 2356 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */ 2357 if (port->type != PORT_16750) { 2358 /* emulated UARTs (Lucent Venus 167x) need two steps */ 2359 if (up->fcr & UART_FCR_ENABLE_FIFO) 2360 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); 2361 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */ 2362 } 2363 serial8250_set_mctrl(port, port->mctrl); 2364 spin_unlock_irqrestore(&port->lock, flags); 2365 serial8250_rpm_put(up); 2366 2367 /* Don't rewrite B0 */ 2368 if (tty_termios_baud_rate(termios)) 2369 tty_termios_encode_baud_rate(termios, baud, baud); 2370 } 2371 EXPORT_SYMBOL(serial8250_do_set_termios); 2372 2373 static void 2374 serial8250_set_termios(struct uart_port *port, struct ktermios *termios, 2375 struct ktermios *old) 2376 { 2377 if (port->set_termios) 2378 port->set_termios(port, termios, old); 2379 else 2380 serial8250_do_set_termios(port, termios, old); 2381 } 2382 2383 static void 2384 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios) 2385 { 2386 if (termios->c_line == N_PPS) { 2387 port->flags |= UPF_HARDPPS_CD; 2388 spin_lock_irq(&port->lock); 2389 serial8250_enable_ms(port); 2390 spin_unlock_irq(&port->lock); 2391 } else { 2392 port->flags &= ~UPF_HARDPPS_CD; 2393 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2394 spin_lock_irq(&port->lock); 2395 serial8250_disable_ms(port); 2396 spin_unlock_irq(&port->lock); 2397 } 2398 } 2399 } 2400 2401 2402 void serial8250_do_pm(struct uart_port *port, unsigned int state, 2403 unsigned int oldstate) 2404 { 2405 struct uart_8250_port *p = up_to_u8250p(port); 2406 2407 serial8250_set_sleep(p, state != 0); 2408 } 2409 EXPORT_SYMBOL(serial8250_do_pm); 2410 2411 static void 2412 serial8250_pm(struct uart_port *port, unsigned int state, 2413 unsigned int oldstate) 2414 { 2415 if (port->pm) 2416 port->pm(port, state, oldstate); 2417 else 2418 serial8250_do_pm(port, state, oldstate); 2419 } 2420 2421 static unsigned int serial8250_port_size(struct uart_8250_port *pt) 2422 { 2423 if (pt->port.mapsize) 2424 return pt->port.mapsize; 2425 if (pt->port.iotype == UPIO_AU) { 2426 if (pt->port.type == PORT_RT2880) 2427 return 0x100; 2428 return 0x1000; 2429 } 2430 if (is_omap1_8250(pt)) 2431 return 0x16 << pt->port.regshift; 2432 2433 return 8 << pt->port.regshift; 2434 } 2435 2436 /* 2437 * Resource handling. 2438 */ 2439 static int serial8250_request_std_resource(struct uart_8250_port *up) 2440 { 2441 unsigned int size = serial8250_port_size(up); 2442 struct uart_port *port = &up->port; 2443 int ret = 0; 2444 2445 switch (port->iotype) { 2446 case UPIO_AU: 2447 case UPIO_TSI: 2448 case UPIO_MEM32: 2449 case UPIO_MEM32BE: 2450 case UPIO_MEM: 2451 if (!port->mapbase) 2452 break; 2453 2454 if (!request_mem_region(port->mapbase, size, "serial")) { 2455 ret = -EBUSY; 2456 break; 2457 } 2458 2459 if (port->flags & UPF_IOREMAP) { 2460 port->membase = ioremap_nocache(port->mapbase, size); 2461 if (!port->membase) { 2462 release_mem_region(port->mapbase, size); 2463 ret = -ENOMEM; 2464 } 2465 } 2466 break; 2467 2468 case UPIO_HUB6: 2469 case UPIO_PORT: 2470 if (!request_region(port->iobase, size, "serial")) 2471 ret = -EBUSY; 2472 break; 2473 } 2474 return ret; 2475 } 2476 2477 static void serial8250_release_std_resource(struct uart_8250_port *up) 2478 { 2479 unsigned int size = serial8250_port_size(up); 2480 struct uart_port *port = &up->port; 2481 2482 switch (port->iotype) { 2483 case UPIO_AU: 2484 case UPIO_TSI: 2485 case UPIO_MEM32: 2486 case UPIO_MEM32BE: 2487 case UPIO_MEM: 2488 if (!port->mapbase) 2489 break; 2490 2491 if (port->flags & UPF_IOREMAP) { 2492 iounmap(port->membase); 2493 port->membase = NULL; 2494 } 2495 2496 release_mem_region(port->mapbase, size); 2497 break; 2498 2499 case UPIO_HUB6: 2500 case UPIO_PORT: 2501 release_region(port->iobase, size); 2502 break; 2503 } 2504 } 2505 2506 static void serial8250_release_port(struct uart_port *port) 2507 { 2508 struct uart_8250_port *up = up_to_u8250p(port); 2509 2510 serial8250_release_std_resource(up); 2511 } 2512 2513 static int serial8250_request_port(struct uart_port *port) 2514 { 2515 struct uart_8250_port *up = up_to_u8250p(port); 2516 int ret; 2517 2518 if (port->type == PORT_8250_CIR) 2519 return -ENODEV; 2520 2521 ret = serial8250_request_std_resource(up); 2522 2523 return ret; 2524 } 2525 2526 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up) 2527 { 2528 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 2529 unsigned char bytes; 2530 2531 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; 2532 2533 return bytes ? bytes : -EOPNOTSUPP; 2534 } 2535 2536 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes) 2537 { 2538 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 2539 int i; 2540 2541 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)]) 2542 return -EOPNOTSUPP; 2543 2544 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) { 2545 if (bytes < conf_type->rxtrig_bytes[i]) 2546 /* Use the nearest lower value */ 2547 return (--i) << UART_FCR_R_TRIG_SHIFT; 2548 } 2549 2550 return UART_FCR_R_TRIG_11; 2551 } 2552 2553 static int do_get_rxtrig(struct tty_port *port) 2554 { 2555 struct uart_state *state = container_of(port, struct uart_state, port); 2556 struct uart_port *uport = state->uart_port; 2557 struct uart_8250_port *up = 2558 container_of(uport, struct uart_8250_port, port); 2559 2560 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) 2561 return -EINVAL; 2562 2563 return fcr_get_rxtrig_bytes(up); 2564 } 2565 2566 static int do_serial8250_get_rxtrig(struct tty_port *port) 2567 { 2568 int rxtrig_bytes; 2569 2570 mutex_lock(&port->mutex); 2571 rxtrig_bytes = do_get_rxtrig(port); 2572 mutex_unlock(&port->mutex); 2573 2574 return rxtrig_bytes; 2575 } 2576 2577 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev, 2578 struct device_attribute *attr, char *buf) 2579 { 2580 struct tty_port *port = dev_get_drvdata(dev); 2581 int rxtrig_bytes; 2582 2583 rxtrig_bytes = do_serial8250_get_rxtrig(port); 2584 if (rxtrig_bytes < 0) 2585 return rxtrig_bytes; 2586 2587 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes); 2588 } 2589 2590 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) 2591 { 2592 struct uart_state *state = container_of(port, struct uart_state, port); 2593 struct uart_port *uport = state->uart_port; 2594 struct uart_8250_port *up = 2595 container_of(uport, struct uart_8250_port, port); 2596 int rxtrig; 2597 2598 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 || 2599 up->fifo_bug) 2600 return -EINVAL; 2601 2602 rxtrig = bytes_to_fcr_rxtrig(up, bytes); 2603 if (rxtrig < 0) 2604 return rxtrig; 2605 2606 serial8250_clear_fifos(up); 2607 up->fcr &= ~UART_FCR_TRIGGER_MASK; 2608 up->fcr |= (unsigned char)rxtrig; 2609 serial_out(up, UART_FCR, up->fcr); 2610 return 0; 2611 } 2612 2613 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes) 2614 { 2615 int ret; 2616 2617 mutex_lock(&port->mutex); 2618 ret = do_set_rxtrig(port, bytes); 2619 mutex_unlock(&port->mutex); 2620 2621 return ret; 2622 } 2623 2624 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev, 2625 struct device_attribute *attr, const char *buf, size_t count) 2626 { 2627 struct tty_port *port = dev_get_drvdata(dev); 2628 unsigned char bytes; 2629 int ret; 2630 2631 if (!count) 2632 return -EINVAL; 2633 2634 ret = kstrtou8(buf, 10, &bytes); 2635 if (ret < 0) 2636 return ret; 2637 2638 ret = do_serial8250_set_rxtrig(port, bytes); 2639 if (ret < 0) 2640 return ret; 2641 2642 return count; 2643 } 2644 2645 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP, 2646 serial8250_get_attr_rx_trig_bytes, 2647 serial8250_set_attr_rx_trig_bytes); 2648 2649 static struct attribute *serial8250_dev_attrs[] = { 2650 &dev_attr_rx_trig_bytes.attr, 2651 NULL, 2652 }; 2653 2654 static struct attribute_group serial8250_dev_attr_group = { 2655 .attrs = serial8250_dev_attrs, 2656 }; 2657 2658 static void register_dev_spec_attr_grp(struct uart_8250_port *up) 2659 { 2660 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 2661 2662 if (conf_type->rxtrig_bytes[0]) 2663 up->port.attr_group = &serial8250_dev_attr_group; 2664 } 2665 2666 static void serial8250_config_port(struct uart_port *port, int flags) 2667 { 2668 struct uart_8250_port *up = up_to_u8250p(port); 2669 int ret; 2670 2671 if (port->type == PORT_8250_CIR) 2672 return; 2673 2674 /* 2675 * Find the region that we can probe for. This in turn 2676 * tells us whether we can probe for the type of port. 2677 */ 2678 ret = serial8250_request_std_resource(up); 2679 if (ret < 0) 2680 return; 2681 2682 if (port->iotype != up->cur_iotype) 2683 set_io_from_upio(port); 2684 2685 if (flags & UART_CONFIG_TYPE) 2686 autoconfig(up); 2687 2688 /* if access method is AU, it is a 16550 with a quirk */ 2689 if (port->type == PORT_16550A && port->iotype == UPIO_AU) 2690 up->bugs |= UART_BUG_NOMSR; 2691 2692 /* HW bugs may trigger IRQ while IIR == NO_INT */ 2693 if (port->type == PORT_TEGRA) 2694 up->bugs |= UART_BUG_NOMSR; 2695 2696 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) 2697 autoconfig_irq(up); 2698 2699 if (port->type == PORT_UNKNOWN) 2700 serial8250_release_std_resource(up); 2701 2702 /* Fixme: probably not the best place for this */ 2703 if ((port->type == PORT_XR17V35X) || 2704 (port->type == PORT_XR17D15X)) 2705 port->handle_irq = exar_handle_irq; 2706 2707 register_dev_spec_attr_grp(up); 2708 up->fcr = uart_config[up->port.type].fcr; 2709 } 2710 2711 static int 2712 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) 2713 { 2714 if (ser->irq >= nr_irqs || ser->irq < 0 || 2715 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || 2716 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || 2717 ser->type == PORT_STARTECH) 2718 return -EINVAL; 2719 return 0; 2720 } 2721 2722 static const char * 2723 serial8250_type(struct uart_port *port) 2724 { 2725 int type = port->type; 2726 2727 if (type >= ARRAY_SIZE(uart_config)) 2728 type = 0; 2729 return uart_config[type].name; 2730 } 2731 2732 static const struct uart_ops serial8250_pops = { 2733 .tx_empty = serial8250_tx_empty, 2734 .set_mctrl = serial8250_set_mctrl, 2735 .get_mctrl = serial8250_get_mctrl, 2736 .stop_tx = serial8250_stop_tx, 2737 .start_tx = serial8250_start_tx, 2738 .throttle = serial8250_throttle, 2739 .unthrottle = serial8250_unthrottle, 2740 .stop_rx = serial8250_stop_rx, 2741 .enable_ms = serial8250_enable_ms, 2742 .break_ctl = serial8250_break_ctl, 2743 .startup = serial8250_startup, 2744 .shutdown = serial8250_shutdown, 2745 .set_termios = serial8250_set_termios, 2746 .set_ldisc = serial8250_set_ldisc, 2747 .pm = serial8250_pm, 2748 .type = serial8250_type, 2749 .release_port = serial8250_release_port, 2750 .request_port = serial8250_request_port, 2751 .config_port = serial8250_config_port, 2752 .verify_port = serial8250_verify_port, 2753 #ifdef CONFIG_CONSOLE_POLL 2754 .poll_get_char = serial8250_get_poll_char, 2755 .poll_put_char = serial8250_put_poll_char, 2756 #endif 2757 }; 2758 2759 void serial8250_init_port(struct uart_8250_port *up) 2760 { 2761 struct uart_port *port = &up->port; 2762 2763 spin_lock_init(&port->lock); 2764 port->ops = &serial8250_pops; 2765 2766 up->cur_iotype = 0xFF; 2767 } 2768 EXPORT_SYMBOL_GPL(serial8250_init_port); 2769 2770 void serial8250_set_defaults(struct uart_8250_port *up) 2771 { 2772 struct uart_port *port = &up->port; 2773 2774 if (up->port.flags & UPF_FIXED_TYPE) { 2775 unsigned int type = up->port.type; 2776 2777 if (!up->port.fifosize) 2778 up->port.fifosize = uart_config[type].fifo_size; 2779 if (!up->tx_loadsz) 2780 up->tx_loadsz = uart_config[type].tx_loadsz; 2781 if (!up->capabilities) 2782 up->capabilities = uart_config[type].flags; 2783 } 2784 2785 set_io_from_upio(port); 2786 2787 /* default dma handlers */ 2788 if (up->dma) { 2789 if (!up->dma->tx_dma) 2790 up->dma->tx_dma = serial8250_tx_dma; 2791 if (!up->dma->rx_dma) 2792 up->dma->rx_dma = serial8250_rx_dma; 2793 } 2794 } 2795 EXPORT_SYMBOL_GPL(serial8250_set_defaults); 2796 2797 #ifdef CONFIG_SERIAL_8250_CONSOLE 2798 2799 static void serial8250_console_putchar(struct uart_port *port, int ch) 2800 { 2801 struct uart_8250_port *up = up_to_u8250p(port); 2802 2803 wait_for_xmitr(up, UART_LSR_THRE); 2804 serial_port_out(port, UART_TX, ch); 2805 } 2806 2807 /* 2808 * Print a string to the serial port trying not to disturb 2809 * any possible real use of the port... 2810 * 2811 * The console_lock must be held when we get here. 2812 */ 2813 void serial8250_console_write(struct uart_8250_port *up, const char *s, 2814 unsigned int count) 2815 { 2816 struct uart_port *port = &up->port; 2817 unsigned long flags; 2818 unsigned int ier; 2819 int locked = 1; 2820 2821 touch_nmi_watchdog(); 2822 2823 serial8250_rpm_get(up); 2824 2825 if (port->sysrq) 2826 locked = 0; 2827 else if (oops_in_progress) 2828 locked = spin_trylock_irqsave(&port->lock, flags); 2829 else 2830 spin_lock_irqsave(&port->lock, flags); 2831 2832 /* 2833 * First save the IER then disable the interrupts 2834 */ 2835 ier = serial_port_in(port, UART_IER); 2836 2837 if (up->capabilities & UART_CAP_UUE) 2838 serial_port_out(port, UART_IER, UART_IER_UUE); 2839 else 2840 serial_port_out(port, UART_IER, 0); 2841 2842 /* check scratch reg to see if port powered off during system sleep */ 2843 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) { 2844 struct ktermios termios; 2845 unsigned int baud, quot, frac = 0; 2846 2847 termios.c_cflag = port->cons->cflag; 2848 if (port->state->port.tty && termios.c_cflag == 0) 2849 termios.c_cflag = port->state->port.tty->termios.c_cflag; 2850 2851 baud = uart_get_baud_rate(port, &termios, NULL, 2852 port->uartclk / 16 / 0xffff, 2853 port->uartclk / 16); 2854 quot = serial8250_get_divisor(up, baud, &frac); 2855 2856 serial8250_set_divisor(port, baud, quot, frac); 2857 serial_port_out(port, UART_LCR, up->lcr); 2858 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS); 2859 2860 up->canary = 0; 2861 } 2862 2863 uart_console_write(port, s, count, serial8250_console_putchar); 2864 2865 /* 2866 * Finally, wait for transmitter to become empty 2867 * and restore the IER 2868 */ 2869 wait_for_xmitr(up, BOTH_EMPTY); 2870 serial_port_out(port, UART_IER, ier); 2871 2872 /* 2873 * The receive handling will happen properly because the 2874 * receive ready bit will still be set; it is not cleared 2875 * on read. However, modem control will not, we must 2876 * call it if we have saved something in the saved flags 2877 * while processing with interrupts off. 2878 */ 2879 if (up->msr_saved_flags) 2880 serial8250_modem_status(up); 2881 2882 if (locked) 2883 spin_unlock_irqrestore(&port->lock, flags); 2884 serial8250_rpm_put(up); 2885 } 2886 2887 static unsigned int probe_baud(struct uart_port *port) 2888 { 2889 unsigned char lcr, dll, dlm; 2890 unsigned int quot; 2891 2892 lcr = serial_port_in(port, UART_LCR); 2893 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB); 2894 dll = serial_port_in(port, UART_DLL); 2895 dlm = serial_port_in(port, UART_DLM); 2896 serial_port_out(port, UART_LCR, lcr); 2897 2898 quot = (dlm << 8) | dll; 2899 return (port->uartclk / 16) / quot; 2900 } 2901 2902 int serial8250_console_setup(struct uart_port *port, char *options, bool probe) 2903 { 2904 int baud = 9600; 2905 int bits = 8; 2906 int parity = 'n'; 2907 int flow = 'n'; 2908 2909 if (!port->iobase && !port->membase) 2910 return -ENODEV; 2911 2912 if (options) 2913 uart_parse_options(options, &baud, &parity, &bits, &flow); 2914 else if (probe) 2915 baud = probe_baud(port); 2916 2917 return uart_set_options(port, port->cons, baud, parity, bits, flow); 2918 } 2919 2920 #endif /* CONFIG_SERIAL_8250_CONSOLE */ 2921 2922 MODULE_LICENSE("GPL"); 2923