1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Base port operations for 8250/16550-type serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * Split from 8250_core.c, Copyright (C) 2001 Russell King. 7 * 8 * A note about mapbase / membase 9 * 10 * mapbase is the physical address of the IO port. 11 * membase is an 'ioremapped' cookie. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/ioport.h> 17 #include <linux/init.h> 18 #include <linux/irq.h> 19 #include <linux/console.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/sysrq.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/tty.h> 25 #include <linux/ratelimit.h> 26 #include <linux/tty_flip.h> 27 #include <linux/serial.h> 28 #include <linux/serial_8250.h> 29 #include <linux/nmi.h> 30 #include <linux/mutex.h> 31 #include <linux/slab.h> 32 #include <linux/uaccess.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/ktime.h> 35 36 #include <asm/io.h> 37 #include <asm/irq.h> 38 39 #include "8250.h" 40 41 /* 42 * Debugging. 43 */ 44 #if 0 45 #define DEBUG_AUTOCONF(fmt...) printk(fmt) 46 #else 47 #define DEBUG_AUTOCONF(fmt...) do { } while (0) 48 #endif 49 50 /* 51 * Here we define the default xmit fifo size used for each type of UART. 52 */ 53 static const struct serial8250_config uart_config[] = { 54 [PORT_UNKNOWN] = { 55 .name = "unknown", 56 .fifo_size = 1, 57 .tx_loadsz = 1, 58 }, 59 [PORT_8250] = { 60 .name = "8250", 61 .fifo_size = 1, 62 .tx_loadsz = 1, 63 }, 64 [PORT_16450] = { 65 .name = "16450", 66 .fifo_size = 1, 67 .tx_loadsz = 1, 68 }, 69 [PORT_16550] = { 70 .name = "16550", 71 .fifo_size = 1, 72 .tx_loadsz = 1, 73 }, 74 [PORT_16550A] = { 75 .name = "16550A", 76 .fifo_size = 16, 77 .tx_loadsz = 16, 78 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 79 .rxtrig_bytes = {1, 4, 8, 14}, 80 .flags = UART_CAP_FIFO, 81 }, 82 [PORT_CIRRUS] = { 83 .name = "Cirrus", 84 .fifo_size = 1, 85 .tx_loadsz = 1, 86 }, 87 [PORT_16650] = { 88 .name = "ST16650", 89 .fifo_size = 1, 90 .tx_loadsz = 1, 91 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 92 }, 93 [PORT_16650V2] = { 94 .name = "ST16650V2", 95 .fifo_size = 32, 96 .tx_loadsz = 16, 97 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 98 UART_FCR_T_TRIG_00, 99 .rxtrig_bytes = {8, 16, 24, 28}, 100 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 101 }, 102 [PORT_16750] = { 103 .name = "TI16750", 104 .fifo_size = 64, 105 .tx_loadsz = 64, 106 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 107 UART_FCR7_64BYTE, 108 .rxtrig_bytes = {1, 16, 32, 56}, 109 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, 110 }, 111 [PORT_STARTECH] = { 112 .name = "Startech", 113 .fifo_size = 1, 114 .tx_loadsz = 1, 115 }, 116 [PORT_16C950] = { 117 .name = "16C950/954", 118 .fifo_size = 128, 119 .tx_loadsz = 128, 120 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, 121 .rxtrig_bytes = {16, 32, 112, 120}, 122 /* UART_CAP_EFR breaks billionon CF bluetooth card. */ 123 .flags = UART_CAP_FIFO | UART_CAP_SLEEP, 124 }, 125 [PORT_16654] = { 126 .name = "ST16654", 127 .fifo_size = 64, 128 .tx_loadsz = 32, 129 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 130 UART_FCR_T_TRIG_10, 131 .rxtrig_bytes = {8, 16, 56, 60}, 132 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 133 }, 134 [PORT_16850] = { 135 .name = "XR16850", 136 .fifo_size = 128, 137 .tx_loadsz = 128, 138 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 140 }, 141 [PORT_RSA] = { 142 .name = "RSA", 143 .fifo_size = 2048, 144 .tx_loadsz = 2048, 145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, 146 .flags = UART_CAP_FIFO, 147 }, 148 [PORT_NS16550A] = { 149 .name = "NS16550A", 150 .fifo_size = 16, 151 .tx_loadsz = 16, 152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 153 .flags = UART_CAP_FIFO | UART_NATSEMI, 154 }, 155 [PORT_XSCALE] = { 156 .name = "XScale", 157 .fifo_size = 32, 158 .tx_loadsz = 32, 159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 160 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, 161 }, 162 [PORT_OCTEON] = { 163 .name = "OCTEON", 164 .fifo_size = 64, 165 .tx_loadsz = 64, 166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 167 .flags = UART_CAP_FIFO, 168 }, 169 [PORT_U6_16550A] = { 170 .name = "U6_16550A", 171 .fifo_size = 64, 172 .tx_loadsz = 64, 173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 174 .flags = UART_CAP_FIFO | UART_CAP_AFE, 175 }, 176 [PORT_TEGRA] = { 177 .name = "Tegra", 178 .fifo_size = 32, 179 .tx_loadsz = 8, 180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 181 UART_FCR_T_TRIG_01, 182 .rxtrig_bytes = {1, 4, 8, 14}, 183 .flags = UART_CAP_FIFO | UART_CAP_RTOIE, 184 }, 185 [PORT_XR17D15X] = { 186 .name = "XR17D15X", 187 .fifo_size = 64, 188 .tx_loadsz = 64, 189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 190 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | 191 UART_CAP_SLEEP, 192 }, 193 [PORT_XR17V35X] = { 194 .name = "XR17V35X", 195 .fifo_size = 256, 196 .tx_loadsz = 256, 197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 | 198 UART_FCR_T_TRIG_11, 199 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | 200 UART_CAP_SLEEP, 201 }, 202 [PORT_LPC3220] = { 203 .name = "LPC3220", 204 .fifo_size = 64, 205 .tx_loadsz = 32, 206 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | 207 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00, 208 .flags = UART_CAP_FIFO, 209 }, 210 [PORT_BRCM_TRUMANAGE] = { 211 .name = "TruManage", 212 .fifo_size = 1, 213 .tx_loadsz = 1024, 214 .flags = UART_CAP_HFIFO, 215 }, 216 [PORT_8250_CIR] = { 217 .name = "CIR port" 218 }, 219 [PORT_ALTR_16550_F32] = { 220 .name = "Altera 16550 FIFO32", 221 .fifo_size = 32, 222 .tx_loadsz = 32, 223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 224 .rxtrig_bytes = {1, 8, 16, 30}, 225 .flags = UART_CAP_FIFO | UART_CAP_AFE, 226 }, 227 [PORT_ALTR_16550_F64] = { 228 .name = "Altera 16550 FIFO64", 229 .fifo_size = 64, 230 .tx_loadsz = 64, 231 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 232 .rxtrig_bytes = {1, 16, 32, 62}, 233 .flags = UART_CAP_FIFO | UART_CAP_AFE, 234 }, 235 [PORT_ALTR_16550_F128] = { 236 .name = "Altera 16550 FIFO128", 237 .fifo_size = 128, 238 .tx_loadsz = 128, 239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 240 .rxtrig_bytes = {1, 32, 64, 126}, 241 .flags = UART_CAP_FIFO | UART_CAP_AFE, 242 }, 243 /* 244 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement 245 * workaround of errata A-008006 which states that tx_loadsz should 246 * be configured less than Maximum supported fifo bytes. 247 */ 248 [PORT_16550A_FSL64] = { 249 .name = "16550A_FSL64", 250 .fifo_size = 64, 251 .tx_loadsz = 63, 252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 253 UART_FCR7_64BYTE, 254 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT, 255 }, 256 [PORT_RT2880] = { 257 .name = "Palmchip BK-3103", 258 .fifo_size = 16, 259 .tx_loadsz = 16, 260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 261 .rxtrig_bytes = {1, 4, 8, 14}, 262 .flags = UART_CAP_FIFO, 263 }, 264 [PORT_DA830] = { 265 .name = "TI DA8xx/66AK2x", 266 .fifo_size = 16, 267 .tx_loadsz = 16, 268 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | 269 UART_FCR_R_TRIG_10, 270 .rxtrig_bytes = {1, 4, 8, 14}, 271 .flags = UART_CAP_FIFO | UART_CAP_AFE, 272 }, 273 [PORT_MTK_BTIF] = { 274 .name = "MediaTek BTIF", 275 .fifo_size = 16, 276 .tx_loadsz = 16, 277 .fcr = UART_FCR_ENABLE_FIFO | 278 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 279 .flags = UART_CAP_FIFO, 280 }, 281 [PORT_NPCM] = { 282 .name = "Nuvoton 16550", 283 .fifo_size = 16, 284 .tx_loadsz = 16, 285 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 286 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 287 .rxtrig_bytes = {1, 4, 8, 14}, 288 .flags = UART_CAP_FIFO, 289 }, 290 [PORT_SUNIX] = { 291 .name = "Sunix", 292 .fifo_size = 128, 293 .tx_loadsz = 128, 294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 295 .rxtrig_bytes = {1, 32, 64, 112}, 296 .flags = UART_CAP_FIFO | UART_CAP_SLEEP, 297 }, 298 [PORT_ASPEED_VUART] = { 299 .name = "ASPEED VUART", 300 .fifo_size = 16, 301 .tx_loadsz = 16, 302 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, 303 .rxtrig_bytes = {1, 4, 8, 14}, 304 .flags = UART_CAP_FIFO, 305 }, 306 [PORT_MCHP16550A] = { 307 .name = "MCHP16550A", 308 .fifo_size = 256, 309 .tx_loadsz = 256, 310 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, 311 .rxtrig_bytes = {2, 66, 130, 194}, 312 .flags = UART_CAP_FIFO, 313 }, 314 [PORT_BCM7271] = { 315 .name = "Broadcom BCM7271 UART", 316 .fifo_size = 32, 317 .tx_loadsz = 32, 318 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, 319 .rxtrig_bytes = {1, 8, 16, 30}, 320 .flags = UART_CAP_FIFO | UART_CAP_AFE, 321 }, 322 }; 323 324 /* Uart divisor latch read */ 325 static u32 default_serial_dl_read(struct uart_8250_port *up) 326 { 327 /* Assign these in pieces to truncate any bits above 7. */ 328 unsigned char dll = serial_in(up, UART_DLL); 329 unsigned char dlm = serial_in(up, UART_DLM); 330 331 return dll | dlm << 8; 332 } 333 334 /* Uart divisor latch write */ 335 static void default_serial_dl_write(struct uart_8250_port *up, u32 value) 336 { 337 serial_out(up, UART_DLL, value & 0xff); 338 serial_out(up, UART_DLM, value >> 8 & 0xff); 339 } 340 341 static unsigned int hub6_serial_in(struct uart_port *p, int offset) 342 { 343 offset = offset << p->regshift; 344 outb(p->hub6 - 1 + offset, p->iobase); 345 return inb(p->iobase + 1); 346 } 347 348 static void hub6_serial_out(struct uart_port *p, int offset, int value) 349 { 350 offset = offset << p->regshift; 351 outb(p->hub6 - 1 + offset, p->iobase); 352 outb(value, p->iobase + 1); 353 } 354 355 static unsigned int mem_serial_in(struct uart_port *p, int offset) 356 { 357 offset = offset << p->regshift; 358 return readb(p->membase + offset); 359 } 360 361 static void mem_serial_out(struct uart_port *p, int offset, int value) 362 { 363 offset = offset << p->regshift; 364 writeb(value, p->membase + offset); 365 } 366 367 static void mem16_serial_out(struct uart_port *p, int offset, int value) 368 { 369 offset = offset << p->regshift; 370 writew(value, p->membase + offset); 371 } 372 373 static unsigned int mem16_serial_in(struct uart_port *p, int offset) 374 { 375 offset = offset << p->regshift; 376 return readw(p->membase + offset); 377 } 378 379 static void mem32_serial_out(struct uart_port *p, int offset, int value) 380 { 381 offset = offset << p->regshift; 382 writel(value, p->membase + offset); 383 } 384 385 static unsigned int mem32_serial_in(struct uart_port *p, int offset) 386 { 387 offset = offset << p->regshift; 388 return readl(p->membase + offset); 389 } 390 391 static void mem32be_serial_out(struct uart_port *p, int offset, int value) 392 { 393 offset = offset << p->regshift; 394 iowrite32be(value, p->membase + offset); 395 } 396 397 static unsigned int mem32be_serial_in(struct uart_port *p, int offset) 398 { 399 offset = offset << p->regshift; 400 return ioread32be(p->membase + offset); 401 } 402 403 static unsigned int io_serial_in(struct uart_port *p, int offset) 404 { 405 offset = offset << p->regshift; 406 return inb(p->iobase + offset); 407 } 408 409 static void io_serial_out(struct uart_port *p, int offset, int value) 410 { 411 offset = offset << p->regshift; 412 outb(value, p->iobase + offset); 413 } 414 415 static int serial8250_default_handle_irq(struct uart_port *port); 416 417 static void set_io_from_upio(struct uart_port *p) 418 { 419 struct uart_8250_port *up = up_to_u8250p(p); 420 421 up->dl_read = default_serial_dl_read; 422 up->dl_write = default_serial_dl_write; 423 424 switch (p->iotype) { 425 case UPIO_HUB6: 426 p->serial_in = hub6_serial_in; 427 p->serial_out = hub6_serial_out; 428 break; 429 430 case UPIO_MEM: 431 p->serial_in = mem_serial_in; 432 p->serial_out = mem_serial_out; 433 break; 434 435 case UPIO_MEM16: 436 p->serial_in = mem16_serial_in; 437 p->serial_out = mem16_serial_out; 438 break; 439 440 case UPIO_MEM32: 441 p->serial_in = mem32_serial_in; 442 p->serial_out = mem32_serial_out; 443 break; 444 445 case UPIO_MEM32BE: 446 p->serial_in = mem32be_serial_in; 447 p->serial_out = mem32be_serial_out; 448 break; 449 450 default: 451 p->serial_in = io_serial_in; 452 p->serial_out = io_serial_out; 453 break; 454 } 455 /* Remember loaded iotype */ 456 up->cur_iotype = p->iotype; 457 p->handle_irq = serial8250_default_handle_irq; 458 } 459 460 static void 461 serial_port_out_sync(struct uart_port *p, int offset, int value) 462 { 463 switch (p->iotype) { 464 case UPIO_MEM: 465 case UPIO_MEM16: 466 case UPIO_MEM32: 467 case UPIO_MEM32BE: 468 case UPIO_AU: 469 p->serial_out(p, offset, value); 470 p->serial_in(p, UART_LCR); /* safe, no side-effects */ 471 break; 472 default: 473 p->serial_out(p, offset, value); 474 } 475 } 476 477 /* 478 * FIFO support. 479 */ 480 static void serial8250_clear_fifos(struct uart_8250_port *p) 481 { 482 if (p->capabilities & UART_CAP_FIFO) { 483 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); 484 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | 485 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 486 serial_out(p, UART_FCR, 0); 487 } 488 } 489 490 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t); 491 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t); 492 493 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) 494 { 495 serial8250_clear_fifos(p); 496 serial_out(p, UART_FCR, p->fcr); 497 } 498 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); 499 500 void serial8250_rpm_get(struct uart_8250_port *p) 501 { 502 if (!(p->capabilities & UART_CAP_RPM)) 503 return; 504 pm_runtime_get_sync(p->port.dev); 505 } 506 EXPORT_SYMBOL_GPL(serial8250_rpm_get); 507 508 void serial8250_rpm_put(struct uart_8250_port *p) 509 { 510 if (!(p->capabilities & UART_CAP_RPM)) 511 return; 512 pm_runtime_mark_last_busy(p->port.dev); 513 pm_runtime_put_autosuspend(p->port.dev); 514 } 515 EXPORT_SYMBOL_GPL(serial8250_rpm_put); 516 517 /** 518 * serial8250_em485_init() - put uart_8250_port into rs485 emulating 519 * @p: uart_8250_port port instance 520 * 521 * The function is used to start rs485 software emulating on the 522 * &struct uart_8250_port* @p. Namely, RTS is switched before/after 523 * transmission. The function is idempotent, so it is safe to call it 524 * multiple times. 525 * 526 * The caller MUST enable interrupt on empty shift register before 527 * calling serial8250_em485_init(). This interrupt is not a part of 528 * 8250 standard, but implementation defined. 529 * 530 * The function is supposed to be called from .rs485_config callback 531 * or from any other callback protected with p->port.lock spinlock. 532 * 533 * See also serial8250_em485_destroy() 534 * 535 * Return 0 - success, -errno - otherwise 536 */ 537 static int serial8250_em485_init(struct uart_8250_port *p) 538 { 539 /* Port locked to synchronize UART_IER access against the console. */ 540 lockdep_assert_held_once(&p->port.lock); 541 542 if (p->em485) 543 goto deassert_rts; 544 545 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC); 546 if (!p->em485) 547 return -ENOMEM; 548 549 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC, 550 HRTIMER_MODE_REL); 551 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC, 552 HRTIMER_MODE_REL); 553 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx; 554 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx; 555 p->em485->port = p; 556 p->em485->active_timer = NULL; 557 p->em485->tx_stopped = true; 558 559 deassert_rts: 560 if (p->em485->tx_stopped) 561 p->rs485_stop_tx(p); 562 563 return 0; 564 } 565 566 /** 567 * serial8250_em485_destroy() - put uart_8250_port into normal state 568 * @p: uart_8250_port port instance 569 * 570 * The function is used to stop rs485 software emulating on the 571 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to 572 * call it multiple times. 573 * 574 * The function is supposed to be called from .rs485_config callback 575 * or from any other callback protected with p->port.lock spinlock. 576 * 577 * See also serial8250_em485_init() 578 */ 579 void serial8250_em485_destroy(struct uart_8250_port *p) 580 { 581 if (!p->em485) 582 return; 583 584 hrtimer_cancel(&p->em485->start_tx_timer); 585 hrtimer_cancel(&p->em485->stop_tx_timer); 586 587 kfree(p->em485); 588 p->em485 = NULL; 589 } 590 EXPORT_SYMBOL_GPL(serial8250_em485_destroy); 591 592 struct serial_rs485 serial8250_em485_supported = { 593 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 594 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX, 595 .delay_rts_before_send = 1, 596 .delay_rts_after_send = 1, 597 }; 598 EXPORT_SYMBOL_GPL(serial8250_em485_supported); 599 600 /** 601 * serial8250_em485_config() - generic ->rs485_config() callback 602 * @port: uart port 603 * @termios: termios structure 604 * @rs485: rs485 settings 605 * 606 * Generic callback usable by 8250 uart drivers to activate rs485 settings 607 * if the uart is incapable of driving RTS as a Transmit Enable signal in 608 * hardware, relying on software emulation instead. 609 */ 610 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios, 611 struct serial_rs485 *rs485) 612 { 613 struct uart_8250_port *up = up_to_u8250p(port); 614 615 /* 616 * Both serial8250_em485_init() and serial8250_em485_destroy() 617 * are idempotent. 618 */ 619 if (rs485->flags & SER_RS485_ENABLED) 620 return serial8250_em485_init(up); 621 622 serial8250_em485_destroy(up); 623 return 0; 624 } 625 EXPORT_SYMBOL_GPL(serial8250_em485_config); 626 627 /* 628 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than 629 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is 630 * empty and the HW can idle again. 631 */ 632 void serial8250_rpm_get_tx(struct uart_8250_port *p) 633 { 634 unsigned char rpm_active; 635 636 if (!(p->capabilities & UART_CAP_RPM)) 637 return; 638 639 rpm_active = xchg(&p->rpm_tx_active, 1); 640 if (rpm_active) 641 return; 642 pm_runtime_get_sync(p->port.dev); 643 } 644 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx); 645 646 void serial8250_rpm_put_tx(struct uart_8250_port *p) 647 { 648 unsigned char rpm_active; 649 650 if (!(p->capabilities & UART_CAP_RPM)) 651 return; 652 653 rpm_active = xchg(&p->rpm_tx_active, 0); 654 if (!rpm_active) 655 return; 656 pm_runtime_mark_last_busy(p->port.dev); 657 pm_runtime_put_autosuspend(p->port.dev); 658 } 659 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx); 660 661 /* 662 * IER sleep support. UARTs which have EFRs need the "extended 663 * capability" bit enabled. Note that on XR16C850s, we need to 664 * reset LCR to write to IER. 665 */ 666 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) 667 { 668 unsigned char lcr = 0, efr = 0; 669 670 serial8250_rpm_get(p); 671 672 if (p->capabilities & UART_CAP_SLEEP) { 673 /* Synchronize UART_IER access against the console. */ 674 uart_port_lock_irq(&p->port); 675 if (p->capabilities & UART_CAP_EFR) { 676 lcr = serial_in(p, UART_LCR); 677 efr = serial_in(p, UART_EFR); 678 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); 679 serial_out(p, UART_EFR, UART_EFR_ECB); 680 serial_out(p, UART_LCR, 0); 681 } 682 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); 683 if (p->capabilities & UART_CAP_EFR) { 684 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); 685 serial_out(p, UART_EFR, efr); 686 serial_out(p, UART_LCR, lcr); 687 } 688 uart_port_unlock_irq(&p->port); 689 } 690 691 serial8250_rpm_put(p); 692 } 693 694 static void serial8250_clear_IER(struct uart_8250_port *up) 695 { 696 if (up->capabilities & UART_CAP_UUE) 697 serial_out(up, UART_IER, UART_IER_UUE); 698 else 699 serial_out(up, UART_IER, 0); 700 } 701 702 #ifdef CONFIG_SERIAL_8250_RSA 703 /* 704 * Attempts to turn on the RSA FIFO. Returns zero on failure. 705 * We set the port uart clock rate if we succeed. 706 */ 707 static int __enable_rsa(struct uart_8250_port *up) 708 { 709 unsigned char mode; 710 int result; 711 712 mode = serial_in(up, UART_RSA_MSR); 713 result = mode & UART_RSA_MSR_FIFO; 714 715 if (!result) { 716 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); 717 mode = serial_in(up, UART_RSA_MSR); 718 result = mode & UART_RSA_MSR_FIFO; 719 } 720 721 if (result) 722 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; 723 724 return result; 725 } 726 727 static void enable_rsa(struct uart_8250_port *up) 728 { 729 if (up->port.type == PORT_RSA) { 730 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 731 uart_port_lock_irq(&up->port); 732 __enable_rsa(up); 733 uart_port_unlock_irq(&up->port); 734 } 735 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 736 serial_out(up, UART_RSA_FRR, 0); 737 } 738 } 739 740 /* 741 * Attempts to turn off the RSA FIFO. Returns zero on failure. 742 * It is unknown why interrupts were disabled in here. However, 743 * the caller is expected to preserve this behaviour by grabbing 744 * the spinlock before calling this function. 745 */ 746 static void disable_rsa(struct uart_8250_port *up) 747 { 748 unsigned char mode; 749 int result; 750 751 if (up->port.type == PORT_RSA && 752 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 753 uart_port_lock_irq(&up->port); 754 755 mode = serial_in(up, UART_RSA_MSR); 756 result = !(mode & UART_RSA_MSR_FIFO); 757 758 if (!result) { 759 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); 760 mode = serial_in(up, UART_RSA_MSR); 761 result = !(mode & UART_RSA_MSR_FIFO); 762 } 763 764 if (result) 765 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 766 uart_port_unlock_irq(&up->port); 767 } 768 } 769 #endif /* CONFIG_SERIAL_8250_RSA */ 770 771 /* 772 * This is a quickie test to see how big the FIFO is. 773 * It doesn't work at all the time, more's the pity. 774 */ 775 static int size_fifo(struct uart_8250_port *up) 776 { 777 unsigned char old_fcr, old_mcr, old_lcr; 778 u32 old_dl; 779 int count; 780 781 old_lcr = serial_in(up, UART_LCR); 782 serial_out(up, UART_LCR, 0); 783 old_fcr = serial_in(up, UART_FCR); 784 old_mcr = serial8250_in_MCR(up); 785 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 786 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 787 serial8250_out_MCR(up, UART_MCR_LOOP); 788 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 789 old_dl = serial_dl_read(up); 790 serial_dl_write(up, 0x0001); 791 serial_out(up, UART_LCR, UART_LCR_WLEN8); 792 for (count = 0; count < 256; count++) 793 serial_out(up, UART_TX, count); 794 mdelay(20);/* FIXME - schedule_timeout */ 795 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && 796 (count < 256); count++) 797 serial_in(up, UART_RX); 798 serial_out(up, UART_FCR, old_fcr); 799 serial8250_out_MCR(up, old_mcr); 800 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 801 serial_dl_write(up, old_dl); 802 serial_out(up, UART_LCR, old_lcr); 803 804 return count; 805 } 806 807 /* 808 * Read UART ID using the divisor method - set DLL and DLM to zero 809 * and the revision will be in DLL and device type in DLM. We 810 * preserve the device state across this. 811 */ 812 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) 813 { 814 unsigned char old_lcr; 815 unsigned int id, old_dl; 816 817 old_lcr = serial_in(p, UART_LCR); 818 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); 819 old_dl = serial_dl_read(p); 820 serial_dl_write(p, 0); 821 id = serial_dl_read(p); 822 serial_dl_write(p, old_dl); 823 824 serial_out(p, UART_LCR, old_lcr); 825 826 return id; 827 } 828 829 /* 830 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. 831 * When this function is called we know it is at least a StarTech 832 * 16650 V2, but it might be one of several StarTech UARTs, or one of 833 * its clones. (We treat the broken original StarTech 16650 V1 as a 834 * 16550, and why not? Startech doesn't seem to even acknowledge its 835 * existence.) 836 * 837 * What evil have men's minds wrought... 838 */ 839 static void autoconfig_has_efr(struct uart_8250_port *up) 840 { 841 unsigned int id1, id2, id3, rev; 842 843 /* 844 * Everything with an EFR has SLEEP 845 */ 846 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 847 848 /* 849 * First we check to see if it's an Oxford Semiconductor UART. 850 * 851 * If we have to do this here because some non-National 852 * Semiconductor clone chips lock up if you try writing to the 853 * LSR register (which serial_icr_read does) 854 */ 855 856 /* 857 * Check for Oxford Semiconductor 16C950. 858 * 859 * EFR [4] must be set else this test fails. 860 * 861 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) 862 * claims that it's needed for 952 dual UART's (which are not 863 * recommended for new designs). 864 */ 865 up->acr = 0; 866 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 867 serial_out(up, UART_EFR, UART_EFR_ECB); 868 serial_out(up, UART_LCR, 0x00); 869 id1 = serial_icr_read(up, UART_ID1); 870 id2 = serial_icr_read(up, UART_ID2); 871 id3 = serial_icr_read(up, UART_ID3); 872 rev = serial_icr_read(up, UART_REV); 873 874 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); 875 876 if (id1 == 0x16 && id2 == 0xC9 && 877 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { 878 up->port.type = PORT_16C950; 879 880 /* 881 * Enable work around for the Oxford Semiconductor 952 rev B 882 * chip which causes it to seriously miscalculate baud rates 883 * when DLL is 0. 884 */ 885 if (id3 == 0x52 && rev == 0x01) 886 up->bugs |= UART_BUG_QUOT; 887 return; 888 } 889 890 /* 891 * We check for a XR16C850 by setting DLL and DLM to 0, and then 892 * reading back DLL and DLM. The chip type depends on the DLM 893 * value read back: 894 * 0x10 - XR16C850 and the DLL contains the chip revision. 895 * 0x12 - XR16C2850. 896 * 0x14 - XR16C854. 897 */ 898 id1 = autoconfig_read_divisor_id(up); 899 DEBUG_AUTOCONF("850id=%04x ", id1); 900 901 id2 = id1 >> 8; 902 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { 903 up->port.type = PORT_16850; 904 return; 905 } 906 907 /* 908 * It wasn't an XR16C850. 909 * 910 * We distinguish between the '654 and the '650 by counting 911 * how many bytes are in the FIFO. I'm using this for now, 912 * since that's the technique that was sent to me in the 913 * serial driver update, but I'm not convinced this works. 914 * I've had problems doing this in the past. -TYT 915 */ 916 if (size_fifo(up) == 64) 917 up->port.type = PORT_16654; 918 else 919 up->port.type = PORT_16650V2; 920 } 921 922 /* 923 * We detected a chip without a FIFO. Only two fall into 924 * this category - the original 8250 and the 16450. The 925 * 16450 has a scratch register (accessible with LCR=0) 926 */ 927 static void autoconfig_8250(struct uart_8250_port *up) 928 { 929 unsigned char scratch, status1, status2; 930 931 up->port.type = PORT_8250; 932 933 scratch = serial_in(up, UART_SCR); 934 serial_out(up, UART_SCR, 0xa5); 935 status1 = serial_in(up, UART_SCR); 936 serial_out(up, UART_SCR, 0x5a); 937 status2 = serial_in(up, UART_SCR); 938 serial_out(up, UART_SCR, scratch); 939 940 if (status1 == 0xa5 && status2 == 0x5a) 941 up->port.type = PORT_16450; 942 } 943 944 static int broken_efr(struct uart_8250_port *up) 945 { 946 /* 947 * Exar ST16C2550 "A2" devices incorrectly detect as 948 * having an EFR, and report an ID of 0x0201. See 949 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html 950 */ 951 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) 952 return 1; 953 954 return 0; 955 } 956 957 /* 958 * We know that the chip has FIFOs. Does it have an EFR? The 959 * EFR is located in the same register position as the IIR and 960 * we know the top two bits of the IIR are currently set. The 961 * EFR should contain zero. Try to read the EFR. 962 */ 963 static void autoconfig_16550a(struct uart_8250_port *up) 964 { 965 unsigned char status1, status2; 966 unsigned int iersave; 967 968 /* Port locked to synchronize UART_IER access against the console. */ 969 lockdep_assert_held_once(&up->port.lock); 970 971 up->port.type = PORT_16550A; 972 up->capabilities |= UART_CAP_FIFO; 973 974 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) && 975 !(up->port.flags & UPF_FULL_PROBE)) 976 return; 977 978 /* 979 * Check for presence of the EFR when DLAB is set. 980 * Only ST16C650V1 UARTs pass this test. 981 */ 982 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 983 if (serial_in(up, UART_EFR) == 0) { 984 serial_out(up, UART_EFR, 0xA8); 985 if (serial_in(up, UART_EFR) != 0) { 986 DEBUG_AUTOCONF("EFRv1 "); 987 up->port.type = PORT_16650; 988 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 989 } else { 990 serial_out(up, UART_LCR, 0); 991 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 992 UART_FCR7_64BYTE); 993 status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 994 serial_out(up, UART_FCR, 0); 995 serial_out(up, UART_LCR, 0); 996 997 if (status1 == UART_IIR_FIFO_ENABLED_16750) 998 up->port.type = PORT_16550A_FSL64; 999 else 1000 DEBUG_AUTOCONF("Motorola 8xxx DUART "); 1001 } 1002 serial_out(up, UART_EFR, 0); 1003 return; 1004 } 1005 1006 /* 1007 * Maybe it requires 0xbf to be written to the LCR. 1008 * (other ST16C650V2 UARTs, TI16C752A, etc) 1009 */ 1010 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1011 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { 1012 DEBUG_AUTOCONF("EFRv2 "); 1013 autoconfig_has_efr(up); 1014 return; 1015 } 1016 1017 /* 1018 * Check for a National Semiconductor SuperIO chip. 1019 * Attempt to switch to bank 2, read the value of the LOOP bit 1020 * from EXCR1. Switch back to bank 0, change it in MCR. Then 1021 * switch back to bank 2, read it from EXCR1 again and check 1022 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 1023 */ 1024 serial_out(up, UART_LCR, 0); 1025 status1 = serial8250_in_MCR(up); 1026 serial_out(up, UART_LCR, 0xE0); 1027 status2 = serial_in(up, 0x02); /* EXCR1 */ 1028 1029 if (!((status2 ^ status1) & UART_MCR_LOOP)) { 1030 serial_out(up, UART_LCR, 0); 1031 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP); 1032 serial_out(up, UART_LCR, 0xE0); 1033 status2 = serial_in(up, 0x02); /* EXCR1 */ 1034 serial_out(up, UART_LCR, 0); 1035 serial8250_out_MCR(up, status1); 1036 1037 if ((status2 ^ status1) & UART_MCR_LOOP) { 1038 unsigned short quot; 1039 1040 serial_out(up, UART_LCR, 0xE0); 1041 1042 quot = serial_dl_read(up); 1043 quot <<= 3; 1044 1045 if (ns16550a_goto_highspeed(up)) 1046 serial_dl_write(up, quot); 1047 1048 serial_out(up, UART_LCR, 0); 1049 1050 up->port.uartclk = 921600*16; 1051 up->port.type = PORT_NS16550A; 1052 up->capabilities |= UART_NATSEMI; 1053 return; 1054 } 1055 } 1056 1057 /* 1058 * No EFR. Try to detect a TI16750, which only sets bit 5 of 1059 * the IIR when 64 byte FIFO mode is enabled when DLAB is set. 1060 * Try setting it with and without DLAB set. Cheap clones 1061 * set bit 5 without DLAB set. 1062 */ 1063 serial_out(up, UART_LCR, 0); 1064 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1065 status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 1066 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1067 1068 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1069 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1070 status2 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 1071 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1072 1073 serial_out(up, UART_LCR, 0); 1074 1075 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); 1076 1077 if (status1 == UART_IIR_FIFO_ENABLED_16550A && 1078 status2 == UART_IIR_FIFO_ENABLED_16750) { 1079 up->port.type = PORT_16750; 1080 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; 1081 return; 1082 } 1083 1084 /* 1085 * Try writing and reading the UART_IER_UUE bit (b6). 1086 * If it works, this is probably one of the Xscale platform's 1087 * internal UARTs. 1088 * We're going to explicitly set the UUE bit to 0 before 1089 * trying to write and read a 1 just to make sure it's not 1090 * already a 1 and maybe locked there before we even start. 1091 */ 1092 iersave = serial_in(up, UART_IER); 1093 serial_out(up, UART_IER, iersave & ~UART_IER_UUE); 1094 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { 1095 /* 1096 * OK it's in a known zero state, try writing and reading 1097 * without disturbing the current state of the other bits. 1098 */ 1099 serial_out(up, UART_IER, iersave | UART_IER_UUE); 1100 if (serial_in(up, UART_IER) & UART_IER_UUE) { 1101 /* 1102 * It's an Xscale. 1103 * We'll leave the UART_IER_UUE bit set to 1 (enabled). 1104 */ 1105 DEBUG_AUTOCONF("Xscale "); 1106 up->port.type = PORT_XSCALE; 1107 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; 1108 return; 1109 } 1110 } else { 1111 /* 1112 * If we got here we couldn't force the IER_UUE bit to 0. 1113 * Log it and continue. 1114 */ 1115 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); 1116 } 1117 serial_out(up, UART_IER, iersave); 1118 1119 /* 1120 * We distinguish between 16550A and U6 16550A by counting 1121 * how many bytes are in the FIFO. 1122 */ 1123 if (up->port.type == PORT_16550A && size_fifo(up) == 64) { 1124 up->port.type = PORT_U6_16550A; 1125 up->capabilities |= UART_CAP_AFE; 1126 } 1127 } 1128 1129 /* 1130 * This routine is called by rs_init() to initialize a specific serial 1131 * port. It determines what type of UART chip this serial port is 1132 * using: 8250, 16450, 16550, 16550A. The important question is 1133 * whether or not this UART is a 16550A or not, since this will 1134 * determine whether or not we can use its FIFO features or not. 1135 */ 1136 static void autoconfig(struct uart_8250_port *up) 1137 { 1138 unsigned char status1, scratch, scratch2, scratch3; 1139 unsigned char save_lcr, save_mcr; 1140 struct uart_port *port = &up->port; 1141 unsigned long flags; 1142 unsigned int old_capabilities; 1143 1144 if (!port->iobase && !port->mapbase && !port->membase) 1145 return; 1146 1147 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ", 1148 port->name, port->iobase, port->membase); 1149 1150 /* 1151 * We really do need global IRQs disabled here - we're going to 1152 * be frobbing the chips IRQ enable register to see if it exists. 1153 * 1154 * Synchronize UART_IER access against the console. 1155 */ 1156 uart_port_lock_irqsave(port, &flags); 1157 1158 up->capabilities = 0; 1159 up->bugs = 0; 1160 1161 if (!(port->flags & UPF_BUGGY_UART)) { 1162 /* 1163 * Do a simple existence test first; if we fail this, 1164 * there's no point trying anything else. 1165 * 1166 * 0x80 is used as a nonsense port to prevent against 1167 * false positives due to ISA bus float. The 1168 * assumption is that 0x80 is a non-existent port; 1169 * which should be safe since include/asm/io.h also 1170 * makes this assumption. 1171 * 1172 * Note: this is safe as long as MCR bit 4 is clear 1173 * and the device is in "PC" mode. 1174 */ 1175 scratch = serial_in(up, UART_IER); 1176 serial_out(up, UART_IER, 0); 1177 #ifdef __i386__ 1178 outb(0xff, 0x080); 1179 #endif 1180 /* 1181 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL 1182 * 16C754B) allow only to modify them if an EFR bit is set. 1183 */ 1184 scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR; 1185 serial_out(up, UART_IER, UART_IER_ALL_INTR); 1186 #ifdef __i386__ 1187 outb(0, 0x080); 1188 #endif 1189 scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR; 1190 serial_out(up, UART_IER, scratch); 1191 if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) { 1192 /* 1193 * We failed; there's nothing here 1194 */ 1195 uart_port_unlock_irqrestore(port, flags); 1196 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", 1197 scratch2, scratch3); 1198 goto out; 1199 } 1200 } 1201 1202 save_mcr = serial8250_in_MCR(up); 1203 save_lcr = serial_in(up, UART_LCR); 1204 1205 /* 1206 * Check to see if a UART is really there. Certain broken 1207 * internal modems based on the Rockwell chipset fail this 1208 * test, because they apparently don't implement the loopback 1209 * test mode. So this test is skipped on the COM 1 through 1210 * COM 4 ports. This *should* be safe, since no board 1211 * manufacturer would be stupid enough to design a board 1212 * that conflicts with COM 1-4 --- we hope! 1213 */ 1214 if (!(port->flags & UPF_SKIP_TEST)) { 1215 serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS); 1216 status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS; 1217 serial8250_out_MCR(up, save_mcr); 1218 if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) { 1219 uart_port_unlock_irqrestore(port, flags); 1220 DEBUG_AUTOCONF("LOOP test failed (%02x) ", 1221 status1); 1222 goto out; 1223 } 1224 } 1225 1226 /* 1227 * We're pretty sure there's a port here. Lets find out what 1228 * type of port it is. The IIR top two bits allows us to find 1229 * out if it's 8250 or 16450, 16550, 16550A or later. This 1230 * determines what we test for next. 1231 * 1232 * We also initialise the EFR (if any) to zero for later. The 1233 * EFR occupies the same register location as the FCR and IIR. 1234 */ 1235 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1236 serial_out(up, UART_EFR, 0); 1237 serial_out(up, UART_LCR, 0); 1238 1239 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1240 1241 switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) { 1242 case UART_IIR_FIFO_ENABLED_8250: 1243 autoconfig_8250(up); 1244 break; 1245 case UART_IIR_FIFO_ENABLED_16550: 1246 port->type = PORT_16550; 1247 break; 1248 case UART_IIR_FIFO_ENABLED_16550A: 1249 autoconfig_16550a(up); 1250 break; 1251 default: 1252 port->type = PORT_UNKNOWN; 1253 break; 1254 } 1255 1256 #ifdef CONFIG_SERIAL_8250_RSA 1257 /* 1258 * Only probe for RSA ports if we got the region. 1259 */ 1260 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA && 1261 __enable_rsa(up)) 1262 port->type = PORT_RSA; 1263 #endif 1264 1265 serial_out(up, UART_LCR, save_lcr); 1266 1267 port->fifosize = uart_config[up->port.type].fifo_size; 1268 old_capabilities = up->capabilities; 1269 up->capabilities = uart_config[port->type].flags; 1270 up->tx_loadsz = uart_config[port->type].tx_loadsz; 1271 1272 if (port->type == PORT_UNKNOWN) 1273 goto out_unlock; 1274 1275 /* 1276 * Reset the UART. 1277 */ 1278 #ifdef CONFIG_SERIAL_8250_RSA 1279 if (port->type == PORT_RSA) 1280 serial_out(up, UART_RSA_FRR, 0); 1281 #endif 1282 serial8250_out_MCR(up, save_mcr); 1283 serial8250_clear_fifos(up); 1284 serial_in(up, UART_RX); 1285 serial8250_clear_IER(up); 1286 1287 out_unlock: 1288 uart_port_unlock_irqrestore(port, flags); 1289 1290 /* 1291 * Check if the device is a Fintek F81216A 1292 */ 1293 if (port->type == PORT_16550A && port->iotype == UPIO_PORT) 1294 fintek_8250_probe(up); 1295 1296 if (up->capabilities != old_capabilities) { 1297 dev_warn(port->dev, "detected caps %08x should be %08x\n", 1298 old_capabilities, up->capabilities); 1299 } 1300 out: 1301 DEBUG_AUTOCONF("iir=%d ", scratch); 1302 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name); 1303 } 1304 1305 static void autoconfig_irq(struct uart_8250_port *up) 1306 { 1307 struct uart_port *port = &up->port; 1308 unsigned char save_mcr, save_ier; 1309 unsigned char save_ICP = 0; 1310 unsigned int ICP = 0; 1311 unsigned long irqs; 1312 int irq; 1313 1314 if (port->flags & UPF_FOURPORT) { 1315 ICP = (port->iobase & 0xfe0) | 0x1f; 1316 save_ICP = inb_p(ICP); 1317 outb_p(0x80, ICP); 1318 inb_p(ICP); 1319 } 1320 1321 /* forget possible initially masked and pending IRQ */ 1322 probe_irq_off(probe_irq_on()); 1323 save_mcr = serial8250_in_MCR(up); 1324 /* Synchronize UART_IER access against the console. */ 1325 uart_port_lock_irq(port); 1326 save_ier = serial_in(up, UART_IER); 1327 uart_port_unlock_irq(port); 1328 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2); 1329 1330 irqs = probe_irq_on(); 1331 serial8250_out_MCR(up, 0); 1332 udelay(10); 1333 if (port->flags & UPF_FOURPORT) { 1334 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS); 1335 } else { 1336 serial8250_out_MCR(up, 1337 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); 1338 } 1339 /* Synchronize UART_IER access against the console. */ 1340 uart_port_lock_irq(port); 1341 serial_out(up, UART_IER, UART_IER_ALL_INTR); 1342 uart_port_unlock_irq(port); 1343 serial_in(up, UART_LSR); 1344 serial_in(up, UART_RX); 1345 serial_in(up, UART_IIR); 1346 serial_in(up, UART_MSR); 1347 serial_out(up, UART_TX, 0xFF); 1348 udelay(20); 1349 irq = probe_irq_off(irqs); 1350 1351 serial8250_out_MCR(up, save_mcr); 1352 /* Synchronize UART_IER access against the console. */ 1353 uart_port_lock_irq(port); 1354 serial_out(up, UART_IER, save_ier); 1355 uart_port_unlock_irq(port); 1356 1357 if (port->flags & UPF_FOURPORT) 1358 outb_p(save_ICP, ICP); 1359 1360 port->irq = (irq > 0) ? irq : 0; 1361 } 1362 1363 static void serial8250_stop_rx(struct uart_port *port) 1364 { 1365 struct uart_8250_port *up = up_to_u8250p(port); 1366 1367 /* Port locked to synchronize UART_IER access against the console. */ 1368 lockdep_assert_held_once(&port->lock); 1369 1370 serial8250_rpm_get(up); 1371 1372 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1373 up->port.read_status_mask &= ~UART_LSR_DR; 1374 serial_port_out(port, UART_IER, up->ier); 1375 1376 serial8250_rpm_put(up); 1377 } 1378 1379 /** 1380 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback 1381 * @p: uart 8250 port 1382 * 1383 * Generic callback usable by 8250 uart drivers to stop rs485 transmission. 1384 */ 1385 void serial8250_em485_stop_tx(struct uart_8250_port *p) 1386 { 1387 unsigned char mcr = serial8250_in_MCR(p); 1388 1389 /* Port locked to synchronize UART_IER access against the console. */ 1390 lockdep_assert_held_once(&p->port.lock); 1391 1392 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND) 1393 mcr |= UART_MCR_RTS; 1394 else 1395 mcr &= ~UART_MCR_RTS; 1396 serial8250_out_MCR(p, mcr); 1397 1398 /* 1399 * Empty the RX FIFO, we are not interested in anything 1400 * received during the half-duplex transmission. 1401 * Enable previously disabled RX interrupts. 1402 */ 1403 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) { 1404 serial8250_clear_and_reinit_fifos(p); 1405 1406 p->ier |= UART_IER_RLSI | UART_IER_RDI; 1407 serial_port_out(&p->port, UART_IER, p->ier); 1408 } 1409 } 1410 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx); 1411 1412 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t) 1413 { 1414 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485, 1415 stop_tx_timer); 1416 struct uart_8250_port *p = em485->port; 1417 unsigned long flags; 1418 1419 serial8250_rpm_get(p); 1420 uart_port_lock_irqsave(&p->port, &flags); 1421 if (em485->active_timer == &em485->stop_tx_timer) { 1422 p->rs485_stop_tx(p); 1423 em485->active_timer = NULL; 1424 em485->tx_stopped = true; 1425 } 1426 uart_port_unlock_irqrestore(&p->port, flags); 1427 serial8250_rpm_put(p); 1428 1429 return HRTIMER_NORESTART; 1430 } 1431 1432 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 1433 { 1434 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 1435 } 1436 1437 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay) 1438 { 1439 struct uart_8250_em485 *em485 = p->em485; 1440 1441 /* Port locked to synchronize UART_IER access against the console. */ 1442 lockdep_assert_held_once(&p->port.lock); 1443 1444 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC; 1445 1446 /* 1447 * rs485_stop_tx() is going to set RTS according to config 1448 * AND flush RX FIFO if required. 1449 */ 1450 if (stop_delay > 0) { 1451 em485->active_timer = &em485->stop_tx_timer; 1452 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL); 1453 } else { 1454 p->rs485_stop_tx(p); 1455 em485->active_timer = NULL; 1456 em485->tx_stopped = true; 1457 } 1458 } 1459 1460 static inline void __stop_tx(struct uart_8250_port *p) 1461 { 1462 struct uart_8250_em485 *em485 = p->em485; 1463 1464 if (em485) { 1465 u16 lsr = serial_lsr_in(p); 1466 u64 stop_delay = 0; 1467 1468 if (!(lsr & UART_LSR_THRE)) 1469 return; 1470 /* 1471 * To provide required timing and allow FIFO transfer, 1472 * __stop_tx_rs485() must be called only when both FIFO and 1473 * shift register are empty. The device driver should either 1474 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will 1475 * enlarge stop_tx_timer by the tx time of one frame to cover 1476 * for emptying of the shift register. 1477 */ 1478 if (!(lsr & UART_LSR_TEMT)) { 1479 if (!(p->capabilities & UART_CAP_NOTEMT)) 1480 return; 1481 /* 1482 * RTS might get deasserted too early with the normal 1483 * frame timing formula. It seems to suggest THRE might 1484 * get asserted already during tx of the stop bit 1485 * rather than after it is fully sent. 1486 * Roughly estimate 1 extra bit here with / 7. 1487 */ 1488 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7); 1489 } 1490 1491 __stop_tx_rs485(p, stop_delay); 1492 } 1493 1494 if (serial8250_clear_THRI(p)) 1495 serial8250_rpm_put_tx(p); 1496 } 1497 1498 static void serial8250_stop_tx(struct uart_port *port) 1499 { 1500 struct uart_8250_port *up = up_to_u8250p(port); 1501 1502 serial8250_rpm_get(up); 1503 __stop_tx(up); 1504 1505 /* 1506 * We really want to stop the transmitter from sending. 1507 */ 1508 if (port->type == PORT_16C950) { 1509 up->acr |= UART_ACR_TXDIS; 1510 serial_icr_write(up, UART_ACR, up->acr); 1511 } 1512 serial8250_rpm_put(up); 1513 } 1514 1515 static inline void __start_tx(struct uart_port *port) 1516 { 1517 struct uart_8250_port *up = up_to_u8250p(port); 1518 1519 if (up->dma && !up->dma->tx_dma(up)) 1520 return; 1521 1522 if (serial8250_set_THRI(up)) { 1523 if (up->bugs & UART_BUG_TXEN) { 1524 u16 lsr = serial_lsr_in(up); 1525 1526 if (lsr & UART_LSR_THRE) 1527 serial8250_tx_chars(up); 1528 } 1529 } 1530 1531 /* 1532 * Re-enable the transmitter if we disabled it. 1533 */ 1534 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 1535 up->acr &= ~UART_ACR_TXDIS; 1536 serial_icr_write(up, UART_ACR, up->acr); 1537 } 1538 } 1539 1540 /** 1541 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback 1542 * @up: uart 8250 port 1543 * 1544 * Generic callback usable by 8250 uart drivers to start rs485 transmission. 1545 * Assumes that setting the RTS bit in the MCR register means RTS is high. 1546 * (Some chips use inverse semantics.) Further assumes that reception is 1547 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the 1548 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.) 1549 */ 1550 void serial8250_em485_start_tx(struct uart_8250_port *up) 1551 { 1552 unsigned char mcr = serial8250_in_MCR(up); 1553 1554 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1555 serial8250_stop_rx(&up->port); 1556 1557 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) 1558 mcr |= UART_MCR_RTS; 1559 else 1560 mcr &= ~UART_MCR_RTS; 1561 serial8250_out_MCR(up, mcr); 1562 } 1563 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx); 1564 1565 /* Returns false, if start_tx_timer was setup to defer TX start */ 1566 static bool start_tx_rs485(struct uart_port *port) 1567 { 1568 struct uart_8250_port *up = up_to_u8250p(port); 1569 struct uart_8250_em485 *em485 = up->em485; 1570 1571 /* 1572 * While serial8250_em485_handle_stop_tx() is a noop if 1573 * em485->active_timer != &em485->stop_tx_timer, it might happen that 1574 * the timer is still armed and triggers only after the current bunch of 1575 * chars is send and em485->active_timer == &em485->stop_tx_timer again. 1576 * So cancel the timer. There is still a theoretical race condition if 1577 * the timer is already running and only comes around to check for 1578 * em485->active_timer when &em485->stop_tx_timer is armed again. 1579 */ 1580 if (em485->active_timer == &em485->stop_tx_timer) 1581 hrtimer_try_to_cancel(&em485->stop_tx_timer); 1582 1583 em485->active_timer = NULL; 1584 1585 if (em485->tx_stopped) { 1586 em485->tx_stopped = false; 1587 1588 up->rs485_start_tx(up); 1589 1590 if (up->port.rs485.delay_rts_before_send > 0) { 1591 em485->active_timer = &em485->start_tx_timer; 1592 start_hrtimer_ms(&em485->start_tx_timer, 1593 up->port.rs485.delay_rts_before_send); 1594 return false; 1595 } 1596 } 1597 1598 return true; 1599 } 1600 1601 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t) 1602 { 1603 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485, 1604 start_tx_timer); 1605 struct uart_8250_port *p = em485->port; 1606 unsigned long flags; 1607 1608 uart_port_lock_irqsave(&p->port, &flags); 1609 if (em485->active_timer == &em485->start_tx_timer) { 1610 __start_tx(&p->port); 1611 em485->active_timer = NULL; 1612 } 1613 uart_port_unlock_irqrestore(&p->port, flags); 1614 1615 return HRTIMER_NORESTART; 1616 } 1617 1618 static void serial8250_start_tx(struct uart_port *port) 1619 { 1620 struct uart_8250_port *up = up_to_u8250p(port); 1621 struct uart_8250_em485 *em485 = up->em485; 1622 1623 /* Port locked to synchronize UART_IER access against the console. */ 1624 lockdep_assert_held_once(&port->lock); 1625 1626 if (!port->x_char && kfifo_is_empty(&port->state->port.xmit_fifo)) 1627 return; 1628 1629 serial8250_rpm_get_tx(up); 1630 1631 if (em485) { 1632 if ((em485->active_timer == &em485->start_tx_timer) || 1633 !start_tx_rs485(port)) 1634 return; 1635 } 1636 __start_tx(port); 1637 } 1638 1639 static void serial8250_throttle(struct uart_port *port) 1640 { 1641 port->throttle(port); 1642 } 1643 1644 static void serial8250_unthrottle(struct uart_port *port) 1645 { 1646 port->unthrottle(port); 1647 } 1648 1649 static void serial8250_disable_ms(struct uart_port *port) 1650 { 1651 struct uart_8250_port *up = up_to_u8250p(port); 1652 1653 /* Port locked to synchronize UART_IER access against the console. */ 1654 lockdep_assert_held_once(&port->lock); 1655 1656 /* no MSR capabilities */ 1657 if (up->bugs & UART_BUG_NOMSR) 1658 return; 1659 1660 mctrl_gpio_disable_ms(up->gpios); 1661 1662 up->ier &= ~UART_IER_MSI; 1663 serial_port_out(port, UART_IER, up->ier); 1664 } 1665 1666 static void serial8250_enable_ms(struct uart_port *port) 1667 { 1668 struct uart_8250_port *up = up_to_u8250p(port); 1669 1670 /* Port locked to synchronize UART_IER access against the console. */ 1671 lockdep_assert_held_once(&port->lock); 1672 1673 /* no MSR capabilities */ 1674 if (up->bugs & UART_BUG_NOMSR) 1675 return; 1676 1677 mctrl_gpio_enable_ms(up->gpios); 1678 1679 up->ier |= UART_IER_MSI; 1680 1681 serial8250_rpm_get(up); 1682 serial_port_out(port, UART_IER, up->ier); 1683 serial8250_rpm_put(up); 1684 } 1685 1686 void serial8250_read_char(struct uart_8250_port *up, u16 lsr) 1687 { 1688 struct uart_port *port = &up->port; 1689 u8 ch, flag = TTY_NORMAL; 1690 1691 if (likely(lsr & UART_LSR_DR)) 1692 ch = serial_in(up, UART_RX); 1693 else 1694 /* 1695 * Intel 82571 has a Serial Over Lan device that will 1696 * set UART_LSR_BI without setting UART_LSR_DR when 1697 * it receives a break. To avoid reading from the 1698 * receive buffer without UART_LSR_DR bit set, we 1699 * just force the read character to be 0 1700 */ 1701 ch = 0; 1702 1703 port->icount.rx++; 1704 1705 lsr |= up->lsr_saved_flags; 1706 up->lsr_saved_flags = 0; 1707 1708 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { 1709 if (lsr & UART_LSR_BI) { 1710 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 1711 port->icount.brk++; 1712 /* 1713 * We do the SysRQ and SAK checking 1714 * here because otherwise the break 1715 * may get masked by ignore_status_mask 1716 * or read_status_mask. 1717 */ 1718 if (uart_handle_break(port)) 1719 return; 1720 } else if (lsr & UART_LSR_PE) 1721 port->icount.parity++; 1722 else if (lsr & UART_LSR_FE) 1723 port->icount.frame++; 1724 if (lsr & UART_LSR_OE) 1725 port->icount.overrun++; 1726 1727 /* 1728 * Mask off conditions which should be ignored. 1729 */ 1730 lsr &= port->read_status_mask; 1731 1732 if (lsr & UART_LSR_BI) { 1733 dev_dbg(port->dev, "handling break\n"); 1734 flag = TTY_BREAK; 1735 } else if (lsr & UART_LSR_PE) 1736 flag = TTY_PARITY; 1737 else if (lsr & UART_LSR_FE) 1738 flag = TTY_FRAME; 1739 } 1740 if (uart_prepare_sysrq_char(port, ch)) 1741 return; 1742 1743 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); 1744 } 1745 EXPORT_SYMBOL_GPL(serial8250_read_char); 1746 1747 /* 1748 * serial8250_rx_chars - Read characters. The first LSR value must be passed in. 1749 * 1750 * Returns LSR bits. The caller should rely only on non-Rx related LSR bits 1751 * (such as THRE) because the LSR value might come from an already consumed 1752 * character. 1753 */ 1754 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr) 1755 { 1756 struct uart_port *port = &up->port; 1757 int max_count = 256; 1758 1759 do { 1760 serial8250_read_char(up, lsr); 1761 if (--max_count == 0) 1762 break; 1763 lsr = serial_in(up, UART_LSR); 1764 } while (lsr & (UART_LSR_DR | UART_LSR_BI)); 1765 1766 tty_flip_buffer_push(&port->state->port); 1767 return lsr; 1768 } 1769 EXPORT_SYMBOL_GPL(serial8250_rx_chars); 1770 1771 void serial8250_tx_chars(struct uart_8250_port *up) 1772 { 1773 struct uart_port *port = &up->port; 1774 struct tty_port *tport = &port->state->port; 1775 int count; 1776 1777 if (port->x_char) { 1778 uart_xchar_out(port, UART_TX); 1779 return; 1780 } 1781 if (uart_tx_stopped(port)) { 1782 serial8250_stop_tx(port); 1783 return; 1784 } 1785 if (kfifo_is_empty(&tport->xmit_fifo)) { 1786 __stop_tx(up); 1787 return; 1788 } 1789 1790 count = up->tx_loadsz; 1791 do { 1792 unsigned char c; 1793 1794 if (!uart_fifo_get(port, &c)) 1795 break; 1796 1797 serial_out(up, UART_TX, c); 1798 if (up->bugs & UART_BUG_TXRACE) { 1799 /* 1800 * The Aspeed BMC virtual UARTs have a bug where data 1801 * may get stuck in the BMC's Tx FIFO from bursts of 1802 * writes on the APB interface. 1803 * 1804 * Delay back-to-back writes by a read cycle to avoid 1805 * stalling the VUART. Read a register that won't have 1806 * side-effects and discard the result. 1807 */ 1808 serial_in(up, UART_SCR); 1809 } 1810 1811 if ((up->capabilities & UART_CAP_HFIFO) && 1812 !uart_lsr_tx_empty(serial_in(up, UART_LSR))) 1813 break; 1814 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */ 1815 if ((up->capabilities & UART_CAP_MINI) && 1816 !(serial_in(up, UART_LSR) & UART_LSR_THRE)) 1817 break; 1818 } while (--count > 0); 1819 1820 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1821 uart_write_wakeup(port); 1822 1823 /* 1824 * With RPM enabled, we have to wait until the FIFO is empty before the 1825 * HW can go idle. So we get here once again with empty FIFO and disable 1826 * the interrupt and RPM in __stop_tx() 1827 */ 1828 if (kfifo_is_empty(&tport->xmit_fifo) && 1829 !(up->capabilities & UART_CAP_RPM)) 1830 __stop_tx(up); 1831 } 1832 EXPORT_SYMBOL_GPL(serial8250_tx_chars); 1833 1834 /* Caller holds uart port lock */ 1835 unsigned int serial8250_modem_status(struct uart_8250_port *up) 1836 { 1837 struct uart_port *port = &up->port; 1838 unsigned int status = serial_in(up, UART_MSR); 1839 1840 status |= up->msr_saved_flags; 1841 up->msr_saved_flags = 0; 1842 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 1843 port->state != NULL) { 1844 if (status & UART_MSR_TERI) 1845 port->icount.rng++; 1846 if (status & UART_MSR_DDSR) 1847 port->icount.dsr++; 1848 if (status & UART_MSR_DDCD) 1849 uart_handle_dcd_change(port, status & UART_MSR_DCD); 1850 if (status & UART_MSR_DCTS) 1851 uart_handle_cts_change(port, status & UART_MSR_CTS); 1852 1853 wake_up_interruptible(&port->state->port.delta_msr_wait); 1854 } 1855 1856 return status; 1857 } 1858 EXPORT_SYMBOL_GPL(serial8250_modem_status); 1859 1860 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1861 { 1862 switch (iir & 0x3f) { 1863 case UART_IIR_THRI: 1864 /* 1865 * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT 1866 * because it's impossible to do an informed decision about 1867 * that with IIR_THRI. 1868 * 1869 * This also fixes one known DMA Rx corruption issue where 1870 * DR is asserted but DMA Rx only gets a corrupted zero byte 1871 * (too early DR?). 1872 */ 1873 return false; 1874 case UART_IIR_RDI: 1875 if (!up->dma->rx_running) 1876 break; 1877 fallthrough; 1878 case UART_IIR_RLSI: 1879 case UART_IIR_RX_TIMEOUT: 1880 serial8250_rx_dma_flush(up); 1881 return true; 1882 } 1883 return up->dma->rx_dma(up); 1884 } 1885 1886 /* 1887 * This handles the interrupt from one port. 1888 */ 1889 int serial8250_handle_irq(struct uart_port *port, unsigned int iir) 1890 { 1891 struct uart_8250_port *up = up_to_u8250p(port); 1892 struct tty_port *tport = &port->state->port; 1893 bool skip_rx = false; 1894 unsigned long flags; 1895 u16 status; 1896 1897 if (iir & UART_IIR_NO_INT) 1898 return 0; 1899 1900 uart_port_lock_irqsave(port, &flags); 1901 1902 status = serial_lsr_in(up); 1903 1904 /* 1905 * If port is stopped and there are no error conditions in the 1906 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer 1907 * overflow. Not servicing, RX FIFO would trigger auto HW flow 1908 * control when FIFO occupancy reaches preset threshold, thus 1909 * halting RX. This only works when auto HW flow control is 1910 * available. 1911 */ 1912 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) && 1913 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) && 1914 !(port->read_status_mask & UART_LSR_DR)) 1915 skip_rx = true; 1916 1917 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) { 1918 struct irq_data *d; 1919 1920 d = irq_get_irq_data(port->irq); 1921 if (d && irqd_is_wakeup_set(d)) 1922 pm_wakeup_event(tport->tty->dev, 0); 1923 if (!up->dma || handle_rx_dma(up, iir)) 1924 status = serial8250_rx_chars(up, status); 1925 } 1926 serial8250_modem_status(up); 1927 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) { 1928 if (!up->dma || up->dma->tx_err) 1929 serial8250_tx_chars(up); 1930 else if (!up->dma->tx_running) 1931 __stop_tx(up); 1932 } 1933 1934 uart_unlock_and_check_sysrq_irqrestore(port, flags); 1935 1936 return 1; 1937 } 1938 EXPORT_SYMBOL_GPL(serial8250_handle_irq); 1939 1940 static int serial8250_default_handle_irq(struct uart_port *port) 1941 { 1942 struct uart_8250_port *up = up_to_u8250p(port); 1943 unsigned int iir; 1944 int ret; 1945 1946 serial8250_rpm_get(up); 1947 1948 iir = serial_port_in(port, UART_IIR); 1949 ret = serial8250_handle_irq(port, iir); 1950 1951 serial8250_rpm_put(up); 1952 return ret; 1953 } 1954 1955 /* 1956 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP 1957 * have a programmable TX threshold that triggers the THRE interrupt in 1958 * the IIR register. In this case, the THRE interrupt indicates the FIFO 1959 * has space available. Load it up with tx_loadsz bytes. 1960 */ 1961 static int serial8250_tx_threshold_handle_irq(struct uart_port *port) 1962 { 1963 unsigned long flags; 1964 unsigned int iir = serial_port_in(port, UART_IIR); 1965 1966 /* TX Threshold IRQ triggered so load up FIFO */ 1967 if ((iir & UART_IIR_ID) == UART_IIR_THRI) { 1968 struct uart_8250_port *up = up_to_u8250p(port); 1969 1970 uart_port_lock_irqsave(port, &flags); 1971 serial8250_tx_chars(up); 1972 uart_port_unlock_irqrestore(port, flags); 1973 } 1974 1975 iir = serial_port_in(port, UART_IIR); 1976 return serial8250_handle_irq(port, iir); 1977 } 1978 1979 static unsigned int serial8250_tx_empty(struct uart_port *port) 1980 { 1981 struct uart_8250_port *up = up_to_u8250p(port); 1982 unsigned int result = 0; 1983 unsigned long flags; 1984 1985 serial8250_rpm_get(up); 1986 1987 uart_port_lock_irqsave(port, &flags); 1988 if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up))) 1989 result = TIOCSER_TEMT; 1990 uart_port_unlock_irqrestore(port, flags); 1991 1992 serial8250_rpm_put(up); 1993 1994 return result; 1995 } 1996 1997 unsigned int serial8250_do_get_mctrl(struct uart_port *port) 1998 { 1999 struct uart_8250_port *up = up_to_u8250p(port); 2000 unsigned int status; 2001 unsigned int val; 2002 2003 serial8250_rpm_get(up); 2004 status = serial8250_modem_status(up); 2005 serial8250_rpm_put(up); 2006 2007 val = serial8250_MSR_to_TIOCM(status); 2008 if (up->gpios) 2009 return mctrl_gpio_get(up->gpios, &val); 2010 2011 return val; 2012 } 2013 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl); 2014 2015 static unsigned int serial8250_get_mctrl(struct uart_port *port) 2016 { 2017 if (port->get_mctrl) 2018 return port->get_mctrl(port); 2019 return serial8250_do_get_mctrl(port); 2020 } 2021 2022 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl) 2023 { 2024 struct uart_8250_port *up = up_to_u8250p(port); 2025 unsigned char mcr; 2026 2027 mcr = serial8250_TIOCM_to_MCR(mctrl); 2028 2029 mcr |= up->mcr; 2030 2031 serial8250_out_MCR(up, mcr); 2032 } 2033 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl); 2034 2035 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 2036 { 2037 if (port->rs485.flags & SER_RS485_ENABLED) 2038 return; 2039 2040 if (port->set_mctrl) 2041 port->set_mctrl(port, mctrl); 2042 else 2043 serial8250_do_set_mctrl(port, mctrl); 2044 } 2045 2046 static void serial8250_break_ctl(struct uart_port *port, int break_state) 2047 { 2048 struct uart_8250_port *up = up_to_u8250p(port); 2049 unsigned long flags; 2050 2051 serial8250_rpm_get(up); 2052 uart_port_lock_irqsave(port, &flags); 2053 if (break_state == -1) 2054 up->lcr |= UART_LCR_SBC; 2055 else 2056 up->lcr &= ~UART_LCR_SBC; 2057 serial_port_out(port, UART_LCR, up->lcr); 2058 uart_port_unlock_irqrestore(port, flags); 2059 serial8250_rpm_put(up); 2060 } 2061 2062 static void wait_for_lsr(struct uart_8250_port *up, int bits) 2063 { 2064 unsigned int status, tmout = 10000; 2065 2066 /* Wait up to 10ms for the character(s) to be sent. */ 2067 for (;;) { 2068 status = serial_lsr_in(up); 2069 2070 if ((status & bits) == bits) 2071 break; 2072 if (--tmout == 0) 2073 break; 2074 udelay(1); 2075 touch_nmi_watchdog(); 2076 } 2077 } 2078 2079 /* 2080 * Wait for transmitter & holding register to empty 2081 */ 2082 static void wait_for_xmitr(struct uart_8250_port *up, int bits) 2083 { 2084 unsigned int tmout; 2085 2086 wait_for_lsr(up, bits); 2087 2088 /* Wait up to 1s for flow control if necessary */ 2089 if (up->port.flags & UPF_CONS_FLOW) { 2090 for (tmout = 1000000; tmout; tmout--) { 2091 unsigned int msr = serial_in(up, UART_MSR); 2092 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 2093 if (msr & UART_MSR_CTS) 2094 break; 2095 udelay(1); 2096 touch_nmi_watchdog(); 2097 } 2098 } 2099 } 2100 2101 #ifdef CONFIG_CONSOLE_POLL 2102 /* 2103 * Console polling routines for writing and reading from the uart while 2104 * in an interrupt or debug context. 2105 */ 2106 2107 static int serial8250_get_poll_char(struct uart_port *port) 2108 { 2109 struct uart_8250_port *up = up_to_u8250p(port); 2110 int status; 2111 u16 lsr; 2112 2113 serial8250_rpm_get(up); 2114 2115 lsr = serial_port_in(port, UART_LSR); 2116 2117 if (!(lsr & UART_LSR_DR)) { 2118 status = NO_POLL_CHAR; 2119 goto out; 2120 } 2121 2122 status = serial_port_in(port, UART_RX); 2123 out: 2124 serial8250_rpm_put(up); 2125 return status; 2126 } 2127 2128 2129 static void serial8250_put_poll_char(struct uart_port *port, 2130 unsigned char c) 2131 { 2132 unsigned int ier; 2133 struct uart_8250_port *up = up_to_u8250p(port); 2134 2135 /* 2136 * Normally the port is locked to synchronize UART_IER access 2137 * against the console. However, this function is only used by 2138 * KDB/KGDB, where it may not be possible to acquire the port 2139 * lock because all other CPUs are quiesced. The quiescence 2140 * should allow safe lockless usage here. 2141 */ 2142 2143 serial8250_rpm_get(up); 2144 /* 2145 * First save the IER then disable the interrupts 2146 */ 2147 ier = serial_port_in(port, UART_IER); 2148 serial8250_clear_IER(up); 2149 2150 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY); 2151 /* 2152 * Send the character out. 2153 */ 2154 serial_port_out(port, UART_TX, c); 2155 2156 /* 2157 * Finally, wait for transmitter to become empty 2158 * and restore the IER 2159 */ 2160 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY); 2161 serial_port_out(port, UART_IER, ier); 2162 serial8250_rpm_put(up); 2163 } 2164 2165 #endif /* CONFIG_CONSOLE_POLL */ 2166 2167 int serial8250_do_startup(struct uart_port *port) 2168 { 2169 struct uart_8250_port *up = up_to_u8250p(port); 2170 unsigned long flags; 2171 unsigned char iir; 2172 int retval; 2173 u16 lsr; 2174 2175 if (!port->fifosize) 2176 port->fifosize = uart_config[port->type].fifo_size; 2177 if (!up->tx_loadsz) 2178 up->tx_loadsz = uart_config[port->type].tx_loadsz; 2179 if (!up->capabilities) 2180 up->capabilities = uart_config[port->type].flags; 2181 up->mcr = 0; 2182 2183 if (port->iotype != up->cur_iotype) 2184 set_io_from_upio(port); 2185 2186 serial8250_rpm_get(up); 2187 if (port->type == PORT_16C950) { 2188 /* 2189 * Wake up and initialize UART 2190 * 2191 * Synchronize UART_IER access against the console. 2192 */ 2193 uart_port_lock_irqsave(port, &flags); 2194 up->acr = 0; 2195 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2196 serial_port_out(port, UART_EFR, UART_EFR_ECB); 2197 serial_port_out(port, UART_IER, 0); 2198 serial_port_out(port, UART_LCR, 0); 2199 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 2200 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2201 serial_port_out(port, UART_EFR, UART_EFR_ECB); 2202 serial_port_out(port, UART_LCR, 0); 2203 uart_port_unlock_irqrestore(port, flags); 2204 } 2205 2206 if (port->type == PORT_DA830) { 2207 /* 2208 * Reset the port 2209 * 2210 * Synchronize UART_IER access against the console. 2211 */ 2212 uart_port_lock_irqsave(port, &flags); 2213 serial_port_out(port, UART_IER, 0); 2214 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0); 2215 uart_port_unlock_irqrestore(port, flags); 2216 mdelay(10); 2217 2218 /* Enable Tx, Rx and free run mode */ 2219 serial_port_out(port, UART_DA830_PWREMU_MGMT, 2220 UART_DA830_PWREMU_MGMT_UTRST | 2221 UART_DA830_PWREMU_MGMT_URRST | 2222 UART_DA830_PWREMU_MGMT_FREE); 2223 } 2224 2225 #ifdef CONFIG_SERIAL_8250_RSA 2226 /* 2227 * If this is an RSA port, see if we can kick it up to the 2228 * higher speed clock. 2229 */ 2230 enable_rsa(up); 2231 #endif 2232 2233 /* 2234 * Clear the FIFO buffers and disable them. 2235 * (they will be reenabled in set_termios()) 2236 */ 2237 serial8250_clear_fifos(up); 2238 2239 /* 2240 * Clear the interrupt registers. 2241 */ 2242 serial_port_in(port, UART_LSR); 2243 serial_port_in(port, UART_RX); 2244 serial_port_in(port, UART_IIR); 2245 serial_port_in(port, UART_MSR); 2246 2247 /* 2248 * At this point, there's no way the LSR could still be 0xff; 2249 * if it is, then bail out, because there's likely no UART 2250 * here. 2251 */ 2252 if (!(port->flags & UPF_BUGGY_UART) && 2253 (serial_port_in(port, UART_LSR) == 0xff)) { 2254 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n"); 2255 retval = -ENODEV; 2256 goto out; 2257 } 2258 2259 /* 2260 * For a XR16C850, we need to set the trigger levels 2261 */ 2262 if (port->type == PORT_16850) { 2263 unsigned char fctr; 2264 2265 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 2266 2267 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); 2268 serial_port_out(port, UART_FCTR, 2269 fctr | UART_FCTR_TRGD | UART_FCTR_RX); 2270 serial_port_out(port, UART_TRG, UART_TRG_96); 2271 serial_port_out(port, UART_FCTR, 2272 fctr | UART_FCTR_TRGD | UART_FCTR_TX); 2273 serial_port_out(port, UART_TRG, UART_TRG_96); 2274 2275 serial_port_out(port, UART_LCR, 0); 2276 } 2277 2278 /* 2279 * For the Altera 16550 variants, set TX threshold trigger level. 2280 */ 2281 if (((port->type == PORT_ALTR_16550_F32) || 2282 (port->type == PORT_ALTR_16550_F64) || 2283 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) { 2284 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */ 2285 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) { 2286 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n"); 2287 } else { 2288 serial_port_out(port, UART_ALTR_AFR, 2289 UART_ALTR_EN_TXFIFO_LW); 2290 serial_port_out(port, UART_ALTR_TX_LOW, 2291 port->fifosize - up->tx_loadsz); 2292 port->handle_irq = serial8250_tx_threshold_handle_irq; 2293 } 2294 } 2295 2296 /* Check if we need to have shared IRQs */ 2297 if (port->irq && (up->port.flags & UPF_SHARE_IRQ)) 2298 up->port.irqflags |= IRQF_SHARED; 2299 2300 retval = up->ops->setup_irq(up); 2301 if (retval) 2302 goto out; 2303 2304 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) { 2305 unsigned char iir1; 2306 2307 if (port->irqflags & IRQF_SHARED) 2308 disable_irq_nosync(port->irq); 2309 2310 /* 2311 * Test for UARTs that do not reassert THRE when the 2312 * transmitter is idle and the interrupt has already 2313 * been cleared. Real 16550s should always reassert 2314 * this interrupt whenever the transmitter is idle and 2315 * the interrupt is enabled. Delays are necessary to 2316 * allow register changes to become visible. 2317 * 2318 * Synchronize UART_IER access against the console. 2319 */ 2320 uart_port_lock_irqsave(port, &flags); 2321 2322 wait_for_xmitr(up, UART_LSR_THRE); 2323 serial_port_out_sync(port, UART_IER, UART_IER_THRI); 2324 udelay(1); /* allow THRE to set */ 2325 iir1 = serial_port_in(port, UART_IIR); 2326 serial_port_out(port, UART_IER, 0); 2327 serial_port_out_sync(port, UART_IER, UART_IER_THRI); 2328 udelay(1); /* allow a working UART time to re-assert THRE */ 2329 iir = serial_port_in(port, UART_IIR); 2330 serial_port_out(port, UART_IER, 0); 2331 2332 uart_port_unlock_irqrestore(port, flags); 2333 2334 if (port->irqflags & IRQF_SHARED) 2335 enable_irq(port->irq); 2336 2337 /* 2338 * If the interrupt is not reasserted, or we otherwise 2339 * don't trust the iir, setup a timer to kick the UART 2340 * on a regular basis. 2341 */ 2342 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || 2343 up->port.flags & UPF_BUG_THRE) { 2344 up->bugs |= UART_BUG_THRE; 2345 } 2346 } 2347 2348 up->ops->setup_timer(up); 2349 2350 /* 2351 * Now, initialize the UART 2352 */ 2353 serial_port_out(port, UART_LCR, UART_LCR_WLEN8); 2354 2355 uart_port_lock_irqsave(port, &flags); 2356 if (up->port.flags & UPF_FOURPORT) { 2357 if (!up->port.irq) 2358 up->port.mctrl |= TIOCM_OUT1; 2359 } else 2360 /* 2361 * Most PC uarts need OUT2 raised to enable interrupts. 2362 */ 2363 if (port->irq) 2364 up->port.mctrl |= TIOCM_OUT2; 2365 2366 serial8250_set_mctrl(port, port->mctrl); 2367 2368 /* 2369 * Serial over Lan (SoL) hack: 2370 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be 2371 * used for Serial Over Lan. Those chips take a longer time than a 2372 * normal serial device to signalize that a transmission data was 2373 * queued. Due to that, the above test generally fails. One solution 2374 * would be to delay the reading of iir. However, this is not 2375 * reliable, since the timeout is variable. So, let's just don't 2376 * test if we receive TX irq. This way, we'll never enable 2377 * UART_BUG_TXEN. 2378 */ 2379 if (up->port.quirks & UPQ_NO_TXEN_TEST) 2380 goto dont_test_tx_en; 2381 2382 /* 2383 * Do a quick test to see if we receive an interrupt when we enable 2384 * the TX irq. 2385 */ 2386 serial_port_out(port, UART_IER, UART_IER_THRI); 2387 lsr = serial_port_in(port, UART_LSR); 2388 iir = serial_port_in(port, UART_IIR); 2389 serial_port_out(port, UART_IER, 0); 2390 2391 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { 2392 if (!(up->bugs & UART_BUG_TXEN)) { 2393 up->bugs |= UART_BUG_TXEN; 2394 dev_dbg(port->dev, "enabling bad tx status workarounds\n"); 2395 } 2396 } else { 2397 up->bugs &= ~UART_BUG_TXEN; 2398 } 2399 2400 dont_test_tx_en: 2401 uart_port_unlock_irqrestore(port, flags); 2402 2403 /* 2404 * Clear the interrupt registers again for luck, and clear the 2405 * saved flags to avoid getting false values from polling 2406 * routines or the previous session. 2407 */ 2408 serial_port_in(port, UART_LSR); 2409 serial_port_in(port, UART_RX); 2410 serial_port_in(port, UART_IIR); 2411 serial_port_in(port, UART_MSR); 2412 up->lsr_saved_flags = 0; 2413 up->msr_saved_flags = 0; 2414 2415 /* 2416 * Request DMA channels for both RX and TX. 2417 */ 2418 if (up->dma) { 2419 const char *msg = NULL; 2420 2421 if (uart_console(port)) 2422 msg = "forbid DMA for kernel console"; 2423 else if (serial8250_request_dma(up)) 2424 msg = "failed to request DMA"; 2425 if (msg) { 2426 dev_warn_ratelimited(port->dev, "%s\n", msg); 2427 up->dma = NULL; 2428 } 2429 } 2430 2431 /* 2432 * Set the IER shadow for rx interrupts but defer actual interrupt 2433 * enable until after the FIFOs are enabled; otherwise, an already- 2434 * active sender can swamp the interrupt handler with "too much work". 2435 */ 2436 up->ier = UART_IER_RLSI | UART_IER_RDI; 2437 2438 if (port->flags & UPF_FOURPORT) { 2439 unsigned int icp; 2440 /* 2441 * Enable interrupts on the AST Fourport board 2442 */ 2443 icp = (port->iobase & 0xfe0) | 0x01f; 2444 outb_p(0x80, icp); 2445 inb_p(icp); 2446 } 2447 retval = 0; 2448 out: 2449 serial8250_rpm_put(up); 2450 return retval; 2451 } 2452 EXPORT_SYMBOL_GPL(serial8250_do_startup); 2453 2454 static int serial8250_startup(struct uart_port *port) 2455 { 2456 if (port->startup) 2457 return port->startup(port); 2458 return serial8250_do_startup(port); 2459 } 2460 2461 void serial8250_do_shutdown(struct uart_port *port) 2462 { 2463 struct uart_8250_port *up = up_to_u8250p(port); 2464 unsigned long flags; 2465 2466 serial8250_rpm_get(up); 2467 /* 2468 * Disable interrupts from this port 2469 * 2470 * Synchronize UART_IER access against the console. 2471 */ 2472 uart_port_lock_irqsave(port, &flags); 2473 up->ier = 0; 2474 serial_port_out(port, UART_IER, 0); 2475 uart_port_unlock_irqrestore(port, flags); 2476 2477 synchronize_irq(port->irq); 2478 2479 if (up->dma) 2480 serial8250_release_dma(up); 2481 2482 uart_port_lock_irqsave(port, &flags); 2483 if (port->flags & UPF_FOURPORT) { 2484 /* reset interrupts on the AST Fourport board */ 2485 inb((port->iobase & 0xfe0) | 0x1f); 2486 port->mctrl |= TIOCM_OUT1; 2487 } else 2488 port->mctrl &= ~TIOCM_OUT2; 2489 2490 serial8250_set_mctrl(port, port->mctrl); 2491 uart_port_unlock_irqrestore(port, flags); 2492 2493 /* 2494 * Disable break condition and FIFOs 2495 */ 2496 serial_port_out(port, UART_LCR, 2497 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); 2498 serial8250_clear_fifos(up); 2499 2500 #ifdef CONFIG_SERIAL_8250_RSA 2501 /* 2502 * Reset the RSA board back to 115kbps compat mode. 2503 */ 2504 disable_rsa(up); 2505 #endif 2506 2507 /* 2508 * Read data port to reset things, and then unlink from 2509 * the IRQ chain. 2510 */ 2511 serial_port_in(port, UART_RX); 2512 serial8250_rpm_put(up); 2513 2514 up->ops->release_irq(up); 2515 } 2516 EXPORT_SYMBOL_GPL(serial8250_do_shutdown); 2517 2518 static void serial8250_shutdown(struct uart_port *port) 2519 { 2520 if (port->shutdown) 2521 port->shutdown(port); 2522 else 2523 serial8250_do_shutdown(port); 2524 } 2525 2526 static unsigned int serial8250_do_get_divisor(struct uart_port *port, 2527 unsigned int baud, 2528 unsigned int *frac) 2529 { 2530 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER; 2531 struct uart_8250_port *up = up_to_u8250p(port); 2532 unsigned int quot; 2533 2534 /* 2535 * Handle magic divisors for baud rates above baud_base on SMSC 2536 * Super I/O chips. We clamp custom rates from clk/6 and clk/12 2537 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These 2538 * magic divisors actually reprogram the baud rate generator's 2539 * reference clock derived from chips's 14.318MHz clock input. 2540 * 2541 * Documentation claims that with these magic divisors the base 2542 * frequencies of 7.3728MHz and 3.6864MHz are used respectively 2543 * for the extra baud rates of 460800bps and 230400bps rather 2544 * than the usual base frequency of 1.8462MHz. However empirical 2545 * evidence contradicts that. 2546 * 2547 * Instead bit 7 of the DLM register (bit 15 of the divisor) is 2548 * effectively used as a clock prescaler selection bit for the 2549 * base frequency of 7.3728MHz, always used. If set to 0, then 2550 * the base frequency is divided by 4 for use by the Baud Rate 2551 * Generator, for the usual arrangement where the value of 1 of 2552 * the divisor produces the baud rate of 115200bps. Conversely, 2553 * if set to 1 and high-speed operation has been enabled with the 2554 * Serial Port Mode Register in the Device Configuration Space, 2555 * then the base frequency is supplied directly to the Baud Rate 2556 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003, 2557 * 0x8004, etc. the respective baud rates produced are 460800bps, 2558 * 230400bps, 153600bps, 115200bps, etc. 2559 * 2560 * In all cases only low 15 bits of the divisor are used to divide 2561 * the baud base and therefore 32767 is the maximum divisor value 2562 * possible, even though documentation says that the programmable 2563 * Baud Rate Generator is capable of dividing the internal PLL 2564 * clock by any divisor from 1 to 65535. 2565 */ 2566 if (magic_multiplier && baud >= port->uartclk / 6) 2567 quot = 0x8001; 2568 else if (magic_multiplier && baud >= port->uartclk / 12) 2569 quot = 0x8002; 2570 else 2571 quot = uart_get_divisor(port, baud); 2572 2573 /* 2574 * Oxford Semi 952 rev B workaround 2575 */ 2576 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) 2577 quot++; 2578 2579 return quot; 2580 } 2581 2582 static unsigned int serial8250_get_divisor(struct uart_port *port, 2583 unsigned int baud, 2584 unsigned int *frac) 2585 { 2586 if (port->get_divisor) 2587 return port->get_divisor(port, baud, frac); 2588 2589 return serial8250_do_get_divisor(port, baud, frac); 2590 } 2591 2592 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, 2593 tcflag_t c_cflag) 2594 { 2595 unsigned char cval; 2596 2597 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag)); 2598 2599 if (c_cflag & CSTOPB) 2600 cval |= UART_LCR_STOP; 2601 if (c_cflag & PARENB) 2602 cval |= UART_LCR_PARITY; 2603 if (!(c_cflag & PARODD)) 2604 cval |= UART_LCR_EPAR; 2605 if (c_cflag & CMSPAR) 2606 cval |= UART_LCR_SPAR; 2607 2608 return cval; 2609 } 2610 2611 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud, 2612 unsigned int quot, unsigned int quot_frac) 2613 { 2614 struct uart_8250_port *up = up_to_u8250p(port); 2615 2616 /* Workaround to enable 115200 baud on OMAP1510 internal ports */ 2617 if (is_omap1510_8250(up)) { 2618 if (baud == 115200) { 2619 quot = 1; 2620 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); 2621 } else 2622 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); 2623 } 2624 2625 /* 2626 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, 2627 * otherwise just set DLAB 2628 */ 2629 if (up->capabilities & UART_NATSEMI) 2630 serial_port_out(port, UART_LCR, 0xe0); 2631 else 2632 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB); 2633 2634 serial_dl_write(up, quot); 2635 } 2636 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor); 2637 2638 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud, 2639 unsigned int quot, unsigned int quot_frac) 2640 { 2641 if (port->set_divisor) 2642 port->set_divisor(port, baud, quot, quot_frac); 2643 else 2644 serial8250_do_set_divisor(port, baud, quot, quot_frac); 2645 } 2646 2647 static unsigned int serial8250_get_baud_rate(struct uart_port *port, 2648 struct ktermios *termios, 2649 const struct ktermios *old) 2650 { 2651 unsigned int tolerance = port->uartclk / 100; 2652 unsigned int min; 2653 unsigned int max; 2654 2655 /* 2656 * Handle magic divisors for baud rates above baud_base on SMSC 2657 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but 2658 * disable divisor values beyond 32767, which are unavailable. 2659 */ 2660 if (port->flags & UPF_MAGIC_MULTIPLIER) { 2661 min = port->uartclk / 16 / UART_DIV_MAX >> 1; 2662 max = (port->uartclk + tolerance) / 4; 2663 } else { 2664 min = port->uartclk / 16 / UART_DIV_MAX; 2665 max = (port->uartclk + tolerance) / 16; 2666 } 2667 2668 /* 2669 * Ask the core to calculate the divisor for us. 2670 * Allow 1% tolerance at the upper limit so uart clks marginally 2671 * slower than nominal still match standard baud rates without 2672 * causing transmission errors. 2673 */ 2674 return uart_get_baud_rate(port, termios, old, min, max); 2675 } 2676 2677 /* 2678 * Note in order to avoid the tty port mutex deadlock don't use the next method 2679 * within the uart port callbacks. Primarily it's supposed to be utilized to 2680 * handle a sudden reference clock rate change. 2681 */ 2682 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk) 2683 { 2684 struct tty_port *tport = &port->state->port; 2685 struct tty_struct *tty; 2686 2687 tty = tty_port_tty_get(tport); 2688 if (!tty) { 2689 mutex_lock(&tport->mutex); 2690 port->uartclk = uartclk; 2691 mutex_unlock(&tport->mutex); 2692 return; 2693 } 2694 2695 down_write(&tty->termios_rwsem); 2696 mutex_lock(&tport->mutex); 2697 2698 if (port->uartclk == uartclk) 2699 goto out_unlock; 2700 2701 port->uartclk = uartclk; 2702 2703 if (!tty_port_initialized(tport)) 2704 goto out_unlock; 2705 2706 serial8250_do_set_termios(port, &tty->termios, NULL); 2707 2708 out_unlock: 2709 mutex_unlock(&tport->mutex); 2710 up_write(&tty->termios_rwsem); 2711 tty_kref_put(tty); 2712 } 2713 EXPORT_SYMBOL_GPL(serial8250_update_uartclk); 2714 2715 void 2716 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, 2717 const struct ktermios *old) 2718 { 2719 struct uart_8250_port *up = up_to_u8250p(port); 2720 unsigned char cval; 2721 unsigned long flags; 2722 unsigned int baud, quot, frac = 0; 2723 2724 if (up->capabilities & UART_CAP_MINI) { 2725 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); 2726 if ((termios->c_cflag & CSIZE) == CS5 || 2727 (termios->c_cflag & CSIZE) == CS6) 2728 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7; 2729 } 2730 cval = serial8250_compute_lcr(up, termios->c_cflag); 2731 2732 baud = serial8250_get_baud_rate(port, termios, old); 2733 quot = serial8250_get_divisor(port, baud, &frac); 2734 2735 /* 2736 * Ok, we're now changing the port state. Do it with 2737 * interrupts disabled. 2738 * 2739 * Synchronize UART_IER access against the console. 2740 */ 2741 serial8250_rpm_get(up); 2742 uart_port_lock_irqsave(port, &flags); 2743 2744 up->lcr = cval; /* Save computed LCR */ 2745 2746 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { 2747 if (baud < 2400 && !up->dma) { 2748 up->fcr &= ~UART_FCR_TRIGGER_MASK; 2749 up->fcr |= UART_FCR_TRIGGER_1; 2750 } 2751 } 2752 2753 /* 2754 * MCR-based auto flow control. When AFE is enabled, RTS will be 2755 * deasserted when the receive FIFO contains more characters than 2756 * the trigger, or the MCR RTS bit is cleared. 2757 */ 2758 if (up->capabilities & UART_CAP_AFE) { 2759 up->mcr &= ~UART_MCR_AFE; 2760 if (termios->c_cflag & CRTSCTS) 2761 up->mcr |= UART_MCR_AFE; 2762 } 2763 2764 /* 2765 * Update the per-port timeout. 2766 */ 2767 uart_update_timeout(port, termios->c_cflag, baud); 2768 2769 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 2770 if (termios->c_iflag & INPCK) 2771 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 2772 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2773 port->read_status_mask |= UART_LSR_BI; 2774 2775 /* 2776 * Characters to ignore 2777 */ 2778 port->ignore_status_mask = 0; 2779 if (termios->c_iflag & IGNPAR) 2780 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 2781 if (termios->c_iflag & IGNBRK) { 2782 port->ignore_status_mask |= UART_LSR_BI; 2783 /* 2784 * If we're ignoring parity and break indicators, 2785 * ignore overruns too (for real raw support). 2786 */ 2787 if (termios->c_iflag & IGNPAR) 2788 port->ignore_status_mask |= UART_LSR_OE; 2789 } 2790 2791 /* 2792 * ignore all characters if CREAD is not set 2793 */ 2794 if ((termios->c_cflag & CREAD) == 0) 2795 port->ignore_status_mask |= UART_LSR_DR; 2796 2797 /* 2798 * CTS flow control flag and modem status interrupts 2799 */ 2800 up->ier &= ~UART_IER_MSI; 2801 if (!(up->bugs & UART_BUG_NOMSR) && 2802 UART_ENABLE_MS(&up->port, termios->c_cflag)) 2803 up->ier |= UART_IER_MSI; 2804 if (up->capabilities & UART_CAP_UUE) 2805 up->ier |= UART_IER_UUE; 2806 if (up->capabilities & UART_CAP_RTOIE) 2807 up->ier |= UART_IER_RTOIE; 2808 2809 serial_port_out(port, UART_IER, up->ier); 2810 2811 if (up->capabilities & UART_CAP_EFR) { 2812 unsigned char efr = 0; 2813 /* 2814 * TI16C752/Startech hardware flow control. FIXME: 2815 * - TI16C752 requires control thresholds to be set. 2816 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. 2817 */ 2818 if (termios->c_cflag & CRTSCTS) 2819 efr |= UART_EFR_CTS; 2820 2821 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2822 if (port->flags & UPF_EXAR_EFR) 2823 serial_port_out(port, UART_XR_EFR, efr); 2824 else 2825 serial_port_out(port, UART_EFR, efr); 2826 } 2827 2828 serial8250_set_divisor(port, baud, quot, frac); 2829 2830 /* 2831 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR 2832 * is written without DLAB set, this mode will be disabled. 2833 */ 2834 if (port->type == PORT_16750) 2835 serial_port_out(port, UART_FCR, up->fcr); 2836 2837 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */ 2838 if (port->type != PORT_16750) { 2839 /* emulated UARTs (Lucent Venus 167x) need two steps */ 2840 if (up->fcr & UART_FCR_ENABLE_FIFO) 2841 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); 2842 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */ 2843 } 2844 serial8250_set_mctrl(port, port->mctrl); 2845 uart_port_unlock_irqrestore(port, flags); 2846 serial8250_rpm_put(up); 2847 2848 /* Don't rewrite B0 */ 2849 if (tty_termios_baud_rate(termios)) 2850 tty_termios_encode_baud_rate(termios, baud, baud); 2851 } 2852 EXPORT_SYMBOL(serial8250_do_set_termios); 2853 2854 static void 2855 serial8250_set_termios(struct uart_port *port, struct ktermios *termios, 2856 const struct ktermios *old) 2857 { 2858 if (port->set_termios) 2859 port->set_termios(port, termios, old); 2860 else 2861 serial8250_do_set_termios(port, termios, old); 2862 } 2863 2864 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios) 2865 { 2866 if (termios->c_line == N_PPS) { 2867 port->flags |= UPF_HARDPPS_CD; 2868 uart_port_lock_irq(port); 2869 serial8250_enable_ms(port); 2870 uart_port_unlock_irq(port); 2871 } else { 2872 port->flags &= ~UPF_HARDPPS_CD; 2873 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2874 uart_port_lock_irq(port); 2875 serial8250_disable_ms(port); 2876 uart_port_unlock_irq(port); 2877 } 2878 } 2879 } 2880 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc); 2881 2882 static void 2883 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios) 2884 { 2885 if (port->set_ldisc) 2886 port->set_ldisc(port, termios); 2887 else 2888 serial8250_do_set_ldisc(port, termios); 2889 } 2890 2891 void serial8250_do_pm(struct uart_port *port, unsigned int state, 2892 unsigned int oldstate) 2893 { 2894 struct uart_8250_port *p = up_to_u8250p(port); 2895 2896 serial8250_set_sleep(p, state != 0); 2897 } 2898 EXPORT_SYMBOL(serial8250_do_pm); 2899 2900 static void 2901 serial8250_pm(struct uart_port *port, unsigned int state, 2902 unsigned int oldstate) 2903 { 2904 if (port->pm) 2905 port->pm(port, state, oldstate); 2906 else 2907 serial8250_do_pm(port, state, oldstate); 2908 } 2909 2910 static unsigned int serial8250_port_size(struct uart_8250_port *pt) 2911 { 2912 if (pt->port.mapsize) 2913 return pt->port.mapsize; 2914 if (is_omap1_8250(pt)) 2915 return 0x16 << pt->port.regshift; 2916 2917 return 8 << pt->port.regshift; 2918 } 2919 2920 /* 2921 * Resource handling. 2922 */ 2923 static int serial8250_request_std_resource(struct uart_8250_port *up) 2924 { 2925 unsigned int size = serial8250_port_size(up); 2926 struct uart_port *port = &up->port; 2927 int ret = 0; 2928 2929 switch (port->iotype) { 2930 case UPIO_AU: 2931 case UPIO_TSI: 2932 case UPIO_MEM32: 2933 case UPIO_MEM32BE: 2934 case UPIO_MEM16: 2935 case UPIO_MEM: 2936 if (!port->mapbase) { 2937 ret = -EINVAL; 2938 break; 2939 } 2940 2941 if (!request_mem_region(port->mapbase, size, "serial")) { 2942 ret = -EBUSY; 2943 break; 2944 } 2945 2946 if (port->flags & UPF_IOREMAP) { 2947 port->membase = ioremap(port->mapbase, size); 2948 if (!port->membase) { 2949 release_mem_region(port->mapbase, size); 2950 ret = -ENOMEM; 2951 } 2952 } 2953 break; 2954 2955 case UPIO_HUB6: 2956 case UPIO_PORT: 2957 if (!request_region(port->iobase, size, "serial")) 2958 ret = -EBUSY; 2959 break; 2960 } 2961 return ret; 2962 } 2963 2964 static void serial8250_release_std_resource(struct uart_8250_port *up) 2965 { 2966 unsigned int size = serial8250_port_size(up); 2967 struct uart_port *port = &up->port; 2968 2969 switch (port->iotype) { 2970 case UPIO_AU: 2971 case UPIO_TSI: 2972 case UPIO_MEM32: 2973 case UPIO_MEM32BE: 2974 case UPIO_MEM16: 2975 case UPIO_MEM: 2976 if (!port->mapbase) 2977 break; 2978 2979 if (port->flags & UPF_IOREMAP) { 2980 iounmap(port->membase); 2981 port->membase = NULL; 2982 } 2983 2984 release_mem_region(port->mapbase, size); 2985 break; 2986 2987 case UPIO_HUB6: 2988 case UPIO_PORT: 2989 release_region(port->iobase, size); 2990 break; 2991 } 2992 } 2993 2994 static void serial8250_release_port(struct uart_port *port) 2995 { 2996 struct uart_8250_port *up = up_to_u8250p(port); 2997 2998 serial8250_release_std_resource(up); 2999 } 3000 3001 static int serial8250_request_port(struct uart_port *port) 3002 { 3003 struct uart_8250_port *up = up_to_u8250p(port); 3004 3005 return serial8250_request_std_resource(up); 3006 } 3007 3008 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up) 3009 { 3010 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 3011 unsigned char bytes; 3012 3013 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; 3014 3015 return bytes ? bytes : -EOPNOTSUPP; 3016 } 3017 3018 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes) 3019 { 3020 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 3021 int i; 3022 3023 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)]) 3024 return -EOPNOTSUPP; 3025 3026 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) { 3027 if (bytes < conf_type->rxtrig_bytes[i]) 3028 /* Use the nearest lower value */ 3029 return (--i) << UART_FCR_R_TRIG_SHIFT; 3030 } 3031 3032 return UART_FCR_R_TRIG_11; 3033 } 3034 3035 static int do_get_rxtrig(struct tty_port *port) 3036 { 3037 struct uart_state *state = container_of(port, struct uart_state, port); 3038 struct uart_port *uport = state->uart_port; 3039 struct uart_8250_port *up = up_to_u8250p(uport); 3040 3041 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) 3042 return -EINVAL; 3043 3044 return fcr_get_rxtrig_bytes(up); 3045 } 3046 3047 static int do_serial8250_get_rxtrig(struct tty_port *port) 3048 { 3049 int rxtrig_bytes; 3050 3051 mutex_lock(&port->mutex); 3052 rxtrig_bytes = do_get_rxtrig(port); 3053 mutex_unlock(&port->mutex); 3054 3055 return rxtrig_bytes; 3056 } 3057 3058 static ssize_t rx_trig_bytes_show(struct device *dev, 3059 struct device_attribute *attr, char *buf) 3060 { 3061 struct tty_port *port = dev_get_drvdata(dev); 3062 int rxtrig_bytes; 3063 3064 rxtrig_bytes = do_serial8250_get_rxtrig(port); 3065 if (rxtrig_bytes < 0) 3066 return rxtrig_bytes; 3067 3068 return sysfs_emit(buf, "%d\n", rxtrig_bytes); 3069 } 3070 3071 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) 3072 { 3073 struct uart_state *state = container_of(port, struct uart_state, port); 3074 struct uart_port *uport = state->uart_port; 3075 struct uart_8250_port *up = up_to_u8250p(uport); 3076 int rxtrig; 3077 3078 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) 3079 return -EINVAL; 3080 3081 rxtrig = bytes_to_fcr_rxtrig(up, bytes); 3082 if (rxtrig < 0) 3083 return rxtrig; 3084 3085 serial8250_clear_fifos(up); 3086 up->fcr &= ~UART_FCR_TRIGGER_MASK; 3087 up->fcr |= (unsigned char)rxtrig; 3088 serial_out(up, UART_FCR, up->fcr); 3089 return 0; 3090 } 3091 3092 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes) 3093 { 3094 int ret; 3095 3096 mutex_lock(&port->mutex); 3097 ret = do_set_rxtrig(port, bytes); 3098 mutex_unlock(&port->mutex); 3099 3100 return ret; 3101 } 3102 3103 static ssize_t rx_trig_bytes_store(struct device *dev, 3104 struct device_attribute *attr, const char *buf, size_t count) 3105 { 3106 struct tty_port *port = dev_get_drvdata(dev); 3107 unsigned char bytes; 3108 int ret; 3109 3110 if (!count) 3111 return -EINVAL; 3112 3113 ret = kstrtou8(buf, 10, &bytes); 3114 if (ret < 0) 3115 return ret; 3116 3117 ret = do_serial8250_set_rxtrig(port, bytes); 3118 if (ret < 0) 3119 return ret; 3120 3121 return count; 3122 } 3123 3124 static DEVICE_ATTR_RW(rx_trig_bytes); 3125 3126 static struct attribute *serial8250_dev_attrs[] = { 3127 &dev_attr_rx_trig_bytes.attr, 3128 NULL 3129 }; 3130 3131 static struct attribute_group serial8250_dev_attr_group = { 3132 .attrs = serial8250_dev_attrs, 3133 }; 3134 3135 static void register_dev_spec_attr_grp(struct uart_8250_port *up) 3136 { 3137 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 3138 3139 if (conf_type->rxtrig_bytes[0]) 3140 up->port.attr_group = &serial8250_dev_attr_group; 3141 } 3142 3143 static void serial8250_config_port(struct uart_port *port, int flags) 3144 { 3145 struct uart_8250_port *up = up_to_u8250p(port); 3146 int ret; 3147 3148 /* 3149 * Find the region that we can probe for. This in turn 3150 * tells us whether we can probe for the type of port. 3151 */ 3152 ret = serial8250_request_std_resource(up); 3153 if (ret < 0) 3154 return; 3155 3156 if (port->iotype != up->cur_iotype) 3157 set_io_from_upio(port); 3158 3159 if (flags & UART_CONFIG_TYPE) 3160 autoconfig(up); 3161 3162 /* HW bugs may trigger IRQ while IIR == NO_INT */ 3163 if (port->type == PORT_TEGRA) 3164 up->bugs |= UART_BUG_NOMSR; 3165 3166 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) 3167 autoconfig_irq(up); 3168 3169 if (port->type == PORT_UNKNOWN) 3170 serial8250_release_std_resource(up); 3171 3172 register_dev_spec_attr_grp(up); 3173 up->fcr = uart_config[up->port.type].fcr; 3174 } 3175 3176 static int 3177 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) 3178 { 3179 if (ser->irq >= nr_irqs || ser->irq < 0 || 3180 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || 3181 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || 3182 ser->type == PORT_STARTECH) 3183 return -EINVAL; 3184 return 0; 3185 } 3186 3187 static const char *serial8250_type(struct uart_port *port) 3188 { 3189 int type = port->type; 3190 3191 if (type >= ARRAY_SIZE(uart_config)) 3192 type = 0; 3193 return uart_config[type].name; 3194 } 3195 3196 static const struct uart_ops serial8250_pops = { 3197 .tx_empty = serial8250_tx_empty, 3198 .set_mctrl = serial8250_set_mctrl, 3199 .get_mctrl = serial8250_get_mctrl, 3200 .stop_tx = serial8250_stop_tx, 3201 .start_tx = serial8250_start_tx, 3202 .throttle = serial8250_throttle, 3203 .unthrottle = serial8250_unthrottle, 3204 .stop_rx = serial8250_stop_rx, 3205 .enable_ms = serial8250_enable_ms, 3206 .break_ctl = serial8250_break_ctl, 3207 .startup = serial8250_startup, 3208 .shutdown = serial8250_shutdown, 3209 .set_termios = serial8250_set_termios, 3210 .set_ldisc = serial8250_set_ldisc, 3211 .pm = serial8250_pm, 3212 .type = serial8250_type, 3213 .release_port = serial8250_release_port, 3214 .request_port = serial8250_request_port, 3215 .config_port = serial8250_config_port, 3216 .verify_port = serial8250_verify_port, 3217 #ifdef CONFIG_CONSOLE_POLL 3218 .poll_get_char = serial8250_get_poll_char, 3219 .poll_put_char = serial8250_put_poll_char, 3220 #endif 3221 }; 3222 3223 void serial8250_init_port(struct uart_8250_port *up) 3224 { 3225 struct uart_port *port = &up->port; 3226 3227 spin_lock_init(&port->lock); 3228 port->ctrl_id = 0; 3229 port->pm = NULL; 3230 port->ops = &serial8250_pops; 3231 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 3232 3233 up->cur_iotype = 0xFF; 3234 } 3235 EXPORT_SYMBOL_GPL(serial8250_init_port); 3236 3237 void serial8250_set_defaults(struct uart_8250_port *up) 3238 { 3239 struct uart_port *port = &up->port; 3240 3241 if (up->port.flags & UPF_FIXED_TYPE) { 3242 unsigned int type = up->port.type; 3243 3244 if (!up->port.fifosize) 3245 up->port.fifosize = uart_config[type].fifo_size; 3246 if (!up->tx_loadsz) 3247 up->tx_loadsz = uart_config[type].tx_loadsz; 3248 if (!up->capabilities) 3249 up->capabilities = uart_config[type].flags; 3250 } 3251 3252 set_io_from_upio(port); 3253 3254 /* default dma handlers */ 3255 if (up->dma) { 3256 if (!up->dma->tx_dma) 3257 up->dma->tx_dma = serial8250_tx_dma; 3258 if (!up->dma->rx_dma) 3259 up->dma->rx_dma = serial8250_rx_dma; 3260 } 3261 } 3262 EXPORT_SYMBOL_GPL(serial8250_set_defaults); 3263 3264 #ifdef CONFIG_SERIAL_8250_CONSOLE 3265 3266 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch) 3267 { 3268 struct uart_8250_port *up = up_to_u8250p(port); 3269 3270 wait_for_xmitr(up, UART_LSR_THRE); 3271 serial_port_out(port, UART_TX, ch); 3272 } 3273 3274 /* 3275 * Restore serial console when h/w power-off detected 3276 */ 3277 static void serial8250_console_restore(struct uart_8250_port *up) 3278 { 3279 struct uart_port *port = &up->port; 3280 struct ktermios termios; 3281 unsigned int baud, quot, frac = 0; 3282 3283 termios.c_cflag = port->cons->cflag; 3284 termios.c_ispeed = port->cons->ispeed; 3285 termios.c_ospeed = port->cons->ospeed; 3286 if (port->state->port.tty && termios.c_cflag == 0) { 3287 termios.c_cflag = port->state->port.tty->termios.c_cflag; 3288 termios.c_ispeed = port->state->port.tty->termios.c_ispeed; 3289 termios.c_ospeed = port->state->port.tty->termios.c_ospeed; 3290 } 3291 3292 baud = serial8250_get_baud_rate(port, &termios, NULL); 3293 quot = serial8250_get_divisor(port, baud, &frac); 3294 3295 serial8250_set_divisor(port, baud, quot, frac); 3296 serial_port_out(port, UART_LCR, up->lcr); 3297 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS); 3298 } 3299 3300 /* 3301 * Print a string to the serial port using the device FIFO 3302 * 3303 * It sends fifosize bytes and then waits for the fifo 3304 * to get empty. 3305 */ 3306 static void serial8250_console_fifo_write(struct uart_8250_port *up, 3307 const char *s, unsigned int count) 3308 { 3309 int i; 3310 const char *end = s + count; 3311 unsigned int fifosize = up->tx_loadsz; 3312 bool cr_sent = false; 3313 3314 while (s != end) { 3315 wait_for_lsr(up, UART_LSR_THRE); 3316 3317 for (i = 0; i < fifosize && s != end; ++i) { 3318 if (*s == '\n' && !cr_sent) { 3319 serial_out(up, UART_TX, '\r'); 3320 cr_sent = true; 3321 } else { 3322 serial_out(up, UART_TX, *s++); 3323 cr_sent = false; 3324 } 3325 } 3326 } 3327 } 3328 3329 /* 3330 * Print a string to the serial port trying not to disturb 3331 * any possible real use of the port... 3332 * 3333 * The console_lock must be held when we get here. 3334 * 3335 * Doing runtime PM is really a bad idea for the kernel console. 3336 * Thus, we assume the function is called when device is powered up. 3337 */ 3338 void serial8250_console_write(struct uart_8250_port *up, const char *s, 3339 unsigned int count) 3340 { 3341 struct uart_8250_em485 *em485 = up->em485; 3342 struct uart_port *port = &up->port; 3343 unsigned long flags; 3344 unsigned int ier, use_fifo; 3345 int locked = 1; 3346 3347 touch_nmi_watchdog(); 3348 3349 if (oops_in_progress) 3350 locked = uart_port_trylock_irqsave(port, &flags); 3351 else 3352 uart_port_lock_irqsave(port, &flags); 3353 3354 /* 3355 * First save the IER then disable the interrupts 3356 */ 3357 ier = serial_port_in(port, UART_IER); 3358 serial8250_clear_IER(up); 3359 3360 /* check scratch reg to see if port powered off during system sleep */ 3361 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) { 3362 serial8250_console_restore(up); 3363 up->canary = 0; 3364 } 3365 3366 if (em485) { 3367 if (em485->tx_stopped) 3368 up->rs485_start_tx(up); 3369 mdelay(port->rs485.delay_rts_before_send); 3370 } 3371 3372 use_fifo = (up->capabilities & UART_CAP_FIFO) && 3373 /* 3374 * BCM283x requires to check the fifo 3375 * after each byte. 3376 */ 3377 !(up->capabilities & UART_CAP_MINI) && 3378 /* 3379 * tx_loadsz contains the transmit fifo size 3380 */ 3381 up->tx_loadsz > 1 && 3382 (up->fcr & UART_FCR_ENABLE_FIFO) && 3383 port->state && 3384 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) && 3385 /* 3386 * After we put a data in the fifo, the controller will send 3387 * it regardless of the CTS state. Therefore, only use fifo 3388 * if we don't use control flow. 3389 */ 3390 !(up->port.flags & UPF_CONS_FLOW); 3391 3392 if (likely(use_fifo)) 3393 serial8250_console_fifo_write(up, s, count); 3394 else 3395 uart_console_write(port, s, count, serial8250_console_putchar); 3396 3397 /* 3398 * Finally, wait for transmitter to become empty 3399 * and restore the IER 3400 */ 3401 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY); 3402 3403 if (em485) { 3404 mdelay(port->rs485.delay_rts_after_send); 3405 if (em485->tx_stopped) 3406 up->rs485_stop_tx(up); 3407 } 3408 3409 serial_port_out(port, UART_IER, ier); 3410 3411 /* 3412 * The receive handling will happen properly because the 3413 * receive ready bit will still be set; it is not cleared 3414 * on read. However, modem control will not, we must 3415 * call it if we have saved something in the saved flags 3416 * while processing with interrupts off. 3417 */ 3418 if (up->msr_saved_flags) 3419 serial8250_modem_status(up); 3420 3421 if (locked) 3422 uart_port_unlock_irqrestore(port, flags); 3423 } 3424 3425 static unsigned int probe_baud(struct uart_port *port) 3426 { 3427 unsigned char lcr, dll, dlm; 3428 unsigned int quot; 3429 3430 lcr = serial_port_in(port, UART_LCR); 3431 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB); 3432 dll = serial_port_in(port, UART_DLL); 3433 dlm = serial_port_in(port, UART_DLM); 3434 serial_port_out(port, UART_LCR, lcr); 3435 3436 quot = (dlm << 8) | dll; 3437 return (port->uartclk / 16) / quot; 3438 } 3439 3440 int serial8250_console_setup(struct uart_port *port, char *options, bool probe) 3441 { 3442 int baud = 9600; 3443 int bits = 8; 3444 int parity = 'n'; 3445 int flow = 'n'; 3446 int ret; 3447 3448 if (!port->iobase && !port->membase) 3449 return -ENODEV; 3450 3451 if (options) 3452 uart_parse_options(options, &baud, &parity, &bits, &flow); 3453 else if (probe) 3454 baud = probe_baud(port); 3455 3456 ret = uart_set_options(port, port->cons, baud, parity, bits, flow); 3457 if (ret) 3458 return ret; 3459 3460 if (port->dev) 3461 pm_runtime_get_sync(port->dev); 3462 3463 return 0; 3464 } 3465 3466 int serial8250_console_exit(struct uart_port *port) 3467 { 3468 if (port->dev) 3469 pm_runtime_put_sync(port->dev); 3470 3471 return 0; 3472 } 3473 3474 #endif /* CONFIG_SERIAL_8250_CONSOLE */ 3475 3476 MODULE_DESCRIPTION("Base port operations for 8250/16550-type serial ports"); 3477 MODULE_LICENSE("GPL"); 3478