1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type MCHP PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. 8 */ 9 10 #include <linux/array_size.h> 11 #include <linux/bitfield.h> 12 #include <linux/bits.h> 13 #include <linux/circ_buf.h> 14 #include <linux/device.h> 15 #include <linux/errno.h> 16 #include <linux/gfp_types.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/minmax.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/overflow.h> 23 #include <linux/pci.h> 24 #include <linux/pm.h> 25 #include <linux/serial_core.h> 26 #include <linux/serial_reg.h> 27 #include <linux/serial_8250.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/time.h> 31 #include <linux/tty.h> 32 #include <linux/tty_flip.h> 33 #include <linux/types.h> 34 #include <linux/units.h> 35 36 #include <asm/byteorder.h> 37 38 #include "8250.h" 39 #include "8250_pcilib.h" 40 41 #define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 42 #define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 43 #define PCI_DEVICE_ID_EFAR_PCI11101 0xa022 44 #define PCI_DEVICE_ID_EFAR_PCI11400 0xa032 45 #define PCI_DEVICE_ID_EFAR_PCI11414 0xa042 46 47 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001 48 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002 49 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003 50 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004 51 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005 52 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006 53 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007 54 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008 55 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009 56 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a 57 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b 58 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c 59 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d 60 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e 61 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f 62 63 #define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI12000 64 #define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI11010 65 #define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI11101 66 #define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI11400 67 #define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI11414 68 69 #define UART_SYSTEM_ADDR_BASE 0x1000 70 #define UART_DEV_REV_REG (UART_SYSTEM_ADDR_BASE + 0x00) 71 #define UART_DEV_REV_MASK GENMASK(7, 0) 72 #define UART_SYSLOCK_REG (UART_SYSTEM_ADDR_BASE + 0xA0) 73 #define UART_SYSLOCK BIT(2) 74 #define SYSLOCK_SLEEP_TIMEOUT 100 75 #define SYSLOCK_RETRY_CNT 1000 76 77 #define UART_RX_BYTE_FIFO 0x00 78 #define UART_TX_BYTE_FIFO 0x00 79 #define UART_FIFO_CTL 0x02 80 81 #define UART_MODEM_CTL_REG 0x04 82 #define UART_MODEM_CTL_RTS_SET BIT(1) 83 84 #define UART_LINE_STAT_REG 0x05 85 #define UART_LINE_XMIT_CHECK_MASK GENMASK(6, 5) 86 87 #define UART_ACTV_REG 0x11 88 #define UART_BLOCK_SET_ACTIVE BIT(0) 89 90 #define UART_PCI_CTRL_REG 0x80 91 #define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4) 92 #define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0) 93 94 #define ADCL_CFG_REG 0x40 95 #define ADCL_CFG_POL_SEL BIT(2) 96 #define ADCL_CFG_PIN_SEL BIT(1) 97 #define ADCL_CFG_EN BIT(0) 98 99 #define UART_BIT_SAMPLE_CNT_8 8 100 #define UART_BIT_SAMPLE_CNT_16 16 101 #define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) 102 #define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) 103 #define FRAC_DIV_TX_END_POINT_MASK GENMASK(23, 20) 104 105 #define UART_WAKE_REG 0x8C 106 #define UART_WAKE_MASK_REG 0x90 107 #define UART_WAKE_N_PIN BIT(2) 108 #define UART_WAKE_NCTS BIT(1) 109 #define UART_WAKE_INT BIT(0) 110 #define UART_WAKE_SRCS \ 111 (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) 112 113 #define UART_BAUD_CLK_DIVISOR_REG 0x54 114 #define FRAC_DIV_CFG_REG 0x58 115 116 #define UART_RESET_REG 0x94 117 #define UART_RESET_D3_RESET_DISABLE BIT(16) 118 119 #define UART_BURST_STATUS_REG 0x9C 120 #define UART_TX_BURST_FIFO 0xA0 121 #define UART_RX_BURST_FIFO 0xA4 122 123 #define UART_BIT_DIVISOR_8 0x26731000 124 #define UART_BIT_DIVISOR_16 0x6ef71000 125 #define UART_BAUD_4MBPS 4000000 126 127 #define MAX_PORTS 4 128 #define PORT_OFFSET 0x100 129 #define RX_BUF_SIZE 512 130 #define UART_BYTE_SIZE 1 131 #define UART_BURST_SIZE 4 132 133 #define UART_BST_STAT_RX_COUNT_MASK 0x00FF 134 #define UART_BST_STAT_TX_COUNT_MASK 0xFF00 135 #define UART_BST_STAT_IIR_INT_PEND 0x100000 136 #define UART_LSR_OVERRUN_ERR_CLR 0x43 137 #define UART_BST_STAT_LSR_RX_MASK 0x9F000000 138 #define UART_BST_STAT_LSR_RX_ERR_MASK 0x9E000000 139 #define UART_BST_STAT_LSR_OVERRUN_ERR 0x2000000 140 #define UART_BST_STAT_LSR_PARITY_ERR 0x4000000 141 #define UART_BST_STAT_LSR_FRAME_ERR 0x8000000 142 #define UART_BST_STAT_LSR_THRE 0x20000000 143 144 #define GET_MODEM_CTL_RTS_STATUS(reg) ((reg) & UART_MODEM_CTL_RTS_SET) 145 #define GET_RTS_PIN_STATUS(val) (((val) & TIOCM_RTS) >> 1) 146 #define RTS_TOGGLE_STATUS_MASK(val, reg) (GET_MODEM_CTL_RTS_STATUS(reg) \ 147 != GET_RTS_PIN_STATUS(val)) 148 149 struct pci1xxxx_8250 { 150 unsigned int nr; 151 u8 dev_rev; 152 u8 pad[3]; 153 void __iomem *membase; 154 int line[] __counted_by(nr); 155 }; 156 157 static const struct serial_rs485 pci1xxxx_rs485_supported = { 158 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | 159 SER_RS485_RTS_AFTER_SEND, 160 .delay_rts_after_send = 1, 161 /* Delay RTS before send is not supported */ 162 }; 163 164 static int pci1xxxx_set_sys_lock(struct pci1xxxx_8250 *port) 165 { 166 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); 167 return readl(port->membase + UART_SYSLOCK_REG); 168 } 169 170 static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_8250 *port) 171 { 172 u32 regval; 173 174 return readx_poll_timeout(pci1xxxx_set_sys_lock, port, regval, 175 (regval & UART_SYSLOCK), 176 SYSLOCK_SLEEP_TIMEOUT, 177 SYSLOCK_RETRY_CNT * SYSLOCK_SLEEP_TIMEOUT); 178 } 179 180 static void pci1xxxx_release_sys_lock(struct pci1xxxx_8250 *port) 181 { 182 writel(0x0, port->membase + UART_SYSLOCK_REG); 183 } 184 185 static const int logical_to_physical_port_idx[][MAX_PORTS] = { 186 {0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */ 187 {0, 1, 2, 3}, /* PCI4p */ 188 {0, 1, 2, -1}, /* PCI3p012 */ 189 {0, 1, 3, -1}, /* PCI3p013 */ 190 {0, 2, 3, -1}, /* PCI3p023 */ 191 {1, 2, 3, -1}, /* PCI3p123 */ 192 {0, 1, -1, -1}, /* PCI2p01 */ 193 {0, 2, -1, -1}, /* PCI2p02 */ 194 {0, 3, -1, -1}, /* PCI2p03 */ 195 {1, 2, -1, -1}, /* PCI2p12 */ 196 {1, 3, -1, -1}, /* PCI2p13 */ 197 {2, 3, -1, -1}, /* PCI2p23 */ 198 {0, -1, -1, -1}, /* PCI1p0 */ 199 {1, -1, -1, -1}, /* PCI1p1 */ 200 {2, -1, -1, -1}, /* PCI1p2 */ 201 {3, -1, -1, -1}, /* PCI1p3 */ 202 }; 203 204 static int pci1xxxx_get_num_ports(struct pci_dev *dev) 205 { 206 switch (dev->subsystem_device) { 207 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: 208 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: 209 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: 210 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: 211 case PCI_SUBDEVICE_ID_EFAR_PCI12000: 212 case PCI_SUBDEVICE_ID_EFAR_PCI11010: 213 case PCI_SUBDEVICE_ID_EFAR_PCI11101: 214 case PCI_SUBDEVICE_ID_EFAR_PCI11400: 215 default: 216 return 1; 217 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: 218 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: 219 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: 220 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: 221 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: 222 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: 223 return 2; 224 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: 225 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: 226 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: 227 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: 228 return 3; 229 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: 230 case PCI_SUBDEVICE_ID_EFAR_PCI11414: 231 return 4; 232 } 233 } 234 235 static unsigned int pci1xxxx_get_divisor(struct uart_port *port, 236 unsigned int baud, unsigned int *frac) 237 { 238 unsigned int uart_sample_cnt; 239 unsigned int quot; 240 241 if (baud >= UART_BAUD_4MBPS) 242 uart_sample_cnt = UART_BIT_SAMPLE_CNT_8; 243 else 244 uart_sample_cnt = UART_BIT_SAMPLE_CNT_16; 245 246 /* 247 * Calculate baud rate sampling period in nanoseconds. 248 * Fractional part x denotes x/255 parts of a nanosecond. 249 */ 250 quot = NSEC_PER_SEC / (baud * uart_sample_cnt); 251 *frac = (NSEC_PER_SEC - quot * baud * uart_sample_cnt) * 252 255 / uart_sample_cnt / baud; 253 254 return quot; 255 } 256 257 static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, 258 unsigned int quot, unsigned int frac) 259 { 260 if (baud >= UART_BAUD_4MBPS) 261 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); 262 else 263 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); 264 265 writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, 266 port->membase + UART_BAUD_CLK_DIVISOR_REG); 267 } 268 269 static void pci1xxxx_set_mctrl(struct uart_port *port, unsigned int mctrl) 270 { 271 u32 fract_div_cfg_reg; 272 u32 line_stat_reg; 273 u32 modem_ctl_reg; 274 u32 adcl_cfg_reg; 275 276 adcl_cfg_reg = readl(port->membase + ADCL_CFG_REG); 277 278 /* HW is responsible in ADCL_EN case */ 279 if ((adcl_cfg_reg & (ADCL_CFG_EN | ADCL_CFG_PIN_SEL))) 280 return; 281 282 modem_ctl_reg = readl(port->membase + UART_MODEM_CTL_REG); 283 284 serial8250_do_set_mctrl(port, mctrl); 285 286 if (RTS_TOGGLE_STATUS_MASK(mctrl, modem_ctl_reg)) { 287 line_stat_reg = readl(port->membase + UART_LINE_STAT_REG); 288 if (line_stat_reg & UART_LINE_XMIT_CHECK_MASK) { 289 fract_div_cfg_reg = readl(port->membase + 290 FRAC_DIV_CFG_REG); 291 292 writel((fract_div_cfg_reg & 293 ~(FRAC_DIV_TX_END_POINT_MASK)), 294 port->membase + FRAC_DIV_CFG_REG); 295 296 /* Enable ADC and set the nRTS pin */ 297 writel((adcl_cfg_reg | (ADCL_CFG_EN | 298 ADCL_CFG_PIN_SEL)), 299 port->membase + ADCL_CFG_REG); 300 301 /* Revert to the original settings */ 302 writel(adcl_cfg_reg, port->membase + ADCL_CFG_REG); 303 304 writel(fract_div_cfg_reg, port->membase + 305 FRAC_DIV_CFG_REG); 306 } 307 } 308 } 309 310 static int pci1xxxx_rs485_config(struct uart_port *port, 311 struct ktermios *termios, 312 struct serial_rs485 *rs485) 313 { 314 u32 delay_in_baud_periods; 315 u32 baud_period_in_ns; 316 u32 mode_cfg = 0; 317 u32 sample_cnt; 318 u32 clock_div; 319 u32 frac_div; 320 321 frac_div = readl(port->membase + FRAC_DIV_CFG_REG); 322 323 if (frac_div == UART_BIT_DIVISOR_16) 324 sample_cnt = UART_BIT_SAMPLE_CNT_16; 325 else 326 sample_cnt = UART_BIT_SAMPLE_CNT_8; 327 328 /* 329 * pci1xxxx's uart hardware supports only RTS delay after 330 * Tx and in units of bit times to a maximum of 15 331 */ 332 if (rs485->flags & SER_RS485_ENABLED) { 333 mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; 334 335 if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) 336 mode_cfg |= ADCL_CFG_POL_SEL; 337 338 if (rs485->delay_rts_after_send) { 339 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); 340 baud_period_in_ns = 341 FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * 342 sample_cnt; 343 delay_in_baud_periods = 344 rs485->delay_rts_after_send * NSEC_PER_MSEC / 345 baud_period_in_ns; 346 delay_in_baud_periods = 347 min_t(u32, delay_in_baud_periods, 348 FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); 349 mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, 350 delay_in_baud_periods); 351 rs485->delay_rts_after_send = 352 baud_period_in_ns * delay_in_baud_periods / 353 NSEC_PER_MSEC; 354 } 355 } 356 writel(mode_cfg, port->membase + ADCL_CFG_REG); 357 return 0; 358 } 359 360 static u32 pci1xxxx_read_burst_status(struct uart_port *port) 361 { 362 u32 status; 363 364 status = readl(port->membase + UART_BURST_STATUS_REG); 365 if (status & UART_BST_STAT_LSR_RX_ERR_MASK) { 366 if (status & UART_BST_STAT_LSR_OVERRUN_ERR) { 367 writeb(UART_LSR_OVERRUN_ERR_CLR, 368 port->membase + UART_FIFO_CTL); 369 port->icount.overrun++; 370 } 371 372 if (status & UART_BST_STAT_LSR_FRAME_ERR) 373 port->icount.frame++; 374 375 if (status & UART_BST_STAT_LSR_PARITY_ERR) 376 port->icount.parity++; 377 } 378 return status; 379 } 380 381 static void pci1xxxx_process_read_data(struct uart_port *port, 382 unsigned char *rx_buff, u32 *buff_index, 383 u32 *valid_byte_count) 384 { 385 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE; 386 u32 *burst_buf; 387 388 /* 389 * Depending on the RX Trigger Level the number of bytes that can be 390 * stored in RX FIFO at a time varies. Each transaction reads data 391 * in DWORDs. If there are less than four remaining valid_byte_count 392 * to read, the data is received one byte at a time. 393 */ 394 while (valid_burst_count--) { 395 if (*buff_index > (RX_BUF_SIZE - UART_BURST_SIZE)) 396 break; 397 burst_buf = (u32 *)&rx_buff[*buff_index]; 398 *burst_buf = readl(port->membase + UART_RX_BURST_FIFO); 399 *buff_index += UART_BURST_SIZE; 400 *valid_byte_count -= UART_BURST_SIZE; 401 } 402 403 while (*valid_byte_count) { 404 if (*buff_index >= RX_BUF_SIZE) 405 break; 406 rx_buff[*buff_index] = readb(port->membase + 407 UART_RX_BYTE_FIFO); 408 *buff_index += UART_BYTE_SIZE; 409 *valid_byte_count -= UART_BYTE_SIZE; 410 } 411 } 412 413 static void pci1xxxx_rx_burst(struct uart_port *port, u32 uart_status) 414 { 415 u32 valid_byte_count = uart_status & UART_BST_STAT_RX_COUNT_MASK; 416 struct tty_port *tty_port = &port->state->port; 417 unsigned char rx_buff[RX_BUF_SIZE]; 418 u32 buff_index = 0; 419 u32 copied_len; 420 421 if (valid_byte_count != 0 && 422 valid_byte_count < RX_BUF_SIZE) { 423 pci1xxxx_process_read_data(port, rx_buff, &buff_index, 424 &valid_byte_count); 425 426 copied_len = (u32)tty_insert_flip_string(tty_port, rx_buff, 427 buff_index); 428 429 if (copied_len != buff_index) 430 port->icount.overrun += buff_index - copied_len; 431 432 port->icount.rx += buff_index; 433 tty_flip_buffer_push(tty_port); 434 } 435 } 436 437 static void pci1xxxx_process_write_data(struct uart_port *port, 438 int *data_empty_count, 439 u32 *valid_byte_count) 440 { 441 struct tty_port *tport = &port->state->port; 442 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE; 443 444 /* 445 * Each transaction transfers data in DWORDs. If there are less than 446 * four remaining valid_byte_count to transfer or if the circular 447 * buffer has insufficient space for a DWORD, the data is transferred 448 * one byte at a time. 449 */ 450 while (valid_burst_count) { 451 u32 c; 452 453 if (*data_empty_count - UART_BURST_SIZE < 0) 454 break; 455 if (kfifo_len(&tport->xmit_fifo) < UART_BURST_SIZE) 456 break; 457 if (WARN_ON(kfifo_out(&tport->xmit_fifo, (u8 *)&c, sizeof(c)) != 458 sizeof(c))) 459 break; 460 writel(c, port->membase + UART_TX_BURST_FIFO); 461 *valid_byte_count -= UART_BURST_SIZE; 462 *data_empty_count -= UART_BURST_SIZE; 463 valid_burst_count -= UART_BYTE_SIZE; 464 } 465 466 while (*valid_byte_count) { 467 u8 c; 468 469 if (!kfifo_get(&tport->xmit_fifo, &c)) 470 break; 471 writeb(c, port->membase + UART_TX_BYTE_FIFO); 472 *data_empty_count -= UART_BYTE_SIZE; 473 *valid_byte_count -= UART_BYTE_SIZE; 474 475 /* 476 * If there are any pending burst count, data is handled by 477 * transmitting DWORDs at a time. 478 */ 479 if (valid_burst_count && 480 kfifo_len(&tport->xmit_fifo) >= UART_BURST_SIZE) 481 break; 482 } 483 } 484 485 static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status) 486 { 487 struct uart_8250_port *up = up_to_u8250p(port); 488 struct tty_port *tport = &port->state->port; 489 u32 valid_byte_count; 490 int data_empty_count; 491 492 if (port->x_char) { 493 writeb(port->x_char, port->membase + UART_TX); 494 port->icount.tx++; 495 port->x_char = 0; 496 return; 497 } 498 499 if ((uart_tx_stopped(port)) || kfifo_is_empty(&tport->xmit_fifo)) { 500 port->ops->stop_tx(port); 501 } else { 502 data_empty_count = (pci1xxxx_read_burst_status(port) & 503 UART_BST_STAT_TX_COUNT_MASK) >> 8; 504 do { 505 valid_byte_count = kfifo_len(&tport->xmit_fifo); 506 507 pci1xxxx_process_write_data(port, 508 &data_empty_count, 509 &valid_byte_count); 510 511 port->icount.tx++; 512 if (kfifo_is_empty(&tport->xmit_fifo)) 513 break; 514 } while (data_empty_count && valid_byte_count); 515 } 516 517 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 518 uart_write_wakeup(port); 519 520 /* 521 * With RPM enabled, we have to wait until the FIFO is empty before 522 * the HW can go idle. So we get here once again with empty FIFO and 523 * disable the interrupt and RPM in __stop_tx() 524 */ 525 if (kfifo_is_empty(&tport->xmit_fifo) && 526 !(up->capabilities & UART_CAP_RPM)) 527 port->ops->stop_tx(port); 528 } 529 530 static int pci1xxxx_handle_irq(struct uart_port *port) 531 { 532 unsigned long flags; 533 u32 status; 534 535 status = pci1xxxx_read_burst_status(port); 536 537 if (status & UART_BST_STAT_IIR_INT_PEND) 538 return 0; 539 540 spin_lock_irqsave(&port->lock, flags); 541 542 if (status & UART_BST_STAT_LSR_RX_MASK) 543 pci1xxxx_rx_burst(port, status); 544 545 if (status & UART_BST_STAT_LSR_THRE) 546 pci1xxxx_tx_burst(port, status); 547 548 spin_unlock_irqrestore(&port->lock, flags); 549 550 return 1; 551 } 552 553 static bool pci1xxxx_port_suspend(int line) 554 { 555 struct uart_8250_port *up = serial8250_get_port(line); 556 struct uart_port *port = &up->port; 557 struct tty_port *tport = &port->state->port; 558 unsigned long flags; 559 bool ret = false; 560 u8 wakeup_mask; 561 562 mutex_lock(&tport->mutex); 563 if (port->suspended == 0 && port->dev) { 564 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); 565 566 uart_port_lock_irqsave(port, &flags); 567 port->mctrl &= ~TIOCM_OUT2; 568 port->ops->set_mctrl(port, port->mctrl); 569 uart_port_unlock_irqrestore(port, flags); 570 571 ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; 572 } 573 574 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 575 mutex_unlock(&tport->mutex); 576 577 return ret; 578 } 579 580 static void pci1xxxx_port_resume(int line) 581 { 582 struct uart_8250_port *up = serial8250_get_port(line); 583 struct uart_port *port = &up->port; 584 struct tty_port *tport = &port->state->port; 585 unsigned long flags; 586 587 mutex_lock(&tport->mutex); 588 writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); 589 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 590 591 if (port->suspended == 0) { 592 uart_port_lock_irqsave(port, &flags); 593 port->mctrl |= TIOCM_OUT2; 594 port->ops->set_mctrl(port, port->mctrl); 595 uart_port_unlock_irqrestore(port, flags); 596 } 597 mutex_unlock(&tport->mutex); 598 } 599 600 static int pci1xxxx_suspend(struct device *dev) 601 { 602 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); 603 struct pci_dev *pcidev = to_pci_dev(dev); 604 bool wakeup = false; 605 unsigned int data; 606 void __iomem *p; 607 int i; 608 609 for (i = 0; i < priv->nr; i++) { 610 if (priv->line[i] >= 0) { 611 serial8250_suspend_port(priv->line[i]); 612 wakeup |= pci1xxxx_port_suspend(priv->line[i]); 613 } 614 } 615 616 p = pci_ioremap_bar(pcidev, 0); 617 if (!p) { 618 dev_err(dev, "remapping of bar 0 memory failed"); 619 return -ENOMEM; 620 } 621 622 data = readl(p + UART_RESET_REG); 623 writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); 624 625 if (wakeup) 626 writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); 627 628 iounmap(p); 629 device_set_wakeup_enable(dev, true); 630 pci_wake_from_d3(pcidev, true); 631 632 return 0; 633 } 634 635 static int pci1xxxx_resume(struct device *dev) 636 { 637 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); 638 struct pci_dev *pcidev = to_pci_dev(dev); 639 unsigned int data; 640 void __iomem *p; 641 int i; 642 643 p = pci_ioremap_bar(pcidev, 0); 644 if (!p) { 645 dev_err(dev, "remapping of bar 0 memory failed"); 646 return -ENOMEM; 647 } 648 649 data = readl(p + UART_RESET_REG); 650 writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); 651 iounmap(p); 652 653 for (i = 0; i < priv->nr; i++) { 654 if (priv->line[i] >= 0) { 655 pci1xxxx_port_resume(priv->line[i]); 656 serial8250_resume_port(priv->line[i]); 657 } 658 } 659 660 return 0; 661 } 662 663 static int pci1xxxx_setup(struct pci_dev *pdev, 664 struct uart_8250_port *port, int port_idx, int rev) 665 { 666 int ret; 667 668 port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; 669 port->port.type = PORT_MCHP16550A; 670 /* 671 * 8250 core considers prescaller value to be always 16. 672 * The MCHP ports support downscaled mode and hence the 673 * functional UART clock can be lower, i.e. 62.5MHz, than 674 * software expects in order to support higher baud rates. 675 * Assign here 64MHz to support 4Mbps. 676 * 677 * The value itself is not really used anywhere except baud 678 * rate calculations, so we can mangle it as we wish. 679 */ 680 port->port.uartclk = 64 * HZ_PER_MHZ; 681 port->port.set_termios = serial8250_do_set_termios; 682 port->port.get_divisor = pci1xxxx_get_divisor; 683 port->port.set_divisor = pci1xxxx_set_divisor; 684 port->port.rs485_config = pci1xxxx_rs485_config; 685 port->port.rs485_supported = pci1xxxx_rs485_supported; 686 687 /* 688 * C0 and later revisions support Burst operation. 689 * RTS workaround in mctrl is applicable only to B0. 690 */ 691 if (rev >= 0xC0) 692 port->port.handle_irq = pci1xxxx_handle_irq; 693 else if (rev == 0xB0) 694 port->port.set_mctrl = pci1xxxx_set_mctrl; 695 696 ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0); 697 if (ret < 0) 698 return ret; 699 700 writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); 701 writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); 702 writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); 703 704 return 0; 705 } 706 707 static unsigned int pci1xxxx_get_max_port(int subsys_dev) 708 { 709 unsigned int i = MAX_PORTS; 710 711 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) 712 while (i--) { 713 if (logical_to_physical_port_idx[subsys_dev][i] != -1) 714 return logical_to_physical_port_idx[subsys_dev][i] + 1; 715 } 716 717 if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414) 718 return 4; 719 720 return 1; 721 } 722 723 static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port) 724 { 725 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) 726 return logical_to_physical_port_idx[subsys_dev][port]; 727 728 return logical_to_physical_port_idx[0][port]; 729 } 730 731 static int pci1xxxx_get_device_revision(struct pci1xxxx_8250 *priv) 732 { 733 u32 regval; 734 int ret; 735 736 /* 737 * DEV REV is a system register, HW Syslock bit 738 * should be acquired before accessing the register 739 */ 740 ret = pci1xxxx_acquire_sys_lock(priv); 741 if (ret) 742 return ret; 743 744 regval = readl(priv->membase + UART_DEV_REV_REG); 745 priv->dev_rev = regval & UART_DEV_REV_MASK; 746 747 pci1xxxx_release_sys_lock(priv); 748 749 return 0; 750 } 751 752 static int pci1xxxx_serial_probe(struct pci_dev *pdev, 753 const struct pci_device_id *id) 754 { 755 struct device *dev = &pdev->dev; 756 struct pci1xxxx_8250 *priv; 757 struct uart_8250_port uart; 758 unsigned int max_vec_reqd; 759 unsigned int nr_ports, i; 760 int num_vectors; 761 int subsys_dev; 762 int port_idx; 763 int ret; 764 int rc; 765 766 rc = pcim_enable_device(pdev); 767 if (rc) 768 return rc; 769 770 nr_ports = pci1xxxx_get_num_ports(pdev); 771 772 priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL); 773 if (!priv) 774 return -ENOMEM; 775 776 priv->membase = pci_ioremap_bar(pdev, 0); 777 if (!priv->membase) 778 return -ENOMEM; 779 780 ret = pci1xxxx_get_device_revision(priv); 781 if (ret) 782 return ret; 783 784 pci_set_master(pdev); 785 786 priv->nr = nr_ports; 787 788 subsys_dev = pdev->subsystem_device; 789 max_vec_reqd = pci1xxxx_get_max_port(subsys_dev); 790 791 num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES); 792 if (num_vectors < 0) { 793 pci_iounmap(pdev, priv->membase); 794 return num_vectors; 795 } 796 797 memset(&uart, 0, sizeof(uart)); 798 uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 799 uart.port.dev = dev; 800 801 if (num_vectors == max_vec_reqd) 802 writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG); 803 804 for (i = 0; i < nr_ports; i++) { 805 priv->line[i] = -ENODEV; 806 807 port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i); 808 809 if (num_vectors == max_vec_reqd) 810 uart.port.irq = pci_irq_vector(pdev, port_idx); 811 else 812 uart.port.irq = pci_irq_vector(pdev, 0); 813 814 rc = pci1xxxx_setup(pdev, &uart, port_idx, priv->dev_rev); 815 if (rc) { 816 dev_warn(dev, "Failed to setup port %u\n", i); 817 continue; 818 } 819 820 priv->line[i] = serial8250_register_8250_port(&uart); 821 if (priv->line[i] < 0) { 822 dev_warn(dev, 823 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 824 uart.port.iobase, uart.port.irq, uart.port.iotype, 825 priv->line[i]); 826 } 827 } 828 829 pci_set_drvdata(pdev, priv); 830 831 return 0; 832 } 833 834 static void pci1xxxx_serial_remove(struct pci_dev *dev) 835 { 836 struct pci1xxxx_8250 *priv = pci_get_drvdata(dev); 837 unsigned int i; 838 839 for (i = 0; i < priv->nr; i++) { 840 if (priv->line[i] >= 0) 841 serial8250_unregister_port(priv->line[i]); 842 } 843 844 pci_free_irq_vectors(dev); 845 pci_iounmap(dev, priv->membase); 846 } 847 848 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume); 849 850 static const struct pci_device_id pci1xxxx_pci_tbl[] = { 851 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, 852 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, 853 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) }, 854 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) }, 855 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) }, 856 {} 857 }; 858 MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); 859 860 static struct pci_driver pci1xxxx_pci_driver = { 861 .name = "pci1xxxx serial", 862 .probe = pci1xxxx_serial_probe, 863 .remove = pci1xxxx_serial_remove, 864 .driver = { 865 .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), 866 }, 867 .id_table = pci1xxxx_pci_tbl, 868 }; 869 module_pci_driver(pci1xxxx_pci_driver); 870 871 static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1)); 872 873 MODULE_IMPORT_NS("SERIAL_8250_PCI"); 874 MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module"); 875 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>"); 876 MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>"); 877 MODULE_LICENSE("GPL"); 878