1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 #include <linux/bitfield.h> 23 24 #include <asm/byteorder.h> 25 #include <asm/io.h> 26 27 #include "8250.h" 28 #include "8250_pcilib.h" 29 30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 32 #define PCI_DEVICE_ID_OCTPRO 0x0001 33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 46 #define PCI_DEVICE_ID_TITAN_200I 0x8028 47 #define PCI_DEVICE_ID_TITAN_400I 0x8048 48 #define PCI_DEVICE_ID_TITAN_800I 0x8088 49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 52 #define PCI_DEVICE_ID_TITAN_100E 0xA010 53 #define PCI_DEVICE_ID_TITAN_200E 0xA012 54 #define PCI_DEVICE_ID_TITAN_400E 0xA013 55 #define PCI_DEVICE_ID_TITAN_800E 0xA014 56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 67 68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253 69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173 70 71 #define PCI_VENDOR_ID_AGESTAR 0x5372 72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 75 76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470 77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853 78 79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027 82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046 84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121 85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145 87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323 93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343 95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 97 98 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 99 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 100 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 101 102 /* 103 * init function returns: 104 * > 0 - number of ports 105 * = 0 - use board->num_ports 106 * < 0 - error 107 */ 108 struct pci_serial_quirk { 109 u32 vendor; 110 u32 device; 111 u32 subvendor; 112 u32 subdevice; 113 int (*probe)(struct pci_dev *dev); 114 int (*init)(struct pci_dev *dev); 115 int (*setup)(struct serial_private *, 116 const struct pciserial_board *, 117 struct uart_8250_port *, int); 118 void (*exit)(struct pci_dev *dev); 119 }; 120 121 struct f815xxa_data { 122 spinlock_t lock; 123 int idx; 124 }; 125 126 struct serial_private { 127 struct pci_dev *dev; 128 unsigned int nr; 129 struct pci_serial_quirk *quirk; 130 const struct pciserial_board *board; 131 int line[]; 132 }; 133 134 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 135 136 static const struct pci_device_id pci_use_msi[] = { 137 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 138 0xA000, 0x1000) }, 139 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 140 0xA000, 0x1000) }, 141 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 142 0xA000, 0x1000) }, 143 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 144 0xA000, 0x1000) }, 145 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 146 PCI_ANY_ID, PCI_ANY_ID) }, 147 { } 148 }; 149 150 static int pci_default_setup(struct serial_private*, 151 const struct pciserial_board*, struct uart_8250_port *, int); 152 153 static void moan_device(const char *str, struct pci_dev *dev) 154 { 155 pci_err(dev, "%s\n" 156 "Please send the output of lspci -vv, this\n" 157 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 158 "manufacturer and name of serial board or\n" 159 "modem board to <linux-serial@vger.kernel.org>.\n", 160 str, dev->vendor, dev->device, 161 dev->subsystem_vendor, dev->subsystem_device); 162 } 163 164 static int 165 setup_port(struct serial_private *priv, struct uart_8250_port *port, 166 u8 bar, unsigned int offset, int regshift) 167 { 168 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); 169 } 170 171 /* 172 * ADDI-DATA GmbH communication cards <info@addi-data.com> 173 */ 174 static int addidata_apci7800_setup(struct serial_private *priv, 175 const struct pciserial_board *board, 176 struct uart_8250_port *port, int idx) 177 { 178 unsigned int bar = 0, offset = board->first_offset; 179 bar = FL_GET_BASE(board->flags); 180 181 if (idx < 2) { 182 offset += idx * board->uart_offset; 183 } else if ((idx >= 2) && (idx < 4)) { 184 bar += 1; 185 offset += ((idx - 2) * board->uart_offset); 186 } else if ((idx >= 4) && (idx < 6)) { 187 bar += 2; 188 offset += ((idx - 4) * board->uart_offset); 189 } else if (idx >= 6) { 190 bar += 3; 191 offset += ((idx - 6) * board->uart_offset); 192 } 193 194 return setup_port(priv, port, bar, offset, board->reg_shift); 195 } 196 197 /* 198 * AFAVLAB uses a different mixture of BARs and offsets 199 * Not that ugly ;) -- HW 200 */ 201 static int 202 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 203 struct uart_8250_port *port, int idx) 204 { 205 unsigned int bar, offset = board->first_offset; 206 207 bar = FL_GET_BASE(board->flags); 208 if (idx < 4) 209 bar += idx; 210 else { 211 bar = 4; 212 offset += (idx - 4) * board->uart_offset; 213 } 214 215 return setup_port(priv, port, bar, offset, board->reg_shift); 216 } 217 218 /* 219 * HP's Remote Management Console. The Diva chip came in several 220 * different versions. N-class, L2000 and A500 have two Diva chips, each 221 * with 3 UARTs (the third UART on the second chip is unused). Superdome 222 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 223 * one Diva chip, but it has been expanded to 5 UARTs. 224 */ 225 static int pci_hp_diva_init(struct pci_dev *dev) 226 { 227 int rc = 0; 228 229 switch (dev->subsystem_device) { 230 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 231 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 232 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 233 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 234 rc = 3; 235 break; 236 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 237 rc = 2; 238 break; 239 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 240 rc = 4; 241 break; 242 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 243 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 244 rc = 1; 245 break; 246 } 247 248 return rc; 249 } 250 251 /* 252 * HP's Diva chip puts the 4th/5th serial port further out, and 253 * some serial ports are supposed to be hidden on certain models. 254 */ 255 static int 256 pci_hp_diva_setup(struct serial_private *priv, 257 const struct pciserial_board *board, 258 struct uart_8250_port *port, int idx) 259 { 260 unsigned int offset = board->first_offset; 261 unsigned int bar = FL_GET_BASE(board->flags); 262 263 switch (priv->dev->subsystem_device) { 264 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 265 if (idx == 3) 266 idx++; 267 break; 268 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 269 if (idx > 0) 270 idx++; 271 if (idx > 2) 272 idx++; 273 break; 274 } 275 if (idx > 2) 276 offset = 0x18; 277 278 offset += idx * board->uart_offset; 279 280 return setup_port(priv, port, bar, offset, board->reg_shift); 281 } 282 283 /* 284 * Added for EKF Intel i960 serial boards 285 */ 286 static int pci_inteli960ni_init(struct pci_dev *dev) 287 { 288 u32 oldval; 289 290 if (!(dev->subsystem_device & 0x1000)) 291 return -ENODEV; 292 293 /* is firmware started? */ 294 pci_read_config_dword(dev, 0x44, &oldval); 295 if (oldval == 0x00001000L) { /* RESET value */ 296 pci_dbg(dev, "Local i960 firmware missing\n"); 297 return -ENODEV; 298 } 299 return 0; 300 } 301 302 /* 303 * Some PCI serial cards using the PLX 9050 PCI interface chip require 304 * that the card interrupt be explicitly enabled or disabled. This 305 * seems to be mainly needed on card using the PLX which also use I/O 306 * mapped memory. 307 */ 308 static int pci_plx9050_init(struct pci_dev *dev) 309 { 310 u8 irq_config; 311 void __iomem *p; 312 313 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 314 moan_device("no memory in bar 0", dev); 315 return 0; 316 } 317 318 irq_config = 0x41; 319 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 320 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 321 irq_config = 0x43; 322 323 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 324 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 325 /* 326 * As the megawolf cards have the int pins active 327 * high, and have 2 UART chips, both ints must be 328 * enabled on the 9050. Also, the UARTS are set in 329 * 16450 mode by default, so we have to enable the 330 * 16C950 'enhanced' mode so that we can use the 331 * deep FIFOs 332 */ 333 irq_config = 0x5b; 334 /* 335 * enable/disable interrupts 336 */ 337 p = ioremap(pci_resource_start(dev, 0), 0x80); 338 if (p == NULL) 339 return -ENOMEM; 340 writel(irq_config, p + 0x4c); 341 342 /* 343 * Read the register back to ensure that it took effect. 344 */ 345 readl(p + 0x4c); 346 iounmap(p); 347 348 return 0; 349 } 350 351 static void pci_plx9050_exit(struct pci_dev *dev) 352 { 353 u8 __iomem *p; 354 355 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 356 return; 357 358 /* 359 * disable interrupts 360 */ 361 p = ioremap(pci_resource_start(dev, 0), 0x80); 362 if (p != NULL) { 363 writel(0, p + 0x4c); 364 365 /* 366 * Read the register back to ensure that it took effect. 367 */ 368 readl(p + 0x4c); 369 iounmap(p); 370 } 371 } 372 373 #define NI8420_INT_ENABLE_REG 0x38 374 #define NI8420_INT_ENABLE_BIT 0x2000 375 376 static void pci_ni8420_exit(struct pci_dev *dev) 377 { 378 void __iomem *p; 379 unsigned int bar = 0; 380 381 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 382 moan_device("no memory in bar", dev); 383 return; 384 } 385 386 p = pci_ioremap_bar(dev, bar); 387 if (p == NULL) 388 return; 389 390 /* Disable the CPU Interrupt */ 391 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 392 p + NI8420_INT_ENABLE_REG); 393 iounmap(p); 394 } 395 396 397 /* MITE registers */ 398 #define MITE_IOWBSR1 0xc4 399 #define MITE_IOWCR1 0xf4 400 #define MITE_LCIMR1 0x08 401 #define MITE_LCIMR2 0x10 402 403 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 404 405 static void pci_ni8430_exit(struct pci_dev *dev) 406 { 407 void __iomem *p; 408 unsigned int bar = 0; 409 410 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 411 moan_device("no memory in bar", dev); 412 return; 413 } 414 415 p = pci_ioremap_bar(dev, bar); 416 if (p == NULL) 417 return; 418 419 /* Disable the CPU Interrupt */ 420 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 421 iounmap(p); 422 } 423 424 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 425 static int 426 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 427 struct uart_8250_port *port, int idx) 428 { 429 unsigned int bar, offset = board->first_offset; 430 431 bar = 0; 432 433 if (idx < 4) { 434 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 435 offset += idx * board->uart_offset; 436 } else if (idx < 8) { 437 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 438 offset += idx * board->uart_offset + 0xC00; 439 } else /* we have only 8 ports on PMC-OCTALPRO */ 440 return 1; 441 442 return setup_port(priv, port, bar, offset, board->reg_shift); 443 } 444 445 /* 446 * This does initialization for PMC OCTALPRO cards: 447 * maps the device memory, resets the UARTs (needed, bc 448 * if the module is removed and inserted again, the card 449 * is in the sleep mode) and enables global interrupt. 450 */ 451 452 /* global control register offset for SBS PMC-OctalPro */ 453 #define OCT_REG_CR_OFF 0x500 454 455 static int sbs_init(struct pci_dev *dev) 456 { 457 u8 __iomem *p; 458 459 p = pci_ioremap_bar(dev, 0); 460 461 if (p == NULL) 462 return -ENOMEM; 463 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 464 writeb(0x10, p + OCT_REG_CR_OFF); 465 udelay(50); 466 writeb(0x0, p + OCT_REG_CR_OFF); 467 468 /* Set bit-2 (INTENABLE) of Control Register */ 469 writeb(0x4, p + OCT_REG_CR_OFF); 470 iounmap(p); 471 472 return 0; 473 } 474 475 /* 476 * Disables the global interrupt of PMC-OctalPro 477 */ 478 479 static void sbs_exit(struct pci_dev *dev) 480 { 481 u8 __iomem *p; 482 483 p = pci_ioremap_bar(dev, 0); 484 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 485 if (p != NULL) 486 writeb(0, p + OCT_REG_CR_OFF); 487 iounmap(p); 488 } 489 490 /* 491 * SIIG serial cards have an PCI interface chip which also controls 492 * the UART clocking frequency. Each UART can be clocked independently 493 * (except cards equipped with 4 UARTs) and initial clocking settings 494 * are stored in the EEPROM chip. It can cause problems because this 495 * version of serial driver doesn't support differently clocked UART's 496 * on single PCI card. To prevent this, initialization functions set 497 * high frequency clocking for all UART's on given card. It is safe (I 498 * hope) because it doesn't touch EEPROM settings to prevent conflicts 499 * with other OSes (like M$ DOS). 500 * 501 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 502 * 503 * There is two family of SIIG serial cards with different PCI 504 * interface chip and different configuration methods: 505 * - 10x cards have control registers in IO and/or memory space; 506 * - 20x cards have control registers in standard PCI configuration space. 507 * 508 * Note: all 10x cards have PCI device ids 0x10.. 509 * all 20x cards have PCI device ids 0x20.. 510 * 511 * There are also Quartet Serial cards which use Oxford Semiconductor 512 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 513 * 514 * Note: some SIIG cards are probed by the parport_serial object. 515 */ 516 517 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 518 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 519 520 static int pci_siig10x_init(struct pci_dev *dev) 521 { 522 u16 data; 523 void __iomem *p; 524 525 switch (dev->device & 0xfff8) { 526 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 527 data = 0xffdf; 528 break; 529 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 530 data = 0xf7ff; 531 break; 532 default: /* 1S1P, 4S */ 533 data = 0xfffb; 534 break; 535 } 536 537 p = ioremap(pci_resource_start(dev, 0), 0x80); 538 if (p == NULL) 539 return -ENOMEM; 540 541 writew(readw(p + 0x28) & data, p + 0x28); 542 readw(p + 0x28); 543 iounmap(p); 544 return 0; 545 } 546 547 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 548 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 549 550 static int pci_siig20x_init(struct pci_dev *dev) 551 { 552 u8 data; 553 554 /* Change clock frequency for the first UART. */ 555 pci_read_config_byte(dev, 0x6f, &data); 556 pci_write_config_byte(dev, 0x6f, data & 0xef); 557 558 /* If this card has 2 UART, we have to do the same with second UART. */ 559 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 560 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 561 pci_read_config_byte(dev, 0x73, &data); 562 pci_write_config_byte(dev, 0x73, data & 0xef); 563 } 564 return 0; 565 } 566 567 static int pci_siig_init(struct pci_dev *dev) 568 { 569 unsigned int type = dev->device & 0xff00; 570 571 if (type == 0x1000) 572 return pci_siig10x_init(dev); 573 if (type == 0x2000) 574 return pci_siig20x_init(dev); 575 576 moan_device("Unknown SIIG card", dev); 577 return -ENODEV; 578 } 579 580 static int pci_siig_setup(struct serial_private *priv, 581 const struct pciserial_board *board, 582 struct uart_8250_port *port, int idx) 583 { 584 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 585 586 if (idx > 3) { 587 bar = 4; 588 offset = (idx - 4) * 8; 589 } 590 591 return setup_port(priv, port, bar, offset, 0); 592 } 593 594 /* 595 * Timedia has an explosion of boards, and to avoid the PCI table from 596 * growing *huge*, we use this function to collapse some 70 entries 597 * in the PCI table into one, for sanity's and compactness's sake. 598 */ 599 static const unsigned short timedia_single_port[] = { 600 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 601 }; 602 603 static const unsigned short timedia_dual_port[] = { 604 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 605 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 606 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 607 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 608 0xD079, 0 609 }; 610 611 static const unsigned short timedia_quad_port[] = { 612 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 613 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 614 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 615 0xB157, 0 616 }; 617 618 static const unsigned short timedia_eight_port[] = { 619 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 620 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 621 }; 622 623 static const struct timedia_struct { 624 int num; 625 const unsigned short *ids; 626 } timedia_data[] = { 627 { 1, timedia_single_port }, 628 { 2, timedia_dual_port }, 629 { 4, timedia_quad_port }, 630 { 8, timedia_eight_port } 631 }; 632 633 /* 634 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 635 * listing them individually, this driver merely grabs them all with 636 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 637 * and should be left free to be claimed by parport_serial instead. 638 */ 639 static int pci_timedia_probe(struct pci_dev *dev) 640 { 641 /* 642 * Check the third digit of the subdevice ID 643 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 644 */ 645 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 646 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 647 dev->subsystem_device); 648 return -ENODEV; 649 } 650 651 return 0; 652 } 653 654 static int pci_timedia_init(struct pci_dev *dev) 655 { 656 const unsigned short *ids; 657 int i, j; 658 659 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 660 ids = timedia_data[i].ids; 661 for (j = 0; ids[j]; j++) 662 if (dev->subsystem_device == ids[j]) 663 return timedia_data[i].num; 664 } 665 return 0; 666 } 667 668 /* 669 * Timedia/SUNIX uses a mixture of BARs and offsets 670 * Ugh, this is ugly as all hell --- TYT 671 */ 672 static int 673 pci_timedia_setup(struct serial_private *priv, 674 const struct pciserial_board *board, 675 struct uart_8250_port *port, int idx) 676 { 677 unsigned int bar = 0, offset = board->first_offset; 678 679 switch (idx) { 680 case 0: 681 bar = 0; 682 break; 683 case 1: 684 offset = board->uart_offset; 685 bar = 0; 686 break; 687 case 2: 688 bar = 1; 689 break; 690 case 3: 691 offset = board->uart_offset; 692 fallthrough; 693 case 4: /* BAR 2 */ 694 case 5: /* BAR 3 */ 695 case 6: /* BAR 4 */ 696 case 7: /* BAR 5 */ 697 bar = idx - 2; 698 } 699 700 return setup_port(priv, port, bar, offset, board->reg_shift); 701 } 702 703 /* 704 * Some Titan cards are also a little weird 705 */ 706 static int 707 titan_400l_800l_setup(struct serial_private *priv, 708 const struct pciserial_board *board, 709 struct uart_8250_port *port, int idx) 710 { 711 unsigned int bar, offset = board->first_offset; 712 713 switch (idx) { 714 case 0: 715 bar = 1; 716 break; 717 case 1: 718 bar = 2; 719 break; 720 default: 721 bar = 4; 722 offset = (idx - 2) * board->uart_offset; 723 } 724 725 return setup_port(priv, port, bar, offset, board->reg_shift); 726 } 727 728 static int pci_xircom_init(struct pci_dev *dev) 729 { 730 msleep(100); 731 return 0; 732 } 733 734 static int pci_ni8420_init(struct pci_dev *dev) 735 { 736 void __iomem *p; 737 unsigned int bar = 0; 738 739 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 740 moan_device("no memory in bar", dev); 741 return 0; 742 } 743 744 p = pci_ioremap_bar(dev, bar); 745 if (p == NULL) 746 return -ENOMEM; 747 748 /* Enable CPU Interrupt */ 749 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 750 p + NI8420_INT_ENABLE_REG); 751 752 iounmap(p); 753 return 0; 754 } 755 756 #define MITE_IOWBSR1_WSIZE 0xa 757 #define MITE_IOWBSR1_WIN_OFFSET 0x800 758 #define MITE_IOWBSR1_WENAB (1 << 7) 759 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 760 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 761 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 762 763 static int pci_ni8430_init(struct pci_dev *dev) 764 { 765 void __iomem *p; 766 struct pci_bus_region region; 767 u32 device_window; 768 unsigned int bar = 0; 769 770 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 771 moan_device("no memory in bar", dev); 772 return 0; 773 } 774 775 p = pci_ioremap_bar(dev, bar); 776 if (p == NULL) 777 return -ENOMEM; 778 779 /* 780 * Set device window address and size in BAR0, while acknowledging that 781 * the resource structure may contain a translated address that differs 782 * from the address the device responds to. 783 */ 784 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 785 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 786 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 787 writel(device_window, p + MITE_IOWBSR1); 788 789 /* Set window access to go to RAMSEL IO address space */ 790 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 791 p + MITE_IOWCR1); 792 793 /* Enable IO Bus Interrupt 0 */ 794 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 795 796 /* Enable CPU Interrupt */ 797 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 798 799 iounmap(p); 800 return 0; 801 } 802 803 /* UART Port Control Register */ 804 #define NI8430_PORTCON 0x0f 805 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 806 807 static int 808 pci_ni8430_setup(struct serial_private *priv, 809 const struct pciserial_board *board, 810 struct uart_8250_port *port, int idx) 811 { 812 struct pci_dev *dev = priv->dev; 813 void __iomem *p; 814 unsigned int bar, offset = board->first_offset; 815 816 if (idx >= board->num_ports) 817 return 1; 818 819 bar = FL_GET_BASE(board->flags); 820 offset += idx * board->uart_offset; 821 822 p = pci_ioremap_bar(dev, bar); 823 if (!p) 824 return -ENOMEM; 825 826 /* enable the transceiver */ 827 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 828 p + offset + NI8430_PORTCON); 829 830 iounmap(p); 831 832 return setup_port(priv, port, bar, offset, board->reg_shift); 833 } 834 835 static int pci_netmos_9900_setup(struct serial_private *priv, 836 const struct pciserial_board *board, 837 struct uart_8250_port *port, int idx) 838 { 839 unsigned int bar; 840 841 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 842 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 843 /* netmos apparently orders BARs by datasheet layout, so serial 844 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 845 */ 846 bar = 3 * idx; 847 848 return setup_port(priv, port, bar, 0, board->reg_shift); 849 } 850 851 return pci_default_setup(priv, board, port, idx); 852 } 853 854 /* the 99xx series comes with a range of device IDs and a variety 855 * of capabilities: 856 * 857 * 9900 has varying capabilities and can cascade to sub-controllers 858 * (cascading should be purely internal) 859 * 9904 is hardwired with 4 serial ports 860 * 9912 and 9922 are hardwired with 2 serial ports 861 */ 862 static int pci_netmos_9900_numports(struct pci_dev *dev) 863 { 864 unsigned int c = dev->class; 865 unsigned int pi; 866 unsigned short sub_serports; 867 868 pi = c & 0xff; 869 870 if (pi == 2) 871 return 1; 872 873 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 874 /* two possibilities: 0x30ps encodes number of parallel and 875 * serial ports, or 0x1000 indicates *something*. This is not 876 * immediately obvious, since the 2s1p+4s configuration seems 877 * to offer all functionality on functions 0..2, while still 878 * advertising the same function 3 as the 4s+2s1p config. 879 */ 880 sub_serports = dev->subsystem_device & 0xf; 881 if (sub_serports > 0) 882 return sub_serports; 883 884 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 885 return 0; 886 } 887 888 moan_device("unknown NetMos/Mostech program interface", dev); 889 return 0; 890 } 891 892 static int pci_netmos_init(struct pci_dev *dev) 893 { 894 /* subdevice 0x00PS means <P> parallel, <S> serial */ 895 unsigned int num_serial = dev->subsystem_device & 0xf; 896 897 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 898 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 899 return 0; 900 901 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 902 dev->subsystem_device == 0x0299) 903 return 0; 904 905 switch (dev->device) { /* FALLTHROUGH on all */ 906 case PCI_DEVICE_ID_NETMOS_9904: 907 case PCI_DEVICE_ID_NETMOS_9912: 908 case PCI_DEVICE_ID_NETMOS_9922: 909 case PCI_DEVICE_ID_NETMOS_9900: 910 num_serial = pci_netmos_9900_numports(dev); 911 break; 912 913 default: 914 break; 915 } 916 917 if (num_serial == 0) { 918 moan_device("unknown NetMos/Mostech device", dev); 919 return -ENODEV; 920 } 921 922 return num_serial; 923 } 924 925 /* 926 * These chips are available with optionally one parallel port and up to 927 * two serial ports. Unfortunately they all have the same product id. 928 * 929 * Basic configuration is done over a region of 32 I/O ports. The base 930 * ioport is called INTA or INTC, depending on docs/other drivers. 931 * 932 * The region of the 32 I/O ports is configured in POSIO0R... 933 */ 934 935 /* registers */ 936 #define ITE_887x_MISCR 0x9c 937 #define ITE_887x_INTCBAR 0x78 938 #define ITE_887x_UARTBAR 0x7c 939 #define ITE_887x_PS0BAR 0x10 940 #define ITE_887x_POSIO0 0x60 941 942 /* I/O space size */ 943 #define ITE_887x_IOSIZE 32 944 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 945 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 946 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 947 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 948 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 949 #define ITE_887x_POSIO_SPEED (3 << 29) 950 /* enable IO_Space bit */ 951 #define ITE_887x_POSIO_ENABLE (1 << 31) 952 953 /* inta_addr are the configuration addresses of the ITE */ 954 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 955 static int pci_ite887x_init(struct pci_dev *dev) 956 { 957 int ret, i, type; 958 struct resource *iobase = NULL; 959 u32 miscr, uartbar, ioport; 960 961 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 962 return serial_8250_warn_need_ioport(dev); 963 964 /* search for the base-ioport */ 965 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 966 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 967 "ite887x"); 968 if (iobase != NULL) { 969 /* write POSIO0R - speed | size | ioport */ 970 pci_write_config_dword(dev, ITE_887x_POSIO0, 971 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 972 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 973 /* write INTCBAR - ioport */ 974 pci_write_config_dword(dev, ITE_887x_INTCBAR, 975 inta_addr[i]); 976 ret = inb(inta_addr[i]); 977 if (ret != 0xff) { 978 /* ioport connected */ 979 break; 980 } 981 release_region(iobase->start, ITE_887x_IOSIZE); 982 } 983 } 984 985 if (i == ARRAY_SIZE(inta_addr)) { 986 pci_err(dev, "could not find iobase\n"); 987 return -ENODEV; 988 } 989 990 /* start of undocumented type checking (see parport_pc.c) */ 991 type = inb(iobase->start + 0x18) & 0x0f; 992 993 switch (type) { 994 case 0x2: /* ITE8871 (1P) */ 995 case 0xa: /* ITE8875 (1P) */ 996 ret = 0; 997 break; 998 case 0xe: /* ITE8872 (2S1P) */ 999 ret = 2; 1000 break; 1001 case 0x6: /* ITE8873 (1S) */ 1002 ret = 1; 1003 break; 1004 case 0x8: /* ITE8874 (2S) */ 1005 ret = 2; 1006 break; 1007 default: 1008 moan_device("Unknown ITE887x", dev); 1009 ret = -ENODEV; 1010 } 1011 1012 /* configure all serial ports */ 1013 for (i = 0; i < ret; i++) { 1014 /* read the I/O port from the device */ 1015 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 1016 &ioport); 1017 ioport &= 0x0000FF00; /* the actual base address */ 1018 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 1019 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 1020 ITE_887x_POSIO_IOSIZE_8 | ioport); 1021 1022 /* write the ioport to the UARTBAR */ 1023 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 1024 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 1025 uartbar |= (ioport << (16 * i)); /* set the ioport */ 1026 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 1027 1028 /* get current config */ 1029 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 1030 /* disable interrupts (UARTx_Routing[3:0]) */ 1031 miscr &= ~(0xf << (12 - 4 * i)); 1032 /* activate the UART (UARTx_En) */ 1033 miscr |= 1 << (23 - i); 1034 /* write new config with activated UART */ 1035 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 1036 } 1037 1038 if (ret <= 0) { 1039 /* the device has no UARTs if we get here */ 1040 release_region(iobase->start, ITE_887x_IOSIZE); 1041 } 1042 1043 return ret; 1044 } 1045 1046 static void pci_ite887x_exit(struct pci_dev *dev) 1047 { 1048 u32 ioport; 1049 /* the ioport is bit 0-15 in POSIO0R */ 1050 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 1051 ioport &= 0xffff; 1052 release_region(ioport, ITE_887x_IOSIZE); 1053 } 1054 1055 /* 1056 * Oxford Semiconductor Inc. 1057 * Check if an OxSemi device is part of the Tornado range of devices. 1058 */ 1059 #define PCI_VENDOR_ID_ENDRUN 0x7401 1060 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1061 1062 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1063 { 1064 /* OxSemi Tornado devices are all 0xCxxx */ 1065 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1066 (dev->device & 0xf000) != 0xc000) 1067 return false; 1068 1069 /* EndRun devices are all 0xExxx */ 1070 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1071 (dev->device & 0xf000) != 0xe000) 1072 return false; 1073 1074 return true; 1075 } 1076 1077 /* 1078 * Determine the number of ports available on a Tornado device. 1079 */ 1080 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1081 { 1082 u8 __iomem *p; 1083 unsigned long deviceID; 1084 unsigned int number_uarts = 0; 1085 1086 if (!pci_oxsemi_tornado_p(dev)) 1087 return 0; 1088 1089 p = pci_iomap(dev, 0, 5); 1090 if (p == NULL) 1091 return -ENOMEM; 1092 1093 deviceID = ioread32(p); 1094 /* Tornado device */ 1095 if (deviceID == 0x07000200) { 1096 number_uarts = ioread8(p + 4); 1097 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1098 number_uarts, 1099 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1100 "EndRun" : "Oxford"); 1101 } 1102 pci_iounmap(dev, p); 1103 return number_uarts; 1104 } 1105 1106 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1107 #define OXSEMI_TORNADO_TCR_MASK 0xf 1108 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1109 #define OXSEMI_TORNADO_CPR_MIN 0x008 1110 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1111 1112 /* 1113 * Determine the oversampling rate, the clock prescaler, and the clock 1114 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1115 * which is four times the baud base, and the prescaler increments in 1116 * steps of 1/8. Therefore to make calculations on integers we need 1117 * to use a scaled clock rate, which is the baud base multiplied by 32 1118 * (or our assumed UART clock rate multiplied by 2). 1119 * 1120 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1121 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1122 * values between 1.000 and 63.875 inclusive (operation for values from 1123 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1124 * unsigned 16-bit integer. 1125 * 1126 * For the most accurate baud rate we use a table of predetermined 1127 * oversampling rates and clock prescalers that records all possible 1128 * products of the two parameters in the range from 4 up to 255 inclusive, 1129 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1130 * by 8. The table is sorted by the decreasing value of the oversampling 1131 * rate and ties are resolved by sorting by the decreasing value of the 1132 * product. This way preference is given to higher oversampling rates. 1133 * 1134 * We iterate over the table and choose the product of an oversampling 1135 * rate and a clock prescaler that gives the lowest integer division 1136 * result deviation, or if an exact integer divider is found we stop 1137 * looking for it right away. We do some fixup if the resulting clock 1138 * divisor required would be out of its unsigned 16-bit integer range. 1139 * 1140 * Finally we abuse the supposed fractional part returned to encode the 1141 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1142 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1143 */ 1144 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1145 unsigned int baud, 1146 unsigned int *frac) 1147 { 1148 static u8 p[][2] = { 1149 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1150 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1151 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1152 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1153 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1154 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1155 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1156 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1157 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1158 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1159 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1160 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1161 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1162 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1163 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1164 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1165 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1166 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1167 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1168 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1169 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1170 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1171 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1172 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1173 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1174 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1175 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1176 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1177 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1178 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1179 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1180 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1181 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1182 { 4, 9, }, { 4, 8, }, 1183 }; 1184 /* Scale the quotient for comparison to get the fractional part. */ 1185 const unsigned int quot_scale = 65536; 1186 unsigned int sclk = port->uartclk * 2; 1187 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1188 unsigned int best_squot; 1189 unsigned int squot; 1190 unsigned int quot; 1191 u16 cpr; 1192 u8 tcr; 1193 int i; 1194 1195 /* Old custom speed handling. */ 1196 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1197 unsigned int cust_div = port->custom_divisor; 1198 1199 quot = cust_div & UART_DIV_MAX; 1200 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1201 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1202 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1203 cpr = OXSEMI_TORNADO_CPR_DEF; 1204 } else { 1205 best_squot = quot_scale; 1206 for (i = 0; i < ARRAY_SIZE(p); i++) { 1207 unsigned int spre; 1208 unsigned int srem; 1209 u8 cp; 1210 u8 tc; 1211 1212 tc = p[i][0]; 1213 cp = p[i][1]; 1214 spre = tc * cp; 1215 1216 srem = sdiv % spre; 1217 if (srem > spre / 2) 1218 srem = spre - srem; 1219 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1220 1221 if (srem == 0) { 1222 tcr = tc; 1223 cpr = cp; 1224 quot = sdiv / spre; 1225 break; 1226 } else if (squot < best_squot) { 1227 best_squot = squot; 1228 tcr = tc; 1229 cpr = cp; 1230 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1231 } 1232 } 1233 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1234 quot % 2 == 0) { 1235 quot >>= 1; 1236 tcr <<= 1; 1237 } 1238 while (quot > UART_DIV_MAX) { 1239 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1240 quot >>= 1; 1241 tcr <<= 1; 1242 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1243 quot >>= 1; 1244 cpr <<= 1; 1245 } else { 1246 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1247 cpr = OXSEMI_TORNADO_CPR_MASK; 1248 } 1249 } 1250 } 1251 1252 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1253 return quot; 1254 } 1255 1256 /* 1257 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1258 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1259 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1260 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1261 * has to be written first, followed by CPR2, which occupies the location 1262 * of CKS used with earlier UART designs. 1263 */ 1264 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1265 unsigned int baud, 1266 unsigned int quot, 1267 unsigned int quot_frac) 1268 { 1269 struct uart_8250_port *up = up_to_u8250p(port); 1270 u8 cpr2 = quot_frac >> 16; 1271 u8 cpr = quot_frac >> 8; 1272 u8 tcr = quot_frac; 1273 1274 serial_icr_write(up, UART_TCR, tcr); 1275 serial_icr_write(up, UART_CPR, cpr); 1276 serial_icr_write(up, UART_CKS, cpr2); 1277 serial8250_do_set_divisor(port, baud, quot); 1278 } 1279 1280 /* 1281 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1282 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1283 */ 1284 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1285 unsigned int mctrl) 1286 { 1287 struct uart_8250_port *up = up_to_u8250p(port); 1288 1289 up->mcr |= UART_MCR_CLKSEL; 1290 serial8250_do_set_mctrl(port, mctrl); 1291 } 1292 1293 /* 1294 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1295 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1296 */ 1297 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1298 const struct pciserial_board *board, 1299 struct uart_8250_port *up, int idx) 1300 { 1301 struct pci_dev *dev = priv->dev; 1302 1303 if (pci_oxsemi_tornado_p(dev)) { 1304 up->port.flags |= UPF_FULL_PROBE; 1305 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1306 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1307 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1308 } 1309 1310 return pci_default_setup(priv, board, up, idx); 1311 } 1312 1313 #define QPCR_TEST_FOR1 0x3F 1314 #define QPCR_TEST_GET1 0x00 1315 #define QPCR_TEST_FOR2 0x40 1316 #define QPCR_TEST_GET2 0x40 1317 #define QPCR_TEST_FOR3 0x80 1318 #define QPCR_TEST_GET3 0x40 1319 #define QPCR_TEST_FOR4 0xC0 1320 #define QPCR_TEST_GET4 0x80 1321 1322 #define QOPR_CLOCK_X1 0x0000 1323 #define QOPR_CLOCK_X2 0x0001 1324 #define QOPR_CLOCK_X4 0x0002 1325 #define QOPR_CLOCK_X8 0x0003 1326 #define QOPR_CLOCK_RATE_MASK 0x0003 1327 1328 /* Quatech devices have their own extra interface features */ 1329 static struct pci_device_id quatech_cards[] = { 1330 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1331 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1332 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1333 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1334 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1335 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1336 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1337 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1338 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1339 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1340 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1341 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1342 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1343 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1344 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1345 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1346 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1347 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1348 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1349 { 0, } 1350 }; 1351 1352 static int pci_quatech_rqopr(struct uart_8250_port *port) 1353 { 1354 unsigned long base = port->port.iobase; 1355 u8 LCR, val; 1356 1357 LCR = inb(base + UART_LCR); 1358 outb(0xBF, base + UART_LCR); 1359 val = inb(base + UART_SCR); 1360 outb(LCR, base + UART_LCR); 1361 return val; 1362 } 1363 1364 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1365 { 1366 unsigned long base = port->port.iobase; 1367 u8 LCR; 1368 1369 LCR = inb(base + UART_LCR); 1370 outb(0xBF, base + UART_LCR); 1371 inb(base + UART_SCR); 1372 outb(qopr, base + UART_SCR); 1373 outb(LCR, base + UART_LCR); 1374 } 1375 1376 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1377 { 1378 unsigned long base = port->port.iobase; 1379 u8 LCR, val, qmcr; 1380 1381 LCR = inb(base + UART_LCR); 1382 outb(0xBF, base + UART_LCR); 1383 val = inb(base + UART_SCR); 1384 outb(val | 0x10, base + UART_SCR); 1385 qmcr = inb(base + UART_MCR); 1386 outb(val, base + UART_SCR); 1387 outb(LCR, base + UART_LCR); 1388 1389 return qmcr; 1390 } 1391 1392 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1393 { 1394 unsigned long base = port->port.iobase; 1395 u8 LCR, val; 1396 1397 LCR = inb(base + UART_LCR); 1398 outb(0xBF, base + UART_LCR); 1399 val = inb(base + UART_SCR); 1400 outb(val | 0x10, base + UART_SCR); 1401 outb(qmcr, base + UART_MCR); 1402 outb(val, base + UART_SCR); 1403 outb(LCR, base + UART_LCR); 1404 } 1405 1406 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1407 { 1408 unsigned long base = port->port.iobase; 1409 u8 LCR, val; 1410 1411 LCR = inb(base + UART_LCR); 1412 outb(0xBF, base + UART_LCR); 1413 val = inb(base + UART_SCR); 1414 if (val & 0x20) { 1415 outb(0x80, UART_LCR); 1416 if (!(inb(UART_SCR) & 0x20)) { 1417 outb(LCR, base + UART_LCR); 1418 return 1; 1419 } 1420 } 1421 return 0; 1422 } 1423 1424 static int pci_quatech_test(struct uart_8250_port *port) 1425 { 1426 u8 reg, qopr; 1427 1428 qopr = pci_quatech_rqopr(port); 1429 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1430 reg = pci_quatech_rqopr(port) & 0xC0; 1431 if (reg != QPCR_TEST_GET1) 1432 return -EINVAL; 1433 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1434 reg = pci_quatech_rqopr(port) & 0xC0; 1435 if (reg != QPCR_TEST_GET2) 1436 return -EINVAL; 1437 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1438 reg = pci_quatech_rqopr(port) & 0xC0; 1439 if (reg != QPCR_TEST_GET3) 1440 return -EINVAL; 1441 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1442 reg = pci_quatech_rqopr(port) & 0xC0; 1443 if (reg != QPCR_TEST_GET4) 1444 return -EINVAL; 1445 1446 pci_quatech_wqopr(port, qopr); 1447 return 0; 1448 } 1449 1450 static int pci_quatech_clock(struct uart_8250_port *port) 1451 { 1452 u8 qopr, reg, set; 1453 unsigned long clock; 1454 1455 if (pci_quatech_test(port) < 0) 1456 return 1843200; 1457 1458 qopr = pci_quatech_rqopr(port); 1459 1460 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1461 reg = pci_quatech_rqopr(port); 1462 if (reg & QOPR_CLOCK_X8) { 1463 clock = 1843200; 1464 goto out; 1465 } 1466 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1467 reg = pci_quatech_rqopr(port); 1468 if (!(reg & QOPR_CLOCK_X8)) { 1469 clock = 1843200; 1470 goto out; 1471 } 1472 reg &= QOPR_CLOCK_X8; 1473 if (reg == QOPR_CLOCK_X2) { 1474 clock = 3685400; 1475 set = QOPR_CLOCK_X2; 1476 } else if (reg == QOPR_CLOCK_X4) { 1477 clock = 7372800; 1478 set = QOPR_CLOCK_X4; 1479 } else if (reg == QOPR_CLOCK_X8) { 1480 clock = 14745600; 1481 set = QOPR_CLOCK_X8; 1482 } else { 1483 clock = 1843200; 1484 set = QOPR_CLOCK_X1; 1485 } 1486 qopr &= ~QOPR_CLOCK_RATE_MASK; 1487 qopr |= set; 1488 1489 out: 1490 pci_quatech_wqopr(port, qopr); 1491 return clock; 1492 } 1493 1494 static int pci_quatech_rs422(struct uart_8250_port *port) 1495 { 1496 u8 qmcr; 1497 int rs422 = 0; 1498 1499 if (!pci_quatech_has_qmcr(port)) 1500 return 0; 1501 qmcr = pci_quatech_rqmcr(port); 1502 pci_quatech_wqmcr(port, 0xFF); 1503 if (pci_quatech_rqmcr(port)) 1504 rs422 = 1; 1505 pci_quatech_wqmcr(port, qmcr); 1506 return rs422; 1507 } 1508 1509 static int pci_quatech_init(struct pci_dev *dev) 1510 { 1511 const struct pci_device_id *match; 1512 bool amcc = false; 1513 1514 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1515 return serial_8250_warn_need_ioport(dev); 1516 1517 match = pci_match_id(quatech_cards, dev); 1518 if (match) 1519 amcc = match->driver_data; 1520 else 1521 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1522 1523 if (amcc) { 1524 unsigned long base = pci_resource_start(dev, 0); 1525 if (base) { 1526 u32 tmp; 1527 1528 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1529 tmp = inl(base + 0x3c); 1530 outl(tmp | 0x01000000, base + 0x3c); 1531 outl(tmp & ~0x01000000, base + 0x3c); 1532 } 1533 } 1534 return 0; 1535 } 1536 1537 static int pci_quatech_setup(struct serial_private *priv, 1538 const struct pciserial_board *board, 1539 struct uart_8250_port *port, int idx) 1540 { 1541 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1542 return serial_8250_warn_need_ioport(priv->dev); 1543 1544 /* Needed by pci_quatech calls below */ 1545 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1546 /* Set up the clocking */ 1547 port->port.uartclk = pci_quatech_clock(port); 1548 /* For now just warn about RS422 */ 1549 if (pci_quatech_rs422(port)) 1550 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1551 return pci_default_setup(priv, board, port, idx); 1552 } 1553 1554 static int pci_default_setup(struct serial_private *priv, 1555 const struct pciserial_board *board, 1556 struct uart_8250_port *port, int idx) 1557 { 1558 unsigned int bar, offset = board->first_offset, maxnr; 1559 1560 bar = FL_GET_BASE(board->flags); 1561 if (board->flags & FL_BASE_BARS) 1562 bar += idx; 1563 else 1564 offset += idx * board->uart_offset; 1565 1566 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1567 (board->reg_shift + 3); 1568 1569 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1570 return 1; 1571 1572 return setup_port(priv, port, bar, offset, board->reg_shift); 1573 } 1574 1575 static int 1576 ce4100_serial_setup(struct serial_private *priv, 1577 const struct pciserial_board *board, 1578 struct uart_8250_port *port, int idx) 1579 { 1580 int ret; 1581 1582 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1583 port->port.iotype = UPIO_MEM32; 1584 port->port.type = PORT_XSCALE; 1585 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1586 port->port.regshift = 2; 1587 1588 return ret; 1589 } 1590 1591 static int 1592 pci_omegapci_setup(struct serial_private *priv, 1593 const struct pciserial_board *board, 1594 struct uart_8250_port *port, int idx) 1595 { 1596 return setup_port(priv, port, 2, idx * 8, 0); 1597 } 1598 1599 static int 1600 pci_brcm_trumanage_setup(struct serial_private *priv, 1601 const struct pciserial_board *board, 1602 struct uart_8250_port *port, int idx) 1603 { 1604 int ret = pci_default_setup(priv, board, port, idx); 1605 1606 port->port.type = PORT_BRCM_TRUMANAGE; 1607 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1608 return ret; 1609 } 1610 1611 /* RTS will control by MCR if this bit is 0 */ 1612 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1613 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1614 #define FINTEK_RTS_INVERT BIT(5) 1615 1616 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1617 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1618 struct serial_rs485 *rs485) 1619 { 1620 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1621 u8 setting; 1622 u8 *index = (u8 *) port->private_data; 1623 1624 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1625 1626 if (rs485->flags & SER_RS485_ENABLED) { 1627 /* Enable RTS H/W control mode */ 1628 setting |= FINTEK_RTS_CONTROL_BY_HW; 1629 1630 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1631 /* RTS driving high on TX */ 1632 setting &= ~FINTEK_RTS_INVERT; 1633 } else { 1634 /* RTS driving low on TX */ 1635 setting |= FINTEK_RTS_INVERT; 1636 } 1637 } else { 1638 /* Disable RTS H/W control mode */ 1639 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1640 } 1641 1642 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1643 1644 return 0; 1645 } 1646 1647 static const struct serial_rs485 pci_fintek_rs485_supported = { 1648 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 1649 /* F81504/508/512 does not support RTS delay before or after send */ 1650 }; 1651 1652 static int pci_fintek_setup(struct serial_private *priv, 1653 const struct pciserial_board *board, 1654 struct uart_8250_port *port, int idx) 1655 { 1656 struct pci_dev *pdev = priv->dev; 1657 u8 *data; 1658 u8 config_base; 1659 u16 iobase; 1660 1661 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1662 return serial_8250_warn_need_ioport(pdev); 1663 1664 config_base = 0x40 + 0x08 * idx; 1665 1666 /* Get the io address from configuration space */ 1667 pci_read_config_word(pdev, config_base + 4, &iobase); 1668 1669 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1670 1671 port->port.iotype = UPIO_PORT; 1672 port->port.iobase = iobase; 1673 port->port.rs485_config = pci_fintek_rs485_config; 1674 port->port.rs485_supported = pci_fintek_rs485_supported; 1675 1676 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1677 if (!data) 1678 return -ENOMEM; 1679 1680 /* preserve index in PCI configuration space */ 1681 *data = idx; 1682 port->port.private_data = data; 1683 1684 return 0; 1685 } 1686 1687 static int pci_fintek_init(struct pci_dev *dev) 1688 { 1689 unsigned long iobase; 1690 u32 max_port, i; 1691 resource_size_t bar_data[3]; 1692 u8 config_base; 1693 struct serial_private *priv = pci_get_drvdata(dev); 1694 1695 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1696 return serial_8250_warn_need_ioport(dev); 1697 1698 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1699 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1700 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1701 return -ENODEV; 1702 1703 switch (dev->device) { 1704 case 0x1104: /* 4 ports */ 1705 case 0x1108: /* 8 ports */ 1706 max_port = dev->device & 0xff; 1707 break; 1708 case 0x1112: /* 12 ports */ 1709 max_port = 12; 1710 break; 1711 default: 1712 return -EINVAL; 1713 } 1714 1715 /* Get the io address dispatch from the BIOS */ 1716 bar_data[0] = pci_resource_start(dev, 5); 1717 bar_data[1] = pci_resource_start(dev, 4); 1718 bar_data[2] = pci_resource_start(dev, 3); 1719 1720 for (i = 0; i < max_port; ++i) { 1721 /* UART0 configuration offset start from 0x40 */ 1722 config_base = 0x40 + 0x08 * i; 1723 1724 /* Calculate Real IO Port */ 1725 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1726 1727 /* Enable UART I/O port */ 1728 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1729 1730 /* Select 128-byte FIFO and 8x FIFO threshold */ 1731 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1732 1733 /* LSB UART */ 1734 pci_write_config_byte(dev, config_base + 0x04, 1735 (u8)(iobase & 0xff)); 1736 1737 /* MSB UART */ 1738 pci_write_config_byte(dev, config_base + 0x05, 1739 (u8)((iobase & 0xff00) >> 8)); 1740 1741 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1742 1743 if (!priv) { 1744 /* First init without port data 1745 * force init to RS232 Mode 1746 */ 1747 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1748 } 1749 } 1750 1751 return max_port; 1752 } 1753 1754 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1755 { 1756 struct f815xxa_data *data = p->private_data; 1757 unsigned long flags; 1758 1759 spin_lock_irqsave(&data->lock, flags); 1760 writeb(value, p->membase + offset); 1761 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1762 spin_unlock_irqrestore(&data->lock, flags); 1763 } 1764 1765 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1766 const struct pciserial_board *board, 1767 struct uart_8250_port *port, int idx) 1768 { 1769 struct pci_dev *pdev = priv->dev; 1770 struct f815xxa_data *data; 1771 1772 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1773 if (!data) 1774 return -ENOMEM; 1775 1776 data->idx = idx; 1777 spin_lock_init(&data->lock); 1778 1779 port->port.private_data = data; 1780 port->port.iotype = UPIO_MEM; 1781 port->port.flags |= UPF_IOREMAP; 1782 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1783 port->port.serial_out = f815xxa_mem_serial_out; 1784 1785 return 0; 1786 } 1787 1788 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1789 { 1790 u32 max_port, i; 1791 int config_base; 1792 1793 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1794 return -ENODEV; 1795 1796 switch (dev->device) { 1797 case 0x1204: /* 4 ports */ 1798 case 0x1208: /* 8 ports */ 1799 max_port = dev->device & 0xff; 1800 break; 1801 case 0x1212: /* 12 ports */ 1802 max_port = 12; 1803 break; 1804 default: 1805 return -EINVAL; 1806 } 1807 1808 /* Set to mmio decode */ 1809 pci_write_config_byte(dev, 0x209, 0x40); 1810 1811 for (i = 0; i < max_port; ++i) { 1812 /* UART0 configuration offset start from 0x2A0 */ 1813 config_base = 0x2A0 + 0x08 * i; 1814 1815 /* Select 128-byte FIFO and 8x FIFO threshold */ 1816 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1817 1818 /* Enable UART I/O port */ 1819 pci_write_config_byte(dev, config_base + 0, 0x01); 1820 } 1821 1822 return max_port; 1823 } 1824 1825 static int skip_tx_en_setup(struct serial_private *priv, 1826 const struct pciserial_board *board, 1827 struct uart_8250_port *port, int idx) 1828 { 1829 port->port.quirks |= UPQ_NO_TXEN_TEST; 1830 pci_dbg(priv->dev, 1831 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1832 priv->dev->vendor, priv->dev->device, 1833 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1834 1835 return pci_default_setup(priv, board, port, idx); 1836 } 1837 1838 static void kt_handle_break(struct uart_port *p) 1839 { 1840 struct uart_8250_port *up = up_to_u8250p(p); 1841 /* 1842 * On receipt of a BI, serial device in Intel ME (Intel 1843 * management engine) needs to have its fifos cleared for sane 1844 * SOL (Serial Over Lan) output. 1845 */ 1846 serial8250_clear_and_reinit_fifos(up); 1847 } 1848 1849 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1850 { 1851 struct uart_8250_port *up = up_to_u8250p(p); 1852 unsigned int val; 1853 1854 /* 1855 * When the Intel ME (management engine) gets reset its serial 1856 * port registers could return 0 momentarily. Functions like 1857 * serial8250_console_write, read and save the IER, perform 1858 * some operation and then restore it. In order to avoid 1859 * setting IER register inadvertently to 0, if the value read 1860 * is 0, double check with ier value in uart_8250_port and use 1861 * that instead. up->ier should be the same value as what is 1862 * currently configured. 1863 */ 1864 val = inb(p->iobase + offset); 1865 if (offset == UART_IER) { 1866 if (val == 0) 1867 val = up->ier; 1868 } 1869 return val; 1870 } 1871 1872 static int kt_serial_setup(struct serial_private *priv, 1873 const struct pciserial_board *board, 1874 struct uart_8250_port *port, int idx) 1875 { 1876 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1877 return serial_8250_warn_need_ioport(priv->dev); 1878 1879 port->port.flags |= UPF_BUG_THRE; 1880 port->port.serial_in = kt_serial_in; 1881 port->port.handle_break = kt_handle_break; 1882 return skip_tx_en_setup(priv, board, port, idx); 1883 } 1884 1885 static int pci_eg20t_init(struct pci_dev *dev) 1886 { 1887 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1888 return -ENODEV; 1889 #else 1890 return 0; 1891 #endif 1892 } 1893 1894 static int 1895 pci_wch_ch353_setup(struct serial_private *priv, 1896 const struct pciserial_board *board, 1897 struct uart_8250_port *port, int idx) 1898 { 1899 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1900 return serial_8250_warn_need_ioport(priv->dev); 1901 1902 port->port.flags |= UPF_FIXED_TYPE; 1903 port->port.type = PORT_16550A; 1904 return pci_default_setup(priv, board, port, idx); 1905 } 1906 1907 static int 1908 pci_wch_ch355_setup(struct serial_private *priv, 1909 const struct pciserial_board *board, 1910 struct uart_8250_port *port, int idx) 1911 { 1912 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1913 return serial_8250_warn_need_ioport(priv->dev); 1914 1915 port->port.flags |= UPF_FIXED_TYPE; 1916 port->port.type = PORT_16550A; 1917 return pci_default_setup(priv, board, port, idx); 1918 } 1919 1920 static int 1921 pci_wch_ch38x_setup(struct serial_private *priv, 1922 const struct pciserial_board *board, 1923 struct uart_8250_port *port, int idx) 1924 { 1925 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1926 return serial_8250_warn_need_ioport(priv->dev); 1927 1928 port->port.flags |= UPF_FIXED_TYPE; 1929 port->port.type = PORT_16850; 1930 return pci_default_setup(priv, board, port, idx); 1931 } 1932 1933 1934 #define CH384_XINT_ENABLE_REG 0xEB 1935 #define CH384_XINT_ENABLE_BIT 0x02 1936 1937 static int pci_wch_ch38x_init(struct pci_dev *dev) 1938 { 1939 int max_port; 1940 unsigned long iobase; 1941 1942 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1943 return serial_8250_warn_need_ioport(dev); 1944 1945 switch (dev->device) { 1946 case 0x3853: /* 8 ports */ 1947 max_port = 8; 1948 break; 1949 default: 1950 return -EINVAL; 1951 } 1952 1953 iobase = pci_resource_start(dev, 0); 1954 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1955 1956 return max_port; 1957 } 1958 1959 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1960 { 1961 unsigned long iobase; 1962 1963 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) { 1964 serial_8250_warn_need_ioport(dev); 1965 return; 1966 } 1967 1968 iobase = pci_resource_start(dev, 0); 1969 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1970 } 1971 1972 1973 static int 1974 pci_sunix_setup(struct serial_private *priv, 1975 const struct pciserial_board *board, 1976 struct uart_8250_port *port, int idx) 1977 { 1978 int bar; 1979 int offset; 1980 1981 port->port.flags |= UPF_FIXED_TYPE; 1982 port->port.type = PORT_SUNIX; 1983 1984 if (idx < 4) { 1985 bar = 0; 1986 offset = idx * board->uart_offset; 1987 } else { 1988 bar = 1; 1989 idx -= 4; 1990 idx = div_s64_rem(idx, 4, &offset); 1991 offset = idx * 64 + offset * board->uart_offset; 1992 } 1993 1994 return setup_port(priv, port, bar, offset, 0); 1995 } 1996 1997 #define MOXA_PUART_GPIO_EN 0x09 1998 #define MOXA_PUART_GPIO_OUT 0x0A 1999 2000 #define MOXA_GPIO_PIN2 BIT(2) 2001 2002 #define MOXA_RS232 0x00 2003 #define MOXA_RS422 0x01 2004 #define MOXA_RS485_4W 0x0B 2005 #define MOXA_RS485_2W 0x0F 2006 #define MOXA_UIR_OFFSET 0x04 2007 #define MOXA_EVEN_RS_MASK GENMASK(3, 0) 2008 #define MOXA_ODD_RS_MASK GENMASK(7, 4) 2009 2010 enum { 2011 MOXA_SUPP_RS232 = BIT(0), 2012 MOXA_SUPP_RS422 = BIT(1), 2013 MOXA_SUPP_RS485 = BIT(2), 2014 }; 2015 2016 static unsigned short moxa_get_nports(unsigned short device) 2017 { 2018 switch (device) { 2019 case PCI_DEVICE_ID_MOXA_CP116E_A_A: 2020 case PCI_DEVICE_ID_MOXA_CP116E_A_B: 2021 return 8; 2022 } 2023 2024 return FIELD_GET(0x00F0, device); 2025 } 2026 2027 static bool pci_moxa_is_mini_pcie(unsigned short device) 2028 { 2029 if (device == PCI_DEVICE_ID_MOXA_CP102N || 2030 device == PCI_DEVICE_ID_MOXA_CP104N || 2031 device == PCI_DEVICE_ID_MOXA_CP112N || 2032 device == PCI_DEVICE_ID_MOXA_CP114N || 2033 device == PCI_DEVICE_ID_MOXA_CP132N || 2034 device == PCI_DEVICE_ID_MOXA_CP134N) 2035 return true; 2036 2037 return false; 2038 } 2039 2040 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev) 2041 { 2042 switch (dev->device & 0x0F00) { 2043 case 0x0000: 2044 case 0x0600: 2045 return MOXA_SUPP_RS232; 2046 case 0x0100: 2047 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 2048 case 0x0300: 2049 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 2050 } 2051 return 0; 2052 } 2053 2054 static int pci_moxa_set_interface(const struct pci_dev *dev, 2055 unsigned int port_idx, 2056 u8 mode) 2057 { 2058 resource_size_t iobar_addr = pci_resource_start(dev, 2); 2059 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2; 2060 u8 val; 2061 2062 val = inb(UIR_addr); 2063 2064 if (port_idx % 2) { 2065 val &= ~MOXA_ODD_RS_MASK; 2066 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode); 2067 } else { 2068 val &= ~MOXA_EVEN_RS_MASK; 2069 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode); 2070 } 2071 outb(val, UIR_addr); 2072 2073 return 0; 2074 } 2075 2076 static int pci_moxa_init(struct pci_dev *dev) 2077 { 2078 unsigned short device = dev->device; 2079 resource_size_t iobar_addr = pci_resource_start(dev, 2); 2080 unsigned int i, num_ports = moxa_get_nports(device); 2081 u8 val, init_mode = MOXA_RS232; 2082 2083 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 2084 return serial_8250_warn_need_ioport(dev); 2085 2086 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) { 2087 init_mode = MOXA_RS422; 2088 } 2089 for (i = 0; i < num_ports; ++i) 2090 pci_moxa_set_interface(dev, i, init_mode); 2091 2092 /* 2093 * Enable hardware buffer to prevent break signal output when system boots up. 2094 * This hardware buffer is only supported on Mini PCIe series. 2095 */ 2096 if (pci_moxa_is_mini_pcie(device)) { 2097 /* Set GPIO direction */ 2098 val = inb(iobar_addr + MOXA_PUART_GPIO_EN); 2099 val |= MOXA_GPIO_PIN2; 2100 outb(val, iobar_addr + MOXA_PUART_GPIO_EN); 2101 /* Enable low GPIO */ 2102 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT); 2103 val &= ~MOXA_GPIO_PIN2; 2104 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT); 2105 } 2106 2107 return num_ports; 2108 } 2109 2110 static int 2111 pci_moxa_setup(struct serial_private *priv, 2112 const struct pciserial_board *board, 2113 struct uart_8250_port *port, int idx) 2114 { 2115 unsigned int bar = FL_GET_BASE(board->flags); 2116 int offset; 2117 2118 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 2119 return serial_8250_warn_need_ioport(priv->dev); 2120 2121 if (board->num_ports == 4 && idx == 3) 2122 offset = 7 * board->uart_offset; 2123 else 2124 offset = idx * board->uart_offset; 2125 2126 return setup_port(priv, port, bar, offset, 0); 2127 } 2128 2129 /* 2130 * Master list of serial port init/setup/exit quirks. 2131 * This does not describe the general nature of the port. 2132 * (ie, baud base, number and location of ports, etc) 2133 * 2134 * This list is ordered alphabetically by vendor then device. 2135 * Specific entries must come before more generic entries. 2136 */ 2137 static struct pci_serial_quirk pci_serial_quirks[] = { 2138 /* 2139 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2140 */ 2141 { 2142 .vendor = PCI_VENDOR_ID_AMCC, 2143 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2144 .subvendor = PCI_ANY_ID, 2145 .subdevice = PCI_ANY_ID, 2146 .setup = addidata_apci7800_setup, 2147 }, 2148 /* 2149 * AFAVLAB cards - these may be called via parport_serial 2150 * It is not clear whether this applies to all products. 2151 */ 2152 { 2153 .vendor = PCI_VENDOR_ID_AFAVLAB, 2154 .device = PCI_ANY_ID, 2155 .subvendor = PCI_ANY_ID, 2156 .subdevice = PCI_ANY_ID, 2157 .setup = afavlab_setup, 2158 }, 2159 /* 2160 * HP Diva 2161 */ 2162 { 2163 .vendor = PCI_VENDOR_ID_HP, 2164 .device = PCI_DEVICE_ID_HP_DIVA, 2165 .subvendor = PCI_ANY_ID, 2166 .subdevice = PCI_ANY_ID, 2167 .init = pci_hp_diva_init, 2168 .setup = pci_hp_diva_setup, 2169 }, 2170 /* 2171 * HPE PCI serial device 2172 */ 2173 { 2174 .vendor = PCI_VENDOR_ID_HP_3PAR, 2175 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2176 .subvendor = PCI_ANY_ID, 2177 .subdevice = PCI_ANY_ID, 2178 .setup = pci_hp_diva_setup, 2179 }, 2180 /* 2181 * Intel 2182 */ 2183 { 2184 .vendor = PCI_VENDOR_ID_INTEL, 2185 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2186 .subvendor = 0xe4bf, 2187 .subdevice = PCI_ANY_ID, 2188 .init = pci_inteli960ni_init, 2189 .setup = pci_default_setup, 2190 }, 2191 { 2192 .vendor = PCI_VENDOR_ID_INTEL, 2193 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2194 .subvendor = PCI_ANY_ID, 2195 .subdevice = PCI_ANY_ID, 2196 .setup = skip_tx_en_setup, 2197 }, 2198 { 2199 .vendor = PCI_VENDOR_ID_INTEL, 2200 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2201 .subvendor = PCI_ANY_ID, 2202 .subdevice = PCI_ANY_ID, 2203 .setup = skip_tx_en_setup, 2204 }, 2205 { 2206 .vendor = PCI_VENDOR_ID_INTEL, 2207 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2208 .subvendor = PCI_ANY_ID, 2209 .subdevice = PCI_ANY_ID, 2210 .setup = skip_tx_en_setup, 2211 }, 2212 { 2213 .vendor = PCI_VENDOR_ID_INTEL, 2214 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2215 .subvendor = PCI_ANY_ID, 2216 .subdevice = PCI_ANY_ID, 2217 .setup = ce4100_serial_setup, 2218 }, 2219 { 2220 .vendor = PCI_VENDOR_ID_INTEL, 2221 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2222 .subvendor = PCI_ANY_ID, 2223 .subdevice = PCI_ANY_ID, 2224 .setup = kt_serial_setup, 2225 }, 2226 /* 2227 * ITE 2228 */ 2229 { 2230 .vendor = PCI_VENDOR_ID_ITE, 2231 .device = PCI_DEVICE_ID_ITE_8872, 2232 .subvendor = PCI_ANY_ID, 2233 .subdevice = PCI_ANY_ID, 2234 .init = pci_ite887x_init, 2235 .setup = pci_default_setup, 2236 .exit = pci_ite887x_exit, 2237 }, 2238 /* 2239 * National Instruments 2240 */ 2241 { 2242 .vendor = PCI_VENDOR_ID_NI, 2243 .device = PCI_DEVICE_ID_NI_PCI23216, 2244 .subvendor = PCI_ANY_ID, 2245 .subdevice = PCI_ANY_ID, 2246 .init = pci_ni8420_init, 2247 .setup = pci_default_setup, 2248 .exit = pci_ni8420_exit, 2249 }, 2250 { 2251 .vendor = PCI_VENDOR_ID_NI, 2252 .device = PCI_DEVICE_ID_NI_PCI2328, 2253 .subvendor = PCI_ANY_ID, 2254 .subdevice = PCI_ANY_ID, 2255 .init = pci_ni8420_init, 2256 .setup = pci_default_setup, 2257 .exit = pci_ni8420_exit, 2258 }, 2259 { 2260 .vendor = PCI_VENDOR_ID_NI, 2261 .device = PCI_DEVICE_ID_NI_PCI2324, 2262 .subvendor = PCI_ANY_ID, 2263 .subdevice = PCI_ANY_ID, 2264 .init = pci_ni8420_init, 2265 .setup = pci_default_setup, 2266 .exit = pci_ni8420_exit, 2267 }, 2268 { 2269 .vendor = PCI_VENDOR_ID_NI, 2270 .device = PCI_DEVICE_ID_NI_PCI2322, 2271 .subvendor = PCI_ANY_ID, 2272 .subdevice = PCI_ANY_ID, 2273 .init = pci_ni8420_init, 2274 .setup = pci_default_setup, 2275 .exit = pci_ni8420_exit, 2276 }, 2277 { 2278 .vendor = PCI_VENDOR_ID_NI, 2279 .device = PCI_DEVICE_ID_NI_PCI2324I, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .init = pci_ni8420_init, 2283 .setup = pci_default_setup, 2284 .exit = pci_ni8420_exit, 2285 }, 2286 { 2287 .vendor = PCI_VENDOR_ID_NI, 2288 .device = PCI_DEVICE_ID_NI_PCI2322I, 2289 .subvendor = PCI_ANY_ID, 2290 .subdevice = PCI_ANY_ID, 2291 .init = pci_ni8420_init, 2292 .setup = pci_default_setup, 2293 .exit = pci_ni8420_exit, 2294 }, 2295 { 2296 .vendor = PCI_VENDOR_ID_NI, 2297 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2298 .subvendor = PCI_ANY_ID, 2299 .subdevice = PCI_ANY_ID, 2300 .init = pci_ni8420_init, 2301 .setup = pci_default_setup, 2302 .exit = pci_ni8420_exit, 2303 }, 2304 { 2305 .vendor = PCI_VENDOR_ID_NI, 2306 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2307 .subvendor = PCI_ANY_ID, 2308 .subdevice = PCI_ANY_ID, 2309 .init = pci_ni8420_init, 2310 .setup = pci_default_setup, 2311 .exit = pci_ni8420_exit, 2312 }, 2313 { 2314 .vendor = PCI_VENDOR_ID_NI, 2315 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2316 .subvendor = PCI_ANY_ID, 2317 .subdevice = PCI_ANY_ID, 2318 .init = pci_ni8420_init, 2319 .setup = pci_default_setup, 2320 .exit = pci_ni8420_exit, 2321 }, 2322 { 2323 .vendor = PCI_VENDOR_ID_NI, 2324 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2325 .subvendor = PCI_ANY_ID, 2326 .subdevice = PCI_ANY_ID, 2327 .init = pci_ni8420_init, 2328 .setup = pci_default_setup, 2329 .exit = pci_ni8420_exit, 2330 }, 2331 { 2332 .vendor = PCI_VENDOR_ID_NI, 2333 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2334 .subvendor = PCI_ANY_ID, 2335 .subdevice = PCI_ANY_ID, 2336 .init = pci_ni8420_init, 2337 .setup = pci_default_setup, 2338 .exit = pci_ni8420_exit, 2339 }, 2340 { 2341 .vendor = PCI_VENDOR_ID_NI, 2342 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2343 .subvendor = PCI_ANY_ID, 2344 .subdevice = PCI_ANY_ID, 2345 .init = pci_ni8420_init, 2346 .setup = pci_default_setup, 2347 .exit = pci_ni8420_exit, 2348 }, 2349 { 2350 .vendor = PCI_VENDOR_ID_NI, 2351 .device = PCI_ANY_ID, 2352 .subvendor = PCI_ANY_ID, 2353 .subdevice = PCI_ANY_ID, 2354 .init = pci_ni8430_init, 2355 .setup = pci_ni8430_setup, 2356 .exit = pci_ni8430_exit, 2357 }, 2358 /* Quatech */ 2359 { 2360 .vendor = PCI_VENDOR_ID_QUATECH, 2361 .device = PCI_ANY_ID, 2362 .subvendor = PCI_ANY_ID, 2363 .subdevice = PCI_ANY_ID, 2364 .init = pci_quatech_init, 2365 .setup = pci_quatech_setup, 2366 }, 2367 /* 2368 * Panacom 2369 */ 2370 { 2371 .vendor = PCI_VENDOR_ID_PANACOM, 2372 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2373 .subvendor = PCI_ANY_ID, 2374 .subdevice = PCI_ANY_ID, 2375 .init = pci_plx9050_init, 2376 .setup = pci_default_setup, 2377 .exit = pci_plx9050_exit, 2378 }, 2379 { 2380 .vendor = PCI_VENDOR_ID_PANACOM, 2381 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2382 .subvendor = PCI_ANY_ID, 2383 .subdevice = PCI_ANY_ID, 2384 .init = pci_plx9050_init, 2385 .setup = pci_default_setup, 2386 .exit = pci_plx9050_exit, 2387 }, 2388 /* 2389 * PLX 2390 */ 2391 { 2392 .vendor = PCI_VENDOR_ID_PLX, 2393 .device = PCI_DEVICE_ID_PLX_9050, 2394 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2395 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2396 .init = pci_plx9050_init, 2397 .setup = pci_default_setup, 2398 .exit = pci_plx9050_exit, 2399 }, 2400 { 2401 .vendor = PCI_VENDOR_ID_PLX, 2402 .device = PCI_DEVICE_ID_PLX_9050, 2403 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2404 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2405 .init = pci_plx9050_init, 2406 .setup = pci_default_setup, 2407 .exit = pci_plx9050_exit, 2408 }, 2409 { 2410 .vendor = PCI_VENDOR_ID_PLX, 2411 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2412 .subvendor = PCI_VENDOR_ID_PLX, 2413 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2414 .init = pci_plx9050_init, 2415 .setup = pci_default_setup, 2416 .exit = pci_plx9050_exit, 2417 }, 2418 /* 2419 * SBS Technologies, Inc., PMC-OCTALPRO 232 2420 */ 2421 { 2422 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2423 .device = PCI_DEVICE_ID_OCTPRO, 2424 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2425 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2426 .init = sbs_init, 2427 .setup = sbs_setup, 2428 .exit = sbs_exit, 2429 }, 2430 /* 2431 * SBS Technologies, Inc., PMC-OCTALPRO 422 2432 */ 2433 { 2434 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2435 .device = PCI_DEVICE_ID_OCTPRO, 2436 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2437 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2438 .init = sbs_init, 2439 .setup = sbs_setup, 2440 .exit = sbs_exit, 2441 }, 2442 /* 2443 * SBS Technologies, Inc., P-Octal 232 2444 */ 2445 { 2446 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2447 .device = PCI_DEVICE_ID_OCTPRO, 2448 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2449 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2450 .init = sbs_init, 2451 .setup = sbs_setup, 2452 .exit = sbs_exit, 2453 }, 2454 /* 2455 * SBS Technologies, Inc., P-Octal 422 2456 */ 2457 { 2458 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2459 .device = PCI_DEVICE_ID_OCTPRO, 2460 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2461 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2462 .init = sbs_init, 2463 .setup = sbs_setup, 2464 .exit = sbs_exit, 2465 }, 2466 /* 2467 * SIIG cards - these may be called via parport_serial 2468 */ 2469 { 2470 .vendor = PCI_VENDOR_ID_SIIG, 2471 .device = PCI_ANY_ID, 2472 .subvendor = PCI_ANY_ID, 2473 .subdevice = PCI_ANY_ID, 2474 .init = pci_siig_init, 2475 .setup = pci_siig_setup, 2476 }, 2477 /* 2478 * Titan cards 2479 */ 2480 { 2481 .vendor = PCI_VENDOR_ID_TITAN, 2482 .device = PCI_DEVICE_ID_TITAN_400L, 2483 .subvendor = PCI_ANY_ID, 2484 .subdevice = PCI_ANY_ID, 2485 .setup = titan_400l_800l_setup, 2486 }, 2487 { 2488 .vendor = PCI_VENDOR_ID_TITAN, 2489 .device = PCI_DEVICE_ID_TITAN_800L, 2490 .subvendor = PCI_ANY_ID, 2491 .subdevice = PCI_ANY_ID, 2492 .setup = titan_400l_800l_setup, 2493 }, 2494 /* 2495 * Timedia cards 2496 */ 2497 { 2498 .vendor = PCI_VENDOR_ID_TIMEDIA, 2499 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2500 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2501 .subdevice = PCI_ANY_ID, 2502 .probe = pci_timedia_probe, 2503 .init = pci_timedia_init, 2504 .setup = pci_timedia_setup, 2505 }, 2506 { 2507 .vendor = PCI_VENDOR_ID_TIMEDIA, 2508 .device = PCI_ANY_ID, 2509 .subvendor = PCI_ANY_ID, 2510 .subdevice = PCI_ANY_ID, 2511 .setup = pci_timedia_setup, 2512 }, 2513 /* 2514 * Sunix PCI serial boards 2515 */ 2516 { 2517 .vendor = PCI_VENDOR_ID_SUNIX, 2518 .device = PCI_DEVICE_ID_SUNIX_1999, 2519 .subvendor = PCI_VENDOR_ID_SUNIX, 2520 .subdevice = PCI_ANY_ID, 2521 .setup = pci_sunix_setup, 2522 }, 2523 /* 2524 * Xircom cards 2525 */ 2526 { 2527 .vendor = PCI_VENDOR_ID_XIRCOM, 2528 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2529 .subvendor = PCI_ANY_ID, 2530 .subdevice = PCI_ANY_ID, 2531 .init = pci_xircom_init, 2532 .setup = pci_default_setup, 2533 }, 2534 /* 2535 * Netmos cards - these may be called via parport_serial 2536 */ 2537 { 2538 .vendor = PCI_VENDOR_ID_NETMOS, 2539 .device = PCI_ANY_ID, 2540 .subvendor = PCI_ANY_ID, 2541 .subdevice = PCI_ANY_ID, 2542 .init = pci_netmos_init, 2543 .setup = pci_netmos_9900_setup, 2544 }, 2545 /* 2546 * EndRun Technologies 2547 */ 2548 { 2549 .vendor = PCI_VENDOR_ID_ENDRUN, 2550 .device = PCI_ANY_ID, 2551 .subvendor = PCI_ANY_ID, 2552 .subdevice = PCI_ANY_ID, 2553 .init = pci_oxsemi_tornado_init, 2554 .setup = pci_default_setup, 2555 }, 2556 /* 2557 * For Oxford Semiconductor Tornado based devices 2558 */ 2559 { 2560 .vendor = PCI_VENDOR_ID_OXSEMI, 2561 .device = PCI_ANY_ID, 2562 .subvendor = PCI_ANY_ID, 2563 .subdevice = PCI_ANY_ID, 2564 .init = pci_oxsemi_tornado_init, 2565 .setup = pci_oxsemi_tornado_setup, 2566 }, 2567 { 2568 .vendor = PCI_VENDOR_ID_MAINPINE, 2569 .device = PCI_ANY_ID, 2570 .subvendor = PCI_ANY_ID, 2571 .subdevice = PCI_ANY_ID, 2572 .init = pci_oxsemi_tornado_init, 2573 .setup = pci_oxsemi_tornado_setup, 2574 }, 2575 { 2576 .vendor = PCI_VENDOR_ID_DIGI, 2577 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2578 .subvendor = PCI_SUBVENDOR_ID_IBM, 2579 .subdevice = PCI_ANY_ID, 2580 .init = pci_oxsemi_tornado_init, 2581 .setup = pci_oxsemi_tornado_setup, 2582 }, 2583 /* 2584 * Brainboxes devices - all Oxsemi based 2585 */ 2586 { 2587 .vendor = PCI_VENDOR_ID_INTASHIELD, 2588 .device = 0x4027, 2589 .subvendor = PCI_ANY_ID, 2590 .subdevice = PCI_ANY_ID, 2591 .init = pci_oxsemi_tornado_init, 2592 .setup = pci_oxsemi_tornado_setup, 2593 }, 2594 { 2595 .vendor = PCI_VENDOR_ID_INTASHIELD, 2596 .device = 0x4028, 2597 .subvendor = PCI_ANY_ID, 2598 .subdevice = PCI_ANY_ID, 2599 .init = pci_oxsemi_tornado_init, 2600 .setup = pci_oxsemi_tornado_setup, 2601 }, 2602 { 2603 .vendor = PCI_VENDOR_ID_INTASHIELD, 2604 .device = 0x4029, 2605 .subvendor = PCI_ANY_ID, 2606 .subdevice = PCI_ANY_ID, 2607 .init = pci_oxsemi_tornado_init, 2608 .setup = pci_oxsemi_tornado_setup, 2609 }, 2610 { 2611 .vendor = PCI_VENDOR_ID_INTASHIELD, 2612 .device = 0x4019, 2613 .subvendor = PCI_ANY_ID, 2614 .subdevice = PCI_ANY_ID, 2615 .init = pci_oxsemi_tornado_init, 2616 .setup = pci_oxsemi_tornado_setup, 2617 }, 2618 { 2619 .vendor = PCI_VENDOR_ID_INTASHIELD, 2620 .device = 0x4016, 2621 .subvendor = PCI_ANY_ID, 2622 .subdevice = PCI_ANY_ID, 2623 .init = pci_oxsemi_tornado_init, 2624 .setup = pci_oxsemi_tornado_setup, 2625 }, 2626 { 2627 .vendor = PCI_VENDOR_ID_INTASHIELD, 2628 .device = 0x4015, 2629 .subvendor = PCI_ANY_ID, 2630 .subdevice = PCI_ANY_ID, 2631 .init = pci_oxsemi_tornado_init, 2632 .setup = pci_oxsemi_tornado_setup, 2633 }, 2634 { 2635 .vendor = PCI_VENDOR_ID_INTASHIELD, 2636 .device = 0x400A, 2637 .subvendor = PCI_ANY_ID, 2638 .subdevice = PCI_ANY_ID, 2639 .init = pci_oxsemi_tornado_init, 2640 .setup = pci_oxsemi_tornado_setup, 2641 }, 2642 { 2643 .vendor = PCI_VENDOR_ID_INTASHIELD, 2644 .device = 0x400E, 2645 .subvendor = PCI_ANY_ID, 2646 .subdevice = PCI_ANY_ID, 2647 .init = pci_oxsemi_tornado_init, 2648 .setup = pci_oxsemi_tornado_setup, 2649 }, 2650 { 2651 .vendor = PCI_VENDOR_ID_INTASHIELD, 2652 .device = 0x400C, 2653 .subvendor = PCI_ANY_ID, 2654 .subdevice = PCI_ANY_ID, 2655 .init = pci_oxsemi_tornado_init, 2656 .setup = pci_oxsemi_tornado_setup, 2657 }, 2658 { 2659 .vendor = PCI_VENDOR_ID_INTASHIELD, 2660 .device = 0x400B, 2661 .subvendor = PCI_ANY_ID, 2662 .subdevice = PCI_ANY_ID, 2663 .init = pci_oxsemi_tornado_init, 2664 .setup = pci_oxsemi_tornado_setup, 2665 }, 2666 { 2667 .vendor = PCI_VENDOR_ID_INTASHIELD, 2668 .device = 0x400F, 2669 .subvendor = PCI_ANY_ID, 2670 .subdevice = PCI_ANY_ID, 2671 .init = pci_oxsemi_tornado_init, 2672 .setup = pci_oxsemi_tornado_setup, 2673 }, 2674 { 2675 .vendor = PCI_VENDOR_ID_INTASHIELD, 2676 .device = 0x4010, 2677 .subvendor = PCI_ANY_ID, 2678 .subdevice = PCI_ANY_ID, 2679 .init = pci_oxsemi_tornado_init, 2680 .setup = pci_oxsemi_tornado_setup, 2681 }, 2682 { 2683 .vendor = PCI_VENDOR_ID_INTASHIELD, 2684 .device = 0x4011, 2685 .subvendor = PCI_ANY_ID, 2686 .subdevice = PCI_ANY_ID, 2687 .init = pci_oxsemi_tornado_init, 2688 .setup = pci_oxsemi_tornado_setup, 2689 }, 2690 { 2691 .vendor = PCI_VENDOR_ID_INTASHIELD, 2692 .device = 0x401D, 2693 .subvendor = PCI_ANY_ID, 2694 .subdevice = PCI_ANY_ID, 2695 .init = pci_oxsemi_tornado_init, 2696 .setup = pci_oxsemi_tornado_setup, 2697 }, 2698 { 2699 .vendor = PCI_VENDOR_ID_INTASHIELD, 2700 .device = 0x401E, 2701 .subvendor = PCI_ANY_ID, 2702 .subdevice = PCI_ANY_ID, 2703 .init = pci_oxsemi_tornado_init, 2704 .setup = pci_oxsemi_tornado_setup, 2705 }, 2706 { 2707 .vendor = PCI_VENDOR_ID_INTASHIELD, 2708 .device = 0x4013, 2709 .subvendor = PCI_ANY_ID, 2710 .subdevice = PCI_ANY_ID, 2711 .init = pci_oxsemi_tornado_init, 2712 .setup = pci_oxsemi_tornado_setup, 2713 }, 2714 { 2715 .vendor = PCI_VENDOR_ID_INTASHIELD, 2716 .device = 0x4017, 2717 .subvendor = PCI_ANY_ID, 2718 .subdevice = PCI_ANY_ID, 2719 .init = pci_oxsemi_tornado_init, 2720 .setup = pci_oxsemi_tornado_setup, 2721 }, 2722 { 2723 .vendor = PCI_VENDOR_ID_INTASHIELD, 2724 .device = 0x4018, 2725 .subvendor = PCI_ANY_ID, 2726 .subdevice = PCI_ANY_ID, 2727 .init = pci_oxsemi_tornado_init, 2728 .setup = pci_oxsemi_tornado_setup, 2729 }, 2730 { 2731 .vendor = PCI_VENDOR_ID_INTEL, 2732 .device = 0x8811, 2733 .subvendor = PCI_ANY_ID, 2734 .subdevice = PCI_ANY_ID, 2735 .init = pci_eg20t_init, 2736 .setup = pci_default_setup, 2737 }, 2738 { 2739 .vendor = PCI_VENDOR_ID_INTEL, 2740 .device = 0x8812, 2741 .subvendor = PCI_ANY_ID, 2742 .subdevice = PCI_ANY_ID, 2743 .init = pci_eg20t_init, 2744 .setup = pci_default_setup, 2745 }, 2746 { 2747 .vendor = PCI_VENDOR_ID_INTEL, 2748 .device = 0x8813, 2749 .subvendor = PCI_ANY_ID, 2750 .subdevice = PCI_ANY_ID, 2751 .init = pci_eg20t_init, 2752 .setup = pci_default_setup, 2753 }, 2754 { 2755 .vendor = PCI_VENDOR_ID_INTEL, 2756 .device = 0x8814, 2757 .subvendor = PCI_ANY_ID, 2758 .subdevice = PCI_ANY_ID, 2759 .init = pci_eg20t_init, 2760 .setup = pci_default_setup, 2761 }, 2762 { 2763 .vendor = 0x10DB, 2764 .device = 0x8027, 2765 .subvendor = PCI_ANY_ID, 2766 .subdevice = PCI_ANY_ID, 2767 .init = pci_eg20t_init, 2768 .setup = pci_default_setup, 2769 }, 2770 { 2771 .vendor = 0x10DB, 2772 .device = 0x8028, 2773 .subvendor = PCI_ANY_ID, 2774 .subdevice = PCI_ANY_ID, 2775 .init = pci_eg20t_init, 2776 .setup = pci_default_setup, 2777 }, 2778 { 2779 .vendor = 0x10DB, 2780 .device = 0x8029, 2781 .subvendor = PCI_ANY_ID, 2782 .subdevice = PCI_ANY_ID, 2783 .init = pci_eg20t_init, 2784 .setup = pci_default_setup, 2785 }, 2786 { 2787 .vendor = 0x10DB, 2788 .device = 0x800C, 2789 .subvendor = PCI_ANY_ID, 2790 .subdevice = PCI_ANY_ID, 2791 .init = pci_eg20t_init, 2792 .setup = pci_default_setup, 2793 }, 2794 { 2795 .vendor = 0x10DB, 2796 .device = 0x800D, 2797 .subvendor = PCI_ANY_ID, 2798 .subdevice = PCI_ANY_ID, 2799 .init = pci_eg20t_init, 2800 .setup = pci_default_setup, 2801 }, 2802 /* 2803 * Cronyx Omega PCI (PLX-chip based) 2804 */ 2805 { 2806 .vendor = PCI_VENDOR_ID_PLX, 2807 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2808 .subvendor = PCI_ANY_ID, 2809 .subdevice = PCI_ANY_ID, 2810 .setup = pci_omegapci_setup, 2811 }, 2812 /* WCH CH353 1S1P card (16550 clone) */ 2813 { 2814 .vendor = PCI_VENDOR_ID_WCHCN, 2815 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P, 2816 .subvendor = PCI_ANY_ID, 2817 .subdevice = PCI_ANY_ID, 2818 .setup = pci_wch_ch353_setup, 2819 }, 2820 /* WCH CH353 2S1P card (16550 clone) */ 2821 { 2822 .vendor = PCI_VENDOR_ID_WCHCN, 2823 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P, 2824 .subvendor = PCI_ANY_ID, 2825 .subdevice = PCI_ANY_ID, 2826 .setup = pci_wch_ch353_setup, 2827 }, 2828 /* WCH CH353 4S card (16550 clone) */ 2829 { 2830 .vendor = PCI_VENDOR_ID_WCHCN, 2831 .device = PCI_DEVICE_ID_WCHCN_CH353_4S, 2832 .subvendor = PCI_ANY_ID, 2833 .subdevice = PCI_ANY_ID, 2834 .setup = pci_wch_ch353_setup, 2835 }, 2836 /* WCH CH353 2S1PF card (16550 clone) */ 2837 { 2838 .vendor = PCI_VENDOR_ID_WCHCN, 2839 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF, 2840 .subvendor = PCI_ANY_ID, 2841 .subdevice = PCI_ANY_ID, 2842 .setup = pci_wch_ch353_setup, 2843 }, 2844 /* WCH CH352 2S card (16550 clone) */ 2845 { 2846 .vendor = PCI_VENDOR_ID_WCHCN, 2847 .device = PCI_DEVICE_ID_WCHCN_CH352_2S, 2848 .subvendor = PCI_ANY_ID, 2849 .subdevice = PCI_ANY_ID, 2850 .setup = pci_wch_ch353_setup, 2851 }, 2852 /* WCH CH355 4S card (16550 clone) */ 2853 { 2854 .vendor = PCI_VENDOR_ID_WCHCN, 2855 .device = PCI_DEVICE_ID_WCHCN_CH355_4S, 2856 .subvendor = PCI_ANY_ID, 2857 .subdevice = PCI_ANY_ID, 2858 .setup = pci_wch_ch355_setup, 2859 }, 2860 /* WCH CH382 2S card (16850 clone) */ 2861 { 2862 .vendor = PCI_VENDOR_ID_WCHIC, 2863 .device = PCI_DEVICE_ID_WCHIC_CH382_2S, 2864 .subvendor = PCI_ANY_ID, 2865 .subdevice = PCI_ANY_ID, 2866 .setup = pci_wch_ch38x_setup, 2867 }, 2868 /* WCH CH382 2S1P card (16850 clone) */ 2869 { 2870 .vendor = PCI_VENDOR_ID_WCHIC, 2871 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P, 2872 .subvendor = PCI_ANY_ID, 2873 .subdevice = PCI_ANY_ID, 2874 .setup = pci_wch_ch38x_setup, 2875 }, 2876 /* WCH CH384 4S card (16850 clone) */ 2877 { 2878 .vendor = PCI_VENDOR_ID_WCHIC, 2879 .device = PCI_DEVICE_ID_WCHIC_CH384_4S, 2880 .subvendor = PCI_ANY_ID, 2881 .subdevice = PCI_ANY_ID, 2882 .setup = pci_wch_ch38x_setup, 2883 }, 2884 /* WCH CH384 8S card (16850 clone) */ 2885 { 2886 .vendor = PCI_VENDOR_ID_WCHIC, 2887 .device = PCI_DEVICE_ID_WCHIC_CH384_8S, 2888 .subvendor = PCI_ANY_ID, 2889 .subdevice = PCI_ANY_ID, 2890 .init = pci_wch_ch38x_init, 2891 .exit = pci_wch_ch38x_exit, 2892 .setup = pci_wch_ch38x_setup, 2893 }, 2894 /* 2895 * Broadcom TruManage (NetXtreme) 2896 */ 2897 { 2898 .vendor = PCI_VENDOR_ID_BROADCOM, 2899 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2900 .subvendor = PCI_ANY_ID, 2901 .subdevice = PCI_ANY_ID, 2902 .setup = pci_brcm_trumanage_setup, 2903 }, 2904 { 2905 .vendor = 0x1c29, 2906 .device = 0x1104, 2907 .subvendor = PCI_ANY_ID, 2908 .subdevice = PCI_ANY_ID, 2909 .setup = pci_fintek_setup, 2910 .init = pci_fintek_init, 2911 }, 2912 { 2913 .vendor = 0x1c29, 2914 .device = 0x1108, 2915 .subvendor = PCI_ANY_ID, 2916 .subdevice = PCI_ANY_ID, 2917 .setup = pci_fintek_setup, 2918 .init = pci_fintek_init, 2919 }, 2920 { 2921 .vendor = 0x1c29, 2922 .device = 0x1112, 2923 .subvendor = PCI_ANY_ID, 2924 .subdevice = PCI_ANY_ID, 2925 .setup = pci_fintek_setup, 2926 .init = pci_fintek_init, 2927 }, 2928 /* 2929 * MOXA 2930 */ 2931 { 2932 .vendor = PCI_VENDOR_ID_MOXA, 2933 .device = PCI_ANY_ID, 2934 .subvendor = PCI_ANY_ID, 2935 .subdevice = PCI_ANY_ID, 2936 .init = pci_moxa_init, 2937 .setup = pci_moxa_setup, 2938 }, 2939 { 2940 .vendor = 0x1c29, 2941 .device = 0x1204, 2942 .subvendor = PCI_ANY_ID, 2943 .subdevice = PCI_ANY_ID, 2944 .setup = pci_fintek_f815xxa_setup, 2945 .init = pci_fintek_f815xxa_init, 2946 }, 2947 { 2948 .vendor = 0x1c29, 2949 .device = 0x1208, 2950 .subvendor = PCI_ANY_ID, 2951 .subdevice = PCI_ANY_ID, 2952 .setup = pci_fintek_f815xxa_setup, 2953 .init = pci_fintek_f815xxa_init, 2954 }, 2955 { 2956 .vendor = 0x1c29, 2957 .device = 0x1212, 2958 .subvendor = PCI_ANY_ID, 2959 .subdevice = PCI_ANY_ID, 2960 .setup = pci_fintek_f815xxa_setup, 2961 .init = pci_fintek_f815xxa_init, 2962 }, 2963 2964 /* 2965 * Default "match everything" terminator entry 2966 */ 2967 { 2968 .vendor = PCI_ANY_ID, 2969 .device = PCI_ANY_ID, 2970 .subvendor = PCI_ANY_ID, 2971 .subdevice = PCI_ANY_ID, 2972 .setup = pci_default_setup, 2973 } 2974 }; 2975 2976 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2977 { 2978 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2979 } 2980 2981 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2982 { 2983 struct pci_serial_quirk *quirk; 2984 2985 for (quirk = pci_serial_quirks; ; quirk++) 2986 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2987 quirk_id_matches(quirk->device, dev->device) && 2988 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2989 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2990 break; 2991 return quirk; 2992 } 2993 2994 /* 2995 * This is the configuration table for all of the PCI serial boards 2996 * which we support. It is directly indexed by the pci_board_num_t enum 2997 * value, which is encoded in the pci_device_id PCI probe table's 2998 * driver_data member. 2999 * 3000 * The makeup of these names are: 3001 * pbn_bn{_bt}_n_baud{_offsetinhex} 3002 * 3003 * bn = PCI BAR number 3004 * bt = Index using PCI BARs 3005 * n = number of serial ports 3006 * baud = baud rate 3007 * offsetinhex = offset for each sequential port (in hex) 3008 * 3009 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 3010 * 3011 * Please note: in theory if n = 1, _bt infix should make no difference. 3012 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 3013 */ 3014 enum pci_board_num_t { 3015 pbn_default = 0, 3016 3017 pbn_b0_1_115200, 3018 pbn_b0_2_115200, 3019 pbn_b0_4_115200, 3020 pbn_b0_5_115200, 3021 pbn_b0_8_115200, 3022 3023 pbn_b0_1_921600, 3024 pbn_b0_2_921600, 3025 pbn_b0_4_921600, 3026 3027 pbn_b0_2_1130000, 3028 3029 pbn_b0_4_1152000, 3030 3031 pbn_b0_4_1250000, 3032 3033 pbn_b0_2_1843200, 3034 pbn_b0_4_1843200, 3035 3036 pbn_b0_1_15625000, 3037 3038 pbn_b0_bt_1_115200, 3039 pbn_b0_bt_2_115200, 3040 pbn_b0_bt_4_115200, 3041 pbn_b0_bt_8_115200, 3042 3043 pbn_b0_bt_1_460800, 3044 pbn_b0_bt_2_460800, 3045 pbn_b0_bt_4_460800, 3046 3047 pbn_b0_bt_1_921600, 3048 pbn_b0_bt_2_921600, 3049 pbn_b0_bt_4_921600, 3050 pbn_b0_bt_8_921600, 3051 3052 pbn_b1_1_115200, 3053 pbn_b1_2_115200, 3054 pbn_b1_4_115200, 3055 pbn_b1_8_115200, 3056 pbn_b1_16_115200, 3057 3058 pbn_b1_1_921600, 3059 pbn_b1_2_921600, 3060 pbn_b1_4_921600, 3061 pbn_b1_8_921600, 3062 3063 pbn_b1_2_1250000, 3064 3065 pbn_b1_bt_1_115200, 3066 pbn_b1_bt_2_115200, 3067 pbn_b1_bt_4_115200, 3068 3069 pbn_b1_bt_2_921600, 3070 3071 pbn_b1_1_1382400, 3072 pbn_b1_2_1382400, 3073 pbn_b1_4_1382400, 3074 pbn_b1_8_1382400, 3075 3076 pbn_b2_1_115200, 3077 pbn_b2_2_115200, 3078 pbn_b2_4_115200, 3079 pbn_b2_8_115200, 3080 3081 pbn_b2_1_460800, 3082 pbn_b2_4_460800, 3083 pbn_b2_8_460800, 3084 pbn_b2_16_460800, 3085 3086 pbn_b2_1_921600, 3087 pbn_b2_4_921600, 3088 pbn_b2_8_921600, 3089 3090 pbn_b2_8_1152000, 3091 3092 pbn_b2_bt_1_115200, 3093 pbn_b2_bt_2_115200, 3094 pbn_b2_bt_4_115200, 3095 3096 pbn_b2_bt_2_921600, 3097 pbn_b2_bt_4_921600, 3098 3099 pbn_b3_2_115200, 3100 pbn_b3_4_115200, 3101 pbn_b3_8_115200, 3102 3103 pbn_b4_bt_2_921600, 3104 pbn_b4_bt_4_921600, 3105 pbn_b4_bt_8_921600, 3106 3107 /* 3108 * Board-specific versions. 3109 */ 3110 pbn_panacom, 3111 pbn_panacom2, 3112 pbn_panacom4, 3113 pbn_plx_romulus, 3114 pbn_oxsemi, 3115 pbn_oxsemi_1_15625000, 3116 pbn_oxsemi_2_15625000, 3117 pbn_oxsemi_4_15625000, 3118 pbn_oxsemi_8_15625000, 3119 pbn_intel_i960, 3120 pbn_sgi_ioc3, 3121 pbn_computone_4, 3122 pbn_computone_6, 3123 pbn_computone_8, 3124 pbn_sbsxrsio, 3125 pbn_pasemi_1682M, 3126 pbn_ni8430_2, 3127 pbn_ni8430_4, 3128 pbn_ni8430_8, 3129 pbn_ni8430_16, 3130 pbn_ADDIDATA_PCIe_1_3906250, 3131 pbn_ADDIDATA_PCIe_2_3906250, 3132 pbn_ADDIDATA_PCIe_4_3906250, 3133 pbn_ADDIDATA_PCIe_8_3906250, 3134 pbn_ce4100_1_115200, 3135 pbn_omegapci, 3136 pbn_NETMOS9900_2s_115200, 3137 pbn_brcm_trumanage, 3138 pbn_fintek_4, 3139 pbn_fintek_8, 3140 pbn_fintek_12, 3141 pbn_fintek_F81504A, 3142 pbn_fintek_F81508A, 3143 pbn_fintek_F81512A, 3144 pbn_wch382_2, 3145 pbn_wch384_4, 3146 pbn_wch384_8, 3147 pbn_sunix_pci_1s, 3148 pbn_sunix_pci_2s, 3149 pbn_sunix_pci_4s, 3150 pbn_sunix_pci_8s, 3151 pbn_sunix_pci_16s, 3152 pbn_titan_1_4000000, 3153 pbn_titan_2_4000000, 3154 pbn_titan_4_4000000, 3155 pbn_titan_8_4000000, 3156 pbn_moxa_2, 3157 pbn_moxa_4, 3158 pbn_moxa_8, 3159 }; 3160 3161 /* 3162 * uart_offset - the space between channels 3163 * reg_shift - describes how the UART registers are mapped 3164 * to PCI memory by the card. 3165 * For example IER register on SBS, Inc. PMC-OctPro is located at 3166 * offset 0x10 from the UART base, while UART_IER is defined as 1 3167 * in include/linux/serial_reg.h, 3168 * see first lines of serial_in() and serial_out() in 8250.c 3169 */ 3170 3171 static struct pciserial_board pci_boards[] = { 3172 [pbn_default] = { 3173 .flags = FL_BASE0, 3174 .num_ports = 1, 3175 .base_baud = 115200, 3176 .uart_offset = 8, 3177 }, 3178 [pbn_b0_1_115200] = { 3179 .flags = FL_BASE0, 3180 .num_ports = 1, 3181 .base_baud = 115200, 3182 .uart_offset = 8, 3183 }, 3184 [pbn_b0_2_115200] = { 3185 .flags = FL_BASE0, 3186 .num_ports = 2, 3187 .base_baud = 115200, 3188 .uart_offset = 8, 3189 }, 3190 [pbn_b0_4_115200] = { 3191 .flags = FL_BASE0, 3192 .num_ports = 4, 3193 .base_baud = 115200, 3194 .uart_offset = 8, 3195 }, 3196 [pbn_b0_5_115200] = { 3197 .flags = FL_BASE0, 3198 .num_ports = 5, 3199 .base_baud = 115200, 3200 .uart_offset = 8, 3201 }, 3202 [pbn_b0_8_115200] = { 3203 .flags = FL_BASE0, 3204 .num_ports = 8, 3205 .base_baud = 115200, 3206 .uart_offset = 8, 3207 }, 3208 [pbn_b0_1_921600] = { 3209 .flags = FL_BASE0, 3210 .num_ports = 1, 3211 .base_baud = 921600, 3212 .uart_offset = 8, 3213 }, 3214 [pbn_b0_2_921600] = { 3215 .flags = FL_BASE0, 3216 .num_ports = 2, 3217 .base_baud = 921600, 3218 .uart_offset = 8, 3219 }, 3220 [pbn_b0_4_921600] = { 3221 .flags = FL_BASE0, 3222 .num_ports = 4, 3223 .base_baud = 921600, 3224 .uart_offset = 8, 3225 }, 3226 3227 [pbn_b0_2_1130000] = { 3228 .flags = FL_BASE0, 3229 .num_ports = 2, 3230 .base_baud = 1130000, 3231 .uart_offset = 8, 3232 }, 3233 3234 [pbn_b0_4_1152000] = { 3235 .flags = FL_BASE0, 3236 .num_ports = 4, 3237 .base_baud = 1152000, 3238 .uart_offset = 8, 3239 }, 3240 3241 [pbn_b0_4_1250000] = { 3242 .flags = FL_BASE0, 3243 .num_ports = 4, 3244 .base_baud = 1250000, 3245 .uart_offset = 8, 3246 }, 3247 3248 [pbn_b0_2_1843200] = { 3249 .flags = FL_BASE0, 3250 .num_ports = 2, 3251 .base_baud = 1843200, 3252 .uart_offset = 8, 3253 }, 3254 [pbn_b0_4_1843200] = { 3255 .flags = FL_BASE0, 3256 .num_ports = 4, 3257 .base_baud = 1843200, 3258 .uart_offset = 8, 3259 }, 3260 3261 [pbn_b0_1_15625000] = { 3262 .flags = FL_BASE0, 3263 .num_ports = 1, 3264 .base_baud = 15625000, 3265 .uart_offset = 8, 3266 }, 3267 3268 [pbn_b0_bt_1_115200] = { 3269 .flags = FL_BASE0|FL_BASE_BARS, 3270 .num_ports = 1, 3271 .base_baud = 115200, 3272 .uart_offset = 8, 3273 }, 3274 [pbn_b0_bt_2_115200] = { 3275 .flags = FL_BASE0|FL_BASE_BARS, 3276 .num_ports = 2, 3277 .base_baud = 115200, 3278 .uart_offset = 8, 3279 }, 3280 [pbn_b0_bt_4_115200] = { 3281 .flags = FL_BASE0|FL_BASE_BARS, 3282 .num_ports = 4, 3283 .base_baud = 115200, 3284 .uart_offset = 8, 3285 }, 3286 [pbn_b0_bt_8_115200] = { 3287 .flags = FL_BASE0|FL_BASE_BARS, 3288 .num_ports = 8, 3289 .base_baud = 115200, 3290 .uart_offset = 8, 3291 }, 3292 3293 [pbn_b0_bt_1_460800] = { 3294 .flags = FL_BASE0|FL_BASE_BARS, 3295 .num_ports = 1, 3296 .base_baud = 460800, 3297 .uart_offset = 8, 3298 }, 3299 [pbn_b0_bt_2_460800] = { 3300 .flags = FL_BASE0|FL_BASE_BARS, 3301 .num_ports = 2, 3302 .base_baud = 460800, 3303 .uart_offset = 8, 3304 }, 3305 [pbn_b0_bt_4_460800] = { 3306 .flags = FL_BASE0|FL_BASE_BARS, 3307 .num_ports = 4, 3308 .base_baud = 460800, 3309 .uart_offset = 8, 3310 }, 3311 3312 [pbn_b0_bt_1_921600] = { 3313 .flags = FL_BASE0|FL_BASE_BARS, 3314 .num_ports = 1, 3315 .base_baud = 921600, 3316 .uart_offset = 8, 3317 }, 3318 [pbn_b0_bt_2_921600] = { 3319 .flags = FL_BASE0|FL_BASE_BARS, 3320 .num_ports = 2, 3321 .base_baud = 921600, 3322 .uart_offset = 8, 3323 }, 3324 [pbn_b0_bt_4_921600] = { 3325 .flags = FL_BASE0|FL_BASE_BARS, 3326 .num_ports = 4, 3327 .base_baud = 921600, 3328 .uart_offset = 8, 3329 }, 3330 [pbn_b0_bt_8_921600] = { 3331 .flags = FL_BASE0|FL_BASE_BARS, 3332 .num_ports = 8, 3333 .base_baud = 921600, 3334 .uart_offset = 8, 3335 }, 3336 3337 [pbn_b1_1_115200] = { 3338 .flags = FL_BASE1, 3339 .num_ports = 1, 3340 .base_baud = 115200, 3341 .uart_offset = 8, 3342 }, 3343 [pbn_b1_2_115200] = { 3344 .flags = FL_BASE1, 3345 .num_ports = 2, 3346 .base_baud = 115200, 3347 .uart_offset = 8, 3348 }, 3349 [pbn_b1_4_115200] = { 3350 .flags = FL_BASE1, 3351 .num_ports = 4, 3352 .base_baud = 115200, 3353 .uart_offset = 8, 3354 }, 3355 [pbn_b1_8_115200] = { 3356 .flags = FL_BASE1, 3357 .num_ports = 8, 3358 .base_baud = 115200, 3359 .uart_offset = 8, 3360 }, 3361 [pbn_b1_16_115200] = { 3362 .flags = FL_BASE1, 3363 .num_ports = 16, 3364 .base_baud = 115200, 3365 .uart_offset = 8, 3366 }, 3367 3368 [pbn_b1_1_921600] = { 3369 .flags = FL_BASE1, 3370 .num_ports = 1, 3371 .base_baud = 921600, 3372 .uart_offset = 8, 3373 }, 3374 [pbn_b1_2_921600] = { 3375 .flags = FL_BASE1, 3376 .num_ports = 2, 3377 .base_baud = 921600, 3378 .uart_offset = 8, 3379 }, 3380 [pbn_b1_4_921600] = { 3381 .flags = FL_BASE1, 3382 .num_ports = 4, 3383 .base_baud = 921600, 3384 .uart_offset = 8, 3385 }, 3386 [pbn_b1_8_921600] = { 3387 .flags = FL_BASE1, 3388 .num_ports = 8, 3389 .base_baud = 921600, 3390 .uart_offset = 8, 3391 }, 3392 [pbn_b1_2_1250000] = { 3393 .flags = FL_BASE1, 3394 .num_ports = 2, 3395 .base_baud = 1250000, 3396 .uart_offset = 8, 3397 }, 3398 3399 [pbn_b1_bt_1_115200] = { 3400 .flags = FL_BASE1|FL_BASE_BARS, 3401 .num_ports = 1, 3402 .base_baud = 115200, 3403 .uart_offset = 8, 3404 }, 3405 [pbn_b1_bt_2_115200] = { 3406 .flags = FL_BASE1|FL_BASE_BARS, 3407 .num_ports = 2, 3408 .base_baud = 115200, 3409 .uart_offset = 8, 3410 }, 3411 [pbn_b1_bt_4_115200] = { 3412 .flags = FL_BASE1|FL_BASE_BARS, 3413 .num_ports = 4, 3414 .base_baud = 115200, 3415 .uart_offset = 8, 3416 }, 3417 3418 [pbn_b1_bt_2_921600] = { 3419 .flags = FL_BASE1|FL_BASE_BARS, 3420 .num_ports = 2, 3421 .base_baud = 921600, 3422 .uart_offset = 8, 3423 }, 3424 3425 [pbn_b1_1_1382400] = { 3426 .flags = FL_BASE1, 3427 .num_ports = 1, 3428 .base_baud = 1382400, 3429 .uart_offset = 8, 3430 }, 3431 [pbn_b1_2_1382400] = { 3432 .flags = FL_BASE1, 3433 .num_ports = 2, 3434 .base_baud = 1382400, 3435 .uart_offset = 8, 3436 }, 3437 [pbn_b1_4_1382400] = { 3438 .flags = FL_BASE1, 3439 .num_ports = 4, 3440 .base_baud = 1382400, 3441 .uart_offset = 8, 3442 }, 3443 [pbn_b1_8_1382400] = { 3444 .flags = FL_BASE1, 3445 .num_ports = 8, 3446 .base_baud = 1382400, 3447 .uart_offset = 8, 3448 }, 3449 3450 [pbn_b2_1_115200] = { 3451 .flags = FL_BASE2, 3452 .num_ports = 1, 3453 .base_baud = 115200, 3454 .uart_offset = 8, 3455 }, 3456 [pbn_b2_2_115200] = { 3457 .flags = FL_BASE2, 3458 .num_ports = 2, 3459 .base_baud = 115200, 3460 .uart_offset = 8, 3461 }, 3462 [pbn_b2_4_115200] = { 3463 .flags = FL_BASE2, 3464 .num_ports = 4, 3465 .base_baud = 115200, 3466 .uart_offset = 8, 3467 }, 3468 [pbn_b2_8_115200] = { 3469 .flags = FL_BASE2, 3470 .num_ports = 8, 3471 .base_baud = 115200, 3472 .uart_offset = 8, 3473 }, 3474 3475 [pbn_b2_1_460800] = { 3476 .flags = FL_BASE2, 3477 .num_ports = 1, 3478 .base_baud = 460800, 3479 .uart_offset = 8, 3480 }, 3481 [pbn_b2_4_460800] = { 3482 .flags = FL_BASE2, 3483 .num_ports = 4, 3484 .base_baud = 460800, 3485 .uart_offset = 8, 3486 }, 3487 [pbn_b2_8_460800] = { 3488 .flags = FL_BASE2, 3489 .num_ports = 8, 3490 .base_baud = 460800, 3491 .uart_offset = 8, 3492 }, 3493 [pbn_b2_16_460800] = { 3494 .flags = FL_BASE2, 3495 .num_ports = 16, 3496 .base_baud = 460800, 3497 .uart_offset = 8, 3498 }, 3499 3500 [pbn_b2_1_921600] = { 3501 .flags = FL_BASE2, 3502 .num_ports = 1, 3503 .base_baud = 921600, 3504 .uart_offset = 8, 3505 }, 3506 [pbn_b2_4_921600] = { 3507 .flags = FL_BASE2, 3508 .num_ports = 4, 3509 .base_baud = 921600, 3510 .uart_offset = 8, 3511 }, 3512 [pbn_b2_8_921600] = { 3513 .flags = FL_BASE2, 3514 .num_ports = 8, 3515 .base_baud = 921600, 3516 .uart_offset = 8, 3517 }, 3518 3519 [pbn_b2_8_1152000] = { 3520 .flags = FL_BASE2, 3521 .num_ports = 8, 3522 .base_baud = 1152000, 3523 .uart_offset = 8, 3524 }, 3525 3526 [pbn_b2_bt_1_115200] = { 3527 .flags = FL_BASE2|FL_BASE_BARS, 3528 .num_ports = 1, 3529 .base_baud = 115200, 3530 .uart_offset = 8, 3531 }, 3532 [pbn_b2_bt_2_115200] = { 3533 .flags = FL_BASE2|FL_BASE_BARS, 3534 .num_ports = 2, 3535 .base_baud = 115200, 3536 .uart_offset = 8, 3537 }, 3538 [pbn_b2_bt_4_115200] = { 3539 .flags = FL_BASE2|FL_BASE_BARS, 3540 .num_ports = 4, 3541 .base_baud = 115200, 3542 .uart_offset = 8, 3543 }, 3544 3545 [pbn_b2_bt_2_921600] = { 3546 .flags = FL_BASE2|FL_BASE_BARS, 3547 .num_ports = 2, 3548 .base_baud = 921600, 3549 .uart_offset = 8, 3550 }, 3551 [pbn_b2_bt_4_921600] = { 3552 .flags = FL_BASE2|FL_BASE_BARS, 3553 .num_ports = 4, 3554 .base_baud = 921600, 3555 .uart_offset = 8, 3556 }, 3557 3558 [pbn_b3_2_115200] = { 3559 .flags = FL_BASE3, 3560 .num_ports = 2, 3561 .base_baud = 115200, 3562 .uart_offset = 8, 3563 }, 3564 [pbn_b3_4_115200] = { 3565 .flags = FL_BASE3, 3566 .num_ports = 4, 3567 .base_baud = 115200, 3568 .uart_offset = 8, 3569 }, 3570 [pbn_b3_8_115200] = { 3571 .flags = FL_BASE3, 3572 .num_ports = 8, 3573 .base_baud = 115200, 3574 .uart_offset = 8, 3575 }, 3576 3577 [pbn_b4_bt_2_921600] = { 3578 .flags = FL_BASE4, 3579 .num_ports = 2, 3580 .base_baud = 921600, 3581 .uart_offset = 8, 3582 }, 3583 [pbn_b4_bt_4_921600] = { 3584 .flags = FL_BASE4, 3585 .num_ports = 4, 3586 .base_baud = 921600, 3587 .uart_offset = 8, 3588 }, 3589 [pbn_b4_bt_8_921600] = { 3590 .flags = FL_BASE4, 3591 .num_ports = 8, 3592 .base_baud = 921600, 3593 .uart_offset = 8, 3594 }, 3595 3596 /* 3597 * Entries following this are board-specific. 3598 */ 3599 3600 /* 3601 * Panacom - IOMEM 3602 */ 3603 [pbn_panacom] = { 3604 .flags = FL_BASE2, 3605 .num_ports = 2, 3606 .base_baud = 921600, 3607 .uart_offset = 0x400, 3608 .reg_shift = 7, 3609 }, 3610 [pbn_panacom2] = { 3611 .flags = FL_BASE2|FL_BASE_BARS, 3612 .num_ports = 2, 3613 .base_baud = 921600, 3614 .uart_offset = 0x400, 3615 .reg_shift = 7, 3616 }, 3617 [pbn_panacom4] = { 3618 .flags = FL_BASE2|FL_BASE_BARS, 3619 .num_ports = 4, 3620 .base_baud = 921600, 3621 .uart_offset = 0x400, 3622 .reg_shift = 7, 3623 }, 3624 3625 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3626 [pbn_plx_romulus] = { 3627 .flags = FL_BASE2, 3628 .num_ports = 4, 3629 .base_baud = 921600, 3630 .uart_offset = 8 << 2, 3631 .reg_shift = 2, 3632 .first_offset = 0x03, 3633 }, 3634 3635 /* 3636 * This board uses the size of PCI Base region 0 to 3637 * signal now many ports are available 3638 */ 3639 [pbn_oxsemi] = { 3640 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3641 .num_ports = 32, 3642 .base_baud = 115200, 3643 .uart_offset = 8, 3644 }, 3645 [pbn_oxsemi_1_15625000] = { 3646 .flags = FL_BASE0, 3647 .num_ports = 1, 3648 .base_baud = 15625000, 3649 .uart_offset = 0x200, 3650 .first_offset = 0x1000, 3651 }, 3652 [pbn_oxsemi_2_15625000] = { 3653 .flags = FL_BASE0, 3654 .num_ports = 2, 3655 .base_baud = 15625000, 3656 .uart_offset = 0x200, 3657 .first_offset = 0x1000, 3658 }, 3659 [pbn_oxsemi_4_15625000] = { 3660 .flags = FL_BASE0, 3661 .num_ports = 4, 3662 .base_baud = 15625000, 3663 .uart_offset = 0x200, 3664 .first_offset = 0x1000, 3665 }, 3666 [pbn_oxsemi_8_15625000] = { 3667 .flags = FL_BASE0, 3668 .num_ports = 8, 3669 .base_baud = 15625000, 3670 .uart_offset = 0x200, 3671 .first_offset = 0x1000, 3672 }, 3673 3674 3675 /* 3676 * EKF addition for i960 Boards form EKF with serial port. 3677 * Max 256 ports. 3678 */ 3679 [pbn_intel_i960] = { 3680 .flags = FL_BASE0, 3681 .num_ports = 32, 3682 .base_baud = 921600, 3683 .uart_offset = 8 << 2, 3684 .reg_shift = 2, 3685 .first_offset = 0x10000, 3686 }, 3687 [pbn_sgi_ioc3] = { 3688 .flags = FL_BASE0|FL_NOIRQ, 3689 .num_ports = 1, 3690 .base_baud = 458333, 3691 .uart_offset = 8, 3692 .reg_shift = 0, 3693 .first_offset = 0x20178, 3694 }, 3695 3696 /* 3697 * Computone - uses IOMEM. 3698 */ 3699 [pbn_computone_4] = { 3700 .flags = FL_BASE0, 3701 .num_ports = 4, 3702 .base_baud = 921600, 3703 .uart_offset = 0x40, 3704 .reg_shift = 2, 3705 .first_offset = 0x200, 3706 }, 3707 [pbn_computone_6] = { 3708 .flags = FL_BASE0, 3709 .num_ports = 6, 3710 .base_baud = 921600, 3711 .uart_offset = 0x40, 3712 .reg_shift = 2, 3713 .first_offset = 0x200, 3714 }, 3715 [pbn_computone_8] = { 3716 .flags = FL_BASE0, 3717 .num_ports = 8, 3718 .base_baud = 921600, 3719 .uart_offset = 0x40, 3720 .reg_shift = 2, 3721 .first_offset = 0x200, 3722 }, 3723 [pbn_sbsxrsio] = { 3724 .flags = FL_BASE0, 3725 .num_ports = 8, 3726 .base_baud = 460800, 3727 .uart_offset = 256, 3728 .reg_shift = 4, 3729 }, 3730 /* 3731 * PA Semi PWRficient PA6T-1682M on-chip UART 3732 */ 3733 [pbn_pasemi_1682M] = { 3734 .flags = FL_BASE0, 3735 .num_ports = 1, 3736 .base_baud = 8333333, 3737 }, 3738 /* 3739 * National Instruments 843x 3740 */ 3741 [pbn_ni8430_16] = { 3742 .flags = FL_BASE0, 3743 .num_ports = 16, 3744 .base_baud = 3686400, 3745 .uart_offset = 0x10, 3746 .first_offset = 0x800, 3747 }, 3748 [pbn_ni8430_8] = { 3749 .flags = FL_BASE0, 3750 .num_ports = 8, 3751 .base_baud = 3686400, 3752 .uart_offset = 0x10, 3753 .first_offset = 0x800, 3754 }, 3755 [pbn_ni8430_4] = { 3756 .flags = FL_BASE0, 3757 .num_ports = 4, 3758 .base_baud = 3686400, 3759 .uart_offset = 0x10, 3760 .first_offset = 0x800, 3761 }, 3762 [pbn_ni8430_2] = { 3763 .flags = FL_BASE0, 3764 .num_ports = 2, 3765 .base_baud = 3686400, 3766 .uart_offset = 0x10, 3767 .first_offset = 0x800, 3768 }, 3769 /* 3770 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3771 */ 3772 [pbn_ADDIDATA_PCIe_1_3906250] = { 3773 .flags = FL_BASE0, 3774 .num_ports = 1, 3775 .base_baud = 3906250, 3776 .uart_offset = 0x200, 3777 .first_offset = 0x1000, 3778 }, 3779 [pbn_ADDIDATA_PCIe_2_3906250] = { 3780 .flags = FL_BASE0, 3781 .num_ports = 2, 3782 .base_baud = 3906250, 3783 .uart_offset = 0x200, 3784 .first_offset = 0x1000, 3785 }, 3786 [pbn_ADDIDATA_PCIe_4_3906250] = { 3787 .flags = FL_BASE0, 3788 .num_ports = 4, 3789 .base_baud = 3906250, 3790 .uart_offset = 0x200, 3791 .first_offset = 0x1000, 3792 }, 3793 [pbn_ADDIDATA_PCIe_8_3906250] = { 3794 .flags = FL_BASE0, 3795 .num_ports = 8, 3796 .base_baud = 3906250, 3797 .uart_offset = 0x200, 3798 .first_offset = 0x1000, 3799 }, 3800 [pbn_ce4100_1_115200] = { 3801 .flags = FL_BASE_BARS, 3802 .num_ports = 2, 3803 .base_baud = 921600, 3804 .reg_shift = 2, 3805 }, 3806 [pbn_omegapci] = { 3807 .flags = FL_BASE0, 3808 .num_ports = 8, 3809 .base_baud = 115200, 3810 .uart_offset = 0x200, 3811 }, 3812 [pbn_NETMOS9900_2s_115200] = { 3813 .flags = FL_BASE0, 3814 .num_ports = 2, 3815 .base_baud = 115200, 3816 }, 3817 [pbn_brcm_trumanage] = { 3818 .flags = FL_BASE0, 3819 .num_ports = 1, 3820 .reg_shift = 2, 3821 .base_baud = 115200, 3822 }, 3823 [pbn_fintek_4] = { 3824 .num_ports = 4, 3825 .uart_offset = 8, 3826 .base_baud = 115200, 3827 .first_offset = 0x40, 3828 }, 3829 [pbn_fintek_8] = { 3830 .num_ports = 8, 3831 .uart_offset = 8, 3832 .base_baud = 115200, 3833 .first_offset = 0x40, 3834 }, 3835 [pbn_fintek_12] = { 3836 .num_ports = 12, 3837 .uart_offset = 8, 3838 .base_baud = 115200, 3839 .first_offset = 0x40, 3840 }, 3841 [pbn_fintek_F81504A] = { 3842 .num_ports = 4, 3843 .uart_offset = 8, 3844 .base_baud = 115200, 3845 }, 3846 [pbn_fintek_F81508A] = { 3847 .num_ports = 8, 3848 .uart_offset = 8, 3849 .base_baud = 115200, 3850 }, 3851 [pbn_fintek_F81512A] = { 3852 .num_ports = 12, 3853 .uart_offset = 8, 3854 .base_baud = 115200, 3855 }, 3856 [pbn_wch382_2] = { 3857 .flags = FL_BASE0, 3858 .num_ports = 2, 3859 .base_baud = 115200, 3860 .uart_offset = 8, 3861 .first_offset = 0xC0, 3862 }, 3863 [pbn_wch384_4] = { 3864 .flags = FL_BASE0, 3865 .num_ports = 4, 3866 .base_baud = 115200, 3867 .uart_offset = 8, 3868 .first_offset = 0xC0, 3869 }, 3870 [pbn_wch384_8] = { 3871 .flags = FL_BASE0, 3872 .num_ports = 8, 3873 .base_baud = 115200, 3874 .uart_offset = 8, 3875 .first_offset = 0x00, 3876 }, 3877 [pbn_sunix_pci_1s] = { 3878 .num_ports = 1, 3879 .base_baud = 921600, 3880 .uart_offset = 0x8, 3881 }, 3882 [pbn_sunix_pci_2s] = { 3883 .num_ports = 2, 3884 .base_baud = 921600, 3885 .uart_offset = 0x8, 3886 }, 3887 [pbn_sunix_pci_4s] = { 3888 .num_ports = 4, 3889 .base_baud = 921600, 3890 .uart_offset = 0x8, 3891 }, 3892 [pbn_sunix_pci_8s] = { 3893 .num_ports = 8, 3894 .base_baud = 921600, 3895 .uart_offset = 0x8, 3896 }, 3897 [pbn_sunix_pci_16s] = { 3898 .num_ports = 16, 3899 .base_baud = 921600, 3900 .uart_offset = 0x8, 3901 }, 3902 [pbn_titan_1_4000000] = { 3903 .flags = FL_BASE0, 3904 .num_ports = 1, 3905 .base_baud = 4000000, 3906 .uart_offset = 0x200, 3907 .first_offset = 0x1000, 3908 }, 3909 [pbn_titan_2_4000000] = { 3910 .flags = FL_BASE0, 3911 .num_ports = 2, 3912 .base_baud = 4000000, 3913 .uart_offset = 0x200, 3914 .first_offset = 0x1000, 3915 }, 3916 [pbn_titan_4_4000000] = { 3917 .flags = FL_BASE0, 3918 .num_ports = 4, 3919 .base_baud = 4000000, 3920 .uart_offset = 0x200, 3921 .first_offset = 0x1000, 3922 }, 3923 [pbn_titan_8_4000000] = { 3924 .flags = FL_BASE0, 3925 .num_ports = 8, 3926 .base_baud = 4000000, 3927 .uart_offset = 0x200, 3928 .first_offset = 0x1000, 3929 }, 3930 [pbn_moxa_2] = { 3931 .flags = FL_BASE1, 3932 .num_ports = 2, 3933 .base_baud = 921600, 3934 .uart_offset = 0x200, 3935 }, 3936 [pbn_moxa_4] = { 3937 .flags = FL_BASE1, 3938 .num_ports = 4, 3939 .base_baud = 921600, 3940 .uart_offset = 0x200, 3941 }, 3942 [pbn_moxa_8] = { 3943 .flags = FL_BASE1, 3944 .num_ports = 8, 3945 .base_baud = 921600, 3946 .uart_offset = 0x200, 3947 }, 3948 }; 3949 3950 #define REPORT_CONFIG(option) \ 3951 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3952 #define REPORT_8250_CONFIG(option) \ 3953 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3954 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3955 3956 static const struct pci_device_id blacklist[] = { 3957 /* softmodems */ 3958 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3959 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3960 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3961 3962 /* multi-io cards handled by parport_serial */ 3963 /* WCH CH353 2S1P */ 3964 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), }, 3965 /* WCH CH353 1S1P */ 3966 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), }, 3967 /* WCH CH382 2S1P */ 3968 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), }, 3969 3970 /* Intel platforms with MID UART */ 3971 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3972 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3973 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3974 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3975 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3976 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3977 3978 /* Intel platforms with DesignWare UART */ 3979 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3980 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3981 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3982 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3983 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3984 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3985 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3986 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3987 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3988 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3989 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3990 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3991 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3992 3993 /* Exar devices */ 3994 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3995 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3996 3997 /* Pericom devices */ 3998 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3999 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 4000 4001 /* End of the black list */ 4002 { } 4003 }; 4004 4005 static int serial_pci_is_class_communication(struct pci_dev *dev) 4006 { 4007 /* 4008 * If it is not a communications device or the programming 4009 * interface is greater than 6, give up. 4010 */ 4011 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 4012 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 4013 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 4014 (dev->class & 0xff) > 6) 4015 return -ENODEV; 4016 4017 return 0; 4018 } 4019 4020 /* 4021 * Given a complete unknown PCI device, try to use some heuristics to 4022 * guess what the configuration might be, based on the pitiful PCI 4023 * serial specs. Returns 0 on success, -ENODEV on failure. 4024 */ 4025 static int 4026 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 4027 { 4028 int num_iomem, num_port, first_port = -1, i; 4029 int rc; 4030 4031 rc = serial_pci_is_class_communication(dev); 4032 if (rc) 4033 return rc; 4034 4035 /* 4036 * Should we try to make guesses for multiport serial devices later? 4037 */ 4038 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 4039 return -ENODEV; 4040 4041 num_iomem = num_port = 0; 4042 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 4043 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 4044 num_port++; 4045 if (first_port == -1) 4046 first_port = i; 4047 } 4048 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 4049 num_iomem++; 4050 } 4051 4052 /* 4053 * If there is 1 or 0 iomem regions, and exactly one port, 4054 * use it. We guess the number of ports based on the IO 4055 * region size. 4056 */ 4057 if (num_iomem <= 1 && num_port == 1) { 4058 board->flags = first_port; 4059 board->num_ports = pci_resource_len(dev, first_port) / 8; 4060 return 0; 4061 } 4062 4063 /* 4064 * Now guess if we've got a board which indexes by BARs. 4065 * Each IO BAR should be 8 bytes, and they should follow 4066 * consecutively. 4067 */ 4068 first_port = -1; 4069 num_port = 0; 4070 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 4071 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 4072 pci_resource_len(dev, i) == 8 && 4073 (first_port == -1 || (first_port + num_port) == i)) { 4074 num_port++; 4075 if (first_port == -1) 4076 first_port = i; 4077 } 4078 } 4079 4080 if (num_port > 1) { 4081 board->flags = first_port | FL_BASE_BARS; 4082 board->num_ports = num_port; 4083 return 0; 4084 } 4085 4086 return -ENODEV; 4087 } 4088 4089 static inline int 4090 serial_pci_matches(const struct pciserial_board *board, 4091 const struct pciserial_board *guessed) 4092 { 4093 return 4094 board->num_ports == guessed->num_ports && 4095 board->base_baud == guessed->base_baud && 4096 board->uart_offset == guessed->uart_offset && 4097 board->reg_shift == guessed->reg_shift && 4098 board->first_offset == guessed->first_offset; 4099 } 4100 4101 struct serial_private * 4102 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 4103 { 4104 struct uart_8250_port uart; 4105 struct serial_private *priv; 4106 struct pci_serial_quirk *quirk; 4107 int rc, nr_ports, i; 4108 4109 nr_ports = board->num_ports; 4110 4111 /* 4112 * Find an init and setup quirks. 4113 */ 4114 quirk = find_quirk(dev); 4115 4116 /* 4117 * Run the new-style initialization function. 4118 * The initialization function returns: 4119 * <0 - error 4120 * 0 - use board->num_ports 4121 * >0 - number of ports 4122 */ 4123 if (quirk->init) { 4124 rc = quirk->init(dev); 4125 if (rc < 0) { 4126 priv = ERR_PTR(rc); 4127 goto err_out; 4128 } 4129 if (rc) 4130 nr_ports = rc; 4131 } 4132 4133 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 4134 if (!priv) { 4135 priv = ERR_PTR(-ENOMEM); 4136 goto err_deinit; 4137 } 4138 4139 priv->dev = dev; 4140 priv->quirk = quirk; 4141 4142 memset(&uart, 0, sizeof(uart)); 4143 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 4144 uart.port.uartclk = board->base_baud * 16; 4145 4146 if (board->flags & FL_NOIRQ) { 4147 uart.port.irq = 0; 4148 } else { 4149 if (pci_match_id(pci_use_msi, dev)) { 4150 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 4151 pci_set_master(dev); 4152 uart.port.flags &= ~UPF_SHARE_IRQ; 4153 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 4154 } else { 4155 pci_dbg(dev, "Using legacy interrupts\n"); 4156 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX); 4157 } 4158 if (rc < 0) { 4159 kfree(priv); 4160 priv = ERR_PTR(rc); 4161 goto err_deinit; 4162 } 4163 4164 uart.port.irq = pci_irq_vector(dev, 0); 4165 } 4166 4167 uart.port.dev = &dev->dev; 4168 4169 for (i = 0; i < nr_ports; i++) { 4170 if (quirk->setup(priv, board, &uart, i)) 4171 break; 4172 4173 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 4174 uart.port.iobase, uart.port.irq, uart.port.iotype); 4175 4176 priv->line[i] = serial8250_register_8250_port(&uart); 4177 if (priv->line[i] < 0) { 4178 pci_err(dev, 4179 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4180 uart.port.iobase, uart.port.irq, 4181 uart.port.iotype, priv->line[i]); 4182 break; 4183 } 4184 } 4185 priv->nr = i; 4186 priv->board = board; 4187 return priv; 4188 4189 err_deinit: 4190 if (quirk->exit) 4191 quirk->exit(dev); 4192 err_out: 4193 return priv; 4194 } 4195 EXPORT_SYMBOL_GPL(pciserial_init_ports); 4196 4197 static void pciserial_detach_ports(struct serial_private *priv) 4198 { 4199 struct pci_serial_quirk *quirk; 4200 int i; 4201 4202 for (i = 0; i < priv->nr; i++) 4203 serial8250_unregister_port(priv->line[i]); 4204 4205 /* 4206 * Find the exit quirks. 4207 */ 4208 quirk = find_quirk(priv->dev); 4209 if (quirk->exit) 4210 quirk->exit(priv->dev); 4211 } 4212 4213 void pciserial_remove_ports(struct serial_private *priv) 4214 { 4215 pciserial_detach_ports(priv); 4216 kfree(priv); 4217 } 4218 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4219 4220 void pciserial_suspend_ports(struct serial_private *priv) 4221 { 4222 int i; 4223 4224 for (i = 0; i < priv->nr; i++) 4225 if (priv->line[i] >= 0) 4226 serial8250_suspend_port(priv->line[i]); 4227 4228 /* 4229 * Ensure that every init quirk is properly torn down 4230 */ 4231 if (priv->quirk->exit) 4232 priv->quirk->exit(priv->dev); 4233 } 4234 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4235 4236 void pciserial_resume_ports(struct serial_private *priv) 4237 { 4238 int i; 4239 4240 /* 4241 * Ensure that the board is correctly configured. 4242 */ 4243 if (priv->quirk->init) 4244 priv->quirk->init(priv->dev); 4245 4246 for (i = 0; i < priv->nr; i++) 4247 if (priv->line[i] >= 0) 4248 serial8250_resume_port(priv->line[i]); 4249 } 4250 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4251 4252 /* 4253 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4254 * to the arrangement of serial ports on a PCI card. 4255 */ 4256 static int 4257 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4258 { 4259 struct pci_serial_quirk *quirk; 4260 struct serial_private *priv; 4261 const struct pciserial_board *board; 4262 const struct pci_device_id *exclude; 4263 struct pciserial_board tmp; 4264 int rc; 4265 4266 quirk = find_quirk(dev); 4267 if (quirk->probe) { 4268 rc = quirk->probe(dev); 4269 if (rc) 4270 return rc; 4271 } 4272 4273 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4274 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4275 return -EINVAL; 4276 } 4277 4278 board = &pci_boards[ent->driver_data]; 4279 4280 exclude = pci_match_id(blacklist, dev); 4281 if (exclude) { 4282 if (exclude->driver_data) 4283 pci_warn(dev, "ignoring port, enable %s to handle\n", 4284 (const char *)exclude->driver_data); 4285 return -ENODEV; 4286 } 4287 4288 rc = pcim_enable_device(dev); 4289 pci_save_state(dev); 4290 if (rc) 4291 return rc; 4292 4293 if (ent->driver_data == pbn_default) { 4294 /* 4295 * Use a copy of the pci_board entry for this; 4296 * avoid changing entries in the table. 4297 */ 4298 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4299 board = &tmp; 4300 4301 /* 4302 * We matched one of our class entries. Try to 4303 * determine the parameters of this board. 4304 */ 4305 rc = serial_pci_guess_board(dev, &tmp); 4306 if (rc) 4307 return rc; 4308 } else { 4309 /* 4310 * We matched an explicit entry. If we are able to 4311 * detect this boards settings with our heuristic, 4312 * then we no longer need this entry. 4313 */ 4314 memcpy(&tmp, &pci_boards[pbn_default], 4315 sizeof(struct pciserial_board)); 4316 rc = serial_pci_guess_board(dev, &tmp); 4317 if (rc == 0 && serial_pci_matches(board, &tmp)) 4318 moan_device("Redundant entry in serial pci_table.", 4319 dev); 4320 } 4321 4322 priv = pciserial_init_ports(dev, board); 4323 if (IS_ERR(priv)) 4324 return PTR_ERR(priv); 4325 4326 pci_set_drvdata(dev, priv); 4327 return 0; 4328 } 4329 4330 static void pciserial_remove_one(struct pci_dev *dev) 4331 { 4332 struct serial_private *priv = pci_get_drvdata(dev); 4333 4334 pciserial_remove_ports(priv); 4335 } 4336 4337 #ifdef CONFIG_PM_SLEEP 4338 static int pciserial_suspend_one(struct device *dev) 4339 { 4340 struct serial_private *priv = dev_get_drvdata(dev); 4341 4342 if (priv) 4343 pciserial_suspend_ports(priv); 4344 4345 return 0; 4346 } 4347 4348 static int pciserial_resume_one(struct device *dev) 4349 { 4350 struct pci_dev *pdev = to_pci_dev(dev); 4351 struct serial_private *priv = pci_get_drvdata(pdev); 4352 int err; 4353 4354 if (priv) { 4355 /* 4356 * The device may have been disabled. Re-enable it. 4357 */ 4358 err = pci_enable_device(pdev); 4359 /* FIXME: We cannot simply error out here */ 4360 if (err) 4361 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4362 pciserial_resume_ports(priv); 4363 } 4364 return 0; 4365 } 4366 #endif 4367 4368 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4369 pciserial_resume_one); 4370 4371 static const struct pci_device_id serial_pci_tbl[] = { 4372 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4373 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, 4374 pbn_b0_4_921600 }, 4375 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4376 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4377 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4378 pbn_b2_8_921600 }, 4379 /* Advantech also use 0x3618 and 0xf618 */ 4380 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4381 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4382 pbn_b0_4_921600 }, 4383 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4384 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4385 pbn_b0_4_921600 }, 4386 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4387 PCI_SUBVENDOR_ID_CONNECT_TECH, 4388 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4389 pbn_b1_8_1382400 }, 4390 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4391 PCI_SUBVENDOR_ID_CONNECT_TECH, 4392 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4393 pbn_b1_4_1382400 }, 4394 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4395 PCI_SUBVENDOR_ID_CONNECT_TECH, 4396 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4397 pbn_b1_2_1382400 }, 4398 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4399 PCI_SUBVENDOR_ID_CONNECT_TECH, 4400 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4401 pbn_b1_8_1382400 }, 4402 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4403 PCI_SUBVENDOR_ID_CONNECT_TECH, 4404 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4405 pbn_b1_4_1382400 }, 4406 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4407 PCI_SUBVENDOR_ID_CONNECT_TECH, 4408 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4409 pbn_b1_2_1382400 }, 4410 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4411 PCI_SUBVENDOR_ID_CONNECT_TECH, 4412 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4413 pbn_b1_8_921600 }, 4414 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4415 PCI_SUBVENDOR_ID_CONNECT_TECH, 4416 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4417 pbn_b1_8_921600 }, 4418 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4419 PCI_SUBVENDOR_ID_CONNECT_TECH, 4420 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4421 pbn_b1_4_921600 }, 4422 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4423 PCI_SUBVENDOR_ID_CONNECT_TECH, 4424 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4425 pbn_b1_4_921600 }, 4426 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4427 PCI_SUBVENDOR_ID_CONNECT_TECH, 4428 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4429 pbn_b1_2_921600 }, 4430 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4431 PCI_SUBVENDOR_ID_CONNECT_TECH, 4432 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4433 pbn_b1_8_921600 }, 4434 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4435 PCI_SUBVENDOR_ID_CONNECT_TECH, 4436 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4437 pbn_b1_8_921600 }, 4438 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4439 PCI_SUBVENDOR_ID_CONNECT_TECH, 4440 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4441 pbn_b1_4_921600 }, 4442 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4443 PCI_SUBVENDOR_ID_CONNECT_TECH, 4444 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4445 pbn_b1_2_1250000 }, 4446 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4447 PCI_SUBVENDOR_ID_CONNECT_TECH, 4448 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4449 pbn_b0_2_1843200 }, 4450 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4451 PCI_SUBVENDOR_ID_CONNECT_TECH, 4452 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4453 pbn_b0_4_1843200 }, 4454 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4455 PCI_VENDOR_ID_AFAVLAB, 4456 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4457 pbn_b0_4_1152000 }, 4458 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4460 pbn_b2_bt_1_115200 }, 4461 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4463 pbn_b2_bt_2_115200 }, 4464 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4466 pbn_b2_bt_4_115200 }, 4467 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4469 pbn_b2_bt_2_115200 }, 4470 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4472 pbn_b2_bt_4_115200 }, 4473 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4475 pbn_b2_8_115200 }, 4476 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4478 pbn_b2_8_460800 }, 4479 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4481 pbn_b2_8_115200 }, 4482 4483 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4485 pbn_b2_bt_2_115200 }, 4486 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4488 pbn_b2_bt_2_921600 }, 4489 /* 4490 * VScom SPCOM800, from sl@s.pl 4491 */ 4492 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_b2_8_921600 }, 4495 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4497 pbn_b2_4_921600 }, 4498 /* Unknown card - subdevice 0x1584 */ 4499 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4500 PCI_VENDOR_ID_PLX, 4501 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4502 pbn_b2_4_115200 }, 4503 /* Unknown card - subdevice 0x1588 */ 4504 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4505 PCI_VENDOR_ID_PLX, 4506 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4507 pbn_b2_8_115200 }, 4508 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4509 PCI_SUBVENDOR_ID_KEYSPAN, 4510 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4511 pbn_panacom }, 4512 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4514 pbn_panacom4 }, 4515 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4517 pbn_panacom2 }, 4518 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4519 PCI_VENDOR_ID_ESDGMBH, 4520 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4521 pbn_b2_4_115200 }, 4522 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4523 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4524 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4525 pbn_b2_4_460800 }, 4526 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4527 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4528 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4529 pbn_b2_8_460800 }, 4530 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4531 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4532 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4533 pbn_b2_16_460800 }, 4534 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4535 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4536 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4537 pbn_b2_16_460800 }, 4538 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4539 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4540 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4541 pbn_b2_4_460800 }, 4542 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4543 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4544 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4545 pbn_b2_8_460800 }, 4546 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4547 PCI_SUBVENDOR_ID_EXSYS, 4548 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4549 pbn_b2_4_115200 }, 4550 /* 4551 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4552 * (Exoray@isys.ca) 4553 */ 4554 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4555 0x10b5, 0x106a, 0, 0, 4556 pbn_plx_romulus }, 4557 /* 4558 * Quatech cards. These actually have configurable clocks but for 4559 * now we just use the default. 4560 * 4561 * 100 series are RS232, 200 series RS422, 4562 */ 4563 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4565 pbn_b1_4_115200 }, 4566 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4568 pbn_b1_2_115200 }, 4569 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4571 pbn_b2_2_115200 }, 4572 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4574 pbn_b1_2_115200 }, 4575 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4577 pbn_b2_2_115200 }, 4578 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4580 pbn_b1_4_115200 }, 4581 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4583 pbn_b1_8_115200 }, 4584 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4586 pbn_b1_8_115200 }, 4587 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4589 pbn_b1_4_115200 }, 4590 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4592 pbn_b1_2_115200 }, 4593 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4595 pbn_b1_4_115200 }, 4596 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4598 pbn_b1_2_115200 }, 4599 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4601 pbn_b2_4_115200 }, 4602 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4604 pbn_b2_2_115200 }, 4605 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_b2_1_115200 }, 4608 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_b2_4_115200 }, 4611 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4613 pbn_b2_2_115200 }, 4614 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4616 pbn_b2_1_115200 }, 4617 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4619 pbn_b0_8_115200 }, 4620 4621 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4622 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4623 0, 0, 4624 pbn_b0_4_921600 }, 4625 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4626 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4627 0, 0, 4628 pbn_b0_4_1152000 }, 4629 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_b0_bt_2_921600 }, 4632 4633 /* 4634 * The below card is a little controversial since it is the 4635 * subject of a PCI vendor/device ID clash. (See 4636 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4637 * For now just used the hex ID 0x950a. 4638 */ 4639 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4640 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4641 0, 0, pbn_b0_2_115200 }, 4642 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4643 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4644 0, 0, pbn_b0_2_115200 }, 4645 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4647 pbn_b0_2_1130000 }, 4648 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4649 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4650 pbn_b0_1_921600 }, 4651 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4653 pbn_b0_4_115200 }, 4654 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4656 pbn_b0_bt_2_921600 }, 4657 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4659 pbn_b2_8_1152000 }, 4660 4661 /* 4662 * Oxford Semiconductor Inc. Tornado PCI express device range. 4663 */ 4664 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_b0_1_15625000 }, 4667 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4669 pbn_b0_1_15625000 }, 4670 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4672 pbn_oxsemi_1_15625000 }, 4673 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4675 pbn_oxsemi_1_15625000 }, 4676 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_b0_1_15625000 }, 4679 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4681 pbn_b0_1_15625000 }, 4682 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4684 pbn_oxsemi_1_15625000 }, 4685 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4687 pbn_oxsemi_1_15625000 }, 4688 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4690 pbn_b0_1_15625000 }, 4691 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4693 pbn_b0_1_15625000 }, 4694 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4696 pbn_b0_1_15625000 }, 4697 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4699 pbn_b0_1_15625000 }, 4700 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4702 pbn_oxsemi_2_15625000 }, 4703 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4705 pbn_oxsemi_2_15625000 }, 4706 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4708 pbn_oxsemi_4_15625000 }, 4709 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4711 pbn_oxsemi_4_15625000 }, 4712 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4714 pbn_oxsemi_8_15625000 }, 4715 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4717 pbn_oxsemi_8_15625000 }, 4718 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4720 pbn_oxsemi_1_15625000 }, 4721 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4723 pbn_oxsemi_1_15625000 }, 4724 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4726 pbn_oxsemi_1_15625000 }, 4727 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4729 pbn_oxsemi_1_15625000 }, 4730 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4732 pbn_oxsemi_1_15625000 }, 4733 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4735 pbn_oxsemi_1_15625000 }, 4736 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4738 pbn_oxsemi_1_15625000 }, 4739 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4741 pbn_oxsemi_1_15625000 }, 4742 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4744 pbn_oxsemi_1_15625000 }, 4745 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4747 pbn_oxsemi_1_15625000 }, 4748 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4750 pbn_oxsemi_1_15625000 }, 4751 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4753 pbn_oxsemi_1_15625000 }, 4754 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4756 pbn_oxsemi_1_15625000 }, 4757 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4759 pbn_oxsemi_1_15625000 }, 4760 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4762 pbn_oxsemi_1_15625000 }, 4763 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4765 pbn_oxsemi_1_15625000 }, 4766 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4768 pbn_oxsemi_1_15625000 }, 4769 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4771 pbn_oxsemi_1_15625000 }, 4772 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4774 pbn_oxsemi_1_15625000 }, 4775 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4777 pbn_oxsemi_1_15625000 }, 4778 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4780 pbn_oxsemi_1_15625000 }, 4781 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4783 pbn_oxsemi_1_15625000 }, 4784 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4786 pbn_oxsemi_1_15625000 }, 4787 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_oxsemi_1_15625000 }, 4790 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4792 pbn_oxsemi_1_15625000 }, 4793 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4795 pbn_oxsemi_1_15625000 }, 4796 /* 4797 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4798 */ 4799 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4800 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4801 pbn_oxsemi_1_15625000 }, 4802 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4803 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4804 pbn_oxsemi_2_15625000 }, 4805 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4806 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4807 pbn_oxsemi_4_15625000 }, 4808 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4809 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4810 pbn_oxsemi_8_15625000 }, 4811 4812 /* 4813 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4814 */ 4815 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4816 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4817 pbn_oxsemi_2_15625000 }, 4818 /* 4819 * EndRun Technologies. PCI express device range. 4820 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4821 */ 4822 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4824 pbn_oxsemi_2_15625000 }, 4825 4826 /* 4827 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4828 * from skokodyn@yahoo.com 4829 */ 4830 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4831 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4832 pbn_sbsxrsio }, 4833 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4834 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4835 pbn_sbsxrsio }, 4836 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4837 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4838 pbn_sbsxrsio }, 4839 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4840 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4841 pbn_sbsxrsio }, 4842 4843 /* 4844 * Digitan DS560-558, from jimd@esoft.com 4845 */ 4846 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4848 pbn_b1_1_115200 }, 4849 4850 /* 4851 * Titan Electronic cards 4852 * The 400L and 800L have a custom setup quirk. 4853 */ 4854 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4856 pbn_b0_1_921600 }, 4857 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4859 pbn_b0_2_921600 }, 4860 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b0_4_921600 }, 4863 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4865 pbn_b0_4_921600 }, 4866 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4868 pbn_b1_1_921600 }, 4869 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4871 pbn_b1_bt_2_921600 }, 4872 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4874 pbn_b0_bt_4_921600 }, 4875 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4877 pbn_b0_bt_8_921600 }, 4878 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4880 pbn_b4_bt_2_921600 }, 4881 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4883 pbn_b4_bt_4_921600 }, 4884 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4886 pbn_b4_bt_8_921600 }, 4887 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4889 pbn_b0_4_921600 }, 4890 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4892 pbn_b0_4_921600 }, 4893 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4895 pbn_b0_4_921600 }, 4896 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4898 pbn_titan_1_4000000 }, 4899 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4901 pbn_titan_2_4000000 }, 4902 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4904 pbn_titan_4_4000000 }, 4905 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4907 pbn_titan_8_4000000 }, 4908 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4910 pbn_titan_2_4000000 }, 4911 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4913 pbn_titan_2_4000000 }, 4914 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4916 pbn_b0_bt_2_921600 }, 4917 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4919 pbn_b0_4_921600 }, 4920 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4922 pbn_b0_4_921600 }, 4923 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4925 pbn_b0_4_921600 }, 4926 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4928 pbn_b0_4_921600 }, 4929 4930 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4932 pbn_b2_1_460800 }, 4933 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4935 pbn_b2_1_460800 }, 4936 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4938 pbn_b2_1_460800 }, 4939 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4941 pbn_b2_bt_2_921600 }, 4942 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4944 pbn_b2_bt_2_921600 }, 4945 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4947 pbn_b2_bt_2_921600 }, 4948 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4950 pbn_b2_bt_4_921600 }, 4951 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4953 pbn_b2_bt_4_921600 }, 4954 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4956 pbn_b2_bt_4_921600 }, 4957 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4959 pbn_b0_1_921600 }, 4960 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4962 pbn_b0_1_921600 }, 4963 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4965 pbn_b0_1_921600 }, 4966 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4968 pbn_b0_bt_2_921600 }, 4969 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4971 pbn_b0_bt_2_921600 }, 4972 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4974 pbn_b0_bt_2_921600 }, 4975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4977 pbn_b0_bt_4_921600 }, 4978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4980 pbn_b0_bt_4_921600 }, 4981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4983 pbn_b0_bt_4_921600 }, 4984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4986 pbn_b0_bt_8_921600 }, 4987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4989 pbn_b0_bt_8_921600 }, 4990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4992 pbn_b0_bt_8_921600 }, 4993 4994 /* 4995 * Computone devices submitted by Doug McNash dmcnash@computone.com 4996 */ 4997 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4998 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4999 0, 0, pbn_computone_4 }, 5000 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 5001 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 5002 0, 0, pbn_computone_8 }, 5003 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 5004 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 5005 0, 0, pbn_computone_6 }, 5006 5007 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5009 pbn_oxsemi }, 5010 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 5011 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 5012 pbn_b0_bt_1_921600 }, 5013 5014 /* 5015 * Sunix PCI serial boards 5016 */ 5017 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5018 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 5019 pbn_sunix_pci_1s }, 5020 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5021 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 5022 pbn_sunix_pci_2s }, 5023 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5024 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 5025 pbn_sunix_pci_4s }, 5026 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5027 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 5028 pbn_sunix_pci_4s }, 5029 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5030 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 5031 pbn_sunix_pci_8s }, 5032 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5033 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 5034 pbn_sunix_pci_8s }, 5035 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5036 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 5037 pbn_sunix_pci_16s }, 5038 5039 /* 5040 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 5041 */ 5042 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 5043 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5044 pbn_b0_bt_8_115200 }, 5045 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 5046 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5047 pbn_b0_bt_8_115200 }, 5048 5049 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5051 pbn_b0_bt_2_115200 }, 5052 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5054 pbn_b0_bt_2_115200 }, 5055 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5057 pbn_b0_bt_2_115200 }, 5058 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5060 pbn_b0_bt_4_460800 }, 5061 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5063 pbn_b0_bt_4_460800 }, 5064 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5066 pbn_b0_bt_2_460800 }, 5067 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5069 pbn_b0_bt_2_460800 }, 5070 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5072 pbn_b0_bt_2_460800 }, 5073 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5075 pbn_b0_bt_1_115200 }, 5076 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5078 pbn_b0_bt_1_460800 }, 5079 5080 /* 5081 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 5082 * Cards are identified by their subsystem vendor IDs, which 5083 * (in hex) match the model number. 5084 * 5085 * Note that JC140x are RS422/485 cards which require ox950 5086 * ACR = 0x10, and as such are not currently fully supported. 5087 */ 5088 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5089 0x1204, 0x0004, 0, 0, 5090 pbn_b0_4_921600 }, 5091 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5092 0x1208, 0x0004, 0, 0, 5093 pbn_b0_4_921600 }, 5094 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5095 0x1402, 0x0002, 0, 0, 5096 pbn_b0_2_921600 }, */ 5097 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5098 0x1404, 0x0004, 0, 0, 5099 pbn_b0_4_921600 }, */ 5100 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 5101 0x1208, 0x0004, 0, 0, 5102 pbn_b0_4_921600 }, 5103 5104 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5105 0x1204, 0x0004, 0, 0, 5106 pbn_b0_4_921600 }, 5107 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5108 0x1208, 0x0004, 0, 0, 5109 pbn_b0_4_921600 }, 5110 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 5111 0x1208, 0x0004, 0, 0, 5112 pbn_b0_4_921600 }, 5113 /* 5114 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 5115 */ 5116 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5118 pbn_b1_1_1382400 }, 5119 5120 /* 5121 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 5122 */ 5123 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 5124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5125 pbn_b1_1_1382400 }, 5126 5127 /* 5128 * RAStel 2 port modem, gerg@moreton.com.au 5129 */ 5130 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 5131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5132 pbn_b2_bt_2_115200 }, 5133 5134 /* 5135 * EKF addition for i960 Boards form EKF with serial port 5136 */ 5137 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 5138 0xE4BF, PCI_ANY_ID, 0, 0, 5139 pbn_intel_i960 }, 5140 5141 /* 5142 * Xircom Cardbus/Ethernet combos 5143 */ 5144 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 5145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5146 pbn_b0_1_115200 }, 5147 /* 5148 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 5149 */ 5150 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 5151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5152 pbn_b0_1_115200 }, 5153 5154 /* 5155 * Untested PCI modems, sent in from various folks... 5156 */ 5157 5158 /* 5159 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 5160 */ 5161 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 5162 0x1048, 0x1500, 0, 0, 5163 pbn_b1_1_115200 }, 5164 5165 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 5166 0xFF00, 0, 0, 0, 5167 pbn_sgi_ioc3 }, 5168 5169 /* 5170 * HP Diva card 5171 */ 5172 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5173 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 5174 pbn_b1_1_115200 }, 5175 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5177 pbn_b0_5_115200 }, 5178 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 5179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5180 pbn_b2_1_115200 }, 5181 /* HPE PCI serial device */ 5182 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 5183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5184 pbn_b1_1_115200 }, 5185 5186 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5188 pbn_b3_2_115200 }, 5189 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5191 pbn_b3_4_115200 }, 5192 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5194 pbn_b3_8_115200 }, 5195 /* 5196 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5197 */ 5198 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5200 pbn_b0_1_115200 }, 5201 /* 5202 * ITE 5203 */ 5204 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5205 PCI_ANY_ID, PCI_ANY_ID, 5206 0, 0, 5207 pbn_b1_bt_1_115200 }, 5208 5209 /* 5210 * IntaShield IS-100 5211 */ 5212 { PCI_VENDOR_ID_INTASHIELD, 0x0D60, 5213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5214 pbn_b2_1_115200 }, 5215 /* 5216 * IntaShield IS-200 5217 */ 5218 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */ 5220 pbn_b2_2_115200 }, 5221 /* 5222 * IntaShield IS-400 5223 */ 5224 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5226 pbn_b2_4_115200 }, 5227 /* 5228 * IntaShield IX-100 5229 */ 5230 { PCI_VENDOR_ID_INTASHIELD, 0x4027, 5231 PCI_ANY_ID, PCI_ANY_ID, 5232 0, 0, 5233 pbn_oxsemi_1_15625000 }, 5234 /* 5235 * IntaShield IX-200 5236 */ 5237 { PCI_VENDOR_ID_INTASHIELD, 0x4028, 5238 PCI_ANY_ID, PCI_ANY_ID, 5239 0, 0, 5240 pbn_oxsemi_2_15625000 }, 5241 /* 5242 * IntaShield IX-400 5243 */ 5244 { PCI_VENDOR_ID_INTASHIELD, 0x4029, 5245 PCI_ANY_ID, PCI_ANY_ID, 5246 0, 0, 5247 pbn_oxsemi_4_15625000 }, 5248 /* Brainboxes Devices */ 5249 /* 5250 * Brainboxes UC-101 5251 */ 5252 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 5253 PCI_ANY_ID, PCI_ANY_ID, 5254 0, 0, 5255 pbn_b2_2_115200 }, 5256 /* 5257 * Brainboxes UC-235/246 5258 */ 5259 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 5260 PCI_ANY_ID, PCI_ANY_ID, 5261 0, 0, 5262 pbn_b2_1_115200 }, 5263 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2, 5264 PCI_ANY_ID, PCI_ANY_ID, 5265 0, 0, 5266 pbn_b2_1_115200 }, 5267 /* 5268 * Brainboxes UC-253/UC-734 5269 */ 5270 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1, 5271 PCI_ANY_ID, PCI_ANY_ID, 5272 0, 0, 5273 pbn_b2_2_115200 }, 5274 /* 5275 * Brainboxes UC-260/271/701/756 5276 */ 5277 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5278 PCI_ANY_ID, PCI_ANY_ID, 5279 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5280 pbn_b2_4_115200 }, 5281 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5282 PCI_ANY_ID, PCI_ANY_ID, 5283 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5284 pbn_b2_4_115200 }, 5285 /* 5286 * Brainboxes UC-268 5287 */ 5288 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 5289 PCI_ANY_ID, PCI_ANY_ID, 5290 0, 0, 5291 pbn_b2_4_115200 }, 5292 /* 5293 * Brainboxes UC-275/279 5294 */ 5295 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 5296 PCI_ANY_ID, PCI_ANY_ID, 5297 0, 0, 5298 pbn_b2_8_115200 }, 5299 /* 5300 * Brainboxes UC-302 5301 */ 5302 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 5303 PCI_ANY_ID, PCI_ANY_ID, 5304 0, 0, 5305 pbn_b2_2_115200 }, 5306 { PCI_VENDOR_ID_INTASHIELD, 0x08E2, 5307 PCI_ANY_ID, PCI_ANY_ID, 5308 0, 0, 5309 pbn_b2_2_115200 }, 5310 { PCI_VENDOR_ID_INTASHIELD, 0x08E3, 5311 PCI_ANY_ID, PCI_ANY_ID, 5312 0, 0, 5313 pbn_b2_2_115200 }, 5314 /* 5315 * Brainboxes UC-310 5316 */ 5317 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5318 PCI_ANY_ID, PCI_ANY_ID, 5319 0, 0, 5320 pbn_b2_2_115200 }, 5321 /* 5322 * Brainboxes UC-313 5323 */ 5324 { PCI_VENDOR_ID_INTASHIELD, 0x08A1, 5325 PCI_ANY_ID, PCI_ANY_ID, 5326 0, 0, 5327 pbn_b2_2_115200 }, 5328 { PCI_VENDOR_ID_INTASHIELD, 0x08A2, 5329 PCI_ANY_ID, PCI_ANY_ID, 5330 0, 0, 5331 pbn_b2_2_115200 }, 5332 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5333 PCI_ANY_ID, PCI_ANY_ID, 5334 0, 0, 5335 pbn_b2_2_115200 }, 5336 /* 5337 * Brainboxes UC-320/324 5338 */ 5339 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5340 PCI_ANY_ID, PCI_ANY_ID, 5341 0, 0, 5342 pbn_b2_1_115200 }, 5343 /* 5344 * Brainboxes UC-346 5345 */ 5346 { PCI_VENDOR_ID_INTASHIELD, 0x0B01, 5347 PCI_ANY_ID, PCI_ANY_ID, 5348 0, 0, 5349 pbn_b2_4_115200 }, 5350 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5351 PCI_ANY_ID, PCI_ANY_ID, 5352 0, 0, 5353 pbn_b2_4_115200 }, 5354 /* 5355 * Brainboxes UC-357 5356 */ 5357 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5358 PCI_ANY_ID, PCI_ANY_ID, 5359 0, 0, 5360 pbn_b2_2_115200 }, 5361 { PCI_VENDOR_ID_INTASHIELD, 0x0A82, 5362 PCI_ANY_ID, PCI_ANY_ID, 5363 0, 0, 5364 pbn_b2_2_115200 }, 5365 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5366 PCI_ANY_ID, PCI_ANY_ID, 5367 0, 0, 5368 pbn_b2_2_115200 }, 5369 /* 5370 * Brainboxes UC-368 5371 */ 5372 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5373 PCI_ANY_ID, PCI_ANY_ID, 5374 0, 0, 5375 pbn_b2_4_115200 }, 5376 /* 5377 * Brainboxes UC-420 5378 */ 5379 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5380 PCI_ANY_ID, PCI_ANY_ID, 5381 0, 0, 5382 pbn_b2_4_115200 }, 5383 /* 5384 * Brainboxes UC-607 5385 */ 5386 { PCI_VENDOR_ID_INTASHIELD, 0x09A1, 5387 PCI_ANY_ID, PCI_ANY_ID, 5388 0, 0, 5389 pbn_b2_2_115200 }, 5390 { PCI_VENDOR_ID_INTASHIELD, 0x09A2, 5391 PCI_ANY_ID, PCI_ANY_ID, 5392 0, 0, 5393 pbn_b2_2_115200 }, 5394 { PCI_VENDOR_ID_INTASHIELD, 0x09A3, 5395 PCI_ANY_ID, PCI_ANY_ID, 5396 0, 0, 5397 pbn_b2_2_115200 }, 5398 /* 5399 * Brainboxes UC-836 5400 */ 5401 { PCI_VENDOR_ID_INTASHIELD, 0x0D41, 5402 PCI_ANY_ID, PCI_ANY_ID, 5403 0, 0, 5404 pbn_b2_4_115200 }, 5405 /* 5406 * Brainboxes UP-189 5407 */ 5408 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1, 5409 PCI_ANY_ID, PCI_ANY_ID, 5410 0, 0, 5411 pbn_b2_2_115200 }, 5412 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2, 5413 PCI_ANY_ID, PCI_ANY_ID, 5414 0, 0, 5415 pbn_b2_2_115200 }, 5416 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3, 5417 PCI_ANY_ID, PCI_ANY_ID, 5418 0, 0, 5419 pbn_b2_2_115200 }, 5420 /* 5421 * Brainboxes UP-200 5422 */ 5423 { PCI_VENDOR_ID_INTASHIELD, 0x0B21, 5424 PCI_ANY_ID, PCI_ANY_ID, 5425 0, 0, 5426 pbn_b2_2_115200 }, 5427 { PCI_VENDOR_ID_INTASHIELD, 0x0B22, 5428 PCI_ANY_ID, PCI_ANY_ID, 5429 0, 0, 5430 pbn_b2_2_115200 }, 5431 { PCI_VENDOR_ID_INTASHIELD, 0x0B23, 5432 PCI_ANY_ID, PCI_ANY_ID, 5433 0, 0, 5434 pbn_b2_2_115200 }, 5435 /* 5436 * Brainboxes UP-869 5437 */ 5438 { PCI_VENDOR_ID_INTASHIELD, 0x0C01, 5439 PCI_ANY_ID, PCI_ANY_ID, 5440 0, 0, 5441 pbn_b2_2_115200 }, 5442 { PCI_VENDOR_ID_INTASHIELD, 0x0C02, 5443 PCI_ANY_ID, PCI_ANY_ID, 5444 0, 0, 5445 pbn_b2_2_115200 }, 5446 { PCI_VENDOR_ID_INTASHIELD, 0x0C03, 5447 PCI_ANY_ID, PCI_ANY_ID, 5448 0, 0, 5449 pbn_b2_2_115200 }, 5450 /* 5451 * Brainboxes UP-880 5452 */ 5453 { PCI_VENDOR_ID_INTASHIELD, 0x0C21, 5454 PCI_ANY_ID, PCI_ANY_ID, 5455 0, 0, 5456 pbn_b2_2_115200 }, 5457 { PCI_VENDOR_ID_INTASHIELD, 0x0C22, 5458 PCI_ANY_ID, PCI_ANY_ID, 5459 0, 0, 5460 pbn_b2_2_115200 }, 5461 { PCI_VENDOR_ID_INTASHIELD, 0x0C23, 5462 PCI_ANY_ID, PCI_ANY_ID, 5463 0, 0, 5464 pbn_b2_2_115200 }, 5465 /* 5466 * Brainboxes PX-101 5467 */ 5468 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5469 PCI_ANY_ID, PCI_ANY_ID, 5470 0, 0, 5471 pbn_b0_2_115200 }, 5472 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5473 PCI_ANY_ID, PCI_ANY_ID, 5474 0, 0, 5475 pbn_oxsemi_2_15625000 }, 5476 /* 5477 * Brainboxes PX-235/246 5478 */ 5479 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5480 PCI_ANY_ID, PCI_ANY_ID, 5481 0, 0, 5482 pbn_b0_1_115200 }, 5483 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5484 PCI_ANY_ID, PCI_ANY_ID, 5485 0, 0, 5486 pbn_oxsemi_1_15625000 }, 5487 /* 5488 * Brainboxes PX-203/PX-257 5489 */ 5490 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5491 PCI_ANY_ID, PCI_ANY_ID, 5492 0, 0, 5493 pbn_b0_2_115200 }, 5494 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5495 PCI_ANY_ID, PCI_ANY_ID, 5496 0, 0, 5497 pbn_oxsemi_2_15625000 }, 5498 /* 5499 * Brainboxes PX-260/PX-701 5500 */ 5501 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5502 PCI_ANY_ID, PCI_ANY_ID, 5503 0, 0, 5504 pbn_oxsemi_4_15625000 }, 5505 /* 5506 * Brainboxes PX-275/279 5507 */ 5508 { PCI_VENDOR_ID_INTASHIELD, 0x0E41, 5509 PCI_ANY_ID, PCI_ANY_ID, 5510 0, 0, 5511 pbn_b2_8_115200 }, 5512 /* 5513 * Brainboxes PX-310 5514 */ 5515 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5516 PCI_ANY_ID, PCI_ANY_ID, 5517 0, 0, 5518 pbn_oxsemi_2_15625000 }, 5519 /* 5520 * Brainboxes PX-313 5521 */ 5522 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5523 PCI_ANY_ID, PCI_ANY_ID, 5524 0, 0, 5525 pbn_oxsemi_2_15625000 }, 5526 /* 5527 * Brainboxes PX-320/324/PX-376/PX-387 5528 */ 5529 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5530 PCI_ANY_ID, PCI_ANY_ID, 5531 0, 0, 5532 pbn_oxsemi_1_15625000 }, 5533 /* 5534 * Brainboxes PX-335/346 5535 */ 5536 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5537 PCI_ANY_ID, PCI_ANY_ID, 5538 0, 0, 5539 pbn_oxsemi_4_15625000 }, 5540 /* 5541 * Brainboxes PX-368 5542 */ 5543 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5544 PCI_ANY_ID, PCI_ANY_ID, 5545 0, 0, 5546 pbn_oxsemi_4_15625000 }, 5547 /* 5548 * Brainboxes PX-420 5549 */ 5550 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5551 PCI_ANY_ID, PCI_ANY_ID, 5552 0, 0, 5553 pbn_b0_4_115200 }, 5554 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5555 PCI_ANY_ID, PCI_ANY_ID, 5556 0, 0, 5557 pbn_oxsemi_4_15625000 }, 5558 /* 5559 * Brainboxes PX-475 5560 */ 5561 { PCI_VENDOR_ID_INTASHIELD, 0x401D, 5562 PCI_ANY_ID, PCI_ANY_ID, 5563 0, 0, 5564 pbn_oxsemi_1_15625000 }, 5565 /* 5566 * Brainboxes PX-803/PX-857 5567 */ 5568 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5569 PCI_ANY_ID, PCI_ANY_ID, 5570 0, 0, 5571 pbn_b0_2_115200 }, 5572 { PCI_VENDOR_ID_INTASHIELD, 0x4018, 5573 PCI_ANY_ID, PCI_ANY_ID, 5574 0, 0, 5575 pbn_oxsemi_2_15625000 }, 5576 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5577 PCI_ANY_ID, PCI_ANY_ID, 5578 0, 0, 5579 pbn_oxsemi_2_15625000 }, 5580 /* 5581 * Brainboxes PX-820 5582 */ 5583 { PCI_VENDOR_ID_INTASHIELD, 0x4002, 5584 PCI_ANY_ID, PCI_ANY_ID, 5585 0, 0, 5586 pbn_b0_4_115200 }, 5587 { PCI_VENDOR_ID_INTASHIELD, 0x4013, 5588 PCI_ANY_ID, PCI_ANY_ID, 5589 0, 0, 5590 pbn_oxsemi_4_15625000 }, 5591 /* 5592 * Brainboxes PX-835/PX-846 5593 */ 5594 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5595 PCI_ANY_ID, PCI_ANY_ID, 5596 0, 0, 5597 pbn_b0_1_115200 }, 5598 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5599 PCI_ANY_ID, PCI_ANY_ID, 5600 0, 0, 5601 pbn_oxsemi_1_15625000 }, 5602 5603 /* 5604 * Perle PCI-RAS cards 5605 */ 5606 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5607 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5608 0, 0, pbn_b2_4_921600 }, 5609 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5610 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5611 0, 0, pbn_b2_8_921600 }, 5612 5613 /* 5614 * Mainpine series cards: Fairly standard layout but fools 5615 * parts of the autodetect in some cases and uses otherwise 5616 * unmatched communications subclasses in the PCI Express case 5617 */ 5618 5619 { /* RockForceDUO */ 5620 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5621 PCI_VENDOR_ID_MAINPINE, 0x0200, 5622 0, 0, pbn_b0_2_115200 }, 5623 { /* RockForceQUATRO */ 5624 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5625 PCI_VENDOR_ID_MAINPINE, 0x0300, 5626 0, 0, pbn_b0_4_115200 }, 5627 { /* RockForceDUO+ */ 5628 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5629 PCI_VENDOR_ID_MAINPINE, 0x0400, 5630 0, 0, pbn_b0_2_115200 }, 5631 { /* RockForceQUATRO+ */ 5632 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5633 PCI_VENDOR_ID_MAINPINE, 0x0500, 5634 0, 0, pbn_b0_4_115200 }, 5635 { /* RockForce+ */ 5636 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5637 PCI_VENDOR_ID_MAINPINE, 0x0600, 5638 0, 0, pbn_b0_2_115200 }, 5639 { /* RockForce+ */ 5640 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5641 PCI_VENDOR_ID_MAINPINE, 0x0700, 5642 0, 0, pbn_b0_4_115200 }, 5643 { /* RockForceOCTO+ */ 5644 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5645 PCI_VENDOR_ID_MAINPINE, 0x0800, 5646 0, 0, pbn_b0_8_115200 }, 5647 { /* RockForceDUO+ */ 5648 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5649 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5650 0, 0, pbn_b0_2_115200 }, 5651 { /* RockForceQUARTRO+ */ 5652 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5653 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5654 0, 0, pbn_b0_4_115200 }, 5655 { /* RockForceOCTO+ */ 5656 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5657 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5658 0, 0, pbn_b0_8_115200 }, 5659 { /* RockForceD1 */ 5660 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5661 PCI_VENDOR_ID_MAINPINE, 0x2000, 5662 0, 0, pbn_b0_1_115200 }, 5663 { /* RockForceF1 */ 5664 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5665 PCI_VENDOR_ID_MAINPINE, 0x2100, 5666 0, 0, pbn_b0_1_115200 }, 5667 { /* RockForceD2 */ 5668 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5669 PCI_VENDOR_ID_MAINPINE, 0x2200, 5670 0, 0, pbn_b0_2_115200 }, 5671 { /* RockForceF2 */ 5672 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5673 PCI_VENDOR_ID_MAINPINE, 0x2300, 5674 0, 0, pbn_b0_2_115200 }, 5675 { /* RockForceD4 */ 5676 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5677 PCI_VENDOR_ID_MAINPINE, 0x2400, 5678 0, 0, pbn_b0_4_115200 }, 5679 { /* RockForceF4 */ 5680 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5681 PCI_VENDOR_ID_MAINPINE, 0x2500, 5682 0, 0, pbn_b0_4_115200 }, 5683 { /* RockForceD8 */ 5684 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5685 PCI_VENDOR_ID_MAINPINE, 0x2600, 5686 0, 0, pbn_b0_8_115200 }, 5687 { /* RockForceF8 */ 5688 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5689 PCI_VENDOR_ID_MAINPINE, 0x2700, 5690 0, 0, pbn_b0_8_115200 }, 5691 { /* IQ Express D1 */ 5692 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5693 PCI_VENDOR_ID_MAINPINE, 0x3000, 5694 0, 0, pbn_b0_1_115200 }, 5695 { /* IQ Express F1 */ 5696 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5697 PCI_VENDOR_ID_MAINPINE, 0x3100, 5698 0, 0, pbn_b0_1_115200 }, 5699 { /* IQ Express D2 */ 5700 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5701 PCI_VENDOR_ID_MAINPINE, 0x3200, 5702 0, 0, pbn_b0_2_115200 }, 5703 { /* IQ Express F2 */ 5704 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5705 PCI_VENDOR_ID_MAINPINE, 0x3300, 5706 0, 0, pbn_b0_2_115200 }, 5707 { /* IQ Express D4 */ 5708 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5709 PCI_VENDOR_ID_MAINPINE, 0x3400, 5710 0, 0, pbn_b0_4_115200 }, 5711 { /* IQ Express F4 */ 5712 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5713 PCI_VENDOR_ID_MAINPINE, 0x3500, 5714 0, 0, pbn_b0_4_115200 }, 5715 { /* IQ Express D8 */ 5716 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5717 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5718 0, 0, pbn_b0_8_115200 }, 5719 { /* IQ Express F8 */ 5720 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5721 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5722 0, 0, pbn_b0_8_115200 }, 5723 5724 5725 /* 5726 * PA Semi PA6T-1682M on-chip UART 5727 */ 5728 { PCI_VENDOR_ID_PASEMI, 0xa004, 5729 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5730 pbn_pasemi_1682M }, 5731 5732 /* 5733 * National Instruments 5734 */ 5735 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5737 pbn_b1_16_115200 }, 5738 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5740 pbn_b1_8_115200 }, 5741 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5743 pbn_b1_bt_4_115200 }, 5744 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5746 pbn_b1_bt_2_115200 }, 5747 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5749 pbn_b1_bt_4_115200 }, 5750 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5752 pbn_b1_bt_2_115200 }, 5753 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5755 pbn_b1_16_115200 }, 5756 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5758 pbn_b1_8_115200 }, 5759 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5761 pbn_b1_bt_4_115200 }, 5762 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5764 pbn_b1_bt_2_115200 }, 5765 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5767 pbn_b1_bt_4_115200 }, 5768 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5770 pbn_b1_bt_2_115200 }, 5771 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5773 pbn_ni8430_2 }, 5774 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5775 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5776 pbn_ni8430_2 }, 5777 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5779 pbn_ni8430_4 }, 5780 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5782 pbn_ni8430_4 }, 5783 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5785 pbn_ni8430_8 }, 5786 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5788 pbn_ni8430_8 }, 5789 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5791 pbn_ni8430_16 }, 5792 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5794 pbn_ni8430_16 }, 5795 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5796 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5797 pbn_ni8430_2 }, 5798 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5800 pbn_ni8430_2 }, 5801 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5802 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5803 pbn_ni8430_4 }, 5804 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5806 pbn_ni8430_4 }, 5807 5808 /* 5809 * MOXA 5810 */ 5811 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 }, 5812 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 }, 5813 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 }, 5814 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 }, 5815 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 }, 5816 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 }, 5817 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 }, 5818 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 }, 5819 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 }, 5820 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 }, 5821 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 }, 5822 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 }, 5823 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 }, 5824 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 }, 5825 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 }, 5826 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 }, 5827 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 }, 5828 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 }, 5829 5830 /* 5831 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5832 */ 5833 { PCI_VENDOR_ID_ADDIDATA, 5834 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5835 PCI_ANY_ID, 5836 PCI_ANY_ID, 5837 0, 5838 0, 5839 pbn_b0_4_115200 }, 5840 5841 { PCI_VENDOR_ID_ADDIDATA, 5842 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5843 PCI_ANY_ID, 5844 PCI_ANY_ID, 5845 0, 5846 0, 5847 pbn_b0_2_115200 }, 5848 5849 { PCI_VENDOR_ID_ADDIDATA, 5850 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5851 PCI_ANY_ID, 5852 PCI_ANY_ID, 5853 0, 5854 0, 5855 pbn_b0_1_115200 }, 5856 5857 { PCI_VENDOR_ID_AMCC, 5858 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5859 PCI_ANY_ID, 5860 PCI_ANY_ID, 5861 0, 5862 0, 5863 pbn_b1_8_115200 }, 5864 5865 { PCI_VENDOR_ID_ADDIDATA, 5866 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5867 PCI_ANY_ID, 5868 PCI_ANY_ID, 5869 0, 5870 0, 5871 pbn_b0_4_115200 }, 5872 5873 { PCI_VENDOR_ID_ADDIDATA, 5874 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5875 PCI_ANY_ID, 5876 PCI_ANY_ID, 5877 0, 5878 0, 5879 pbn_b0_2_115200 }, 5880 5881 { PCI_VENDOR_ID_ADDIDATA, 5882 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5883 PCI_ANY_ID, 5884 PCI_ANY_ID, 5885 0, 5886 0, 5887 pbn_b0_1_115200 }, 5888 5889 { PCI_VENDOR_ID_ADDIDATA, 5890 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5891 PCI_ANY_ID, 5892 PCI_ANY_ID, 5893 0, 5894 0, 5895 pbn_b0_4_115200 }, 5896 5897 { PCI_VENDOR_ID_ADDIDATA, 5898 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5899 PCI_ANY_ID, 5900 PCI_ANY_ID, 5901 0, 5902 0, 5903 pbn_b0_2_115200 }, 5904 5905 { PCI_VENDOR_ID_ADDIDATA, 5906 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5907 PCI_ANY_ID, 5908 PCI_ANY_ID, 5909 0, 5910 0, 5911 pbn_b0_1_115200 }, 5912 5913 { PCI_VENDOR_ID_ADDIDATA, 5914 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5915 PCI_ANY_ID, 5916 PCI_ANY_ID, 5917 0, 5918 0, 5919 pbn_b0_8_115200 }, 5920 5921 { PCI_VENDOR_ID_ADDIDATA, 5922 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5923 PCI_ANY_ID, 5924 PCI_ANY_ID, 5925 0, 5926 0, 5927 pbn_ADDIDATA_PCIe_4_3906250 }, 5928 5929 { PCI_VENDOR_ID_ADDIDATA, 5930 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5931 PCI_ANY_ID, 5932 PCI_ANY_ID, 5933 0, 5934 0, 5935 pbn_ADDIDATA_PCIe_2_3906250 }, 5936 5937 { PCI_VENDOR_ID_ADDIDATA, 5938 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5939 PCI_ANY_ID, 5940 PCI_ANY_ID, 5941 0, 5942 0, 5943 pbn_ADDIDATA_PCIe_1_3906250 }, 5944 5945 { PCI_VENDOR_ID_ADDIDATA, 5946 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5947 PCI_ANY_ID, 5948 PCI_ANY_ID, 5949 0, 5950 0, 5951 pbn_ADDIDATA_PCIe_8_3906250 }, 5952 5953 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5954 PCI_VENDOR_ID_IBM, 0x0299, 5955 0, 0, pbn_b0_bt_2_115200 }, 5956 5957 /* 5958 * other NetMos 9835 devices are most likely handled by the 5959 * parport_serial driver, check drivers/parport/parport_serial.c 5960 * before adding them here. 5961 */ 5962 5963 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5964 0xA000, 0x1000, 5965 0, 0, pbn_b0_1_115200 }, 5966 5967 /* the 9901 is a rebranded 9912 */ 5968 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5969 0xA000, 0x1000, 5970 0, 0, pbn_b0_1_115200 }, 5971 5972 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5973 0xA000, 0x1000, 5974 0, 0, pbn_b0_1_115200 }, 5975 5976 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5977 0xA000, 0x1000, 5978 0, 0, pbn_b0_1_115200 }, 5979 5980 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5981 0xA000, 0x1000, 5982 0, 0, pbn_b0_1_115200 }, 5983 5984 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5985 0xA000, 0x3002, 5986 0, 0, pbn_NETMOS9900_2s_115200 }, 5987 5988 /* 5989 * Best Connectivity and Rosewill PCI Multi I/O cards 5990 */ 5991 5992 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5993 0xA000, 0x1000, 5994 0, 0, pbn_b0_1_115200 }, 5995 5996 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5997 0xA000, 0x3002, 5998 0, 0, pbn_b0_bt_2_115200 }, 5999 6000 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 6001 0xA000, 0x3004, 6002 0, 0, pbn_b0_bt_4_115200 }, 6003 6004 /* 6005 * ASIX AX99100 PCIe to Multi I/O Controller 6006 */ 6007 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 6008 0xA000, 0x1000, 6009 0, 0, pbn_b0_1_115200 }, 6010 6011 /* Intel CE4100 */ 6012 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 6013 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6014 pbn_ce4100_1_115200 }, 6015 6016 /* 6017 * Cronyx Omega PCI 6018 */ 6019 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 6020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6021 pbn_omegapci }, 6022 6023 /* 6024 * Broadcom TruManage 6025 */ 6026 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 6027 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6028 pbn_brcm_trumanage }, 6029 6030 /* 6031 * AgeStar as-prs2-009 6032 */ 6033 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 6034 PCI_ANY_ID, PCI_ANY_ID, 6035 0, 0, pbn_b0_bt_2_115200 }, 6036 6037 /* 6038 * WCH CH353 series devices: The 2S1P is handled by parport_serial 6039 * so not listed here. 6040 */ 6041 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S, 6042 PCI_ANY_ID, PCI_ANY_ID, 6043 0, 0, pbn_b0_bt_4_115200 }, 6044 6045 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF, 6046 PCI_ANY_ID, PCI_ANY_ID, 6047 0, 0, pbn_b0_bt_2_115200 }, 6048 6049 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S, 6050 PCI_ANY_ID, PCI_ANY_ID, 6051 0, 0, pbn_b0_bt_4_115200 }, 6052 6053 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S, 6054 PCI_ANY_ID, PCI_ANY_ID, 6055 0, 0, pbn_wch382_2 }, 6056 6057 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S, 6058 PCI_ANY_ID, PCI_ANY_ID, 6059 0, 0, pbn_wch384_4 }, 6060 6061 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S, 6062 PCI_ANY_ID, PCI_ANY_ID, 6063 0, 0, pbn_wch384_8 }, 6064 /* 6065 * Realtek RealManage 6066 */ 6067 { PCI_VENDOR_ID_REALTEK, 0x816a, 6068 PCI_ANY_ID, PCI_ANY_ID, 6069 0, 0, pbn_b0_1_115200 }, 6070 6071 { PCI_VENDOR_ID_REALTEK, 0x816b, 6072 PCI_ANY_ID, PCI_ANY_ID, 6073 0, 0, pbn_b0_1_115200 }, 6074 6075 /* Fintek PCI serial cards */ 6076 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 6077 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 6078 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 6079 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 6080 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 6081 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 6082 6083 /* MKS Tenta SCOM-080x serial cards */ 6084 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 6085 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 6086 6087 /* Amazon PCI serial device */ 6088 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 6089 6090 /* 6091 * These entries match devices with class COMMUNICATION_SERIAL, 6092 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 6093 */ 6094 { PCI_ANY_ID, PCI_ANY_ID, 6095 PCI_ANY_ID, PCI_ANY_ID, 6096 PCI_CLASS_COMMUNICATION_SERIAL << 8, 6097 0xffff00, pbn_default }, 6098 { PCI_ANY_ID, PCI_ANY_ID, 6099 PCI_ANY_ID, PCI_ANY_ID, 6100 PCI_CLASS_COMMUNICATION_MODEM << 8, 6101 0xffff00, pbn_default }, 6102 { PCI_ANY_ID, PCI_ANY_ID, 6103 PCI_ANY_ID, PCI_ANY_ID, 6104 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 6105 0xffff00, pbn_default }, 6106 { 0, } 6107 }; 6108 6109 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 6110 pci_channel_state_t state) 6111 { 6112 struct serial_private *priv = pci_get_drvdata(dev); 6113 6114 if (state == pci_channel_io_perm_failure) 6115 return PCI_ERS_RESULT_DISCONNECT; 6116 6117 if (priv) 6118 pciserial_detach_ports(priv); 6119 6120 pci_disable_device(dev); 6121 6122 return PCI_ERS_RESULT_NEED_RESET; 6123 } 6124 6125 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 6126 { 6127 int rc; 6128 6129 rc = pci_enable_device(dev); 6130 6131 if (rc) 6132 return PCI_ERS_RESULT_DISCONNECT; 6133 6134 pci_restore_state(dev); 6135 pci_save_state(dev); 6136 6137 return PCI_ERS_RESULT_RECOVERED; 6138 } 6139 6140 static void serial8250_io_resume(struct pci_dev *dev) 6141 { 6142 struct serial_private *priv = pci_get_drvdata(dev); 6143 struct serial_private *new; 6144 6145 if (!priv) 6146 return; 6147 6148 new = pciserial_init_ports(dev, priv->board); 6149 if (!IS_ERR(new)) { 6150 pci_set_drvdata(dev, new); 6151 kfree(priv); 6152 } 6153 } 6154 6155 static const struct pci_error_handlers serial8250_err_handler = { 6156 .error_detected = serial8250_io_error_detected, 6157 .slot_reset = serial8250_io_slot_reset, 6158 .resume = serial8250_io_resume, 6159 }; 6160 6161 static struct pci_driver serial_pci_driver = { 6162 .name = "serial", 6163 .probe = pciserial_init_one, 6164 .remove = pciserial_remove_one, 6165 .driver = { 6166 .pm = &pciserial_pm_ops, 6167 }, 6168 .id_table = serial_pci_tbl, 6169 .err_handler = &serial8250_err_handler, 6170 }; 6171 6172 module_pci_driver(serial_pci_driver); 6173 6174 MODULE_LICENSE("GPL"); 6175 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 6176 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 6177 MODULE_IMPORT_NS("SERIAL_8250_PCI"); 6178