1 /* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12 #undef DEBUG 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/tty.h> 20 #include <linux/serial_reg.h> 21 #include <linux/serial_core.h> 22 #include <linux/8250_pci.h> 23 #include <linux/bitops.h> 24 25 #include <asm/byteorder.h> 26 #include <asm/io.h> 27 28 #include "8250.h" 29 30 /* 31 * init function returns: 32 * > 0 - number of ports 33 * = 0 - use board->num_ports 34 * < 0 - error 35 */ 36 struct pci_serial_quirk { 37 u32 vendor; 38 u32 device; 39 u32 subvendor; 40 u32 subdevice; 41 int (*probe)(struct pci_dev *dev); 42 int (*init)(struct pci_dev *dev); 43 int (*setup)(struct serial_private *, 44 const struct pciserial_board *, 45 struct uart_8250_port *, int); 46 void (*exit)(struct pci_dev *dev); 47 }; 48 49 #define PCI_NUM_BAR_RESOURCES 6 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 int line[0]; 56 }; 57 58 static int pci_default_setup(struct serial_private*, 59 const struct pciserial_board*, struct uart_8250_port *, int); 60 61 static void moan_device(const char *str, struct pci_dev *dev) 62 { 63 dev_err(&dev->dev, 64 "%s: %s\n" 65 "Please send the output of lspci -vv, this\n" 66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 67 "manufacturer and name of serial board or\n" 68 "modem board to <linux-serial@vger.kernel.org>.\n", 69 pci_name(dev), str, dev->vendor, dev->device, 70 dev->subsystem_vendor, dev->subsystem_device); 71 } 72 73 static int 74 setup_port(struct serial_private *priv, struct uart_8250_port *port, 75 int bar, int offset, int regshift) 76 { 77 struct pci_dev *dev = priv->dev; 78 79 if (bar >= PCI_NUM_BAR_RESOURCES) 80 return -EINVAL; 81 82 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 83 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 84 return -ENOMEM; 85 86 port->port.iotype = UPIO_MEM; 87 port->port.iobase = 0; 88 port->port.mapbase = pci_resource_start(dev, bar) + offset; 89 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 90 port->port.regshift = regshift; 91 } else { 92 port->port.iotype = UPIO_PORT; 93 port->port.iobase = pci_resource_start(dev, bar) + offset; 94 port->port.mapbase = 0; 95 port->port.membase = NULL; 96 port->port.regshift = 0; 97 } 98 return 0; 99 } 100 101 /* 102 * ADDI-DATA GmbH communication cards <info@addi-data.com> 103 */ 104 static int addidata_apci7800_setup(struct serial_private *priv, 105 const struct pciserial_board *board, 106 struct uart_8250_port *port, int idx) 107 { 108 unsigned int bar = 0, offset = board->first_offset; 109 bar = FL_GET_BASE(board->flags); 110 111 if (idx < 2) { 112 offset += idx * board->uart_offset; 113 } else if ((idx >= 2) && (idx < 4)) { 114 bar += 1; 115 offset += ((idx - 2) * board->uart_offset); 116 } else if ((idx >= 4) && (idx < 6)) { 117 bar += 2; 118 offset += ((idx - 4) * board->uart_offset); 119 } else if (idx >= 6) { 120 bar += 3; 121 offset += ((idx - 6) * board->uart_offset); 122 } 123 124 return setup_port(priv, port, bar, offset, board->reg_shift); 125 } 126 127 /* 128 * AFAVLAB uses a different mixture of BARs and offsets 129 * Not that ugly ;) -- HW 130 */ 131 static int 132 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 133 struct uart_8250_port *port, int idx) 134 { 135 unsigned int bar, offset = board->first_offset; 136 137 bar = FL_GET_BASE(board->flags); 138 if (idx < 4) 139 bar += idx; 140 else { 141 bar = 4; 142 offset += (idx - 4) * board->uart_offset; 143 } 144 145 return setup_port(priv, port, bar, offset, board->reg_shift); 146 } 147 148 /* 149 * HP's Remote Management Console. The Diva chip came in several 150 * different versions. N-class, L2000 and A500 have two Diva chips, each 151 * with 3 UARTs (the third UART on the second chip is unused). Superdome 152 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 153 * one Diva chip, but it has been expanded to 5 UARTs. 154 */ 155 static int pci_hp_diva_init(struct pci_dev *dev) 156 { 157 int rc = 0; 158 159 switch (dev->subsystem_device) { 160 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 161 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 162 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 163 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 164 rc = 3; 165 break; 166 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 167 rc = 2; 168 break; 169 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 170 rc = 4; 171 break; 172 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 173 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 174 rc = 1; 175 break; 176 } 177 178 return rc; 179 } 180 181 /* 182 * HP's Diva chip puts the 4th/5th serial port further out, and 183 * some serial ports are supposed to be hidden on certain models. 184 */ 185 static int 186 pci_hp_diva_setup(struct serial_private *priv, 187 const struct pciserial_board *board, 188 struct uart_8250_port *port, int idx) 189 { 190 unsigned int offset = board->first_offset; 191 unsigned int bar = FL_GET_BASE(board->flags); 192 193 switch (priv->dev->subsystem_device) { 194 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 195 if (idx == 3) 196 idx++; 197 break; 198 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 199 if (idx > 0) 200 idx++; 201 if (idx > 2) 202 idx++; 203 break; 204 } 205 if (idx > 2) 206 offset = 0x18; 207 208 offset += idx * board->uart_offset; 209 210 return setup_port(priv, port, bar, offset, board->reg_shift); 211 } 212 213 /* 214 * Added for EKF Intel i960 serial boards 215 */ 216 static int pci_inteli960ni_init(struct pci_dev *dev) 217 { 218 u32 oldval; 219 220 if (!(dev->subsystem_device & 0x1000)) 221 return -ENODEV; 222 223 /* is firmware started? */ 224 pci_read_config_dword(dev, 0x44, &oldval); 225 if (oldval == 0x00001000L) { /* RESET value */ 226 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 227 return -ENODEV; 228 } 229 return 0; 230 } 231 232 /* 233 * Some PCI serial cards using the PLX 9050 PCI interface chip require 234 * that the card interrupt be explicitly enabled or disabled. This 235 * seems to be mainly needed on card using the PLX which also use I/O 236 * mapped memory. 237 */ 238 static int pci_plx9050_init(struct pci_dev *dev) 239 { 240 u8 irq_config; 241 void __iomem *p; 242 243 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 244 moan_device("no memory in bar 0", dev); 245 return 0; 246 } 247 248 irq_config = 0x41; 249 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 250 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 251 irq_config = 0x43; 252 253 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 254 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 255 /* 256 * As the megawolf cards have the int pins active 257 * high, and have 2 UART chips, both ints must be 258 * enabled on the 9050. Also, the UARTS are set in 259 * 16450 mode by default, so we have to enable the 260 * 16C950 'enhanced' mode so that we can use the 261 * deep FIFOs 262 */ 263 irq_config = 0x5b; 264 /* 265 * enable/disable interrupts 266 */ 267 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 268 if (p == NULL) 269 return -ENOMEM; 270 writel(irq_config, p + 0x4c); 271 272 /* 273 * Read the register back to ensure that it took effect. 274 */ 275 readl(p + 0x4c); 276 iounmap(p); 277 278 return 0; 279 } 280 281 static void pci_plx9050_exit(struct pci_dev *dev) 282 { 283 u8 __iomem *p; 284 285 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 286 return; 287 288 /* 289 * disable interrupts 290 */ 291 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 292 if (p != NULL) { 293 writel(0, p + 0x4c); 294 295 /* 296 * Read the register back to ensure that it took effect. 297 */ 298 readl(p + 0x4c); 299 iounmap(p); 300 } 301 } 302 303 #define NI8420_INT_ENABLE_REG 0x38 304 #define NI8420_INT_ENABLE_BIT 0x2000 305 306 static void pci_ni8420_exit(struct pci_dev *dev) 307 { 308 void __iomem *p; 309 unsigned int bar = 0; 310 311 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 312 moan_device("no memory in bar", dev); 313 return; 314 } 315 316 p = pci_ioremap_bar(dev, bar); 317 if (p == NULL) 318 return; 319 320 /* Disable the CPU Interrupt */ 321 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 322 p + NI8420_INT_ENABLE_REG); 323 iounmap(p); 324 } 325 326 327 /* MITE registers */ 328 #define MITE_IOWBSR1 0xc4 329 #define MITE_IOWCR1 0xf4 330 #define MITE_LCIMR1 0x08 331 #define MITE_LCIMR2 0x10 332 333 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 334 335 static void pci_ni8430_exit(struct pci_dev *dev) 336 { 337 void __iomem *p; 338 unsigned int bar = 0; 339 340 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 341 moan_device("no memory in bar", dev); 342 return; 343 } 344 345 p = pci_ioremap_bar(dev, bar); 346 if (p == NULL) 347 return; 348 349 /* Disable the CPU Interrupt */ 350 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 351 iounmap(p); 352 } 353 354 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 355 static int 356 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 357 struct uart_8250_port *port, int idx) 358 { 359 unsigned int bar, offset = board->first_offset; 360 361 bar = 0; 362 363 if (idx < 4) { 364 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 365 offset += idx * board->uart_offset; 366 } else if (idx < 8) { 367 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 368 offset += idx * board->uart_offset + 0xC00; 369 } else /* we have only 8 ports on PMC-OCTALPRO */ 370 return 1; 371 372 return setup_port(priv, port, bar, offset, board->reg_shift); 373 } 374 375 /* 376 * This does initialization for PMC OCTALPRO cards: 377 * maps the device memory, resets the UARTs (needed, bc 378 * if the module is removed and inserted again, the card 379 * is in the sleep mode) and enables global interrupt. 380 */ 381 382 /* global control register offset for SBS PMC-OctalPro */ 383 #define OCT_REG_CR_OFF 0x500 384 385 static int sbs_init(struct pci_dev *dev) 386 { 387 u8 __iomem *p; 388 389 p = pci_ioremap_bar(dev, 0); 390 391 if (p == NULL) 392 return -ENOMEM; 393 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 394 writeb(0x10, p + OCT_REG_CR_OFF); 395 udelay(50); 396 writeb(0x0, p + OCT_REG_CR_OFF); 397 398 /* Set bit-2 (INTENABLE) of Control Register */ 399 writeb(0x4, p + OCT_REG_CR_OFF); 400 iounmap(p); 401 402 return 0; 403 } 404 405 /* 406 * Disables the global interrupt of PMC-OctalPro 407 */ 408 409 static void sbs_exit(struct pci_dev *dev) 410 { 411 u8 __iomem *p; 412 413 p = pci_ioremap_bar(dev, 0); 414 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 415 if (p != NULL) 416 writeb(0, p + OCT_REG_CR_OFF); 417 iounmap(p); 418 } 419 420 /* 421 * SIIG serial cards have an PCI interface chip which also controls 422 * the UART clocking frequency. Each UART can be clocked independently 423 * (except cards equipped with 4 UARTs) and initial clocking settings 424 * are stored in the EEPROM chip. It can cause problems because this 425 * version of serial driver doesn't support differently clocked UART's 426 * on single PCI card. To prevent this, initialization functions set 427 * high frequency clocking for all UART's on given card. It is safe (I 428 * hope) because it doesn't touch EEPROM settings to prevent conflicts 429 * with other OSes (like M$ DOS). 430 * 431 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 432 * 433 * There is two family of SIIG serial cards with different PCI 434 * interface chip and different configuration methods: 435 * - 10x cards have control registers in IO and/or memory space; 436 * - 20x cards have control registers in standard PCI configuration space. 437 * 438 * Note: all 10x cards have PCI device ids 0x10.. 439 * all 20x cards have PCI device ids 0x20.. 440 * 441 * There are also Quartet Serial cards which use Oxford Semiconductor 442 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 443 * 444 * Note: some SIIG cards are probed by the parport_serial object. 445 */ 446 447 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 448 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 449 450 static int pci_siig10x_init(struct pci_dev *dev) 451 { 452 u16 data; 453 void __iomem *p; 454 455 switch (dev->device & 0xfff8) { 456 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 457 data = 0xffdf; 458 break; 459 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 460 data = 0xf7ff; 461 break; 462 default: /* 1S1P, 4S */ 463 data = 0xfffb; 464 break; 465 } 466 467 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 468 if (p == NULL) 469 return -ENOMEM; 470 471 writew(readw(p + 0x28) & data, p + 0x28); 472 readw(p + 0x28); 473 iounmap(p); 474 return 0; 475 } 476 477 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 478 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 479 480 static int pci_siig20x_init(struct pci_dev *dev) 481 { 482 u8 data; 483 484 /* Change clock frequency for the first UART. */ 485 pci_read_config_byte(dev, 0x6f, &data); 486 pci_write_config_byte(dev, 0x6f, data & 0xef); 487 488 /* If this card has 2 UART, we have to do the same with second UART. */ 489 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 490 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 491 pci_read_config_byte(dev, 0x73, &data); 492 pci_write_config_byte(dev, 0x73, data & 0xef); 493 } 494 return 0; 495 } 496 497 static int pci_siig_init(struct pci_dev *dev) 498 { 499 unsigned int type = dev->device & 0xff00; 500 501 if (type == 0x1000) 502 return pci_siig10x_init(dev); 503 else if (type == 0x2000) 504 return pci_siig20x_init(dev); 505 506 moan_device("Unknown SIIG card", dev); 507 return -ENODEV; 508 } 509 510 static int pci_siig_setup(struct serial_private *priv, 511 const struct pciserial_board *board, 512 struct uart_8250_port *port, int idx) 513 { 514 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 515 516 if (idx > 3) { 517 bar = 4; 518 offset = (idx - 4) * 8; 519 } 520 521 return setup_port(priv, port, bar, offset, 0); 522 } 523 524 /* 525 * Timedia has an explosion of boards, and to avoid the PCI table from 526 * growing *huge*, we use this function to collapse some 70 entries 527 * in the PCI table into one, for sanity's and compactness's sake. 528 */ 529 static const unsigned short timedia_single_port[] = { 530 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 531 }; 532 533 static const unsigned short timedia_dual_port[] = { 534 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 535 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 536 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 537 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 538 0xD079, 0 539 }; 540 541 static const unsigned short timedia_quad_port[] = { 542 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 543 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 544 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 545 0xB157, 0 546 }; 547 548 static const unsigned short timedia_eight_port[] = { 549 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 550 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 551 }; 552 553 static const struct timedia_struct { 554 int num; 555 const unsigned short *ids; 556 } timedia_data[] = { 557 { 1, timedia_single_port }, 558 { 2, timedia_dual_port }, 559 { 4, timedia_quad_port }, 560 { 8, timedia_eight_port } 561 }; 562 563 /* 564 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 565 * listing them individually, this driver merely grabs them all with 566 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 567 * and should be left free to be claimed by parport_serial instead. 568 */ 569 static int pci_timedia_probe(struct pci_dev *dev) 570 { 571 /* 572 * Check the third digit of the subdevice ID 573 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 574 */ 575 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 576 dev_info(&dev->dev, 577 "ignoring Timedia subdevice %04x for parport_serial\n", 578 dev->subsystem_device); 579 return -ENODEV; 580 } 581 582 return 0; 583 } 584 585 static int pci_timedia_init(struct pci_dev *dev) 586 { 587 const unsigned short *ids; 588 int i, j; 589 590 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 591 ids = timedia_data[i].ids; 592 for (j = 0; ids[j]; j++) 593 if (dev->subsystem_device == ids[j]) 594 return timedia_data[i].num; 595 } 596 return 0; 597 } 598 599 /* 600 * Timedia/SUNIX uses a mixture of BARs and offsets 601 * Ugh, this is ugly as all hell --- TYT 602 */ 603 static int 604 pci_timedia_setup(struct serial_private *priv, 605 const struct pciserial_board *board, 606 struct uart_8250_port *port, int idx) 607 { 608 unsigned int bar = 0, offset = board->first_offset; 609 610 switch (idx) { 611 case 0: 612 bar = 0; 613 break; 614 case 1: 615 offset = board->uart_offset; 616 bar = 0; 617 break; 618 case 2: 619 bar = 1; 620 break; 621 case 3: 622 offset = board->uart_offset; 623 /* FALLTHROUGH */ 624 case 4: /* BAR 2 */ 625 case 5: /* BAR 3 */ 626 case 6: /* BAR 4 */ 627 case 7: /* BAR 5 */ 628 bar = idx - 2; 629 } 630 631 return setup_port(priv, port, bar, offset, board->reg_shift); 632 } 633 634 /* 635 * Some Titan cards are also a little weird 636 */ 637 static int 638 titan_400l_800l_setup(struct serial_private *priv, 639 const struct pciserial_board *board, 640 struct uart_8250_port *port, int idx) 641 { 642 unsigned int bar, offset = board->first_offset; 643 644 switch (idx) { 645 case 0: 646 bar = 1; 647 break; 648 case 1: 649 bar = 2; 650 break; 651 default: 652 bar = 4; 653 offset = (idx - 2) * board->uart_offset; 654 } 655 656 return setup_port(priv, port, bar, offset, board->reg_shift); 657 } 658 659 static int pci_xircom_init(struct pci_dev *dev) 660 { 661 msleep(100); 662 return 0; 663 } 664 665 static int pci_ni8420_init(struct pci_dev *dev) 666 { 667 void __iomem *p; 668 unsigned int bar = 0; 669 670 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 671 moan_device("no memory in bar", dev); 672 return 0; 673 } 674 675 p = pci_ioremap_bar(dev, bar); 676 if (p == NULL) 677 return -ENOMEM; 678 679 /* Enable CPU Interrupt */ 680 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 681 p + NI8420_INT_ENABLE_REG); 682 683 iounmap(p); 684 return 0; 685 } 686 687 #define MITE_IOWBSR1_WSIZE 0xa 688 #define MITE_IOWBSR1_WIN_OFFSET 0x800 689 #define MITE_IOWBSR1_WENAB (1 << 7) 690 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 691 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 692 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 693 694 static int pci_ni8430_init(struct pci_dev *dev) 695 { 696 void __iomem *p; 697 struct pci_bus_region region; 698 u32 device_window; 699 unsigned int bar = 0; 700 701 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 702 moan_device("no memory in bar", dev); 703 return 0; 704 } 705 706 p = pci_ioremap_bar(dev, bar); 707 if (p == NULL) 708 return -ENOMEM; 709 710 /* 711 * Set device window address and size in BAR0, while acknowledging that 712 * the resource structure may contain a translated address that differs 713 * from the address the device responds to. 714 */ 715 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 716 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 717 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 718 writel(device_window, p + MITE_IOWBSR1); 719 720 /* Set window access to go to RAMSEL IO address space */ 721 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 722 p + MITE_IOWCR1); 723 724 /* Enable IO Bus Interrupt 0 */ 725 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 726 727 /* Enable CPU Interrupt */ 728 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 729 730 iounmap(p); 731 return 0; 732 } 733 734 /* UART Port Control Register */ 735 #define NI8430_PORTCON 0x0f 736 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 737 738 static int 739 pci_ni8430_setup(struct serial_private *priv, 740 const struct pciserial_board *board, 741 struct uart_8250_port *port, int idx) 742 { 743 struct pci_dev *dev = priv->dev; 744 void __iomem *p; 745 unsigned int bar, offset = board->first_offset; 746 747 if (idx >= board->num_ports) 748 return 1; 749 750 bar = FL_GET_BASE(board->flags); 751 offset += idx * board->uart_offset; 752 753 p = pci_ioremap_bar(dev, bar); 754 if (!p) 755 return -ENOMEM; 756 757 /* enable the transceiver */ 758 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 759 p + offset + NI8430_PORTCON); 760 761 iounmap(p); 762 763 return setup_port(priv, port, bar, offset, board->reg_shift); 764 } 765 766 static int pci_netmos_9900_setup(struct serial_private *priv, 767 const struct pciserial_board *board, 768 struct uart_8250_port *port, int idx) 769 { 770 unsigned int bar; 771 772 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 773 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 774 /* netmos apparently orders BARs by datasheet layout, so serial 775 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 776 */ 777 bar = 3 * idx; 778 779 return setup_port(priv, port, bar, 0, board->reg_shift); 780 } else { 781 return pci_default_setup(priv, board, port, idx); 782 } 783 } 784 785 /* the 99xx series comes with a range of device IDs and a variety 786 * of capabilities: 787 * 788 * 9900 has varying capabilities and can cascade to sub-controllers 789 * (cascading should be purely internal) 790 * 9904 is hardwired with 4 serial ports 791 * 9912 and 9922 are hardwired with 2 serial ports 792 */ 793 static int pci_netmos_9900_numports(struct pci_dev *dev) 794 { 795 unsigned int c = dev->class; 796 unsigned int pi; 797 unsigned short sub_serports; 798 799 pi = c & 0xff; 800 801 if (pi == 2) 802 return 1; 803 804 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 805 /* two possibilities: 0x30ps encodes number of parallel and 806 * serial ports, or 0x1000 indicates *something*. This is not 807 * immediately obvious, since the 2s1p+4s configuration seems 808 * to offer all functionality on functions 0..2, while still 809 * advertising the same function 3 as the 4s+2s1p config. 810 */ 811 sub_serports = dev->subsystem_device & 0xf; 812 if (sub_serports > 0) 813 return sub_serports; 814 815 dev_err(&dev->dev, 816 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 817 return 0; 818 } 819 820 moan_device("unknown NetMos/Mostech program interface", dev); 821 return 0; 822 } 823 824 static int pci_netmos_init(struct pci_dev *dev) 825 { 826 /* subdevice 0x00PS means <P> parallel, <S> serial */ 827 unsigned int num_serial = dev->subsystem_device & 0xf; 828 829 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 830 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 831 return 0; 832 833 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 834 dev->subsystem_device == 0x0299) 835 return 0; 836 837 switch (dev->device) { /* FALLTHROUGH on all */ 838 case PCI_DEVICE_ID_NETMOS_9904: 839 case PCI_DEVICE_ID_NETMOS_9912: 840 case PCI_DEVICE_ID_NETMOS_9922: 841 case PCI_DEVICE_ID_NETMOS_9900: 842 num_serial = pci_netmos_9900_numports(dev); 843 break; 844 845 default: 846 break; 847 } 848 849 if (num_serial == 0) { 850 moan_device("unknown NetMos/Mostech device", dev); 851 return -ENODEV; 852 } 853 854 return num_serial; 855 } 856 857 /* 858 * These chips are available with optionally one parallel port and up to 859 * two serial ports. Unfortunately they all have the same product id. 860 * 861 * Basic configuration is done over a region of 32 I/O ports. The base 862 * ioport is called INTA or INTC, depending on docs/other drivers. 863 * 864 * The region of the 32 I/O ports is configured in POSIO0R... 865 */ 866 867 /* registers */ 868 #define ITE_887x_MISCR 0x9c 869 #define ITE_887x_INTCBAR 0x78 870 #define ITE_887x_UARTBAR 0x7c 871 #define ITE_887x_PS0BAR 0x10 872 #define ITE_887x_POSIO0 0x60 873 874 /* I/O space size */ 875 #define ITE_887x_IOSIZE 32 876 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 877 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 878 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 879 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 880 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 881 #define ITE_887x_POSIO_SPEED (3 << 29) 882 /* enable IO_Space bit */ 883 #define ITE_887x_POSIO_ENABLE (1 << 31) 884 885 static int pci_ite887x_init(struct pci_dev *dev) 886 { 887 /* inta_addr are the configuration addresses of the ITE */ 888 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 889 0x200, 0x280, 0 }; 890 int ret, i, type; 891 struct resource *iobase = NULL; 892 u32 miscr, uartbar, ioport; 893 894 /* search for the base-ioport */ 895 i = 0; 896 while (inta_addr[i] && iobase == NULL) { 897 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 898 "ite887x"); 899 if (iobase != NULL) { 900 /* write POSIO0R - speed | size | ioport */ 901 pci_write_config_dword(dev, ITE_887x_POSIO0, 902 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 903 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 904 /* write INTCBAR - ioport */ 905 pci_write_config_dword(dev, ITE_887x_INTCBAR, 906 inta_addr[i]); 907 ret = inb(inta_addr[i]); 908 if (ret != 0xff) { 909 /* ioport connected */ 910 break; 911 } 912 release_region(iobase->start, ITE_887x_IOSIZE); 913 iobase = NULL; 914 } 915 i++; 916 } 917 918 if (!inta_addr[i]) { 919 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 920 return -ENODEV; 921 } 922 923 /* start of undocumented type checking (see parport_pc.c) */ 924 type = inb(iobase->start + 0x18) & 0x0f; 925 926 switch (type) { 927 case 0x2: /* ITE8871 (1P) */ 928 case 0xa: /* ITE8875 (1P) */ 929 ret = 0; 930 break; 931 case 0xe: /* ITE8872 (2S1P) */ 932 ret = 2; 933 break; 934 case 0x6: /* ITE8873 (1S) */ 935 ret = 1; 936 break; 937 case 0x8: /* ITE8874 (2S) */ 938 ret = 2; 939 break; 940 default: 941 moan_device("Unknown ITE887x", dev); 942 ret = -ENODEV; 943 } 944 945 /* configure all serial ports */ 946 for (i = 0; i < ret; i++) { 947 /* read the I/O port from the device */ 948 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 949 &ioport); 950 ioport &= 0x0000FF00; /* the actual base address */ 951 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 952 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 953 ITE_887x_POSIO_IOSIZE_8 | ioport); 954 955 /* write the ioport to the UARTBAR */ 956 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 957 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 958 uartbar |= (ioport << (16 * i)); /* set the ioport */ 959 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 960 961 /* get current config */ 962 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 963 /* disable interrupts (UARTx_Routing[3:0]) */ 964 miscr &= ~(0xf << (12 - 4 * i)); 965 /* activate the UART (UARTx_En) */ 966 miscr |= 1 << (23 - i); 967 /* write new config with activated UART */ 968 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 969 } 970 971 if (ret <= 0) { 972 /* the device has no UARTs if we get here */ 973 release_region(iobase->start, ITE_887x_IOSIZE); 974 } 975 976 return ret; 977 } 978 979 static void pci_ite887x_exit(struct pci_dev *dev) 980 { 981 u32 ioport; 982 /* the ioport is bit 0-15 in POSIO0R */ 983 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 984 ioport &= 0xffff; 985 release_region(ioport, ITE_887x_IOSIZE); 986 } 987 988 /* 989 * EndRun Technologies. 990 * Determine the number of ports available on the device. 991 */ 992 #define PCI_VENDOR_ID_ENDRUN 0x7401 993 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 994 995 static int pci_endrun_init(struct pci_dev *dev) 996 { 997 u8 __iomem *p; 998 unsigned long deviceID; 999 unsigned int number_uarts = 0; 1000 1001 /* EndRun device is all 0xexxx */ 1002 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1003 (dev->device & 0xf000) != 0xe000) 1004 return 0; 1005 1006 p = pci_iomap(dev, 0, 5); 1007 if (p == NULL) 1008 return -ENOMEM; 1009 1010 deviceID = ioread32(p); 1011 /* EndRun device */ 1012 if (deviceID == 0x07000200) { 1013 number_uarts = ioread8(p + 4); 1014 dev_dbg(&dev->dev, 1015 "%d ports detected on EndRun PCI Express device\n", 1016 number_uarts); 1017 } 1018 pci_iounmap(dev, p); 1019 return number_uarts; 1020 } 1021 1022 /* 1023 * Oxford Semiconductor Inc. 1024 * Check that device is part of the Tornado range of devices, then determine 1025 * the number of ports available on the device. 1026 */ 1027 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1028 { 1029 u8 __iomem *p; 1030 unsigned long deviceID; 1031 unsigned int number_uarts = 0; 1032 1033 /* OxSemi Tornado devices are all 0xCxxx */ 1034 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1035 (dev->device & 0xF000) != 0xC000) 1036 return 0; 1037 1038 p = pci_iomap(dev, 0, 5); 1039 if (p == NULL) 1040 return -ENOMEM; 1041 1042 deviceID = ioread32(p); 1043 /* Tornado device */ 1044 if (deviceID == 0x07000200) { 1045 number_uarts = ioread8(p + 4); 1046 dev_dbg(&dev->dev, 1047 "%d ports detected on Oxford PCI Express device\n", 1048 number_uarts); 1049 } 1050 pci_iounmap(dev, p); 1051 return number_uarts; 1052 } 1053 1054 static int pci_asix_setup(struct serial_private *priv, 1055 const struct pciserial_board *board, 1056 struct uart_8250_port *port, int idx) 1057 { 1058 port->bugs |= UART_BUG_PARITY; 1059 return pci_default_setup(priv, board, port, idx); 1060 } 1061 1062 /* Quatech devices have their own extra interface features */ 1063 1064 struct quatech_feature { 1065 u16 devid; 1066 bool amcc; 1067 }; 1068 1069 #define QPCR_TEST_FOR1 0x3F 1070 #define QPCR_TEST_GET1 0x00 1071 #define QPCR_TEST_FOR2 0x40 1072 #define QPCR_TEST_GET2 0x40 1073 #define QPCR_TEST_FOR3 0x80 1074 #define QPCR_TEST_GET3 0x40 1075 #define QPCR_TEST_FOR4 0xC0 1076 #define QPCR_TEST_GET4 0x80 1077 1078 #define QOPR_CLOCK_X1 0x0000 1079 #define QOPR_CLOCK_X2 0x0001 1080 #define QOPR_CLOCK_X4 0x0002 1081 #define QOPR_CLOCK_X8 0x0003 1082 #define QOPR_CLOCK_RATE_MASK 0x0003 1083 1084 1085 static struct quatech_feature quatech_cards[] = { 1086 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1087 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1088 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1089 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1090 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1091 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1092 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1093 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1094 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1095 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1096 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1097 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1098 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1099 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1100 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1101 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1102 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1103 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1104 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1105 { 0, } 1106 }; 1107 1108 static int pci_quatech_amcc(u16 devid) 1109 { 1110 struct quatech_feature *qf = &quatech_cards[0]; 1111 while (qf->devid) { 1112 if (qf->devid == devid) 1113 return qf->amcc; 1114 qf++; 1115 } 1116 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1117 return 0; 1118 }; 1119 1120 static int pci_quatech_rqopr(struct uart_8250_port *port) 1121 { 1122 unsigned long base = port->port.iobase; 1123 u8 LCR, val; 1124 1125 LCR = inb(base + UART_LCR); 1126 outb(0xBF, base + UART_LCR); 1127 val = inb(base + UART_SCR); 1128 outb(LCR, base + UART_LCR); 1129 return val; 1130 } 1131 1132 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1133 { 1134 unsigned long base = port->port.iobase; 1135 u8 LCR; 1136 1137 LCR = inb(base + UART_LCR); 1138 outb(0xBF, base + UART_LCR); 1139 inb(base + UART_SCR); 1140 outb(qopr, base + UART_SCR); 1141 outb(LCR, base + UART_LCR); 1142 } 1143 1144 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1145 { 1146 unsigned long base = port->port.iobase; 1147 u8 LCR, val, qmcr; 1148 1149 LCR = inb(base + UART_LCR); 1150 outb(0xBF, base + UART_LCR); 1151 val = inb(base + UART_SCR); 1152 outb(val | 0x10, base + UART_SCR); 1153 qmcr = inb(base + UART_MCR); 1154 outb(val, base + UART_SCR); 1155 outb(LCR, base + UART_LCR); 1156 1157 return qmcr; 1158 } 1159 1160 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1161 { 1162 unsigned long base = port->port.iobase; 1163 u8 LCR, val; 1164 1165 LCR = inb(base + UART_LCR); 1166 outb(0xBF, base + UART_LCR); 1167 val = inb(base + UART_SCR); 1168 outb(val | 0x10, base + UART_SCR); 1169 outb(qmcr, base + UART_MCR); 1170 outb(val, base + UART_SCR); 1171 outb(LCR, base + UART_LCR); 1172 } 1173 1174 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1175 { 1176 unsigned long base = port->port.iobase; 1177 u8 LCR, val; 1178 1179 LCR = inb(base + UART_LCR); 1180 outb(0xBF, base + UART_LCR); 1181 val = inb(base + UART_SCR); 1182 if (val & 0x20) { 1183 outb(0x80, UART_LCR); 1184 if (!(inb(UART_SCR) & 0x20)) { 1185 outb(LCR, base + UART_LCR); 1186 return 1; 1187 } 1188 } 1189 return 0; 1190 } 1191 1192 static int pci_quatech_test(struct uart_8250_port *port) 1193 { 1194 u8 reg, qopr; 1195 1196 qopr = pci_quatech_rqopr(port); 1197 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1198 reg = pci_quatech_rqopr(port) & 0xC0; 1199 if (reg != QPCR_TEST_GET1) 1200 return -EINVAL; 1201 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1202 reg = pci_quatech_rqopr(port) & 0xC0; 1203 if (reg != QPCR_TEST_GET2) 1204 return -EINVAL; 1205 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1206 reg = pci_quatech_rqopr(port) & 0xC0; 1207 if (reg != QPCR_TEST_GET3) 1208 return -EINVAL; 1209 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1210 reg = pci_quatech_rqopr(port) & 0xC0; 1211 if (reg != QPCR_TEST_GET4) 1212 return -EINVAL; 1213 1214 pci_quatech_wqopr(port, qopr); 1215 return 0; 1216 } 1217 1218 static int pci_quatech_clock(struct uart_8250_port *port) 1219 { 1220 u8 qopr, reg, set; 1221 unsigned long clock; 1222 1223 if (pci_quatech_test(port) < 0) 1224 return 1843200; 1225 1226 qopr = pci_quatech_rqopr(port); 1227 1228 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1229 reg = pci_quatech_rqopr(port); 1230 if (reg & QOPR_CLOCK_X8) { 1231 clock = 1843200; 1232 goto out; 1233 } 1234 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1235 reg = pci_quatech_rqopr(port); 1236 if (!(reg & QOPR_CLOCK_X8)) { 1237 clock = 1843200; 1238 goto out; 1239 } 1240 reg &= QOPR_CLOCK_X8; 1241 if (reg == QOPR_CLOCK_X2) { 1242 clock = 3685400; 1243 set = QOPR_CLOCK_X2; 1244 } else if (reg == QOPR_CLOCK_X4) { 1245 clock = 7372800; 1246 set = QOPR_CLOCK_X4; 1247 } else if (reg == QOPR_CLOCK_X8) { 1248 clock = 14745600; 1249 set = QOPR_CLOCK_X8; 1250 } else { 1251 clock = 1843200; 1252 set = QOPR_CLOCK_X1; 1253 } 1254 qopr &= ~QOPR_CLOCK_RATE_MASK; 1255 qopr |= set; 1256 1257 out: 1258 pci_quatech_wqopr(port, qopr); 1259 return clock; 1260 } 1261 1262 static int pci_quatech_rs422(struct uart_8250_port *port) 1263 { 1264 u8 qmcr; 1265 int rs422 = 0; 1266 1267 if (!pci_quatech_has_qmcr(port)) 1268 return 0; 1269 qmcr = pci_quatech_rqmcr(port); 1270 pci_quatech_wqmcr(port, 0xFF); 1271 if (pci_quatech_rqmcr(port)) 1272 rs422 = 1; 1273 pci_quatech_wqmcr(port, qmcr); 1274 return rs422; 1275 } 1276 1277 static int pci_quatech_init(struct pci_dev *dev) 1278 { 1279 if (pci_quatech_amcc(dev->device)) { 1280 unsigned long base = pci_resource_start(dev, 0); 1281 if (base) { 1282 u32 tmp; 1283 1284 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1285 tmp = inl(base + 0x3c); 1286 outl(tmp | 0x01000000, base + 0x3c); 1287 outl(tmp &= ~0x01000000, base + 0x3c); 1288 } 1289 } 1290 return 0; 1291 } 1292 1293 static int pci_quatech_setup(struct serial_private *priv, 1294 const struct pciserial_board *board, 1295 struct uart_8250_port *port, int idx) 1296 { 1297 /* Needed by pci_quatech calls below */ 1298 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1299 /* Set up the clocking */ 1300 port->port.uartclk = pci_quatech_clock(port); 1301 /* For now just warn about RS422 */ 1302 if (pci_quatech_rs422(port)) 1303 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1304 return pci_default_setup(priv, board, port, idx); 1305 } 1306 1307 static void pci_quatech_exit(struct pci_dev *dev) 1308 { 1309 } 1310 1311 static int pci_default_setup(struct serial_private *priv, 1312 const struct pciserial_board *board, 1313 struct uart_8250_port *port, int idx) 1314 { 1315 unsigned int bar, offset = board->first_offset, maxnr; 1316 1317 bar = FL_GET_BASE(board->flags); 1318 if (board->flags & FL_BASE_BARS) 1319 bar += idx; 1320 else 1321 offset += idx * board->uart_offset; 1322 1323 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1324 (board->reg_shift + 3); 1325 1326 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1327 return 1; 1328 1329 return setup_port(priv, port, bar, offset, board->reg_shift); 1330 } 1331 1332 static int pci_pericom_setup(struct serial_private *priv, 1333 const struct pciserial_board *board, 1334 struct uart_8250_port *port, int idx) 1335 { 1336 unsigned int bar, offset = board->first_offset, maxnr; 1337 1338 bar = FL_GET_BASE(board->flags); 1339 if (board->flags & FL_BASE_BARS) 1340 bar += idx; 1341 else 1342 offset += idx * board->uart_offset; 1343 1344 if (idx==3) 1345 offset = 0x38; 1346 1347 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1348 (board->reg_shift + 3); 1349 1350 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1351 return 1; 1352 1353 return setup_port(priv, port, bar, offset, board->reg_shift); 1354 } 1355 1356 static int 1357 ce4100_serial_setup(struct serial_private *priv, 1358 const struct pciserial_board *board, 1359 struct uart_8250_port *port, int idx) 1360 { 1361 int ret; 1362 1363 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1364 port->port.iotype = UPIO_MEM32; 1365 port->port.type = PORT_XSCALE; 1366 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1367 port->port.regshift = 2; 1368 1369 return ret; 1370 } 1371 1372 static int 1373 pci_omegapci_setup(struct serial_private *priv, 1374 const struct pciserial_board *board, 1375 struct uart_8250_port *port, int idx) 1376 { 1377 return setup_port(priv, port, 2, idx * 8, 0); 1378 } 1379 1380 static int 1381 pci_brcm_trumanage_setup(struct serial_private *priv, 1382 const struct pciserial_board *board, 1383 struct uart_8250_port *port, int idx) 1384 { 1385 int ret = pci_default_setup(priv, board, port, idx); 1386 1387 port->port.type = PORT_BRCM_TRUMANAGE; 1388 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1389 return ret; 1390 } 1391 1392 /* RTS will control by MCR if this bit is 0 */ 1393 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1394 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1395 #define FINTEK_RTS_INVERT BIT(5) 1396 1397 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1398 static int pci_fintek_rs485_config(struct uart_port *port, 1399 struct serial_rs485 *rs485) 1400 { 1401 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1402 u8 setting; 1403 u8 *index = (u8 *) port->private_data; 1404 1405 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1406 1407 if (!rs485) 1408 rs485 = &port->rs485; 1409 else if (rs485->flags & SER_RS485_ENABLED) 1410 memset(rs485->padding, 0, sizeof(rs485->padding)); 1411 else 1412 memset(rs485, 0, sizeof(*rs485)); 1413 1414 /* F81504/508/512 not support RTS delay before or after send */ 1415 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1416 1417 if (rs485->flags & SER_RS485_ENABLED) { 1418 /* Enable RTS H/W control mode */ 1419 setting |= FINTEK_RTS_CONTROL_BY_HW; 1420 1421 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1422 /* RTS driving high on TX */ 1423 setting &= ~FINTEK_RTS_INVERT; 1424 } else { 1425 /* RTS driving low on TX */ 1426 setting |= FINTEK_RTS_INVERT; 1427 } 1428 1429 rs485->delay_rts_after_send = 0; 1430 rs485->delay_rts_before_send = 0; 1431 } else { 1432 /* Disable RTS H/W control mode */ 1433 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1434 } 1435 1436 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1437 1438 if (rs485 != &port->rs485) 1439 port->rs485 = *rs485; 1440 1441 return 0; 1442 } 1443 1444 static int pci_fintek_setup(struct serial_private *priv, 1445 const struct pciserial_board *board, 1446 struct uart_8250_port *port, int idx) 1447 { 1448 struct pci_dev *pdev = priv->dev; 1449 u8 *data; 1450 u8 config_base; 1451 u16 iobase; 1452 1453 config_base = 0x40 + 0x08 * idx; 1454 1455 /* Get the io address from configuration space */ 1456 pci_read_config_word(pdev, config_base + 4, &iobase); 1457 1458 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1459 1460 port->port.iotype = UPIO_PORT; 1461 port->port.iobase = iobase; 1462 port->port.rs485_config = pci_fintek_rs485_config; 1463 1464 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1465 if (!data) 1466 return -ENOMEM; 1467 1468 /* preserve index in PCI configuration space */ 1469 *data = idx; 1470 port->port.private_data = data; 1471 1472 return 0; 1473 } 1474 1475 static int pci_fintek_init(struct pci_dev *dev) 1476 { 1477 unsigned long iobase; 1478 u32 max_port, i; 1479 u32 bar_data[3]; 1480 u8 config_base; 1481 struct serial_private *priv = pci_get_drvdata(dev); 1482 struct uart_8250_port *port; 1483 1484 switch (dev->device) { 1485 case 0x1104: /* 4 ports */ 1486 case 0x1108: /* 8 ports */ 1487 max_port = dev->device & 0xff; 1488 break; 1489 case 0x1112: /* 12 ports */ 1490 max_port = 12; 1491 break; 1492 default: 1493 return -EINVAL; 1494 } 1495 1496 /* Get the io address dispatch from the BIOS */ 1497 pci_read_config_dword(dev, 0x24, &bar_data[0]); 1498 pci_read_config_dword(dev, 0x20, &bar_data[1]); 1499 pci_read_config_dword(dev, 0x1c, &bar_data[2]); 1500 1501 for (i = 0; i < max_port; ++i) { 1502 /* UART0 configuration offset start from 0x40 */ 1503 config_base = 0x40 + 0x08 * i; 1504 1505 /* Calculate Real IO Port */ 1506 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1507 1508 /* Enable UART I/O port */ 1509 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1510 1511 /* Select 128-byte FIFO and 8x FIFO threshold */ 1512 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1513 1514 /* LSB UART */ 1515 pci_write_config_byte(dev, config_base + 0x04, 1516 (u8)(iobase & 0xff)); 1517 1518 /* MSB UART */ 1519 pci_write_config_byte(dev, config_base + 0x05, 1520 (u8)((iobase & 0xff00) >> 8)); 1521 1522 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1523 1524 if (priv) { 1525 /* re-apply RS232/485 mode when 1526 * pciserial_resume_ports() 1527 */ 1528 port = serial8250_get_port(priv->line[i]); 1529 pci_fintek_rs485_config(&port->port, NULL); 1530 } else { 1531 /* First init without port data 1532 * force init to RS232 Mode 1533 */ 1534 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1535 } 1536 } 1537 1538 return max_port; 1539 } 1540 1541 static int skip_tx_en_setup(struct serial_private *priv, 1542 const struct pciserial_board *board, 1543 struct uart_8250_port *port, int idx) 1544 { 1545 port->port.flags |= UPF_NO_TXEN_TEST; 1546 dev_dbg(&priv->dev->dev, 1547 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1548 priv->dev->vendor, priv->dev->device, 1549 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1550 1551 return pci_default_setup(priv, board, port, idx); 1552 } 1553 1554 static void kt_handle_break(struct uart_port *p) 1555 { 1556 struct uart_8250_port *up = up_to_u8250p(p); 1557 /* 1558 * On receipt of a BI, serial device in Intel ME (Intel 1559 * management engine) needs to have its fifos cleared for sane 1560 * SOL (Serial Over Lan) output. 1561 */ 1562 serial8250_clear_and_reinit_fifos(up); 1563 } 1564 1565 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1566 { 1567 struct uart_8250_port *up = up_to_u8250p(p); 1568 unsigned int val; 1569 1570 /* 1571 * When the Intel ME (management engine) gets reset its serial 1572 * port registers could return 0 momentarily. Functions like 1573 * serial8250_console_write, read and save the IER, perform 1574 * some operation and then restore it. In order to avoid 1575 * setting IER register inadvertently to 0, if the value read 1576 * is 0, double check with ier value in uart_8250_port and use 1577 * that instead. up->ier should be the same value as what is 1578 * currently configured. 1579 */ 1580 val = inb(p->iobase + offset); 1581 if (offset == UART_IER) { 1582 if (val == 0) 1583 val = up->ier; 1584 } 1585 return val; 1586 } 1587 1588 static int kt_serial_setup(struct serial_private *priv, 1589 const struct pciserial_board *board, 1590 struct uart_8250_port *port, int idx) 1591 { 1592 port->port.flags |= UPF_BUG_THRE; 1593 port->port.serial_in = kt_serial_in; 1594 port->port.handle_break = kt_handle_break; 1595 return skip_tx_en_setup(priv, board, port, idx); 1596 } 1597 1598 static int pci_eg20t_init(struct pci_dev *dev) 1599 { 1600 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1601 return -ENODEV; 1602 #else 1603 return 0; 1604 #endif 1605 } 1606 1607 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 1608 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 1609 1610 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */ 1611 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */ 1612 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */ 1613 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */ 1614 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */ 1615 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */ 1616 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */ 1617 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */ 1618 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */ 1619 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */ 1620 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */ 1621 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ 1622 1623 static int 1624 pci_xr17c154_setup(struct serial_private *priv, 1625 const struct pciserial_board *board, 1626 struct uart_8250_port *port, int idx) 1627 { 1628 port->port.flags |= UPF_EXAR_EFR; 1629 return pci_default_setup(priv, board, port, idx); 1630 } 1631 1632 static inline int 1633 xr17v35x_has_slave(struct serial_private *priv) 1634 { 1635 const int dev_id = priv->dev->device; 1636 1637 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) || 1638 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358)); 1639 } 1640 1641 static int 1642 pci_xr17v35x_setup(struct serial_private *priv, 1643 const struct pciserial_board *board, 1644 struct uart_8250_port *port, int idx) 1645 { 1646 u8 __iomem *p; 1647 1648 p = pci_ioremap_bar(priv->dev, 0); 1649 if (p == NULL) 1650 return -ENOMEM; 1651 1652 port->port.flags |= UPF_EXAR_EFR; 1653 1654 /* 1655 * Setup the uart clock for the devices on expansion slot to 1656 * half the clock speed of the main chip (which is 125MHz) 1657 */ 1658 if (xr17v35x_has_slave(priv) && idx >= 8) 1659 port->port.uartclk = (7812500 * 16 / 2); 1660 1661 /* 1662 * Setup Multipurpose Input/Output pins. 1663 */ 1664 if (idx == 0) { 1665 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 1666 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 1667 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 1668 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 1669 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 1670 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 1671 writeb(0x00, p + UART_EXAR_MPIOINT_15_8); 1672 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8); 1673 writeb(0x00, p + UART_EXAR_MPIO3T_15_8); 1674 writeb(0x00, p + UART_EXAR_MPIOINV_15_8); 1675 writeb(0x00, p + UART_EXAR_MPIOSEL_15_8); 1676 writeb(0x00, p + UART_EXAR_MPIOOD_15_8); 1677 } 1678 writeb(0x00, p + UART_EXAR_8XMODE); 1679 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1680 writeb(128, p + UART_EXAR_TXTRG); 1681 writeb(128, p + UART_EXAR_RXTRG); 1682 iounmap(p); 1683 1684 return pci_default_setup(priv, board, port, idx); 1685 } 1686 1687 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1688 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1689 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1690 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1691 1692 static int 1693 pci_fastcom335_setup(struct serial_private *priv, 1694 const struct pciserial_board *board, 1695 struct uart_8250_port *port, int idx) 1696 { 1697 u8 __iomem *p; 1698 1699 p = pci_ioremap_bar(priv->dev, 0); 1700 if (p == NULL) 1701 return -ENOMEM; 1702 1703 port->port.flags |= UPF_EXAR_EFR; 1704 1705 /* 1706 * Setup Multipurpose Input/Output pins. 1707 */ 1708 if (idx == 0) { 1709 switch (priv->dev->device) { 1710 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1711 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1712 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0); 1713 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 1714 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 1715 break; 1716 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1717 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1718 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 1719 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0); 1720 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0); 1721 break; 1722 } 1723 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 1724 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 1725 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 1726 } 1727 writeb(0x00, p + UART_EXAR_8XMODE); 1728 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1729 writeb(32, p + UART_EXAR_TXTRG); 1730 writeb(32, p + UART_EXAR_RXTRG); 1731 iounmap(p); 1732 1733 return pci_default_setup(priv, board, port, idx); 1734 } 1735 1736 static int 1737 pci_wch_ch353_setup(struct serial_private *priv, 1738 const struct pciserial_board *board, 1739 struct uart_8250_port *port, int idx) 1740 { 1741 port->port.flags |= UPF_FIXED_TYPE; 1742 port->port.type = PORT_16550A; 1743 return pci_default_setup(priv, board, port, idx); 1744 } 1745 1746 static int 1747 pci_wch_ch355_setup(struct serial_private *priv, 1748 const struct pciserial_board *board, 1749 struct uart_8250_port *port, int idx) 1750 { 1751 port->port.flags |= UPF_FIXED_TYPE; 1752 port->port.type = PORT_16550A; 1753 return pci_default_setup(priv, board, port, idx); 1754 } 1755 1756 static int 1757 pci_wch_ch38x_setup(struct serial_private *priv, 1758 const struct pciserial_board *board, 1759 struct uart_8250_port *port, int idx) 1760 { 1761 port->port.flags |= UPF_FIXED_TYPE; 1762 port->port.type = PORT_16850; 1763 return pci_default_setup(priv, board, port, idx); 1764 } 1765 1766 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1767 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1768 #define PCI_DEVICE_ID_OCTPRO 0x0001 1769 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1770 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1771 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1772 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1773 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1774 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1775 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1776 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1777 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1778 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1779 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1780 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1781 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1782 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1783 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1784 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1785 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1786 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1787 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1788 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1789 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1790 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1791 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1792 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1793 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1794 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1795 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1796 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1797 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1798 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1799 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1800 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1801 #define PCI_VENDOR_ID_WCH 0x4348 1802 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1803 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1804 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1805 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1806 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1807 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1808 #define PCI_VENDOR_ID_AGESTAR 0x5372 1809 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1810 #define PCI_VENDOR_ID_ASIX 0x9710 1811 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1812 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1813 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1814 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1815 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1816 1817 #define PCI_VENDOR_ID_SUNIX 0x1fd4 1818 #define PCI_DEVICE_ID_SUNIX_1999 0x1999 1819 1820 #define PCIE_VENDOR_ID_WCH 0x1c00 1821 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1822 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1823 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1824 1825 #define PCI_VENDOR_ID_PERICOM 0x12D8 1826 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 1827 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 1828 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 1829 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 1830 1831 #define PCI_VENDOR_ID_ACCESIO 0x494f 1832 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1833 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1834 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1835 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1836 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1837 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1838 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1839 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1840 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1841 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1842 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1843 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1844 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1845 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1846 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1847 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1848 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1849 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1850 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1851 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1852 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1853 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1854 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1855 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1856 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1857 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1858 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1859 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1860 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1861 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1862 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1863 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1864 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1865 1866 1867 1868 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1869 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1870 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1871 1872 /* 1873 * Master list of serial port init/setup/exit quirks. 1874 * This does not describe the general nature of the port. 1875 * (ie, baud base, number and location of ports, etc) 1876 * 1877 * This list is ordered alphabetically by vendor then device. 1878 * Specific entries must come before more generic entries. 1879 */ 1880 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1881 /* 1882 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1883 */ 1884 { 1885 .vendor = PCI_VENDOR_ID_AMCC, 1886 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1887 .subvendor = PCI_ANY_ID, 1888 .subdevice = PCI_ANY_ID, 1889 .setup = addidata_apci7800_setup, 1890 }, 1891 /* 1892 * AFAVLAB cards - these may be called via parport_serial 1893 * It is not clear whether this applies to all products. 1894 */ 1895 { 1896 .vendor = PCI_VENDOR_ID_AFAVLAB, 1897 .device = PCI_ANY_ID, 1898 .subvendor = PCI_ANY_ID, 1899 .subdevice = PCI_ANY_ID, 1900 .setup = afavlab_setup, 1901 }, 1902 /* 1903 * HP Diva 1904 */ 1905 { 1906 .vendor = PCI_VENDOR_ID_HP, 1907 .device = PCI_DEVICE_ID_HP_DIVA, 1908 .subvendor = PCI_ANY_ID, 1909 .subdevice = PCI_ANY_ID, 1910 .init = pci_hp_diva_init, 1911 .setup = pci_hp_diva_setup, 1912 }, 1913 /* 1914 * Intel 1915 */ 1916 { 1917 .vendor = PCI_VENDOR_ID_INTEL, 1918 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1919 .subvendor = 0xe4bf, 1920 .subdevice = PCI_ANY_ID, 1921 .init = pci_inteli960ni_init, 1922 .setup = pci_default_setup, 1923 }, 1924 { 1925 .vendor = PCI_VENDOR_ID_INTEL, 1926 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1927 .subvendor = PCI_ANY_ID, 1928 .subdevice = PCI_ANY_ID, 1929 .setup = skip_tx_en_setup, 1930 }, 1931 { 1932 .vendor = PCI_VENDOR_ID_INTEL, 1933 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1934 .subvendor = PCI_ANY_ID, 1935 .subdevice = PCI_ANY_ID, 1936 .setup = skip_tx_en_setup, 1937 }, 1938 { 1939 .vendor = PCI_VENDOR_ID_INTEL, 1940 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1941 .subvendor = PCI_ANY_ID, 1942 .subdevice = PCI_ANY_ID, 1943 .setup = skip_tx_en_setup, 1944 }, 1945 { 1946 .vendor = PCI_VENDOR_ID_INTEL, 1947 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1948 .subvendor = PCI_ANY_ID, 1949 .subdevice = PCI_ANY_ID, 1950 .setup = ce4100_serial_setup, 1951 }, 1952 { 1953 .vendor = PCI_VENDOR_ID_INTEL, 1954 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1955 .subvendor = PCI_ANY_ID, 1956 .subdevice = PCI_ANY_ID, 1957 .setup = kt_serial_setup, 1958 }, 1959 /* 1960 * ITE 1961 */ 1962 { 1963 .vendor = PCI_VENDOR_ID_ITE, 1964 .device = PCI_DEVICE_ID_ITE_8872, 1965 .subvendor = PCI_ANY_ID, 1966 .subdevice = PCI_ANY_ID, 1967 .init = pci_ite887x_init, 1968 .setup = pci_default_setup, 1969 .exit = pci_ite887x_exit, 1970 }, 1971 /* 1972 * National Instruments 1973 */ 1974 { 1975 .vendor = PCI_VENDOR_ID_NI, 1976 .device = PCI_DEVICE_ID_NI_PCI23216, 1977 .subvendor = PCI_ANY_ID, 1978 .subdevice = PCI_ANY_ID, 1979 .init = pci_ni8420_init, 1980 .setup = pci_default_setup, 1981 .exit = pci_ni8420_exit, 1982 }, 1983 { 1984 .vendor = PCI_VENDOR_ID_NI, 1985 .device = PCI_DEVICE_ID_NI_PCI2328, 1986 .subvendor = PCI_ANY_ID, 1987 .subdevice = PCI_ANY_ID, 1988 .init = pci_ni8420_init, 1989 .setup = pci_default_setup, 1990 .exit = pci_ni8420_exit, 1991 }, 1992 { 1993 .vendor = PCI_VENDOR_ID_NI, 1994 .device = PCI_DEVICE_ID_NI_PCI2324, 1995 .subvendor = PCI_ANY_ID, 1996 .subdevice = PCI_ANY_ID, 1997 .init = pci_ni8420_init, 1998 .setup = pci_default_setup, 1999 .exit = pci_ni8420_exit, 2000 }, 2001 { 2002 .vendor = PCI_VENDOR_ID_NI, 2003 .device = PCI_DEVICE_ID_NI_PCI2322, 2004 .subvendor = PCI_ANY_ID, 2005 .subdevice = PCI_ANY_ID, 2006 .init = pci_ni8420_init, 2007 .setup = pci_default_setup, 2008 .exit = pci_ni8420_exit, 2009 }, 2010 { 2011 .vendor = PCI_VENDOR_ID_NI, 2012 .device = PCI_DEVICE_ID_NI_PCI2324I, 2013 .subvendor = PCI_ANY_ID, 2014 .subdevice = PCI_ANY_ID, 2015 .init = pci_ni8420_init, 2016 .setup = pci_default_setup, 2017 .exit = pci_ni8420_exit, 2018 }, 2019 { 2020 .vendor = PCI_VENDOR_ID_NI, 2021 .device = PCI_DEVICE_ID_NI_PCI2322I, 2022 .subvendor = PCI_ANY_ID, 2023 .subdevice = PCI_ANY_ID, 2024 .init = pci_ni8420_init, 2025 .setup = pci_default_setup, 2026 .exit = pci_ni8420_exit, 2027 }, 2028 { 2029 .vendor = PCI_VENDOR_ID_NI, 2030 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2031 .subvendor = PCI_ANY_ID, 2032 .subdevice = PCI_ANY_ID, 2033 .init = pci_ni8420_init, 2034 .setup = pci_default_setup, 2035 .exit = pci_ni8420_exit, 2036 }, 2037 { 2038 .vendor = PCI_VENDOR_ID_NI, 2039 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2040 .subvendor = PCI_ANY_ID, 2041 .subdevice = PCI_ANY_ID, 2042 .init = pci_ni8420_init, 2043 .setup = pci_default_setup, 2044 .exit = pci_ni8420_exit, 2045 }, 2046 { 2047 .vendor = PCI_VENDOR_ID_NI, 2048 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2049 .subvendor = PCI_ANY_ID, 2050 .subdevice = PCI_ANY_ID, 2051 .init = pci_ni8420_init, 2052 .setup = pci_default_setup, 2053 .exit = pci_ni8420_exit, 2054 }, 2055 { 2056 .vendor = PCI_VENDOR_ID_NI, 2057 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2058 .subvendor = PCI_ANY_ID, 2059 .subdevice = PCI_ANY_ID, 2060 .init = pci_ni8420_init, 2061 .setup = pci_default_setup, 2062 .exit = pci_ni8420_exit, 2063 }, 2064 { 2065 .vendor = PCI_VENDOR_ID_NI, 2066 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2067 .subvendor = PCI_ANY_ID, 2068 .subdevice = PCI_ANY_ID, 2069 .init = pci_ni8420_init, 2070 .setup = pci_default_setup, 2071 .exit = pci_ni8420_exit, 2072 }, 2073 { 2074 .vendor = PCI_VENDOR_ID_NI, 2075 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2076 .subvendor = PCI_ANY_ID, 2077 .subdevice = PCI_ANY_ID, 2078 .init = pci_ni8420_init, 2079 .setup = pci_default_setup, 2080 .exit = pci_ni8420_exit, 2081 }, 2082 { 2083 .vendor = PCI_VENDOR_ID_NI, 2084 .device = PCI_ANY_ID, 2085 .subvendor = PCI_ANY_ID, 2086 .subdevice = PCI_ANY_ID, 2087 .init = pci_ni8430_init, 2088 .setup = pci_ni8430_setup, 2089 .exit = pci_ni8430_exit, 2090 }, 2091 /* Quatech */ 2092 { 2093 .vendor = PCI_VENDOR_ID_QUATECH, 2094 .device = PCI_ANY_ID, 2095 .subvendor = PCI_ANY_ID, 2096 .subdevice = PCI_ANY_ID, 2097 .init = pci_quatech_init, 2098 .setup = pci_quatech_setup, 2099 .exit = pci_quatech_exit, 2100 }, 2101 /* 2102 * Panacom 2103 */ 2104 { 2105 .vendor = PCI_VENDOR_ID_PANACOM, 2106 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2107 .subvendor = PCI_ANY_ID, 2108 .subdevice = PCI_ANY_ID, 2109 .init = pci_plx9050_init, 2110 .setup = pci_default_setup, 2111 .exit = pci_plx9050_exit, 2112 }, 2113 { 2114 .vendor = PCI_VENDOR_ID_PANACOM, 2115 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2116 .subvendor = PCI_ANY_ID, 2117 .subdevice = PCI_ANY_ID, 2118 .init = pci_plx9050_init, 2119 .setup = pci_default_setup, 2120 .exit = pci_plx9050_exit, 2121 }, 2122 /* 2123 * Pericom (Only 7954 - It have a offset jump for port 4) 2124 */ 2125 { 2126 .vendor = PCI_VENDOR_ID_PERICOM, 2127 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 2128 .subvendor = PCI_ANY_ID, 2129 .subdevice = PCI_ANY_ID, 2130 .setup = pci_pericom_setup, 2131 }, 2132 /* 2133 * PLX 2134 */ 2135 { 2136 .vendor = PCI_VENDOR_ID_PLX, 2137 .device = PCI_DEVICE_ID_PLX_9050, 2138 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2139 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2140 .init = pci_plx9050_init, 2141 .setup = pci_default_setup, 2142 .exit = pci_plx9050_exit, 2143 }, 2144 { 2145 .vendor = PCI_VENDOR_ID_PLX, 2146 .device = PCI_DEVICE_ID_PLX_9050, 2147 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2148 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2149 .init = pci_plx9050_init, 2150 .setup = pci_default_setup, 2151 .exit = pci_plx9050_exit, 2152 }, 2153 { 2154 .vendor = PCI_VENDOR_ID_PLX, 2155 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2156 .subvendor = PCI_VENDOR_ID_PLX, 2157 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2158 .init = pci_plx9050_init, 2159 .setup = pci_default_setup, 2160 .exit = pci_plx9050_exit, 2161 }, 2162 /* 2163 * SBS Technologies, Inc., PMC-OCTALPRO 232 2164 */ 2165 { 2166 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2167 .device = PCI_DEVICE_ID_OCTPRO, 2168 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2169 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2170 .init = sbs_init, 2171 .setup = sbs_setup, 2172 .exit = sbs_exit, 2173 }, 2174 /* 2175 * SBS Technologies, Inc., PMC-OCTALPRO 422 2176 */ 2177 { 2178 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2179 .device = PCI_DEVICE_ID_OCTPRO, 2180 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2181 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2182 .init = sbs_init, 2183 .setup = sbs_setup, 2184 .exit = sbs_exit, 2185 }, 2186 /* 2187 * SBS Technologies, Inc., P-Octal 232 2188 */ 2189 { 2190 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2191 .device = PCI_DEVICE_ID_OCTPRO, 2192 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2193 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2194 .init = sbs_init, 2195 .setup = sbs_setup, 2196 .exit = sbs_exit, 2197 }, 2198 /* 2199 * SBS Technologies, Inc., P-Octal 422 2200 */ 2201 { 2202 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2203 .device = PCI_DEVICE_ID_OCTPRO, 2204 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2205 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2206 .init = sbs_init, 2207 .setup = sbs_setup, 2208 .exit = sbs_exit, 2209 }, 2210 /* 2211 * SIIG cards - these may be called via parport_serial 2212 */ 2213 { 2214 .vendor = PCI_VENDOR_ID_SIIG, 2215 .device = PCI_ANY_ID, 2216 .subvendor = PCI_ANY_ID, 2217 .subdevice = PCI_ANY_ID, 2218 .init = pci_siig_init, 2219 .setup = pci_siig_setup, 2220 }, 2221 /* 2222 * Titan cards 2223 */ 2224 { 2225 .vendor = PCI_VENDOR_ID_TITAN, 2226 .device = PCI_DEVICE_ID_TITAN_400L, 2227 .subvendor = PCI_ANY_ID, 2228 .subdevice = PCI_ANY_ID, 2229 .setup = titan_400l_800l_setup, 2230 }, 2231 { 2232 .vendor = PCI_VENDOR_ID_TITAN, 2233 .device = PCI_DEVICE_ID_TITAN_800L, 2234 .subvendor = PCI_ANY_ID, 2235 .subdevice = PCI_ANY_ID, 2236 .setup = titan_400l_800l_setup, 2237 }, 2238 /* 2239 * Timedia cards 2240 */ 2241 { 2242 .vendor = PCI_VENDOR_ID_TIMEDIA, 2243 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2244 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2245 .subdevice = PCI_ANY_ID, 2246 .probe = pci_timedia_probe, 2247 .init = pci_timedia_init, 2248 .setup = pci_timedia_setup, 2249 }, 2250 { 2251 .vendor = PCI_VENDOR_ID_TIMEDIA, 2252 .device = PCI_ANY_ID, 2253 .subvendor = PCI_ANY_ID, 2254 .subdevice = PCI_ANY_ID, 2255 .setup = pci_timedia_setup, 2256 }, 2257 /* 2258 * SUNIX (Timedia) cards 2259 * Do not "probe" for these cards as there is at least one combination 2260 * card that should be handled by parport_pc that doesn't match the 2261 * rule in pci_timedia_probe. 2262 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2263 * There are some boards with part number SER5037AL that report 2264 * subdevice ID 0x0002. 2265 */ 2266 { 2267 .vendor = PCI_VENDOR_ID_SUNIX, 2268 .device = PCI_DEVICE_ID_SUNIX_1999, 2269 .subvendor = PCI_VENDOR_ID_SUNIX, 2270 .subdevice = PCI_ANY_ID, 2271 .init = pci_timedia_init, 2272 .setup = pci_timedia_setup, 2273 }, 2274 /* 2275 * Exar cards 2276 */ 2277 { 2278 .vendor = PCI_VENDOR_ID_EXAR, 2279 .device = PCI_DEVICE_ID_EXAR_XR17C152, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .setup = pci_xr17c154_setup, 2283 }, 2284 { 2285 .vendor = PCI_VENDOR_ID_EXAR, 2286 .device = PCI_DEVICE_ID_EXAR_XR17C154, 2287 .subvendor = PCI_ANY_ID, 2288 .subdevice = PCI_ANY_ID, 2289 .setup = pci_xr17c154_setup, 2290 }, 2291 { 2292 .vendor = PCI_VENDOR_ID_EXAR, 2293 .device = PCI_DEVICE_ID_EXAR_XR17C158, 2294 .subvendor = PCI_ANY_ID, 2295 .subdevice = PCI_ANY_ID, 2296 .setup = pci_xr17c154_setup, 2297 }, 2298 { 2299 .vendor = PCI_VENDOR_ID_EXAR, 2300 .device = PCI_DEVICE_ID_EXAR_XR17V352, 2301 .subvendor = PCI_ANY_ID, 2302 .subdevice = PCI_ANY_ID, 2303 .setup = pci_xr17v35x_setup, 2304 }, 2305 { 2306 .vendor = PCI_VENDOR_ID_EXAR, 2307 .device = PCI_DEVICE_ID_EXAR_XR17V354, 2308 .subvendor = PCI_ANY_ID, 2309 .subdevice = PCI_ANY_ID, 2310 .setup = pci_xr17v35x_setup, 2311 }, 2312 { 2313 .vendor = PCI_VENDOR_ID_EXAR, 2314 .device = PCI_DEVICE_ID_EXAR_XR17V358, 2315 .subvendor = PCI_ANY_ID, 2316 .subdevice = PCI_ANY_ID, 2317 .setup = pci_xr17v35x_setup, 2318 }, 2319 { 2320 .vendor = PCI_VENDOR_ID_EXAR, 2321 .device = PCI_DEVICE_ID_EXAR_XR17V4358, 2322 .subvendor = PCI_ANY_ID, 2323 .subdevice = PCI_ANY_ID, 2324 .setup = pci_xr17v35x_setup, 2325 }, 2326 { 2327 .vendor = PCI_VENDOR_ID_EXAR, 2328 .device = PCI_DEVICE_ID_EXAR_XR17V8358, 2329 .subvendor = PCI_ANY_ID, 2330 .subdevice = PCI_ANY_ID, 2331 .setup = pci_xr17v35x_setup, 2332 }, 2333 /* 2334 * Xircom cards 2335 */ 2336 { 2337 .vendor = PCI_VENDOR_ID_XIRCOM, 2338 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2339 .subvendor = PCI_ANY_ID, 2340 .subdevice = PCI_ANY_ID, 2341 .init = pci_xircom_init, 2342 .setup = pci_default_setup, 2343 }, 2344 /* 2345 * Netmos cards - these may be called via parport_serial 2346 */ 2347 { 2348 .vendor = PCI_VENDOR_ID_NETMOS, 2349 .device = PCI_ANY_ID, 2350 .subvendor = PCI_ANY_ID, 2351 .subdevice = PCI_ANY_ID, 2352 .init = pci_netmos_init, 2353 .setup = pci_netmos_9900_setup, 2354 }, 2355 /* 2356 * EndRun Technologies 2357 */ 2358 { 2359 .vendor = PCI_VENDOR_ID_ENDRUN, 2360 .device = PCI_ANY_ID, 2361 .subvendor = PCI_ANY_ID, 2362 .subdevice = PCI_ANY_ID, 2363 .init = pci_endrun_init, 2364 .setup = pci_default_setup, 2365 }, 2366 /* 2367 * For Oxford Semiconductor Tornado based devices 2368 */ 2369 { 2370 .vendor = PCI_VENDOR_ID_OXSEMI, 2371 .device = PCI_ANY_ID, 2372 .subvendor = PCI_ANY_ID, 2373 .subdevice = PCI_ANY_ID, 2374 .init = pci_oxsemi_tornado_init, 2375 .setup = pci_default_setup, 2376 }, 2377 { 2378 .vendor = PCI_VENDOR_ID_MAINPINE, 2379 .device = PCI_ANY_ID, 2380 .subvendor = PCI_ANY_ID, 2381 .subdevice = PCI_ANY_ID, 2382 .init = pci_oxsemi_tornado_init, 2383 .setup = pci_default_setup, 2384 }, 2385 { 2386 .vendor = PCI_VENDOR_ID_DIGI, 2387 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2388 .subvendor = PCI_SUBVENDOR_ID_IBM, 2389 .subdevice = PCI_ANY_ID, 2390 .init = pci_oxsemi_tornado_init, 2391 .setup = pci_default_setup, 2392 }, 2393 { 2394 .vendor = PCI_VENDOR_ID_INTEL, 2395 .device = 0x8811, 2396 .subvendor = PCI_ANY_ID, 2397 .subdevice = PCI_ANY_ID, 2398 .init = pci_eg20t_init, 2399 .setup = pci_default_setup, 2400 }, 2401 { 2402 .vendor = PCI_VENDOR_ID_INTEL, 2403 .device = 0x8812, 2404 .subvendor = PCI_ANY_ID, 2405 .subdevice = PCI_ANY_ID, 2406 .init = pci_eg20t_init, 2407 .setup = pci_default_setup, 2408 }, 2409 { 2410 .vendor = PCI_VENDOR_ID_INTEL, 2411 .device = 0x8813, 2412 .subvendor = PCI_ANY_ID, 2413 .subdevice = PCI_ANY_ID, 2414 .init = pci_eg20t_init, 2415 .setup = pci_default_setup, 2416 }, 2417 { 2418 .vendor = PCI_VENDOR_ID_INTEL, 2419 .device = 0x8814, 2420 .subvendor = PCI_ANY_ID, 2421 .subdevice = PCI_ANY_ID, 2422 .init = pci_eg20t_init, 2423 .setup = pci_default_setup, 2424 }, 2425 { 2426 .vendor = 0x10DB, 2427 .device = 0x8027, 2428 .subvendor = PCI_ANY_ID, 2429 .subdevice = PCI_ANY_ID, 2430 .init = pci_eg20t_init, 2431 .setup = pci_default_setup, 2432 }, 2433 { 2434 .vendor = 0x10DB, 2435 .device = 0x8028, 2436 .subvendor = PCI_ANY_ID, 2437 .subdevice = PCI_ANY_ID, 2438 .init = pci_eg20t_init, 2439 .setup = pci_default_setup, 2440 }, 2441 { 2442 .vendor = 0x10DB, 2443 .device = 0x8029, 2444 .subvendor = PCI_ANY_ID, 2445 .subdevice = PCI_ANY_ID, 2446 .init = pci_eg20t_init, 2447 .setup = pci_default_setup, 2448 }, 2449 { 2450 .vendor = 0x10DB, 2451 .device = 0x800C, 2452 .subvendor = PCI_ANY_ID, 2453 .subdevice = PCI_ANY_ID, 2454 .init = pci_eg20t_init, 2455 .setup = pci_default_setup, 2456 }, 2457 { 2458 .vendor = 0x10DB, 2459 .device = 0x800D, 2460 .subvendor = PCI_ANY_ID, 2461 .subdevice = PCI_ANY_ID, 2462 .init = pci_eg20t_init, 2463 .setup = pci_default_setup, 2464 }, 2465 /* 2466 * Cronyx Omega PCI (PLX-chip based) 2467 */ 2468 { 2469 .vendor = PCI_VENDOR_ID_PLX, 2470 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2471 .subvendor = PCI_ANY_ID, 2472 .subdevice = PCI_ANY_ID, 2473 .setup = pci_omegapci_setup, 2474 }, 2475 /* WCH CH353 1S1P card (16550 clone) */ 2476 { 2477 .vendor = PCI_VENDOR_ID_WCH, 2478 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2479 .subvendor = PCI_ANY_ID, 2480 .subdevice = PCI_ANY_ID, 2481 .setup = pci_wch_ch353_setup, 2482 }, 2483 /* WCH CH353 2S1P card (16550 clone) */ 2484 { 2485 .vendor = PCI_VENDOR_ID_WCH, 2486 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2487 .subvendor = PCI_ANY_ID, 2488 .subdevice = PCI_ANY_ID, 2489 .setup = pci_wch_ch353_setup, 2490 }, 2491 /* WCH CH353 4S card (16550 clone) */ 2492 { 2493 .vendor = PCI_VENDOR_ID_WCH, 2494 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2495 .subvendor = PCI_ANY_ID, 2496 .subdevice = PCI_ANY_ID, 2497 .setup = pci_wch_ch353_setup, 2498 }, 2499 /* WCH CH353 2S1PF card (16550 clone) */ 2500 { 2501 .vendor = PCI_VENDOR_ID_WCH, 2502 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2503 .subvendor = PCI_ANY_ID, 2504 .subdevice = PCI_ANY_ID, 2505 .setup = pci_wch_ch353_setup, 2506 }, 2507 /* WCH CH352 2S card (16550 clone) */ 2508 { 2509 .vendor = PCI_VENDOR_ID_WCH, 2510 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2511 .subvendor = PCI_ANY_ID, 2512 .subdevice = PCI_ANY_ID, 2513 .setup = pci_wch_ch353_setup, 2514 }, 2515 /* WCH CH355 4S card (16550 clone) */ 2516 { 2517 .vendor = PCI_VENDOR_ID_WCH, 2518 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2519 .subvendor = PCI_ANY_ID, 2520 .subdevice = PCI_ANY_ID, 2521 .setup = pci_wch_ch355_setup, 2522 }, 2523 /* WCH CH382 2S card (16850 clone) */ 2524 { 2525 .vendor = PCIE_VENDOR_ID_WCH, 2526 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2527 .subvendor = PCI_ANY_ID, 2528 .subdevice = PCI_ANY_ID, 2529 .setup = pci_wch_ch38x_setup, 2530 }, 2531 /* WCH CH382 2S1P card (16850 clone) */ 2532 { 2533 .vendor = PCIE_VENDOR_ID_WCH, 2534 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2535 .subvendor = PCI_ANY_ID, 2536 .subdevice = PCI_ANY_ID, 2537 .setup = pci_wch_ch38x_setup, 2538 }, 2539 /* WCH CH384 4S card (16850 clone) */ 2540 { 2541 .vendor = PCIE_VENDOR_ID_WCH, 2542 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2543 .subvendor = PCI_ANY_ID, 2544 .subdevice = PCI_ANY_ID, 2545 .setup = pci_wch_ch38x_setup, 2546 }, 2547 /* 2548 * ASIX devices with FIFO bug 2549 */ 2550 { 2551 .vendor = PCI_VENDOR_ID_ASIX, 2552 .device = PCI_ANY_ID, 2553 .subvendor = PCI_ANY_ID, 2554 .subdevice = PCI_ANY_ID, 2555 .setup = pci_asix_setup, 2556 }, 2557 /* 2558 * Commtech, Inc. Fastcom adapters 2559 * 2560 */ 2561 { 2562 .vendor = PCI_VENDOR_ID_COMMTECH, 2563 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 2564 .subvendor = PCI_ANY_ID, 2565 .subdevice = PCI_ANY_ID, 2566 .setup = pci_fastcom335_setup, 2567 }, 2568 { 2569 .vendor = PCI_VENDOR_ID_COMMTECH, 2570 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 2571 .subvendor = PCI_ANY_ID, 2572 .subdevice = PCI_ANY_ID, 2573 .setup = pci_fastcom335_setup, 2574 }, 2575 { 2576 .vendor = PCI_VENDOR_ID_COMMTECH, 2577 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 2578 .subvendor = PCI_ANY_ID, 2579 .subdevice = PCI_ANY_ID, 2580 .setup = pci_fastcom335_setup, 2581 }, 2582 { 2583 .vendor = PCI_VENDOR_ID_COMMTECH, 2584 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 2585 .subvendor = PCI_ANY_ID, 2586 .subdevice = PCI_ANY_ID, 2587 .setup = pci_fastcom335_setup, 2588 }, 2589 { 2590 .vendor = PCI_VENDOR_ID_COMMTECH, 2591 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 2592 .subvendor = PCI_ANY_ID, 2593 .subdevice = PCI_ANY_ID, 2594 .setup = pci_xr17v35x_setup, 2595 }, 2596 { 2597 .vendor = PCI_VENDOR_ID_COMMTECH, 2598 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 2599 .subvendor = PCI_ANY_ID, 2600 .subdevice = PCI_ANY_ID, 2601 .setup = pci_xr17v35x_setup, 2602 }, 2603 { 2604 .vendor = PCI_VENDOR_ID_COMMTECH, 2605 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 2606 .subvendor = PCI_ANY_ID, 2607 .subdevice = PCI_ANY_ID, 2608 .setup = pci_xr17v35x_setup, 2609 }, 2610 /* 2611 * Broadcom TruManage (NetXtreme) 2612 */ 2613 { 2614 .vendor = PCI_VENDOR_ID_BROADCOM, 2615 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2616 .subvendor = PCI_ANY_ID, 2617 .subdevice = PCI_ANY_ID, 2618 .setup = pci_brcm_trumanage_setup, 2619 }, 2620 { 2621 .vendor = 0x1c29, 2622 .device = 0x1104, 2623 .subvendor = PCI_ANY_ID, 2624 .subdevice = PCI_ANY_ID, 2625 .setup = pci_fintek_setup, 2626 .init = pci_fintek_init, 2627 }, 2628 { 2629 .vendor = 0x1c29, 2630 .device = 0x1108, 2631 .subvendor = PCI_ANY_ID, 2632 .subdevice = PCI_ANY_ID, 2633 .setup = pci_fintek_setup, 2634 .init = pci_fintek_init, 2635 }, 2636 { 2637 .vendor = 0x1c29, 2638 .device = 0x1112, 2639 .subvendor = PCI_ANY_ID, 2640 .subdevice = PCI_ANY_ID, 2641 .setup = pci_fintek_setup, 2642 .init = pci_fintek_init, 2643 }, 2644 2645 /* 2646 * Default "match everything" terminator entry 2647 */ 2648 { 2649 .vendor = PCI_ANY_ID, 2650 .device = PCI_ANY_ID, 2651 .subvendor = PCI_ANY_ID, 2652 .subdevice = PCI_ANY_ID, 2653 .setup = pci_default_setup, 2654 } 2655 }; 2656 2657 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2658 { 2659 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2660 } 2661 2662 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2663 { 2664 struct pci_serial_quirk *quirk; 2665 2666 for (quirk = pci_serial_quirks; ; quirk++) 2667 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2668 quirk_id_matches(quirk->device, dev->device) && 2669 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2670 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2671 break; 2672 return quirk; 2673 } 2674 2675 static inline int get_pci_irq(struct pci_dev *dev, 2676 const struct pciserial_board *board) 2677 { 2678 if (board->flags & FL_NOIRQ) 2679 return 0; 2680 else 2681 return dev->irq; 2682 } 2683 2684 /* 2685 * This is the configuration table for all of the PCI serial boards 2686 * which we support. It is directly indexed by the pci_board_num_t enum 2687 * value, which is encoded in the pci_device_id PCI probe table's 2688 * driver_data member. 2689 * 2690 * The makeup of these names are: 2691 * pbn_bn{_bt}_n_baud{_offsetinhex} 2692 * 2693 * bn = PCI BAR number 2694 * bt = Index using PCI BARs 2695 * n = number of serial ports 2696 * baud = baud rate 2697 * offsetinhex = offset for each sequential port (in hex) 2698 * 2699 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2700 * 2701 * Please note: in theory if n = 1, _bt infix should make no difference. 2702 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2703 */ 2704 enum pci_board_num_t { 2705 pbn_default = 0, 2706 2707 pbn_b0_1_115200, 2708 pbn_b0_2_115200, 2709 pbn_b0_4_115200, 2710 pbn_b0_5_115200, 2711 pbn_b0_8_115200, 2712 2713 pbn_b0_1_921600, 2714 pbn_b0_2_921600, 2715 pbn_b0_4_921600, 2716 2717 pbn_b0_2_1130000, 2718 2719 pbn_b0_4_1152000, 2720 2721 pbn_b0_2_1152000_200, 2722 pbn_b0_4_1152000_200, 2723 pbn_b0_8_1152000_200, 2724 2725 pbn_b0_2_1843200, 2726 pbn_b0_4_1843200, 2727 2728 pbn_b0_2_1843200_200, 2729 pbn_b0_4_1843200_200, 2730 pbn_b0_8_1843200_200, 2731 2732 pbn_b0_1_4000000, 2733 2734 pbn_b0_bt_1_115200, 2735 pbn_b0_bt_2_115200, 2736 pbn_b0_bt_4_115200, 2737 pbn_b0_bt_8_115200, 2738 2739 pbn_b0_bt_1_460800, 2740 pbn_b0_bt_2_460800, 2741 pbn_b0_bt_4_460800, 2742 2743 pbn_b0_bt_1_921600, 2744 pbn_b0_bt_2_921600, 2745 pbn_b0_bt_4_921600, 2746 pbn_b0_bt_8_921600, 2747 2748 pbn_b1_1_115200, 2749 pbn_b1_2_115200, 2750 pbn_b1_4_115200, 2751 pbn_b1_8_115200, 2752 pbn_b1_16_115200, 2753 2754 pbn_b1_1_921600, 2755 pbn_b1_2_921600, 2756 pbn_b1_4_921600, 2757 pbn_b1_8_921600, 2758 2759 pbn_b1_2_1250000, 2760 2761 pbn_b1_bt_1_115200, 2762 pbn_b1_bt_2_115200, 2763 pbn_b1_bt_4_115200, 2764 2765 pbn_b1_bt_2_921600, 2766 2767 pbn_b1_1_1382400, 2768 pbn_b1_2_1382400, 2769 pbn_b1_4_1382400, 2770 pbn_b1_8_1382400, 2771 2772 pbn_b2_1_115200, 2773 pbn_b2_2_115200, 2774 pbn_b2_4_115200, 2775 pbn_b2_8_115200, 2776 2777 pbn_b2_1_460800, 2778 pbn_b2_4_460800, 2779 pbn_b2_8_460800, 2780 pbn_b2_16_460800, 2781 2782 pbn_b2_1_921600, 2783 pbn_b2_4_921600, 2784 pbn_b2_8_921600, 2785 2786 pbn_b2_8_1152000, 2787 2788 pbn_b2_bt_1_115200, 2789 pbn_b2_bt_2_115200, 2790 pbn_b2_bt_4_115200, 2791 2792 pbn_b2_bt_2_921600, 2793 pbn_b2_bt_4_921600, 2794 2795 pbn_b3_2_115200, 2796 pbn_b3_4_115200, 2797 pbn_b3_8_115200, 2798 2799 pbn_b4_bt_2_921600, 2800 pbn_b4_bt_4_921600, 2801 pbn_b4_bt_8_921600, 2802 2803 /* 2804 * Board-specific versions. 2805 */ 2806 pbn_panacom, 2807 pbn_panacom2, 2808 pbn_panacom4, 2809 pbn_plx_romulus, 2810 pbn_endrun_2_4000000, 2811 pbn_oxsemi, 2812 pbn_oxsemi_1_4000000, 2813 pbn_oxsemi_2_4000000, 2814 pbn_oxsemi_4_4000000, 2815 pbn_oxsemi_8_4000000, 2816 pbn_intel_i960, 2817 pbn_sgi_ioc3, 2818 pbn_computone_4, 2819 pbn_computone_6, 2820 pbn_computone_8, 2821 pbn_sbsxrsio, 2822 pbn_exar_XR17C152, 2823 pbn_exar_XR17C154, 2824 pbn_exar_XR17C158, 2825 pbn_exar_XR17V352, 2826 pbn_exar_XR17V354, 2827 pbn_exar_XR17V358, 2828 pbn_exar_XR17V4358, 2829 pbn_exar_XR17V8358, 2830 pbn_exar_ibm_saturn, 2831 pbn_pasemi_1682M, 2832 pbn_ni8430_2, 2833 pbn_ni8430_4, 2834 pbn_ni8430_8, 2835 pbn_ni8430_16, 2836 pbn_ADDIDATA_PCIe_1_3906250, 2837 pbn_ADDIDATA_PCIe_2_3906250, 2838 pbn_ADDIDATA_PCIe_4_3906250, 2839 pbn_ADDIDATA_PCIe_8_3906250, 2840 pbn_ce4100_1_115200, 2841 pbn_omegapci, 2842 pbn_NETMOS9900_2s_115200, 2843 pbn_brcm_trumanage, 2844 pbn_fintek_4, 2845 pbn_fintek_8, 2846 pbn_fintek_12, 2847 pbn_wch382_2, 2848 pbn_wch384_4, 2849 pbn_pericom_PI7C9X7951, 2850 pbn_pericom_PI7C9X7952, 2851 pbn_pericom_PI7C9X7954, 2852 pbn_pericom_PI7C9X7958, 2853 }; 2854 2855 /* 2856 * uart_offset - the space between channels 2857 * reg_shift - describes how the UART registers are mapped 2858 * to PCI memory by the card. 2859 * For example IER register on SBS, Inc. PMC-OctPro is located at 2860 * offset 0x10 from the UART base, while UART_IER is defined as 1 2861 * in include/linux/serial_reg.h, 2862 * see first lines of serial_in() and serial_out() in 8250.c 2863 */ 2864 2865 static struct pciserial_board pci_boards[] = { 2866 [pbn_default] = { 2867 .flags = FL_BASE0, 2868 .num_ports = 1, 2869 .base_baud = 115200, 2870 .uart_offset = 8, 2871 }, 2872 [pbn_b0_1_115200] = { 2873 .flags = FL_BASE0, 2874 .num_ports = 1, 2875 .base_baud = 115200, 2876 .uart_offset = 8, 2877 }, 2878 [pbn_b0_2_115200] = { 2879 .flags = FL_BASE0, 2880 .num_ports = 2, 2881 .base_baud = 115200, 2882 .uart_offset = 8, 2883 }, 2884 [pbn_b0_4_115200] = { 2885 .flags = FL_BASE0, 2886 .num_ports = 4, 2887 .base_baud = 115200, 2888 .uart_offset = 8, 2889 }, 2890 [pbn_b0_5_115200] = { 2891 .flags = FL_BASE0, 2892 .num_ports = 5, 2893 .base_baud = 115200, 2894 .uart_offset = 8, 2895 }, 2896 [pbn_b0_8_115200] = { 2897 .flags = FL_BASE0, 2898 .num_ports = 8, 2899 .base_baud = 115200, 2900 .uart_offset = 8, 2901 }, 2902 [pbn_b0_1_921600] = { 2903 .flags = FL_BASE0, 2904 .num_ports = 1, 2905 .base_baud = 921600, 2906 .uart_offset = 8, 2907 }, 2908 [pbn_b0_2_921600] = { 2909 .flags = FL_BASE0, 2910 .num_ports = 2, 2911 .base_baud = 921600, 2912 .uart_offset = 8, 2913 }, 2914 [pbn_b0_4_921600] = { 2915 .flags = FL_BASE0, 2916 .num_ports = 4, 2917 .base_baud = 921600, 2918 .uart_offset = 8, 2919 }, 2920 2921 [pbn_b0_2_1130000] = { 2922 .flags = FL_BASE0, 2923 .num_ports = 2, 2924 .base_baud = 1130000, 2925 .uart_offset = 8, 2926 }, 2927 2928 [pbn_b0_4_1152000] = { 2929 .flags = FL_BASE0, 2930 .num_ports = 4, 2931 .base_baud = 1152000, 2932 .uart_offset = 8, 2933 }, 2934 2935 [pbn_b0_2_1152000_200] = { 2936 .flags = FL_BASE0, 2937 .num_ports = 2, 2938 .base_baud = 1152000, 2939 .uart_offset = 0x200, 2940 }, 2941 2942 [pbn_b0_4_1152000_200] = { 2943 .flags = FL_BASE0, 2944 .num_ports = 4, 2945 .base_baud = 1152000, 2946 .uart_offset = 0x200, 2947 }, 2948 2949 [pbn_b0_8_1152000_200] = { 2950 .flags = FL_BASE0, 2951 .num_ports = 8, 2952 .base_baud = 1152000, 2953 .uart_offset = 0x200, 2954 }, 2955 2956 [pbn_b0_2_1843200] = { 2957 .flags = FL_BASE0, 2958 .num_ports = 2, 2959 .base_baud = 1843200, 2960 .uart_offset = 8, 2961 }, 2962 [pbn_b0_4_1843200] = { 2963 .flags = FL_BASE0, 2964 .num_ports = 4, 2965 .base_baud = 1843200, 2966 .uart_offset = 8, 2967 }, 2968 2969 [pbn_b0_2_1843200_200] = { 2970 .flags = FL_BASE0, 2971 .num_ports = 2, 2972 .base_baud = 1843200, 2973 .uart_offset = 0x200, 2974 }, 2975 [pbn_b0_4_1843200_200] = { 2976 .flags = FL_BASE0, 2977 .num_ports = 4, 2978 .base_baud = 1843200, 2979 .uart_offset = 0x200, 2980 }, 2981 [pbn_b0_8_1843200_200] = { 2982 .flags = FL_BASE0, 2983 .num_ports = 8, 2984 .base_baud = 1843200, 2985 .uart_offset = 0x200, 2986 }, 2987 [pbn_b0_1_4000000] = { 2988 .flags = FL_BASE0, 2989 .num_ports = 1, 2990 .base_baud = 4000000, 2991 .uart_offset = 8, 2992 }, 2993 2994 [pbn_b0_bt_1_115200] = { 2995 .flags = FL_BASE0|FL_BASE_BARS, 2996 .num_ports = 1, 2997 .base_baud = 115200, 2998 .uart_offset = 8, 2999 }, 3000 [pbn_b0_bt_2_115200] = { 3001 .flags = FL_BASE0|FL_BASE_BARS, 3002 .num_ports = 2, 3003 .base_baud = 115200, 3004 .uart_offset = 8, 3005 }, 3006 [pbn_b0_bt_4_115200] = { 3007 .flags = FL_BASE0|FL_BASE_BARS, 3008 .num_ports = 4, 3009 .base_baud = 115200, 3010 .uart_offset = 8, 3011 }, 3012 [pbn_b0_bt_8_115200] = { 3013 .flags = FL_BASE0|FL_BASE_BARS, 3014 .num_ports = 8, 3015 .base_baud = 115200, 3016 .uart_offset = 8, 3017 }, 3018 3019 [pbn_b0_bt_1_460800] = { 3020 .flags = FL_BASE0|FL_BASE_BARS, 3021 .num_ports = 1, 3022 .base_baud = 460800, 3023 .uart_offset = 8, 3024 }, 3025 [pbn_b0_bt_2_460800] = { 3026 .flags = FL_BASE0|FL_BASE_BARS, 3027 .num_ports = 2, 3028 .base_baud = 460800, 3029 .uart_offset = 8, 3030 }, 3031 [pbn_b0_bt_4_460800] = { 3032 .flags = FL_BASE0|FL_BASE_BARS, 3033 .num_ports = 4, 3034 .base_baud = 460800, 3035 .uart_offset = 8, 3036 }, 3037 3038 [pbn_b0_bt_1_921600] = { 3039 .flags = FL_BASE0|FL_BASE_BARS, 3040 .num_ports = 1, 3041 .base_baud = 921600, 3042 .uart_offset = 8, 3043 }, 3044 [pbn_b0_bt_2_921600] = { 3045 .flags = FL_BASE0|FL_BASE_BARS, 3046 .num_ports = 2, 3047 .base_baud = 921600, 3048 .uart_offset = 8, 3049 }, 3050 [pbn_b0_bt_4_921600] = { 3051 .flags = FL_BASE0|FL_BASE_BARS, 3052 .num_ports = 4, 3053 .base_baud = 921600, 3054 .uart_offset = 8, 3055 }, 3056 [pbn_b0_bt_8_921600] = { 3057 .flags = FL_BASE0|FL_BASE_BARS, 3058 .num_ports = 8, 3059 .base_baud = 921600, 3060 .uart_offset = 8, 3061 }, 3062 3063 [pbn_b1_1_115200] = { 3064 .flags = FL_BASE1, 3065 .num_ports = 1, 3066 .base_baud = 115200, 3067 .uart_offset = 8, 3068 }, 3069 [pbn_b1_2_115200] = { 3070 .flags = FL_BASE1, 3071 .num_ports = 2, 3072 .base_baud = 115200, 3073 .uart_offset = 8, 3074 }, 3075 [pbn_b1_4_115200] = { 3076 .flags = FL_BASE1, 3077 .num_ports = 4, 3078 .base_baud = 115200, 3079 .uart_offset = 8, 3080 }, 3081 [pbn_b1_8_115200] = { 3082 .flags = FL_BASE1, 3083 .num_ports = 8, 3084 .base_baud = 115200, 3085 .uart_offset = 8, 3086 }, 3087 [pbn_b1_16_115200] = { 3088 .flags = FL_BASE1, 3089 .num_ports = 16, 3090 .base_baud = 115200, 3091 .uart_offset = 8, 3092 }, 3093 3094 [pbn_b1_1_921600] = { 3095 .flags = FL_BASE1, 3096 .num_ports = 1, 3097 .base_baud = 921600, 3098 .uart_offset = 8, 3099 }, 3100 [pbn_b1_2_921600] = { 3101 .flags = FL_BASE1, 3102 .num_ports = 2, 3103 .base_baud = 921600, 3104 .uart_offset = 8, 3105 }, 3106 [pbn_b1_4_921600] = { 3107 .flags = FL_BASE1, 3108 .num_ports = 4, 3109 .base_baud = 921600, 3110 .uart_offset = 8, 3111 }, 3112 [pbn_b1_8_921600] = { 3113 .flags = FL_BASE1, 3114 .num_ports = 8, 3115 .base_baud = 921600, 3116 .uart_offset = 8, 3117 }, 3118 [pbn_b1_2_1250000] = { 3119 .flags = FL_BASE1, 3120 .num_ports = 2, 3121 .base_baud = 1250000, 3122 .uart_offset = 8, 3123 }, 3124 3125 [pbn_b1_bt_1_115200] = { 3126 .flags = FL_BASE1|FL_BASE_BARS, 3127 .num_ports = 1, 3128 .base_baud = 115200, 3129 .uart_offset = 8, 3130 }, 3131 [pbn_b1_bt_2_115200] = { 3132 .flags = FL_BASE1|FL_BASE_BARS, 3133 .num_ports = 2, 3134 .base_baud = 115200, 3135 .uart_offset = 8, 3136 }, 3137 [pbn_b1_bt_4_115200] = { 3138 .flags = FL_BASE1|FL_BASE_BARS, 3139 .num_ports = 4, 3140 .base_baud = 115200, 3141 .uart_offset = 8, 3142 }, 3143 3144 [pbn_b1_bt_2_921600] = { 3145 .flags = FL_BASE1|FL_BASE_BARS, 3146 .num_ports = 2, 3147 .base_baud = 921600, 3148 .uart_offset = 8, 3149 }, 3150 3151 [pbn_b1_1_1382400] = { 3152 .flags = FL_BASE1, 3153 .num_ports = 1, 3154 .base_baud = 1382400, 3155 .uart_offset = 8, 3156 }, 3157 [pbn_b1_2_1382400] = { 3158 .flags = FL_BASE1, 3159 .num_ports = 2, 3160 .base_baud = 1382400, 3161 .uart_offset = 8, 3162 }, 3163 [pbn_b1_4_1382400] = { 3164 .flags = FL_BASE1, 3165 .num_ports = 4, 3166 .base_baud = 1382400, 3167 .uart_offset = 8, 3168 }, 3169 [pbn_b1_8_1382400] = { 3170 .flags = FL_BASE1, 3171 .num_ports = 8, 3172 .base_baud = 1382400, 3173 .uart_offset = 8, 3174 }, 3175 3176 [pbn_b2_1_115200] = { 3177 .flags = FL_BASE2, 3178 .num_ports = 1, 3179 .base_baud = 115200, 3180 .uart_offset = 8, 3181 }, 3182 [pbn_b2_2_115200] = { 3183 .flags = FL_BASE2, 3184 .num_ports = 2, 3185 .base_baud = 115200, 3186 .uart_offset = 8, 3187 }, 3188 [pbn_b2_4_115200] = { 3189 .flags = FL_BASE2, 3190 .num_ports = 4, 3191 .base_baud = 115200, 3192 .uart_offset = 8, 3193 }, 3194 [pbn_b2_8_115200] = { 3195 .flags = FL_BASE2, 3196 .num_ports = 8, 3197 .base_baud = 115200, 3198 .uart_offset = 8, 3199 }, 3200 3201 [pbn_b2_1_460800] = { 3202 .flags = FL_BASE2, 3203 .num_ports = 1, 3204 .base_baud = 460800, 3205 .uart_offset = 8, 3206 }, 3207 [pbn_b2_4_460800] = { 3208 .flags = FL_BASE2, 3209 .num_ports = 4, 3210 .base_baud = 460800, 3211 .uart_offset = 8, 3212 }, 3213 [pbn_b2_8_460800] = { 3214 .flags = FL_BASE2, 3215 .num_ports = 8, 3216 .base_baud = 460800, 3217 .uart_offset = 8, 3218 }, 3219 [pbn_b2_16_460800] = { 3220 .flags = FL_BASE2, 3221 .num_ports = 16, 3222 .base_baud = 460800, 3223 .uart_offset = 8, 3224 }, 3225 3226 [pbn_b2_1_921600] = { 3227 .flags = FL_BASE2, 3228 .num_ports = 1, 3229 .base_baud = 921600, 3230 .uart_offset = 8, 3231 }, 3232 [pbn_b2_4_921600] = { 3233 .flags = FL_BASE2, 3234 .num_ports = 4, 3235 .base_baud = 921600, 3236 .uart_offset = 8, 3237 }, 3238 [pbn_b2_8_921600] = { 3239 .flags = FL_BASE2, 3240 .num_ports = 8, 3241 .base_baud = 921600, 3242 .uart_offset = 8, 3243 }, 3244 3245 [pbn_b2_8_1152000] = { 3246 .flags = FL_BASE2, 3247 .num_ports = 8, 3248 .base_baud = 1152000, 3249 .uart_offset = 8, 3250 }, 3251 3252 [pbn_b2_bt_1_115200] = { 3253 .flags = FL_BASE2|FL_BASE_BARS, 3254 .num_ports = 1, 3255 .base_baud = 115200, 3256 .uart_offset = 8, 3257 }, 3258 [pbn_b2_bt_2_115200] = { 3259 .flags = FL_BASE2|FL_BASE_BARS, 3260 .num_ports = 2, 3261 .base_baud = 115200, 3262 .uart_offset = 8, 3263 }, 3264 [pbn_b2_bt_4_115200] = { 3265 .flags = FL_BASE2|FL_BASE_BARS, 3266 .num_ports = 4, 3267 .base_baud = 115200, 3268 .uart_offset = 8, 3269 }, 3270 3271 [pbn_b2_bt_2_921600] = { 3272 .flags = FL_BASE2|FL_BASE_BARS, 3273 .num_ports = 2, 3274 .base_baud = 921600, 3275 .uart_offset = 8, 3276 }, 3277 [pbn_b2_bt_4_921600] = { 3278 .flags = FL_BASE2|FL_BASE_BARS, 3279 .num_ports = 4, 3280 .base_baud = 921600, 3281 .uart_offset = 8, 3282 }, 3283 3284 [pbn_b3_2_115200] = { 3285 .flags = FL_BASE3, 3286 .num_ports = 2, 3287 .base_baud = 115200, 3288 .uart_offset = 8, 3289 }, 3290 [pbn_b3_4_115200] = { 3291 .flags = FL_BASE3, 3292 .num_ports = 4, 3293 .base_baud = 115200, 3294 .uart_offset = 8, 3295 }, 3296 [pbn_b3_8_115200] = { 3297 .flags = FL_BASE3, 3298 .num_ports = 8, 3299 .base_baud = 115200, 3300 .uart_offset = 8, 3301 }, 3302 3303 [pbn_b4_bt_2_921600] = { 3304 .flags = FL_BASE4, 3305 .num_ports = 2, 3306 .base_baud = 921600, 3307 .uart_offset = 8, 3308 }, 3309 [pbn_b4_bt_4_921600] = { 3310 .flags = FL_BASE4, 3311 .num_ports = 4, 3312 .base_baud = 921600, 3313 .uart_offset = 8, 3314 }, 3315 [pbn_b4_bt_8_921600] = { 3316 .flags = FL_BASE4, 3317 .num_ports = 8, 3318 .base_baud = 921600, 3319 .uart_offset = 8, 3320 }, 3321 3322 /* 3323 * Entries following this are board-specific. 3324 */ 3325 3326 /* 3327 * Panacom - IOMEM 3328 */ 3329 [pbn_panacom] = { 3330 .flags = FL_BASE2, 3331 .num_ports = 2, 3332 .base_baud = 921600, 3333 .uart_offset = 0x400, 3334 .reg_shift = 7, 3335 }, 3336 [pbn_panacom2] = { 3337 .flags = FL_BASE2|FL_BASE_BARS, 3338 .num_ports = 2, 3339 .base_baud = 921600, 3340 .uart_offset = 0x400, 3341 .reg_shift = 7, 3342 }, 3343 [pbn_panacom4] = { 3344 .flags = FL_BASE2|FL_BASE_BARS, 3345 .num_ports = 4, 3346 .base_baud = 921600, 3347 .uart_offset = 0x400, 3348 .reg_shift = 7, 3349 }, 3350 3351 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3352 [pbn_plx_romulus] = { 3353 .flags = FL_BASE2, 3354 .num_ports = 4, 3355 .base_baud = 921600, 3356 .uart_offset = 8 << 2, 3357 .reg_shift = 2, 3358 .first_offset = 0x03, 3359 }, 3360 3361 /* 3362 * EndRun Technologies 3363 * Uses the size of PCI Base region 0 to 3364 * signal now many ports are available 3365 * 2 port 952 Uart support 3366 */ 3367 [pbn_endrun_2_4000000] = { 3368 .flags = FL_BASE0, 3369 .num_ports = 2, 3370 .base_baud = 4000000, 3371 .uart_offset = 0x200, 3372 .first_offset = 0x1000, 3373 }, 3374 3375 /* 3376 * This board uses the size of PCI Base region 0 to 3377 * signal now many ports are available 3378 */ 3379 [pbn_oxsemi] = { 3380 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3381 .num_ports = 32, 3382 .base_baud = 115200, 3383 .uart_offset = 8, 3384 }, 3385 [pbn_oxsemi_1_4000000] = { 3386 .flags = FL_BASE0, 3387 .num_ports = 1, 3388 .base_baud = 4000000, 3389 .uart_offset = 0x200, 3390 .first_offset = 0x1000, 3391 }, 3392 [pbn_oxsemi_2_4000000] = { 3393 .flags = FL_BASE0, 3394 .num_ports = 2, 3395 .base_baud = 4000000, 3396 .uart_offset = 0x200, 3397 .first_offset = 0x1000, 3398 }, 3399 [pbn_oxsemi_4_4000000] = { 3400 .flags = FL_BASE0, 3401 .num_ports = 4, 3402 .base_baud = 4000000, 3403 .uart_offset = 0x200, 3404 .first_offset = 0x1000, 3405 }, 3406 [pbn_oxsemi_8_4000000] = { 3407 .flags = FL_BASE0, 3408 .num_ports = 8, 3409 .base_baud = 4000000, 3410 .uart_offset = 0x200, 3411 .first_offset = 0x1000, 3412 }, 3413 3414 3415 /* 3416 * EKF addition for i960 Boards form EKF with serial port. 3417 * Max 256 ports. 3418 */ 3419 [pbn_intel_i960] = { 3420 .flags = FL_BASE0, 3421 .num_ports = 32, 3422 .base_baud = 921600, 3423 .uart_offset = 8 << 2, 3424 .reg_shift = 2, 3425 .first_offset = 0x10000, 3426 }, 3427 [pbn_sgi_ioc3] = { 3428 .flags = FL_BASE0|FL_NOIRQ, 3429 .num_ports = 1, 3430 .base_baud = 458333, 3431 .uart_offset = 8, 3432 .reg_shift = 0, 3433 .first_offset = 0x20178, 3434 }, 3435 3436 /* 3437 * Computone - uses IOMEM. 3438 */ 3439 [pbn_computone_4] = { 3440 .flags = FL_BASE0, 3441 .num_ports = 4, 3442 .base_baud = 921600, 3443 .uart_offset = 0x40, 3444 .reg_shift = 2, 3445 .first_offset = 0x200, 3446 }, 3447 [pbn_computone_6] = { 3448 .flags = FL_BASE0, 3449 .num_ports = 6, 3450 .base_baud = 921600, 3451 .uart_offset = 0x40, 3452 .reg_shift = 2, 3453 .first_offset = 0x200, 3454 }, 3455 [pbn_computone_8] = { 3456 .flags = FL_BASE0, 3457 .num_ports = 8, 3458 .base_baud = 921600, 3459 .uart_offset = 0x40, 3460 .reg_shift = 2, 3461 .first_offset = 0x200, 3462 }, 3463 [pbn_sbsxrsio] = { 3464 .flags = FL_BASE0, 3465 .num_ports = 8, 3466 .base_baud = 460800, 3467 .uart_offset = 256, 3468 .reg_shift = 4, 3469 }, 3470 /* 3471 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3472 * Only basic 16550A support. 3473 * XR17C15[24] are not tested, but they should work. 3474 */ 3475 [pbn_exar_XR17C152] = { 3476 .flags = FL_BASE0, 3477 .num_ports = 2, 3478 .base_baud = 921600, 3479 .uart_offset = 0x200, 3480 }, 3481 [pbn_exar_XR17C154] = { 3482 .flags = FL_BASE0, 3483 .num_ports = 4, 3484 .base_baud = 921600, 3485 .uart_offset = 0x200, 3486 }, 3487 [pbn_exar_XR17C158] = { 3488 .flags = FL_BASE0, 3489 .num_ports = 8, 3490 .base_baud = 921600, 3491 .uart_offset = 0x200, 3492 }, 3493 [pbn_exar_XR17V352] = { 3494 .flags = FL_BASE0, 3495 .num_ports = 2, 3496 .base_baud = 7812500, 3497 .uart_offset = 0x400, 3498 .reg_shift = 0, 3499 .first_offset = 0, 3500 }, 3501 [pbn_exar_XR17V354] = { 3502 .flags = FL_BASE0, 3503 .num_ports = 4, 3504 .base_baud = 7812500, 3505 .uart_offset = 0x400, 3506 .reg_shift = 0, 3507 .first_offset = 0, 3508 }, 3509 [pbn_exar_XR17V358] = { 3510 .flags = FL_BASE0, 3511 .num_ports = 8, 3512 .base_baud = 7812500, 3513 .uart_offset = 0x400, 3514 .reg_shift = 0, 3515 .first_offset = 0, 3516 }, 3517 [pbn_exar_XR17V4358] = { 3518 .flags = FL_BASE0, 3519 .num_ports = 12, 3520 .base_baud = 7812500, 3521 .uart_offset = 0x400, 3522 .reg_shift = 0, 3523 .first_offset = 0, 3524 }, 3525 [pbn_exar_XR17V8358] = { 3526 .flags = FL_BASE0, 3527 .num_ports = 16, 3528 .base_baud = 7812500, 3529 .uart_offset = 0x400, 3530 .reg_shift = 0, 3531 .first_offset = 0, 3532 }, 3533 [pbn_exar_ibm_saturn] = { 3534 .flags = FL_BASE0, 3535 .num_ports = 1, 3536 .base_baud = 921600, 3537 .uart_offset = 0x200, 3538 }, 3539 3540 /* 3541 * PA Semi PWRficient PA6T-1682M on-chip UART 3542 */ 3543 [pbn_pasemi_1682M] = { 3544 .flags = FL_BASE0, 3545 .num_ports = 1, 3546 .base_baud = 8333333, 3547 }, 3548 /* 3549 * National Instruments 843x 3550 */ 3551 [pbn_ni8430_16] = { 3552 .flags = FL_BASE0, 3553 .num_ports = 16, 3554 .base_baud = 3686400, 3555 .uart_offset = 0x10, 3556 .first_offset = 0x800, 3557 }, 3558 [pbn_ni8430_8] = { 3559 .flags = FL_BASE0, 3560 .num_ports = 8, 3561 .base_baud = 3686400, 3562 .uart_offset = 0x10, 3563 .first_offset = 0x800, 3564 }, 3565 [pbn_ni8430_4] = { 3566 .flags = FL_BASE0, 3567 .num_ports = 4, 3568 .base_baud = 3686400, 3569 .uart_offset = 0x10, 3570 .first_offset = 0x800, 3571 }, 3572 [pbn_ni8430_2] = { 3573 .flags = FL_BASE0, 3574 .num_ports = 2, 3575 .base_baud = 3686400, 3576 .uart_offset = 0x10, 3577 .first_offset = 0x800, 3578 }, 3579 /* 3580 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3581 */ 3582 [pbn_ADDIDATA_PCIe_1_3906250] = { 3583 .flags = FL_BASE0, 3584 .num_ports = 1, 3585 .base_baud = 3906250, 3586 .uart_offset = 0x200, 3587 .first_offset = 0x1000, 3588 }, 3589 [pbn_ADDIDATA_PCIe_2_3906250] = { 3590 .flags = FL_BASE0, 3591 .num_ports = 2, 3592 .base_baud = 3906250, 3593 .uart_offset = 0x200, 3594 .first_offset = 0x1000, 3595 }, 3596 [pbn_ADDIDATA_PCIe_4_3906250] = { 3597 .flags = FL_BASE0, 3598 .num_ports = 4, 3599 .base_baud = 3906250, 3600 .uart_offset = 0x200, 3601 .first_offset = 0x1000, 3602 }, 3603 [pbn_ADDIDATA_PCIe_8_3906250] = { 3604 .flags = FL_BASE0, 3605 .num_ports = 8, 3606 .base_baud = 3906250, 3607 .uart_offset = 0x200, 3608 .first_offset = 0x1000, 3609 }, 3610 [pbn_ce4100_1_115200] = { 3611 .flags = FL_BASE_BARS, 3612 .num_ports = 2, 3613 .base_baud = 921600, 3614 .reg_shift = 2, 3615 }, 3616 [pbn_omegapci] = { 3617 .flags = FL_BASE0, 3618 .num_ports = 8, 3619 .base_baud = 115200, 3620 .uart_offset = 0x200, 3621 }, 3622 [pbn_NETMOS9900_2s_115200] = { 3623 .flags = FL_BASE0, 3624 .num_ports = 2, 3625 .base_baud = 115200, 3626 }, 3627 [pbn_brcm_trumanage] = { 3628 .flags = FL_BASE0, 3629 .num_ports = 1, 3630 .reg_shift = 2, 3631 .base_baud = 115200, 3632 }, 3633 [pbn_fintek_4] = { 3634 .num_ports = 4, 3635 .uart_offset = 8, 3636 .base_baud = 115200, 3637 .first_offset = 0x40, 3638 }, 3639 [pbn_fintek_8] = { 3640 .num_ports = 8, 3641 .uart_offset = 8, 3642 .base_baud = 115200, 3643 .first_offset = 0x40, 3644 }, 3645 [pbn_fintek_12] = { 3646 .num_ports = 12, 3647 .uart_offset = 8, 3648 .base_baud = 115200, 3649 .first_offset = 0x40, 3650 }, 3651 [pbn_wch382_2] = { 3652 .flags = FL_BASE0, 3653 .num_ports = 2, 3654 .base_baud = 115200, 3655 .uart_offset = 8, 3656 .first_offset = 0xC0, 3657 }, 3658 [pbn_wch384_4] = { 3659 .flags = FL_BASE0, 3660 .num_ports = 4, 3661 .base_baud = 115200, 3662 .uart_offset = 8, 3663 .first_offset = 0xC0, 3664 }, 3665 /* 3666 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3667 */ 3668 [pbn_pericom_PI7C9X7951] = { 3669 .flags = FL_BASE0, 3670 .num_ports = 1, 3671 .base_baud = 921600, 3672 .uart_offset = 0x8, 3673 }, 3674 [pbn_pericom_PI7C9X7952] = { 3675 .flags = FL_BASE0, 3676 .num_ports = 2, 3677 .base_baud = 921600, 3678 .uart_offset = 0x8, 3679 }, 3680 [pbn_pericom_PI7C9X7954] = { 3681 .flags = FL_BASE0, 3682 .num_ports = 4, 3683 .base_baud = 921600, 3684 .uart_offset = 0x8, 3685 }, 3686 [pbn_pericom_PI7C9X7958] = { 3687 .flags = FL_BASE0, 3688 .num_ports = 8, 3689 .base_baud = 921600, 3690 .uart_offset = 0x8, 3691 }, 3692 }; 3693 3694 static const struct pci_device_id blacklist[] = { 3695 /* softmodems */ 3696 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3697 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3698 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3699 3700 /* multi-io cards handled by parport_serial */ 3701 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3702 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3703 { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */ 3704 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3705 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ 3706 3707 /* Moxa Smartio MUE boards handled by 8250_moxa */ 3708 { PCI_VDEVICE(MOXA, 0x1024), }, 3709 { PCI_VDEVICE(MOXA, 0x1025), }, 3710 { PCI_VDEVICE(MOXA, 0x1045), }, 3711 { PCI_VDEVICE(MOXA, 0x1144), }, 3712 { PCI_VDEVICE(MOXA, 0x1160), }, 3713 { PCI_VDEVICE(MOXA, 0x1161), }, 3714 { PCI_VDEVICE(MOXA, 0x1182), }, 3715 { PCI_VDEVICE(MOXA, 0x1183), }, 3716 { PCI_VDEVICE(MOXA, 0x1322), }, 3717 { PCI_VDEVICE(MOXA, 0x1342), }, 3718 { PCI_VDEVICE(MOXA, 0x1381), }, 3719 { PCI_VDEVICE(MOXA, 0x1683), }, 3720 3721 /* Intel platforms with MID UART */ 3722 { PCI_VDEVICE(INTEL, 0x081b), }, 3723 { PCI_VDEVICE(INTEL, 0x081c), }, 3724 { PCI_VDEVICE(INTEL, 0x081d), }, 3725 { PCI_VDEVICE(INTEL, 0x1191), }, 3726 { PCI_VDEVICE(INTEL, 0x19d8), }, 3727 3728 /* Intel platforms with DesignWare UART */ 3729 { PCI_VDEVICE(INTEL, 0x0936), }, 3730 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3731 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3732 { PCI_VDEVICE(INTEL, 0x228a), }, 3733 { PCI_VDEVICE(INTEL, 0x228c), }, 3734 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3735 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3736 }; 3737 3738 /* 3739 * Given a complete unknown PCI device, try to use some heuristics to 3740 * guess what the configuration might be, based on the pitiful PCI 3741 * serial specs. Returns 0 on success, 1 on failure. 3742 */ 3743 static int 3744 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3745 { 3746 const struct pci_device_id *bldev; 3747 int num_iomem, num_port, first_port = -1, i; 3748 3749 /* 3750 * If it is not a communications device or the programming 3751 * interface is greater than 6, give up. 3752 * 3753 * (Should we try to make guesses for multiport serial devices 3754 * later?) 3755 */ 3756 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3757 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3758 (dev->class & 0xff) > 6) 3759 return -ENODEV; 3760 3761 /* 3762 * Do not access blacklisted devices that are known not to 3763 * feature serial ports or are handled by other modules. 3764 */ 3765 for (bldev = blacklist; 3766 bldev < blacklist + ARRAY_SIZE(blacklist); 3767 bldev++) { 3768 if (dev->vendor == bldev->vendor && 3769 dev->device == bldev->device) 3770 return -ENODEV; 3771 } 3772 3773 num_iomem = num_port = 0; 3774 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3775 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3776 num_port++; 3777 if (first_port == -1) 3778 first_port = i; 3779 } 3780 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3781 num_iomem++; 3782 } 3783 3784 /* 3785 * If there is 1 or 0 iomem regions, and exactly one port, 3786 * use it. We guess the number of ports based on the IO 3787 * region size. 3788 */ 3789 if (num_iomem <= 1 && num_port == 1) { 3790 board->flags = first_port; 3791 board->num_ports = pci_resource_len(dev, first_port) / 8; 3792 return 0; 3793 } 3794 3795 /* 3796 * Now guess if we've got a board which indexes by BARs. 3797 * Each IO BAR should be 8 bytes, and they should follow 3798 * consecutively. 3799 */ 3800 first_port = -1; 3801 num_port = 0; 3802 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3803 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3804 pci_resource_len(dev, i) == 8 && 3805 (first_port == -1 || (first_port + num_port) == i)) { 3806 num_port++; 3807 if (first_port == -1) 3808 first_port = i; 3809 } 3810 } 3811 3812 if (num_port > 1) { 3813 board->flags = first_port | FL_BASE_BARS; 3814 board->num_ports = num_port; 3815 return 0; 3816 } 3817 3818 return -ENODEV; 3819 } 3820 3821 static inline int 3822 serial_pci_matches(const struct pciserial_board *board, 3823 const struct pciserial_board *guessed) 3824 { 3825 return 3826 board->num_ports == guessed->num_ports && 3827 board->base_baud == guessed->base_baud && 3828 board->uart_offset == guessed->uart_offset && 3829 board->reg_shift == guessed->reg_shift && 3830 board->first_offset == guessed->first_offset; 3831 } 3832 3833 struct serial_private * 3834 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3835 { 3836 struct uart_8250_port uart; 3837 struct serial_private *priv; 3838 struct pci_serial_quirk *quirk; 3839 int rc, nr_ports, i; 3840 3841 nr_ports = board->num_ports; 3842 3843 /* 3844 * Find an init and setup quirks. 3845 */ 3846 quirk = find_quirk(dev); 3847 3848 /* 3849 * Run the new-style initialization function. 3850 * The initialization function returns: 3851 * <0 - error 3852 * 0 - use board->num_ports 3853 * >0 - number of ports 3854 */ 3855 if (quirk->init) { 3856 rc = quirk->init(dev); 3857 if (rc < 0) { 3858 priv = ERR_PTR(rc); 3859 goto err_out; 3860 } 3861 if (rc) 3862 nr_ports = rc; 3863 } 3864 3865 priv = kzalloc(sizeof(struct serial_private) + 3866 sizeof(unsigned int) * nr_ports, 3867 GFP_KERNEL); 3868 if (!priv) { 3869 priv = ERR_PTR(-ENOMEM); 3870 goto err_deinit; 3871 } 3872 3873 priv->dev = dev; 3874 priv->quirk = quirk; 3875 3876 memset(&uart, 0, sizeof(uart)); 3877 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3878 uart.port.uartclk = board->base_baud * 16; 3879 uart.port.irq = get_pci_irq(dev, board); 3880 uart.port.dev = &dev->dev; 3881 3882 for (i = 0; i < nr_ports; i++) { 3883 if (quirk->setup(priv, board, &uart, i)) 3884 break; 3885 3886 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3887 uart.port.iobase, uart.port.irq, uart.port.iotype); 3888 3889 priv->line[i] = serial8250_register_8250_port(&uart); 3890 if (priv->line[i] < 0) { 3891 dev_err(&dev->dev, 3892 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3893 uart.port.iobase, uart.port.irq, 3894 uart.port.iotype, priv->line[i]); 3895 break; 3896 } 3897 } 3898 priv->nr = i; 3899 return priv; 3900 3901 err_deinit: 3902 if (quirk->exit) 3903 quirk->exit(dev); 3904 err_out: 3905 return priv; 3906 } 3907 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3908 3909 void pciserial_remove_ports(struct serial_private *priv) 3910 { 3911 struct pci_serial_quirk *quirk; 3912 int i; 3913 3914 for (i = 0; i < priv->nr; i++) 3915 serial8250_unregister_port(priv->line[i]); 3916 3917 /* 3918 * Find the exit quirks. 3919 */ 3920 quirk = find_quirk(priv->dev); 3921 if (quirk->exit) 3922 quirk->exit(priv->dev); 3923 3924 kfree(priv); 3925 } 3926 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3927 3928 void pciserial_suspend_ports(struct serial_private *priv) 3929 { 3930 int i; 3931 3932 for (i = 0; i < priv->nr; i++) 3933 if (priv->line[i] >= 0) 3934 serial8250_suspend_port(priv->line[i]); 3935 3936 /* 3937 * Ensure that every init quirk is properly torn down 3938 */ 3939 if (priv->quirk->exit) 3940 priv->quirk->exit(priv->dev); 3941 } 3942 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3943 3944 void pciserial_resume_ports(struct serial_private *priv) 3945 { 3946 int i; 3947 3948 /* 3949 * Ensure that the board is correctly configured. 3950 */ 3951 if (priv->quirk->init) 3952 priv->quirk->init(priv->dev); 3953 3954 for (i = 0; i < priv->nr; i++) 3955 if (priv->line[i] >= 0) 3956 serial8250_resume_port(priv->line[i]); 3957 } 3958 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3959 3960 /* 3961 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3962 * to the arrangement of serial ports on a PCI card. 3963 */ 3964 static int 3965 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3966 { 3967 struct pci_serial_quirk *quirk; 3968 struct serial_private *priv; 3969 const struct pciserial_board *board; 3970 struct pciserial_board tmp; 3971 int rc; 3972 3973 quirk = find_quirk(dev); 3974 if (quirk->probe) { 3975 rc = quirk->probe(dev); 3976 if (rc) 3977 return rc; 3978 } 3979 3980 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3981 dev_err(&dev->dev, "invalid driver_data: %ld\n", 3982 ent->driver_data); 3983 return -EINVAL; 3984 } 3985 3986 board = &pci_boards[ent->driver_data]; 3987 3988 rc = pcim_enable_device(dev); 3989 pci_save_state(dev); 3990 if (rc) 3991 return rc; 3992 3993 if (ent->driver_data == pbn_default) { 3994 /* 3995 * Use a copy of the pci_board entry for this; 3996 * avoid changing entries in the table. 3997 */ 3998 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3999 board = &tmp; 4000 4001 /* 4002 * We matched one of our class entries. Try to 4003 * determine the parameters of this board. 4004 */ 4005 rc = serial_pci_guess_board(dev, &tmp); 4006 if (rc) 4007 return rc; 4008 } else { 4009 /* 4010 * We matched an explicit entry. If we are able to 4011 * detect this boards settings with our heuristic, 4012 * then we no longer need this entry. 4013 */ 4014 memcpy(&tmp, &pci_boards[pbn_default], 4015 sizeof(struct pciserial_board)); 4016 rc = serial_pci_guess_board(dev, &tmp); 4017 if (rc == 0 && serial_pci_matches(board, &tmp)) 4018 moan_device("Redundant entry in serial pci_table.", 4019 dev); 4020 } 4021 4022 priv = pciserial_init_ports(dev, board); 4023 if (IS_ERR(priv)) 4024 return PTR_ERR(priv); 4025 4026 pci_set_drvdata(dev, priv); 4027 return 0; 4028 } 4029 4030 static void pciserial_remove_one(struct pci_dev *dev) 4031 { 4032 struct serial_private *priv = pci_get_drvdata(dev); 4033 4034 pciserial_remove_ports(priv); 4035 } 4036 4037 #ifdef CONFIG_PM_SLEEP 4038 static int pciserial_suspend_one(struct device *dev) 4039 { 4040 struct pci_dev *pdev = to_pci_dev(dev); 4041 struct serial_private *priv = pci_get_drvdata(pdev); 4042 4043 if (priv) 4044 pciserial_suspend_ports(priv); 4045 4046 return 0; 4047 } 4048 4049 static int pciserial_resume_one(struct device *dev) 4050 { 4051 struct pci_dev *pdev = to_pci_dev(dev); 4052 struct serial_private *priv = pci_get_drvdata(pdev); 4053 int err; 4054 4055 if (priv) { 4056 /* 4057 * The device may have been disabled. Re-enable it. 4058 */ 4059 err = pci_enable_device(pdev); 4060 /* FIXME: We cannot simply error out here */ 4061 if (err) 4062 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 4063 pciserial_resume_ports(priv); 4064 } 4065 return 0; 4066 } 4067 #endif 4068 4069 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4070 pciserial_resume_one); 4071 4072 static struct pci_device_id serial_pci_tbl[] = { 4073 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4074 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4075 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4076 pbn_b2_8_921600 }, 4077 /* Advantech also use 0x3618 and 0xf618 */ 4078 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4079 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4080 pbn_b0_4_921600 }, 4081 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4082 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4083 pbn_b0_4_921600 }, 4084 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4085 PCI_SUBVENDOR_ID_CONNECT_TECH, 4086 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4087 pbn_b1_8_1382400 }, 4088 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4089 PCI_SUBVENDOR_ID_CONNECT_TECH, 4090 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4091 pbn_b1_4_1382400 }, 4092 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4093 PCI_SUBVENDOR_ID_CONNECT_TECH, 4094 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4095 pbn_b1_2_1382400 }, 4096 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4097 PCI_SUBVENDOR_ID_CONNECT_TECH, 4098 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4099 pbn_b1_8_1382400 }, 4100 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4101 PCI_SUBVENDOR_ID_CONNECT_TECH, 4102 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4103 pbn_b1_4_1382400 }, 4104 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4105 PCI_SUBVENDOR_ID_CONNECT_TECH, 4106 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4107 pbn_b1_2_1382400 }, 4108 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4109 PCI_SUBVENDOR_ID_CONNECT_TECH, 4110 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4111 pbn_b1_8_921600 }, 4112 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4113 PCI_SUBVENDOR_ID_CONNECT_TECH, 4114 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4115 pbn_b1_8_921600 }, 4116 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4117 PCI_SUBVENDOR_ID_CONNECT_TECH, 4118 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4119 pbn_b1_4_921600 }, 4120 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4121 PCI_SUBVENDOR_ID_CONNECT_TECH, 4122 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4123 pbn_b1_4_921600 }, 4124 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4125 PCI_SUBVENDOR_ID_CONNECT_TECH, 4126 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4127 pbn_b1_2_921600 }, 4128 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4129 PCI_SUBVENDOR_ID_CONNECT_TECH, 4130 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4131 pbn_b1_8_921600 }, 4132 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4133 PCI_SUBVENDOR_ID_CONNECT_TECH, 4134 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4135 pbn_b1_8_921600 }, 4136 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4137 PCI_SUBVENDOR_ID_CONNECT_TECH, 4138 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4139 pbn_b1_4_921600 }, 4140 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4141 PCI_SUBVENDOR_ID_CONNECT_TECH, 4142 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4143 pbn_b1_2_1250000 }, 4144 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4145 PCI_SUBVENDOR_ID_CONNECT_TECH, 4146 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4147 pbn_b0_2_1843200 }, 4148 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4149 PCI_SUBVENDOR_ID_CONNECT_TECH, 4150 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4151 pbn_b0_4_1843200 }, 4152 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4153 PCI_VENDOR_ID_AFAVLAB, 4154 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4155 pbn_b0_4_1152000 }, 4156 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4157 PCI_SUBVENDOR_ID_CONNECT_TECH, 4158 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 4159 pbn_b0_2_1843200_200 }, 4160 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4161 PCI_SUBVENDOR_ID_CONNECT_TECH, 4162 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 4163 pbn_b0_4_1843200_200 }, 4164 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4165 PCI_SUBVENDOR_ID_CONNECT_TECH, 4166 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 4167 pbn_b0_8_1843200_200 }, 4168 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4169 PCI_SUBVENDOR_ID_CONNECT_TECH, 4170 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 4171 pbn_b0_2_1843200_200 }, 4172 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4173 PCI_SUBVENDOR_ID_CONNECT_TECH, 4174 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 4175 pbn_b0_4_1843200_200 }, 4176 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4177 PCI_SUBVENDOR_ID_CONNECT_TECH, 4178 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 4179 pbn_b0_8_1843200_200 }, 4180 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4181 PCI_SUBVENDOR_ID_CONNECT_TECH, 4182 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 4183 pbn_b0_2_1843200_200 }, 4184 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4185 PCI_SUBVENDOR_ID_CONNECT_TECH, 4186 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 4187 pbn_b0_4_1843200_200 }, 4188 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4189 PCI_SUBVENDOR_ID_CONNECT_TECH, 4190 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 4191 pbn_b0_8_1843200_200 }, 4192 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4193 PCI_SUBVENDOR_ID_CONNECT_TECH, 4194 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 4195 pbn_b0_2_1843200_200 }, 4196 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4197 PCI_SUBVENDOR_ID_CONNECT_TECH, 4198 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 4199 pbn_b0_4_1843200_200 }, 4200 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4201 PCI_SUBVENDOR_ID_CONNECT_TECH, 4202 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 4203 pbn_b0_8_1843200_200 }, 4204 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4205 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 4206 0, 0, pbn_exar_ibm_saturn }, 4207 4208 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4210 pbn_b2_bt_1_115200 }, 4211 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4213 pbn_b2_bt_2_115200 }, 4214 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4216 pbn_b2_bt_4_115200 }, 4217 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4219 pbn_b2_bt_2_115200 }, 4220 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4222 pbn_b2_bt_4_115200 }, 4223 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4225 pbn_b2_8_115200 }, 4226 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4228 pbn_b2_8_460800 }, 4229 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4231 pbn_b2_8_115200 }, 4232 4233 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4235 pbn_b2_bt_2_115200 }, 4236 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4238 pbn_b2_bt_2_921600 }, 4239 /* 4240 * VScom SPCOM800, from sl@s.pl 4241 */ 4242 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4244 pbn_b2_8_921600 }, 4245 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4247 pbn_b2_4_921600 }, 4248 /* Unknown card - subdevice 0x1584 */ 4249 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4250 PCI_VENDOR_ID_PLX, 4251 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4252 pbn_b2_4_115200 }, 4253 /* Unknown card - subdevice 0x1588 */ 4254 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4255 PCI_VENDOR_ID_PLX, 4256 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4257 pbn_b2_8_115200 }, 4258 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4259 PCI_SUBVENDOR_ID_KEYSPAN, 4260 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4261 pbn_panacom }, 4262 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4264 pbn_panacom4 }, 4265 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4267 pbn_panacom2 }, 4268 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4269 PCI_VENDOR_ID_ESDGMBH, 4270 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4271 pbn_b2_4_115200 }, 4272 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4273 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4274 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4275 pbn_b2_4_460800 }, 4276 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4277 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4278 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4279 pbn_b2_8_460800 }, 4280 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4281 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4282 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4283 pbn_b2_16_460800 }, 4284 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4285 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4286 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4287 pbn_b2_16_460800 }, 4288 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4289 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4290 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4291 pbn_b2_4_460800 }, 4292 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4293 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4294 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4295 pbn_b2_8_460800 }, 4296 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4297 PCI_SUBVENDOR_ID_EXSYS, 4298 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4299 pbn_b2_4_115200 }, 4300 /* 4301 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4302 * (Exoray@isys.ca) 4303 */ 4304 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4305 0x10b5, 0x106a, 0, 0, 4306 pbn_plx_romulus }, 4307 /* 4308 * EndRun Technologies. PCI express device range. 4309 * EndRun PTP/1588 has 2 Native UARTs. 4310 */ 4311 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4313 pbn_endrun_2_4000000 }, 4314 /* 4315 * Quatech cards. These actually have configurable clocks but for 4316 * now we just use the default. 4317 * 4318 * 100 series are RS232, 200 series RS422, 4319 */ 4320 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4322 pbn_b1_4_115200 }, 4323 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4325 pbn_b1_2_115200 }, 4326 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4328 pbn_b2_2_115200 }, 4329 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4331 pbn_b1_2_115200 }, 4332 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4334 pbn_b2_2_115200 }, 4335 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4337 pbn_b1_4_115200 }, 4338 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4340 pbn_b1_8_115200 }, 4341 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4343 pbn_b1_8_115200 }, 4344 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4346 pbn_b1_4_115200 }, 4347 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4349 pbn_b1_2_115200 }, 4350 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4352 pbn_b1_4_115200 }, 4353 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4355 pbn_b1_2_115200 }, 4356 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4358 pbn_b2_4_115200 }, 4359 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4361 pbn_b2_2_115200 }, 4362 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4364 pbn_b2_1_115200 }, 4365 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4367 pbn_b2_4_115200 }, 4368 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4370 pbn_b2_2_115200 }, 4371 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4373 pbn_b2_1_115200 }, 4374 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4376 pbn_b0_8_115200 }, 4377 4378 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4379 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4380 0, 0, 4381 pbn_b0_4_921600 }, 4382 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4383 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4384 0, 0, 4385 pbn_b0_4_1152000 }, 4386 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4388 pbn_b0_bt_2_921600 }, 4389 4390 /* 4391 * The below card is a little controversial since it is the 4392 * subject of a PCI vendor/device ID clash. (See 4393 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4394 * For now just used the hex ID 0x950a. 4395 */ 4396 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4397 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4398 0, 0, pbn_b0_2_115200 }, 4399 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4400 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4401 0, 0, pbn_b0_2_115200 }, 4402 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4404 pbn_b0_2_1130000 }, 4405 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4406 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4407 pbn_b0_1_921600 }, 4408 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4410 pbn_b0_4_115200 }, 4411 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4413 pbn_b0_bt_2_921600 }, 4414 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4416 pbn_b2_8_1152000 }, 4417 4418 /* 4419 * Oxford Semiconductor Inc. Tornado PCI express device range. 4420 */ 4421 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4423 pbn_b0_1_4000000 }, 4424 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4426 pbn_b0_1_4000000 }, 4427 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4429 pbn_oxsemi_1_4000000 }, 4430 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4432 pbn_oxsemi_1_4000000 }, 4433 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4435 pbn_b0_1_4000000 }, 4436 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4438 pbn_b0_1_4000000 }, 4439 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4441 pbn_oxsemi_1_4000000 }, 4442 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4444 pbn_oxsemi_1_4000000 }, 4445 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4447 pbn_b0_1_4000000 }, 4448 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4450 pbn_b0_1_4000000 }, 4451 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4453 pbn_b0_1_4000000 }, 4454 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4456 pbn_b0_1_4000000 }, 4457 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4459 pbn_oxsemi_2_4000000 }, 4460 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4462 pbn_oxsemi_2_4000000 }, 4463 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4465 pbn_oxsemi_4_4000000 }, 4466 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_oxsemi_4_4000000 }, 4469 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_oxsemi_8_4000000 }, 4472 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_oxsemi_8_4000000 }, 4475 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_oxsemi_1_4000000 }, 4478 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_oxsemi_1_4000000 }, 4481 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_oxsemi_1_4000000 }, 4484 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4486 pbn_oxsemi_1_4000000 }, 4487 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_oxsemi_1_4000000 }, 4490 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_oxsemi_1_4000000 }, 4493 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_oxsemi_1_4000000 }, 4496 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_oxsemi_1_4000000 }, 4499 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_oxsemi_1_4000000 }, 4502 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_oxsemi_1_4000000 }, 4505 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_oxsemi_1_4000000 }, 4508 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_oxsemi_1_4000000 }, 4511 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_oxsemi_1_4000000 }, 4514 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4516 pbn_oxsemi_1_4000000 }, 4517 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4519 pbn_oxsemi_1_4000000 }, 4520 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4522 pbn_oxsemi_1_4000000 }, 4523 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4525 pbn_oxsemi_1_4000000 }, 4526 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4528 pbn_oxsemi_1_4000000 }, 4529 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4531 pbn_oxsemi_1_4000000 }, 4532 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4534 pbn_oxsemi_1_4000000 }, 4535 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4537 pbn_oxsemi_1_4000000 }, 4538 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4540 pbn_oxsemi_1_4000000 }, 4541 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4543 pbn_oxsemi_1_4000000 }, 4544 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4546 pbn_oxsemi_1_4000000 }, 4547 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4549 pbn_oxsemi_1_4000000 }, 4550 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4552 pbn_oxsemi_1_4000000 }, 4553 /* 4554 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4555 */ 4556 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4557 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4558 pbn_oxsemi_1_4000000 }, 4559 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4560 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4561 pbn_oxsemi_2_4000000 }, 4562 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4563 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4564 pbn_oxsemi_4_4000000 }, 4565 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4566 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4567 pbn_oxsemi_8_4000000 }, 4568 4569 /* 4570 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4571 */ 4572 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4573 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4574 pbn_oxsemi_2_4000000 }, 4575 4576 /* 4577 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4578 * from skokodyn@yahoo.com 4579 */ 4580 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4581 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4582 pbn_sbsxrsio }, 4583 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4584 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4585 pbn_sbsxrsio }, 4586 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4587 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4588 pbn_sbsxrsio }, 4589 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4590 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4591 pbn_sbsxrsio }, 4592 4593 /* 4594 * Digitan DS560-558, from jimd@esoft.com 4595 */ 4596 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4598 pbn_b1_1_115200 }, 4599 4600 /* 4601 * Titan Electronic cards 4602 * The 400L and 800L have a custom setup quirk. 4603 */ 4604 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4606 pbn_b0_1_921600 }, 4607 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4609 pbn_b0_2_921600 }, 4610 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4612 pbn_b0_4_921600 }, 4613 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4615 pbn_b0_4_921600 }, 4616 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4618 pbn_b1_1_921600 }, 4619 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4621 pbn_b1_bt_2_921600 }, 4622 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4624 pbn_b0_bt_4_921600 }, 4625 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4627 pbn_b0_bt_8_921600 }, 4628 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_b4_bt_2_921600 }, 4631 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4633 pbn_b4_bt_4_921600 }, 4634 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4636 pbn_b4_bt_8_921600 }, 4637 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_b0_4_921600 }, 4640 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4642 pbn_b0_4_921600 }, 4643 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4645 pbn_b0_4_921600 }, 4646 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4648 pbn_oxsemi_1_4000000 }, 4649 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4651 pbn_oxsemi_2_4000000 }, 4652 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_oxsemi_4_4000000 }, 4655 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4657 pbn_oxsemi_8_4000000 }, 4658 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_oxsemi_2_4000000 }, 4661 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4663 pbn_oxsemi_2_4000000 }, 4664 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_b0_bt_2_921600 }, 4667 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4669 pbn_b0_4_921600 }, 4670 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4672 pbn_b0_4_921600 }, 4673 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4675 pbn_b0_4_921600 }, 4676 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_b0_4_921600 }, 4679 4680 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4682 pbn_b2_1_460800 }, 4683 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_b2_1_460800 }, 4686 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_b2_1_460800 }, 4689 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_b2_bt_2_921600 }, 4692 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4694 pbn_b2_bt_2_921600 }, 4695 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4697 pbn_b2_bt_2_921600 }, 4698 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4700 pbn_b2_bt_4_921600 }, 4701 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4703 pbn_b2_bt_4_921600 }, 4704 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4706 pbn_b2_bt_4_921600 }, 4707 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4709 pbn_b0_1_921600 }, 4710 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4712 pbn_b0_1_921600 }, 4713 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4715 pbn_b0_1_921600 }, 4716 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4718 pbn_b0_bt_2_921600 }, 4719 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4721 pbn_b0_bt_2_921600 }, 4722 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4724 pbn_b0_bt_2_921600 }, 4725 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_b0_bt_4_921600 }, 4728 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4730 pbn_b0_bt_4_921600 }, 4731 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4733 pbn_b0_bt_4_921600 }, 4734 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4736 pbn_b0_bt_8_921600 }, 4737 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4739 pbn_b0_bt_8_921600 }, 4740 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4742 pbn_b0_bt_8_921600 }, 4743 4744 /* 4745 * Computone devices submitted by Doug McNash dmcnash@computone.com 4746 */ 4747 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4748 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4749 0, 0, pbn_computone_4 }, 4750 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4751 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4752 0, 0, pbn_computone_8 }, 4753 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4754 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4755 0, 0, pbn_computone_6 }, 4756 4757 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4759 pbn_oxsemi }, 4760 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4761 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4762 pbn_b0_bt_1_921600 }, 4763 4764 /* 4765 * SUNIX (TIMEDIA) 4766 */ 4767 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4768 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4769 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4770 pbn_b0_bt_1_921600 }, 4771 4772 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4773 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4774 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4775 pbn_b0_bt_1_921600 }, 4776 4777 /* 4778 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4779 */ 4780 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4782 pbn_b0_bt_8_115200 }, 4783 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4785 pbn_b0_bt_8_115200 }, 4786 4787 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_b0_bt_2_115200 }, 4790 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4792 pbn_b0_bt_2_115200 }, 4793 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4795 pbn_b0_bt_2_115200 }, 4796 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4798 pbn_b0_bt_2_115200 }, 4799 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4801 pbn_b0_bt_2_115200 }, 4802 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4804 pbn_b0_bt_4_460800 }, 4805 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4807 pbn_b0_bt_4_460800 }, 4808 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4810 pbn_b0_bt_2_460800 }, 4811 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4813 pbn_b0_bt_2_460800 }, 4814 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4815 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4816 pbn_b0_bt_2_460800 }, 4817 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4818 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4819 pbn_b0_bt_1_115200 }, 4820 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4822 pbn_b0_bt_1_460800 }, 4823 4824 /* 4825 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4826 * Cards are identified by their subsystem vendor IDs, which 4827 * (in hex) match the model number. 4828 * 4829 * Note that JC140x are RS422/485 cards which require ox950 4830 * ACR = 0x10, and as such are not currently fully supported. 4831 */ 4832 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4833 0x1204, 0x0004, 0, 0, 4834 pbn_b0_4_921600 }, 4835 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4836 0x1208, 0x0004, 0, 0, 4837 pbn_b0_4_921600 }, 4838 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4839 0x1402, 0x0002, 0, 0, 4840 pbn_b0_2_921600 }, */ 4841 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4842 0x1404, 0x0004, 0, 0, 4843 pbn_b0_4_921600 }, */ 4844 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4845 0x1208, 0x0004, 0, 0, 4846 pbn_b0_4_921600 }, 4847 4848 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4849 0x1204, 0x0004, 0, 0, 4850 pbn_b0_4_921600 }, 4851 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4852 0x1208, 0x0004, 0, 0, 4853 pbn_b0_4_921600 }, 4854 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4855 0x1208, 0x0004, 0, 0, 4856 pbn_b0_4_921600 }, 4857 /* 4858 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4859 */ 4860 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b1_1_1382400 }, 4863 4864 /* 4865 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4866 */ 4867 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4869 pbn_b1_1_1382400 }, 4870 4871 /* 4872 * RAStel 2 port modem, gerg@moreton.com.au 4873 */ 4874 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4876 pbn_b2_bt_2_115200 }, 4877 4878 /* 4879 * EKF addition for i960 Boards form EKF with serial port 4880 */ 4881 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4882 0xE4BF, PCI_ANY_ID, 0, 0, 4883 pbn_intel_i960 }, 4884 4885 /* 4886 * Xircom Cardbus/Ethernet combos 4887 */ 4888 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4890 pbn_b0_1_115200 }, 4891 /* 4892 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4893 */ 4894 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4896 pbn_b0_1_115200 }, 4897 4898 /* 4899 * Untested PCI modems, sent in from various folks... 4900 */ 4901 4902 /* 4903 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4904 */ 4905 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4906 0x1048, 0x1500, 0, 0, 4907 pbn_b1_1_115200 }, 4908 4909 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4910 0xFF00, 0, 0, 0, 4911 pbn_sgi_ioc3 }, 4912 4913 /* 4914 * HP Diva card 4915 */ 4916 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4917 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4918 pbn_b1_1_115200 }, 4919 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4921 pbn_b0_5_115200 }, 4922 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4924 pbn_b2_1_115200 }, 4925 4926 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4928 pbn_b3_2_115200 }, 4929 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4931 pbn_b3_4_115200 }, 4932 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4934 pbn_b3_8_115200 }, 4935 4936 /* 4937 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 4938 */ 4939 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4940 PCI_ANY_ID, PCI_ANY_ID, 4941 0, 4942 0, pbn_exar_XR17C152 }, 4943 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4944 PCI_ANY_ID, PCI_ANY_ID, 4945 0, 4946 0, pbn_exar_XR17C154 }, 4947 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4948 PCI_ANY_ID, PCI_ANY_ID, 4949 0, 4950 0, pbn_exar_XR17C158 }, 4951 /* 4952 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs 4953 */ 4954 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 4955 PCI_ANY_ID, PCI_ANY_ID, 4956 0, 4957 0, pbn_exar_XR17V352 }, 4958 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 4959 PCI_ANY_ID, PCI_ANY_ID, 4960 0, 4961 0, pbn_exar_XR17V354 }, 4962 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 4963 PCI_ANY_ID, PCI_ANY_ID, 4964 0, 4965 0, pbn_exar_XR17V358 }, 4966 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358, 4967 PCI_ANY_ID, PCI_ANY_ID, 4968 0, 4969 0, pbn_exar_XR17V4358 }, 4970 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358, 4971 PCI_ANY_ID, PCI_ANY_ID, 4972 0, 4973 0, pbn_exar_XR17V8358 }, 4974 /* 4975 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 4976 */ 4977 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 4978 PCI_ANY_ID, PCI_ANY_ID, 4979 0, 4980 0, pbn_pericom_PI7C9X7951 }, 4981 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 4982 PCI_ANY_ID, PCI_ANY_ID, 4983 0, 4984 0, pbn_pericom_PI7C9X7952 }, 4985 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 4986 PCI_ANY_ID, PCI_ANY_ID, 4987 0, 4988 0, pbn_pericom_PI7C9X7954 }, 4989 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 4990 PCI_ANY_ID, PCI_ANY_ID, 4991 0, 4992 0, pbn_pericom_PI7C9X7958 }, 4993 /* 4994 * ACCES I/O Products quad 4995 */ 4996 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4998 pbn_pericom_PI7C9X7954 }, 4999 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5001 pbn_pericom_PI7C9X7954 }, 5002 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5004 pbn_pericom_PI7C9X7954 }, 5005 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5007 pbn_pericom_PI7C9X7954 }, 5008 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5010 pbn_pericom_PI7C9X7954 }, 5011 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5013 pbn_pericom_PI7C9X7954 }, 5014 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5016 pbn_pericom_PI7C9X7954 }, 5017 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 5018 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5019 pbn_pericom_PI7C9X7954 }, 5020 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 5021 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5022 pbn_pericom_PI7C9X7954 }, 5023 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5025 pbn_pericom_PI7C9X7954 }, 5026 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 5027 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5028 pbn_pericom_PI7C9X7954 }, 5029 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 5030 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5031 pbn_pericom_PI7C9X7954 }, 5032 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 5033 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5034 pbn_pericom_PI7C9X7954 }, 5035 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 5036 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5037 pbn_pericom_PI7C9X7954 }, 5038 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 5039 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5040 pbn_pericom_PI7C9X7954 }, 5041 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 5042 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5043 pbn_pericom_PI7C9X7954 }, 5044 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 5045 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5046 pbn_pericom_PI7C9X7954 }, 5047 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 5048 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5049 pbn_pericom_PI7C9X7954 }, 5050 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 5051 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5052 pbn_pericom_PI7C9X7954 }, 5053 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 5054 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5055 pbn_pericom_PI7C9X7954 }, 5056 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 5057 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5058 pbn_pericom_PI7C9X7954 }, 5059 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 5060 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5061 pbn_pericom_PI7C9X7954 }, 5062 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 5063 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5064 pbn_pericom_PI7C9X7954 }, 5065 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 5066 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5067 pbn_pericom_PI7C9X7954 }, 5068 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 5069 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5070 pbn_pericom_PI7C9X7958 }, 5071 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5073 pbn_pericom_PI7C9X7958 }, 5074 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5076 pbn_pericom_PI7C9X7958 }, 5077 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5079 pbn_pericom_PI7C9X7958 }, 5080 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5082 pbn_pericom_PI7C9X7958 }, 5083 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5085 pbn_pericom_PI7C9X7958 }, 5086 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5088 pbn_pericom_PI7C9X7958 }, 5089 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5091 pbn_pericom_PI7C9X7958 }, 5092 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5094 pbn_pericom_PI7C9X7958 }, 5095 /* 5096 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5097 */ 5098 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5100 pbn_b0_1_115200 }, 5101 /* 5102 * ITE 5103 */ 5104 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5105 PCI_ANY_ID, PCI_ANY_ID, 5106 0, 0, 5107 pbn_b1_bt_1_115200 }, 5108 5109 /* 5110 * IntaShield IS-200 5111 */ 5112 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5114 pbn_b2_2_115200 }, 5115 /* 5116 * IntaShield IS-400 5117 */ 5118 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5120 pbn_b2_4_115200 }, 5121 /* 5122 * Perle PCI-RAS cards 5123 */ 5124 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5125 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5126 0, 0, pbn_b2_4_921600 }, 5127 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5128 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5129 0, 0, pbn_b2_8_921600 }, 5130 5131 /* 5132 * Mainpine series cards: Fairly standard layout but fools 5133 * parts of the autodetect in some cases and uses otherwise 5134 * unmatched communications subclasses in the PCI Express case 5135 */ 5136 5137 { /* RockForceDUO */ 5138 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5139 PCI_VENDOR_ID_MAINPINE, 0x0200, 5140 0, 0, pbn_b0_2_115200 }, 5141 { /* RockForceQUATRO */ 5142 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5143 PCI_VENDOR_ID_MAINPINE, 0x0300, 5144 0, 0, pbn_b0_4_115200 }, 5145 { /* RockForceDUO+ */ 5146 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5147 PCI_VENDOR_ID_MAINPINE, 0x0400, 5148 0, 0, pbn_b0_2_115200 }, 5149 { /* RockForceQUATRO+ */ 5150 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5151 PCI_VENDOR_ID_MAINPINE, 0x0500, 5152 0, 0, pbn_b0_4_115200 }, 5153 { /* RockForce+ */ 5154 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5155 PCI_VENDOR_ID_MAINPINE, 0x0600, 5156 0, 0, pbn_b0_2_115200 }, 5157 { /* RockForce+ */ 5158 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5159 PCI_VENDOR_ID_MAINPINE, 0x0700, 5160 0, 0, pbn_b0_4_115200 }, 5161 { /* RockForceOCTO+ */ 5162 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5163 PCI_VENDOR_ID_MAINPINE, 0x0800, 5164 0, 0, pbn_b0_8_115200 }, 5165 { /* RockForceDUO+ */ 5166 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5167 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5168 0, 0, pbn_b0_2_115200 }, 5169 { /* RockForceQUARTRO+ */ 5170 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5171 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5172 0, 0, pbn_b0_4_115200 }, 5173 { /* RockForceOCTO+ */ 5174 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5175 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5176 0, 0, pbn_b0_8_115200 }, 5177 { /* RockForceD1 */ 5178 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5179 PCI_VENDOR_ID_MAINPINE, 0x2000, 5180 0, 0, pbn_b0_1_115200 }, 5181 { /* RockForceF1 */ 5182 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5183 PCI_VENDOR_ID_MAINPINE, 0x2100, 5184 0, 0, pbn_b0_1_115200 }, 5185 { /* RockForceD2 */ 5186 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5187 PCI_VENDOR_ID_MAINPINE, 0x2200, 5188 0, 0, pbn_b0_2_115200 }, 5189 { /* RockForceF2 */ 5190 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5191 PCI_VENDOR_ID_MAINPINE, 0x2300, 5192 0, 0, pbn_b0_2_115200 }, 5193 { /* RockForceD4 */ 5194 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5195 PCI_VENDOR_ID_MAINPINE, 0x2400, 5196 0, 0, pbn_b0_4_115200 }, 5197 { /* RockForceF4 */ 5198 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5199 PCI_VENDOR_ID_MAINPINE, 0x2500, 5200 0, 0, pbn_b0_4_115200 }, 5201 { /* RockForceD8 */ 5202 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5203 PCI_VENDOR_ID_MAINPINE, 0x2600, 5204 0, 0, pbn_b0_8_115200 }, 5205 { /* RockForceF8 */ 5206 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5207 PCI_VENDOR_ID_MAINPINE, 0x2700, 5208 0, 0, pbn_b0_8_115200 }, 5209 { /* IQ Express D1 */ 5210 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5211 PCI_VENDOR_ID_MAINPINE, 0x3000, 5212 0, 0, pbn_b0_1_115200 }, 5213 { /* IQ Express F1 */ 5214 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5215 PCI_VENDOR_ID_MAINPINE, 0x3100, 5216 0, 0, pbn_b0_1_115200 }, 5217 { /* IQ Express D2 */ 5218 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5219 PCI_VENDOR_ID_MAINPINE, 0x3200, 5220 0, 0, pbn_b0_2_115200 }, 5221 { /* IQ Express F2 */ 5222 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5223 PCI_VENDOR_ID_MAINPINE, 0x3300, 5224 0, 0, pbn_b0_2_115200 }, 5225 { /* IQ Express D4 */ 5226 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5227 PCI_VENDOR_ID_MAINPINE, 0x3400, 5228 0, 0, pbn_b0_4_115200 }, 5229 { /* IQ Express F4 */ 5230 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5231 PCI_VENDOR_ID_MAINPINE, 0x3500, 5232 0, 0, pbn_b0_4_115200 }, 5233 { /* IQ Express D8 */ 5234 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5235 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5236 0, 0, pbn_b0_8_115200 }, 5237 { /* IQ Express F8 */ 5238 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5239 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5240 0, 0, pbn_b0_8_115200 }, 5241 5242 5243 /* 5244 * PA Semi PA6T-1682M on-chip UART 5245 */ 5246 { PCI_VENDOR_ID_PASEMI, 0xa004, 5247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5248 pbn_pasemi_1682M }, 5249 5250 /* 5251 * National Instruments 5252 */ 5253 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5255 pbn_b1_16_115200 }, 5256 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5258 pbn_b1_8_115200 }, 5259 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5261 pbn_b1_bt_4_115200 }, 5262 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5264 pbn_b1_bt_2_115200 }, 5265 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5267 pbn_b1_bt_4_115200 }, 5268 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5270 pbn_b1_bt_2_115200 }, 5271 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5273 pbn_b1_16_115200 }, 5274 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5276 pbn_b1_8_115200 }, 5277 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5279 pbn_b1_bt_4_115200 }, 5280 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5282 pbn_b1_bt_2_115200 }, 5283 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5285 pbn_b1_bt_4_115200 }, 5286 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5288 pbn_b1_bt_2_115200 }, 5289 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5291 pbn_ni8430_2 }, 5292 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5294 pbn_ni8430_2 }, 5295 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5297 pbn_ni8430_4 }, 5298 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5300 pbn_ni8430_4 }, 5301 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5303 pbn_ni8430_8 }, 5304 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5306 pbn_ni8430_8 }, 5307 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5309 pbn_ni8430_16 }, 5310 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5312 pbn_ni8430_16 }, 5313 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5315 pbn_ni8430_2 }, 5316 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5318 pbn_ni8430_2 }, 5319 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5321 pbn_ni8430_4 }, 5322 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5324 pbn_ni8430_4 }, 5325 5326 /* 5327 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5328 */ 5329 { PCI_VENDOR_ID_ADDIDATA, 5330 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5331 PCI_ANY_ID, 5332 PCI_ANY_ID, 5333 0, 5334 0, 5335 pbn_b0_4_115200 }, 5336 5337 { PCI_VENDOR_ID_ADDIDATA, 5338 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5339 PCI_ANY_ID, 5340 PCI_ANY_ID, 5341 0, 5342 0, 5343 pbn_b0_2_115200 }, 5344 5345 { PCI_VENDOR_ID_ADDIDATA, 5346 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5347 PCI_ANY_ID, 5348 PCI_ANY_ID, 5349 0, 5350 0, 5351 pbn_b0_1_115200 }, 5352 5353 { PCI_VENDOR_ID_AMCC, 5354 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5355 PCI_ANY_ID, 5356 PCI_ANY_ID, 5357 0, 5358 0, 5359 pbn_b1_8_115200 }, 5360 5361 { PCI_VENDOR_ID_ADDIDATA, 5362 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5363 PCI_ANY_ID, 5364 PCI_ANY_ID, 5365 0, 5366 0, 5367 pbn_b0_4_115200 }, 5368 5369 { PCI_VENDOR_ID_ADDIDATA, 5370 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5371 PCI_ANY_ID, 5372 PCI_ANY_ID, 5373 0, 5374 0, 5375 pbn_b0_2_115200 }, 5376 5377 { PCI_VENDOR_ID_ADDIDATA, 5378 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5379 PCI_ANY_ID, 5380 PCI_ANY_ID, 5381 0, 5382 0, 5383 pbn_b0_1_115200 }, 5384 5385 { PCI_VENDOR_ID_ADDIDATA, 5386 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5387 PCI_ANY_ID, 5388 PCI_ANY_ID, 5389 0, 5390 0, 5391 pbn_b0_4_115200 }, 5392 5393 { PCI_VENDOR_ID_ADDIDATA, 5394 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5395 PCI_ANY_ID, 5396 PCI_ANY_ID, 5397 0, 5398 0, 5399 pbn_b0_2_115200 }, 5400 5401 { PCI_VENDOR_ID_ADDIDATA, 5402 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5403 PCI_ANY_ID, 5404 PCI_ANY_ID, 5405 0, 5406 0, 5407 pbn_b0_1_115200 }, 5408 5409 { PCI_VENDOR_ID_ADDIDATA, 5410 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5411 PCI_ANY_ID, 5412 PCI_ANY_ID, 5413 0, 5414 0, 5415 pbn_b0_8_115200 }, 5416 5417 { PCI_VENDOR_ID_ADDIDATA, 5418 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5419 PCI_ANY_ID, 5420 PCI_ANY_ID, 5421 0, 5422 0, 5423 pbn_ADDIDATA_PCIe_4_3906250 }, 5424 5425 { PCI_VENDOR_ID_ADDIDATA, 5426 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5427 PCI_ANY_ID, 5428 PCI_ANY_ID, 5429 0, 5430 0, 5431 pbn_ADDIDATA_PCIe_2_3906250 }, 5432 5433 { PCI_VENDOR_ID_ADDIDATA, 5434 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5435 PCI_ANY_ID, 5436 PCI_ANY_ID, 5437 0, 5438 0, 5439 pbn_ADDIDATA_PCIe_1_3906250 }, 5440 5441 { PCI_VENDOR_ID_ADDIDATA, 5442 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5443 PCI_ANY_ID, 5444 PCI_ANY_ID, 5445 0, 5446 0, 5447 pbn_ADDIDATA_PCIe_8_3906250 }, 5448 5449 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5450 PCI_VENDOR_ID_IBM, 0x0299, 5451 0, 0, pbn_b0_bt_2_115200 }, 5452 5453 /* 5454 * other NetMos 9835 devices are most likely handled by the 5455 * parport_serial driver, check drivers/parport/parport_serial.c 5456 * before adding them here. 5457 */ 5458 5459 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5460 0xA000, 0x1000, 5461 0, 0, pbn_b0_1_115200 }, 5462 5463 /* the 9901 is a rebranded 9912 */ 5464 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5465 0xA000, 0x1000, 5466 0, 0, pbn_b0_1_115200 }, 5467 5468 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5469 0xA000, 0x1000, 5470 0, 0, pbn_b0_1_115200 }, 5471 5472 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5473 0xA000, 0x1000, 5474 0, 0, pbn_b0_1_115200 }, 5475 5476 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5477 0xA000, 0x1000, 5478 0, 0, pbn_b0_1_115200 }, 5479 5480 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5481 0xA000, 0x3002, 5482 0, 0, pbn_NETMOS9900_2s_115200 }, 5483 5484 /* 5485 * Best Connectivity and Rosewill PCI Multi I/O cards 5486 */ 5487 5488 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5489 0xA000, 0x1000, 5490 0, 0, pbn_b0_1_115200 }, 5491 5492 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5493 0xA000, 0x3002, 5494 0, 0, pbn_b0_bt_2_115200 }, 5495 5496 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5497 0xA000, 0x3004, 5498 0, 0, pbn_b0_bt_4_115200 }, 5499 /* Intel CE4100 */ 5500 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5502 pbn_ce4100_1_115200 }, 5503 5504 /* 5505 * Cronyx Omega PCI 5506 */ 5507 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5509 pbn_omegapci }, 5510 5511 /* 5512 * Broadcom TruManage 5513 */ 5514 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5516 pbn_brcm_trumanage }, 5517 5518 /* 5519 * AgeStar as-prs2-009 5520 */ 5521 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5522 PCI_ANY_ID, PCI_ANY_ID, 5523 0, 0, pbn_b0_bt_2_115200 }, 5524 5525 /* 5526 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5527 * so not listed here. 5528 */ 5529 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5530 PCI_ANY_ID, PCI_ANY_ID, 5531 0, 0, pbn_b0_bt_4_115200 }, 5532 5533 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5534 PCI_ANY_ID, PCI_ANY_ID, 5535 0, 0, pbn_b0_bt_2_115200 }, 5536 5537 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5538 PCI_ANY_ID, PCI_ANY_ID, 5539 0, 0, pbn_b0_bt_4_115200 }, 5540 5541 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5542 PCI_ANY_ID, PCI_ANY_ID, 5543 0, 0, pbn_wch382_2 }, 5544 5545 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5546 PCI_ANY_ID, PCI_ANY_ID, 5547 0, 0, pbn_wch384_4 }, 5548 5549 /* 5550 * Commtech, Inc. Fastcom adapters 5551 */ 5552 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 5553 PCI_ANY_ID, PCI_ANY_ID, 5554 0, 5555 0, pbn_b0_2_1152000_200 }, 5556 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 5557 PCI_ANY_ID, PCI_ANY_ID, 5558 0, 5559 0, pbn_b0_4_1152000_200 }, 5560 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 5561 PCI_ANY_ID, PCI_ANY_ID, 5562 0, 5563 0, pbn_b0_4_1152000_200 }, 5564 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 5565 PCI_ANY_ID, PCI_ANY_ID, 5566 0, 5567 0, pbn_b0_8_1152000_200 }, 5568 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 5569 PCI_ANY_ID, PCI_ANY_ID, 5570 0, 5571 0, pbn_exar_XR17V352 }, 5572 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 5573 PCI_ANY_ID, PCI_ANY_ID, 5574 0, 5575 0, pbn_exar_XR17V354 }, 5576 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 5577 PCI_ANY_ID, PCI_ANY_ID, 5578 0, 5579 0, pbn_exar_XR17V358 }, 5580 5581 /* Fintek PCI serial cards */ 5582 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5583 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5584 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5585 5586 /* 5587 * These entries match devices with class COMMUNICATION_SERIAL, 5588 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5589 */ 5590 { PCI_ANY_ID, PCI_ANY_ID, 5591 PCI_ANY_ID, PCI_ANY_ID, 5592 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5593 0xffff00, pbn_default }, 5594 { PCI_ANY_ID, PCI_ANY_ID, 5595 PCI_ANY_ID, PCI_ANY_ID, 5596 PCI_CLASS_COMMUNICATION_MODEM << 8, 5597 0xffff00, pbn_default }, 5598 { PCI_ANY_ID, PCI_ANY_ID, 5599 PCI_ANY_ID, PCI_ANY_ID, 5600 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5601 0xffff00, pbn_default }, 5602 { 0, } 5603 }; 5604 5605 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5606 pci_channel_state_t state) 5607 { 5608 struct serial_private *priv = pci_get_drvdata(dev); 5609 5610 if (state == pci_channel_io_perm_failure) 5611 return PCI_ERS_RESULT_DISCONNECT; 5612 5613 if (priv) 5614 pciserial_suspend_ports(priv); 5615 5616 pci_disable_device(dev); 5617 5618 return PCI_ERS_RESULT_NEED_RESET; 5619 } 5620 5621 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5622 { 5623 int rc; 5624 5625 rc = pci_enable_device(dev); 5626 5627 if (rc) 5628 return PCI_ERS_RESULT_DISCONNECT; 5629 5630 pci_restore_state(dev); 5631 pci_save_state(dev); 5632 5633 return PCI_ERS_RESULT_RECOVERED; 5634 } 5635 5636 static void serial8250_io_resume(struct pci_dev *dev) 5637 { 5638 struct serial_private *priv = pci_get_drvdata(dev); 5639 5640 if (priv) 5641 pciserial_resume_ports(priv); 5642 } 5643 5644 static const struct pci_error_handlers serial8250_err_handler = { 5645 .error_detected = serial8250_io_error_detected, 5646 .slot_reset = serial8250_io_slot_reset, 5647 .resume = serial8250_io_resume, 5648 }; 5649 5650 static struct pci_driver serial_pci_driver = { 5651 .name = "serial", 5652 .probe = pciserial_init_one, 5653 .remove = pciserial_remove_one, 5654 .driver = { 5655 .pm = &pciserial_pm_ops, 5656 }, 5657 .id_table = serial_pci_tbl, 5658 .err_handler = &serial8250_err_handler, 5659 }; 5660 5661 module_pci_driver(serial_pci_driver); 5662 5663 MODULE_LICENSE("GPL"); 5664 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5665 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5666