1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/tty.h> 17 #include <linux/serial_reg.h> 18 #include <linux/serial_core.h> 19 #include <linux/8250_pci.h> 20 #include <linux/bitops.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/io.h> 24 25 #include "8250.h" 26 27 /* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33 struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44 }; 45 46 struct f815xxa_data { 47 spinlock_t lock; 48 int idx; 49 }; 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 const struct pciserial_board *board; 56 int line[]; 57 }; 58 59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 60 61 static const struct pci_device_id pci_use_msi[] = { 62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 63 0xA000, 0x1000) }, 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 65 0xA000, 0x1000) }, 66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 67 0xA000, 0x1000) }, 68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 69 PCI_ANY_ID, PCI_ANY_ID) }, 70 { } 71 }; 72 73 static int pci_default_setup(struct serial_private*, 74 const struct pciserial_board*, struct uart_8250_port *, int); 75 76 static void moan_device(const char *str, struct pci_dev *dev) 77 { 78 dev_err(&dev->dev, 79 "%s: %s\n" 80 "Please send the output of lspci -vv, this\n" 81 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 82 "manufacturer and name of serial board or\n" 83 "modem board to <linux-serial@vger.kernel.org>.\n", 84 pci_name(dev), str, dev->vendor, dev->device, 85 dev->subsystem_vendor, dev->subsystem_device); 86 } 87 88 static int 89 setup_port(struct serial_private *priv, struct uart_8250_port *port, 90 int bar, int offset, int regshift) 91 { 92 struct pci_dev *dev = priv->dev; 93 94 if (bar >= PCI_STD_NUM_BARS) 95 return -EINVAL; 96 97 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 98 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 99 return -ENOMEM; 100 101 port->port.iotype = UPIO_MEM; 102 port->port.iobase = 0; 103 port->port.mapbase = pci_resource_start(dev, bar) + offset; 104 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 105 port->port.regshift = regshift; 106 } else { 107 port->port.iotype = UPIO_PORT; 108 port->port.iobase = pci_resource_start(dev, bar) + offset; 109 port->port.mapbase = 0; 110 port->port.membase = NULL; 111 port->port.regshift = 0; 112 } 113 return 0; 114 } 115 116 /* 117 * ADDI-DATA GmbH communication cards <info@addi-data.com> 118 */ 119 static int addidata_apci7800_setup(struct serial_private *priv, 120 const struct pciserial_board *board, 121 struct uart_8250_port *port, int idx) 122 { 123 unsigned int bar = 0, offset = board->first_offset; 124 bar = FL_GET_BASE(board->flags); 125 126 if (idx < 2) { 127 offset += idx * board->uart_offset; 128 } else if ((idx >= 2) && (idx < 4)) { 129 bar += 1; 130 offset += ((idx - 2) * board->uart_offset); 131 } else if ((idx >= 4) && (idx < 6)) { 132 bar += 2; 133 offset += ((idx - 4) * board->uart_offset); 134 } else if (idx >= 6) { 135 bar += 3; 136 offset += ((idx - 6) * board->uart_offset); 137 } 138 139 return setup_port(priv, port, bar, offset, board->reg_shift); 140 } 141 142 /* 143 * AFAVLAB uses a different mixture of BARs and offsets 144 * Not that ugly ;) -- HW 145 */ 146 static int 147 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 148 struct uart_8250_port *port, int idx) 149 { 150 unsigned int bar, offset = board->first_offset; 151 152 bar = FL_GET_BASE(board->flags); 153 if (idx < 4) 154 bar += idx; 155 else { 156 bar = 4; 157 offset += (idx - 4) * board->uart_offset; 158 } 159 160 return setup_port(priv, port, bar, offset, board->reg_shift); 161 } 162 163 /* 164 * HP's Remote Management Console. The Diva chip came in several 165 * different versions. N-class, L2000 and A500 have two Diva chips, each 166 * with 3 UARTs (the third UART on the second chip is unused). Superdome 167 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 168 * one Diva chip, but it has been expanded to 5 UARTs. 169 */ 170 static int pci_hp_diva_init(struct pci_dev *dev) 171 { 172 int rc = 0; 173 174 switch (dev->subsystem_device) { 175 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 176 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 177 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 178 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 179 rc = 3; 180 break; 181 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 182 rc = 2; 183 break; 184 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 185 rc = 4; 186 break; 187 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 188 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 189 rc = 1; 190 break; 191 } 192 193 return rc; 194 } 195 196 /* 197 * HP's Diva chip puts the 4th/5th serial port further out, and 198 * some serial ports are supposed to be hidden on certain models. 199 */ 200 static int 201 pci_hp_diva_setup(struct serial_private *priv, 202 const struct pciserial_board *board, 203 struct uart_8250_port *port, int idx) 204 { 205 unsigned int offset = board->first_offset; 206 unsigned int bar = FL_GET_BASE(board->flags); 207 208 switch (priv->dev->subsystem_device) { 209 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 210 if (idx == 3) 211 idx++; 212 break; 213 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 214 if (idx > 0) 215 idx++; 216 if (idx > 2) 217 idx++; 218 break; 219 } 220 if (idx > 2) 221 offset = 0x18; 222 223 offset += idx * board->uart_offset; 224 225 return setup_port(priv, port, bar, offset, board->reg_shift); 226 } 227 228 /* 229 * Added for EKF Intel i960 serial boards 230 */ 231 static int pci_inteli960ni_init(struct pci_dev *dev) 232 { 233 u32 oldval; 234 235 if (!(dev->subsystem_device & 0x1000)) 236 return -ENODEV; 237 238 /* is firmware started? */ 239 pci_read_config_dword(dev, 0x44, &oldval); 240 if (oldval == 0x00001000L) { /* RESET value */ 241 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 242 return -ENODEV; 243 } 244 return 0; 245 } 246 247 /* 248 * Some PCI serial cards using the PLX 9050 PCI interface chip require 249 * that the card interrupt be explicitly enabled or disabled. This 250 * seems to be mainly needed on card using the PLX which also use I/O 251 * mapped memory. 252 */ 253 static int pci_plx9050_init(struct pci_dev *dev) 254 { 255 u8 irq_config; 256 void __iomem *p; 257 258 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 259 moan_device("no memory in bar 0", dev); 260 return 0; 261 } 262 263 irq_config = 0x41; 264 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 265 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 266 irq_config = 0x43; 267 268 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 269 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 270 /* 271 * As the megawolf cards have the int pins active 272 * high, and have 2 UART chips, both ints must be 273 * enabled on the 9050. Also, the UARTS are set in 274 * 16450 mode by default, so we have to enable the 275 * 16C950 'enhanced' mode so that we can use the 276 * deep FIFOs 277 */ 278 irq_config = 0x5b; 279 /* 280 * enable/disable interrupts 281 */ 282 p = ioremap(pci_resource_start(dev, 0), 0x80); 283 if (p == NULL) 284 return -ENOMEM; 285 writel(irq_config, p + 0x4c); 286 287 /* 288 * Read the register back to ensure that it took effect. 289 */ 290 readl(p + 0x4c); 291 iounmap(p); 292 293 return 0; 294 } 295 296 static void pci_plx9050_exit(struct pci_dev *dev) 297 { 298 u8 __iomem *p; 299 300 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 301 return; 302 303 /* 304 * disable interrupts 305 */ 306 p = ioremap(pci_resource_start(dev, 0), 0x80); 307 if (p != NULL) { 308 writel(0, p + 0x4c); 309 310 /* 311 * Read the register back to ensure that it took effect. 312 */ 313 readl(p + 0x4c); 314 iounmap(p); 315 } 316 } 317 318 #define NI8420_INT_ENABLE_REG 0x38 319 #define NI8420_INT_ENABLE_BIT 0x2000 320 321 static void pci_ni8420_exit(struct pci_dev *dev) 322 { 323 void __iomem *p; 324 unsigned int bar = 0; 325 326 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 327 moan_device("no memory in bar", dev); 328 return; 329 } 330 331 p = pci_ioremap_bar(dev, bar); 332 if (p == NULL) 333 return; 334 335 /* Disable the CPU Interrupt */ 336 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 337 p + NI8420_INT_ENABLE_REG); 338 iounmap(p); 339 } 340 341 342 /* MITE registers */ 343 #define MITE_IOWBSR1 0xc4 344 #define MITE_IOWCR1 0xf4 345 #define MITE_LCIMR1 0x08 346 #define MITE_LCIMR2 0x10 347 348 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 349 350 static void pci_ni8430_exit(struct pci_dev *dev) 351 { 352 void __iomem *p; 353 unsigned int bar = 0; 354 355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 356 moan_device("no memory in bar", dev); 357 return; 358 } 359 360 p = pci_ioremap_bar(dev, bar); 361 if (p == NULL) 362 return; 363 364 /* Disable the CPU Interrupt */ 365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 366 iounmap(p); 367 } 368 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 370 static int 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 372 struct uart_8250_port *port, int idx) 373 { 374 unsigned int bar, offset = board->first_offset; 375 376 bar = 0; 377 378 if (idx < 4) { 379 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 380 offset += idx * board->uart_offset; 381 } else if (idx < 8) { 382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 383 offset += idx * board->uart_offset + 0xC00; 384 } else /* we have only 8 ports on PMC-OCTALPRO */ 385 return 1; 386 387 return setup_port(priv, port, bar, offset, board->reg_shift); 388 } 389 390 /* 391 * This does initialization for PMC OCTALPRO cards: 392 * maps the device memory, resets the UARTs (needed, bc 393 * if the module is removed and inserted again, the card 394 * is in the sleep mode) and enables global interrupt. 395 */ 396 397 /* global control register offset for SBS PMC-OctalPro */ 398 #define OCT_REG_CR_OFF 0x500 399 400 static int sbs_init(struct pci_dev *dev) 401 { 402 u8 __iomem *p; 403 404 p = pci_ioremap_bar(dev, 0); 405 406 if (p == NULL) 407 return -ENOMEM; 408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 409 writeb(0x10, p + OCT_REG_CR_OFF); 410 udelay(50); 411 writeb(0x0, p + OCT_REG_CR_OFF); 412 413 /* Set bit-2 (INTENABLE) of Control Register */ 414 writeb(0x4, p + OCT_REG_CR_OFF); 415 iounmap(p); 416 417 return 0; 418 } 419 420 /* 421 * Disables the global interrupt of PMC-OctalPro 422 */ 423 424 static void sbs_exit(struct pci_dev *dev) 425 { 426 u8 __iomem *p; 427 428 p = pci_ioremap_bar(dev, 0); 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 430 if (p != NULL) 431 writeb(0, p + OCT_REG_CR_OFF); 432 iounmap(p); 433 } 434 435 /* 436 * SIIG serial cards have an PCI interface chip which also controls 437 * the UART clocking frequency. Each UART can be clocked independently 438 * (except cards equipped with 4 UARTs) and initial clocking settings 439 * are stored in the EEPROM chip. It can cause problems because this 440 * version of serial driver doesn't support differently clocked UART's 441 * on single PCI card. To prevent this, initialization functions set 442 * high frequency clocking for all UART's on given card. It is safe (I 443 * hope) because it doesn't touch EEPROM settings to prevent conflicts 444 * with other OSes (like M$ DOS). 445 * 446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 447 * 448 * There is two family of SIIG serial cards with different PCI 449 * interface chip and different configuration methods: 450 * - 10x cards have control registers in IO and/or memory space; 451 * - 20x cards have control registers in standard PCI configuration space. 452 * 453 * Note: all 10x cards have PCI device ids 0x10.. 454 * all 20x cards have PCI device ids 0x20.. 455 * 456 * There are also Quartet Serial cards which use Oxford Semiconductor 457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 458 * 459 * Note: some SIIG cards are probed by the parport_serial object. 460 */ 461 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 464 465 static int pci_siig10x_init(struct pci_dev *dev) 466 { 467 u16 data; 468 void __iomem *p; 469 470 switch (dev->device & 0xfff8) { 471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 472 data = 0xffdf; 473 break; 474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 475 data = 0xf7ff; 476 break; 477 default: /* 1S1P, 4S */ 478 data = 0xfffb; 479 break; 480 } 481 482 p = ioremap(pci_resource_start(dev, 0), 0x80); 483 if (p == NULL) 484 return -ENOMEM; 485 486 writew(readw(p + 0x28) & data, p + 0x28); 487 readw(p + 0x28); 488 iounmap(p); 489 return 0; 490 } 491 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 494 495 static int pci_siig20x_init(struct pci_dev *dev) 496 { 497 u8 data; 498 499 /* Change clock frequency for the first UART. */ 500 pci_read_config_byte(dev, 0x6f, &data); 501 pci_write_config_byte(dev, 0x6f, data & 0xef); 502 503 /* If this card has 2 UART, we have to do the same with second UART. */ 504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 506 pci_read_config_byte(dev, 0x73, &data); 507 pci_write_config_byte(dev, 0x73, data & 0xef); 508 } 509 return 0; 510 } 511 512 static int pci_siig_init(struct pci_dev *dev) 513 { 514 unsigned int type = dev->device & 0xff00; 515 516 if (type == 0x1000) 517 return pci_siig10x_init(dev); 518 else if (type == 0x2000) 519 return pci_siig20x_init(dev); 520 521 moan_device("Unknown SIIG card", dev); 522 return -ENODEV; 523 } 524 525 static int pci_siig_setup(struct serial_private *priv, 526 const struct pciserial_board *board, 527 struct uart_8250_port *port, int idx) 528 { 529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 530 531 if (idx > 3) { 532 bar = 4; 533 offset = (idx - 4) * 8; 534 } 535 536 return setup_port(priv, port, bar, offset, 0); 537 } 538 539 /* 540 * Timedia has an explosion of boards, and to avoid the PCI table from 541 * growing *huge*, we use this function to collapse some 70 entries 542 * in the PCI table into one, for sanity's and compactness's sake. 543 */ 544 static const unsigned short timedia_single_port[] = { 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 546 }; 547 548 static const unsigned short timedia_dual_port[] = { 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 553 0xD079, 0 554 }; 555 556 static const unsigned short timedia_quad_port[] = { 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 560 0xB157, 0 561 }; 562 563 static const unsigned short timedia_eight_port[] = { 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 566 }; 567 568 static const struct timedia_struct { 569 int num; 570 const unsigned short *ids; 571 } timedia_data[] = { 572 { 1, timedia_single_port }, 573 { 2, timedia_dual_port }, 574 { 4, timedia_quad_port }, 575 { 8, timedia_eight_port } 576 }; 577 578 /* 579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 580 * listing them individually, this driver merely grabs them all with 581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 582 * and should be left free to be claimed by parport_serial instead. 583 */ 584 static int pci_timedia_probe(struct pci_dev *dev) 585 { 586 /* 587 * Check the third digit of the subdevice ID 588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 589 */ 590 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 591 dev_info(&dev->dev, 592 "ignoring Timedia subdevice %04x for parport_serial\n", 593 dev->subsystem_device); 594 return -ENODEV; 595 } 596 597 return 0; 598 } 599 600 static int pci_timedia_init(struct pci_dev *dev) 601 { 602 const unsigned short *ids; 603 int i, j; 604 605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 606 ids = timedia_data[i].ids; 607 for (j = 0; ids[j]; j++) 608 if (dev->subsystem_device == ids[j]) 609 return timedia_data[i].num; 610 } 611 return 0; 612 } 613 614 /* 615 * Timedia/SUNIX uses a mixture of BARs and offsets 616 * Ugh, this is ugly as all hell --- TYT 617 */ 618 static int 619 pci_timedia_setup(struct serial_private *priv, 620 const struct pciserial_board *board, 621 struct uart_8250_port *port, int idx) 622 { 623 unsigned int bar = 0, offset = board->first_offset; 624 625 switch (idx) { 626 case 0: 627 bar = 0; 628 break; 629 case 1: 630 offset = board->uart_offset; 631 bar = 0; 632 break; 633 case 2: 634 bar = 1; 635 break; 636 case 3: 637 offset = board->uart_offset; 638 fallthrough; 639 case 4: /* BAR 2 */ 640 case 5: /* BAR 3 */ 641 case 6: /* BAR 4 */ 642 case 7: /* BAR 5 */ 643 bar = idx - 2; 644 } 645 646 return setup_port(priv, port, bar, offset, board->reg_shift); 647 } 648 649 /* 650 * Some Titan cards are also a little weird 651 */ 652 static int 653 titan_400l_800l_setup(struct serial_private *priv, 654 const struct pciserial_board *board, 655 struct uart_8250_port *port, int idx) 656 { 657 unsigned int bar, offset = board->first_offset; 658 659 switch (idx) { 660 case 0: 661 bar = 1; 662 break; 663 case 1: 664 bar = 2; 665 break; 666 default: 667 bar = 4; 668 offset = (idx - 2) * board->uart_offset; 669 } 670 671 return setup_port(priv, port, bar, offset, board->reg_shift); 672 } 673 674 static int pci_xircom_init(struct pci_dev *dev) 675 { 676 msleep(100); 677 return 0; 678 } 679 680 static int pci_ni8420_init(struct pci_dev *dev) 681 { 682 void __iomem *p; 683 unsigned int bar = 0; 684 685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 686 moan_device("no memory in bar", dev); 687 return 0; 688 } 689 690 p = pci_ioremap_bar(dev, bar); 691 if (p == NULL) 692 return -ENOMEM; 693 694 /* Enable CPU Interrupt */ 695 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 696 p + NI8420_INT_ENABLE_REG); 697 698 iounmap(p); 699 return 0; 700 } 701 702 #define MITE_IOWBSR1_WSIZE 0xa 703 #define MITE_IOWBSR1_WIN_OFFSET 0x800 704 #define MITE_IOWBSR1_WENAB (1 << 7) 705 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 706 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 707 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 708 709 static int pci_ni8430_init(struct pci_dev *dev) 710 { 711 void __iomem *p; 712 struct pci_bus_region region; 713 u32 device_window; 714 unsigned int bar = 0; 715 716 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 717 moan_device("no memory in bar", dev); 718 return 0; 719 } 720 721 p = pci_ioremap_bar(dev, bar); 722 if (p == NULL) 723 return -ENOMEM; 724 725 /* 726 * Set device window address and size in BAR0, while acknowledging that 727 * the resource structure may contain a translated address that differs 728 * from the address the device responds to. 729 */ 730 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 731 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 733 writel(device_window, p + MITE_IOWBSR1); 734 735 /* Set window access to go to RAMSEL IO address space */ 736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 737 p + MITE_IOWCR1); 738 739 /* Enable IO Bus Interrupt 0 */ 740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 741 742 /* Enable CPU Interrupt */ 743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 744 745 iounmap(p); 746 return 0; 747 } 748 749 /* UART Port Control Register */ 750 #define NI8430_PORTCON 0x0f 751 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 752 753 static int 754 pci_ni8430_setup(struct serial_private *priv, 755 const struct pciserial_board *board, 756 struct uart_8250_port *port, int idx) 757 { 758 struct pci_dev *dev = priv->dev; 759 void __iomem *p; 760 unsigned int bar, offset = board->first_offset; 761 762 if (idx >= board->num_ports) 763 return 1; 764 765 bar = FL_GET_BASE(board->flags); 766 offset += idx * board->uart_offset; 767 768 p = pci_ioremap_bar(dev, bar); 769 if (!p) 770 return -ENOMEM; 771 772 /* enable the transceiver */ 773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 774 p + offset + NI8430_PORTCON); 775 776 iounmap(p); 777 778 return setup_port(priv, port, bar, offset, board->reg_shift); 779 } 780 781 static int pci_netmos_9900_setup(struct serial_private *priv, 782 const struct pciserial_board *board, 783 struct uart_8250_port *port, int idx) 784 { 785 unsigned int bar; 786 787 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 788 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 789 /* netmos apparently orders BARs by datasheet layout, so serial 790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 791 */ 792 bar = 3 * idx; 793 794 return setup_port(priv, port, bar, 0, board->reg_shift); 795 } else { 796 return pci_default_setup(priv, board, port, idx); 797 } 798 } 799 800 /* the 99xx series comes with a range of device IDs and a variety 801 * of capabilities: 802 * 803 * 9900 has varying capabilities and can cascade to sub-controllers 804 * (cascading should be purely internal) 805 * 9904 is hardwired with 4 serial ports 806 * 9912 and 9922 are hardwired with 2 serial ports 807 */ 808 static int pci_netmos_9900_numports(struct pci_dev *dev) 809 { 810 unsigned int c = dev->class; 811 unsigned int pi; 812 unsigned short sub_serports; 813 814 pi = c & 0xff; 815 816 if (pi == 2) 817 return 1; 818 819 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 820 /* two possibilities: 0x30ps encodes number of parallel and 821 * serial ports, or 0x1000 indicates *something*. This is not 822 * immediately obvious, since the 2s1p+4s configuration seems 823 * to offer all functionality on functions 0..2, while still 824 * advertising the same function 3 as the 4s+2s1p config. 825 */ 826 sub_serports = dev->subsystem_device & 0xf; 827 if (sub_serports > 0) 828 return sub_serports; 829 830 dev_err(&dev->dev, 831 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 832 return 0; 833 } 834 835 moan_device("unknown NetMos/Mostech program interface", dev); 836 return 0; 837 } 838 839 static int pci_netmos_init(struct pci_dev *dev) 840 { 841 /* subdevice 0x00PS means <P> parallel, <S> serial */ 842 unsigned int num_serial = dev->subsystem_device & 0xf; 843 844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 845 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 846 return 0; 847 848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 849 dev->subsystem_device == 0x0299) 850 return 0; 851 852 switch (dev->device) { /* FALLTHROUGH on all */ 853 case PCI_DEVICE_ID_NETMOS_9904: 854 case PCI_DEVICE_ID_NETMOS_9912: 855 case PCI_DEVICE_ID_NETMOS_9922: 856 case PCI_DEVICE_ID_NETMOS_9900: 857 num_serial = pci_netmos_9900_numports(dev); 858 break; 859 860 default: 861 break; 862 } 863 864 if (num_serial == 0) { 865 moan_device("unknown NetMos/Mostech device", dev); 866 return -ENODEV; 867 } 868 869 return num_serial; 870 } 871 872 /* 873 * These chips are available with optionally one parallel port and up to 874 * two serial ports. Unfortunately they all have the same product id. 875 * 876 * Basic configuration is done over a region of 32 I/O ports. The base 877 * ioport is called INTA or INTC, depending on docs/other drivers. 878 * 879 * The region of the 32 I/O ports is configured in POSIO0R... 880 */ 881 882 /* registers */ 883 #define ITE_887x_MISCR 0x9c 884 #define ITE_887x_INTCBAR 0x78 885 #define ITE_887x_UARTBAR 0x7c 886 #define ITE_887x_PS0BAR 0x10 887 #define ITE_887x_POSIO0 0x60 888 889 /* I/O space size */ 890 #define ITE_887x_IOSIZE 32 891 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 893 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 896 #define ITE_887x_POSIO_SPEED (3 << 29) 897 /* enable IO_Space bit */ 898 #define ITE_887x_POSIO_ENABLE (1 << 31) 899 900 static int pci_ite887x_init(struct pci_dev *dev) 901 { 902 /* inta_addr are the configuration addresses of the ITE */ 903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 904 0x200, 0x280, 0 }; 905 int ret, i, type; 906 struct resource *iobase = NULL; 907 u32 miscr, uartbar, ioport; 908 909 /* search for the base-ioport */ 910 i = 0; 911 while (inta_addr[i] && iobase == NULL) { 912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 913 "ite887x"); 914 if (iobase != NULL) { 915 /* write POSIO0R - speed | size | ioport */ 916 pci_write_config_dword(dev, ITE_887x_POSIO0, 917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 919 /* write INTCBAR - ioport */ 920 pci_write_config_dword(dev, ITE_887x_INTCBAR, 921 inta_addr[i]); 922 ret = inb(inta_addr[i]); 923 if (ret != 0xff) { 924 /* ioport connected */ 925 break; 926 } 927 release_region(iobase->start, ITE_887x_IOSIZE); 928 iobase = NULL; 929 } 930 i++; 931 } 932 933 if (!inta_addr[i]) { 934 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 935 return -ENODEV; 936 } 937 938 /* start of undocumented type checking (see parport_pc.c) */ 939 type = inb(iobase->start + 0x18) & 0x0f; 940 941 switch (type) { 942 case 0x2: /* ITE8871 (1P) */ 943 case 0xa: /* ITE8875 (1P) */ 944 ret = 0; 945 break; 946 case 0xe: /* ITE8872 (2S1P) */ 947 ret = 2; 948 break; 949 case 0x6: /* ITE8873 (1S) */ 950 ret = 1; 951 break; 952 case 0x8: /* ITE8874 (2S) */ 953 ret = 2; 954 break; 955 default: 956 moan_device("Unknown ITE887x", dev); 957 ret = -ENODEV; 958 } 959 960 /* configure all serial ports */ 961 for (i = 0; i < ret; i++) { 962 /* read the I/O port from the device */ 963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 964 &ioport); 965 ioport &= 0x0000FF00; /* the actual base address */ 966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 968 ITE_887x_POSIO_IOSIZE_8 | ioport); 969 970 /* write the ioport to the UARTBAR */ 971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 973 uartbar |= (ioport << (16 * i)); /* set the ioport */ 974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 975 976 /* get current config */ 977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 978 /* disable interrupts (UARTx_Routing[3:0]) */ 979 miscr &= ~(0xf << (12 - 4 * i)); 980 /* activate the UART (UARTx_En) */ 981 miscr |= 1 << (23 - i); 982 /* write new config with activated UART */ 983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 984 } 985 986 if (ret <= 0) { 987 /* the device has no UARTs if we get here */ 988 release_region(iobase->start, ITE_887x_IOSIZE); 989 } 990 991 return ret; 992 } 993 994 static void pci_ite887x_exit(struct pci_dev *dev) 995 { 996 u32 ioport; 997 /* the ioport is bit 0-15 in POSIO0R */ 998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 999 ioport &= 0xffff; 1000 release_region(ioport, ITE_887x_IOSIZE); 1001 } 1002 1003 /* 1004 * EndRun Technologies. 1005 * Determine the number of ports available on the device. 1006 */ 1007 #define PCI_VENDOR_ID_ENDRUN 0x7401 1008 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1009 1010 static int pci_endrun_init(struct pci_dev *dev) 1011 { 1012 u8 __iomem *p; 1013 unsigned long deviceID; 1014 unsigned int number_uarts = 0; 1015 1016 /* EndRun device is all 0xexxx */ 1017 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1018 (dev->device & 0xf000) != 0xe000) 1019 return 0; 1020 1021 p = pci_iomap(dev, 0, 5); 1022 if (p == NULL) 1023 return -ENOMEM; 1024 1025 deviceID = ioread32(p); 1026 /* EndRun device */ 1027 if (deviceID == 0x07000200) { 1028 number_uarts = ioread8(p + 4); 1029 dev_dbg(&dev->dev, 1030 "%d ports detected on EndRun PCI Express device\n", 1031 number_uarts); 1032 } 1033 pci_iounmap(dev, p); 1034 return number_uarts; 1035 } 1036 1037 /* 1038 * Oxford Semiconductor Inc. 1039 * Check that device is part of the Tornado range of devices, then determine 1040 * the number of ports available on the device. 1041 */ 1042 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1043 { 1044 u8 __iomem *p; 1045 unsigned long deviceID; 1046 unsigned int number_uarts = 0; 1047 1048 /* OxSemi Tornado devices are all 0xCxxx */ 1049 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1050 (dev->device & 0xF000) != 0xC000) 1051 return 0; 1052 1053 p = pci_iomap(dev, 0, 5); 1054 if (p == NULL) 1055 return -ENOMEM; 1056 1057 deviceID = ioread32(p); 1058 /* Tornado device */ 1059 if (deviceID == 0x07000200) { 1060 number_uarts = ioread8(p + 4); 1061 dev_dbg(&dev->dev, 1062 "%d ports detected on Oxford PCI Express device\n", 1063 number_uarts); 1064 } 1065 pci_iounmap(dev, p); 1066 return number_uarts; 1067 } 1068 1069 static int pci_asix_setup(struct serial_private *priv, 1070 const struct pciserial_board *board, 1071 struct uart_8250_port *port, int idx) 1072 { 1073 port->bugs |= UART_BUG_PARITY; 1074 return pci_default_setup(priv, board, port, idx); 1075 } 1076 1077 /* Quatech devices have their own extra interface features */ 1078 1079 struct quatech_feature { 1080 u16 devid; 1081 bool amcc; 1082 }; 1083 1084 #define QPCR_TEST_FOR1 0x3F 1085 #define QPCR_TEST_GET1 0x00 1086 #define QPCR_TEST_FOR2 0x40 1087 #define QPCR_TEST_GET2 0x40 1088 #define QPCR_TEST_FOR3 0x80 1089 #define QPCR_TEST_GET3 0x40 1090 #define QPCR_TEST_FOR4 0xC0 1091 #define QPCR_TEST_GET4 0x80 1092 1093 #define QOPR_CLOCK_X1 0x0000 1094 #define QOPR_CLOCK_X2 0x0001 1095 #define QOPR_CLOCK_X4 0x0002 1096 #define QOPR_CLOCK_X8 0x0003 1097 #define QOPR_CLOCK_RATE_MASK 0x0003 1098 1099 1100 static struct quatech_feature quatech_cards[] = { 1101 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1102 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1103 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1104 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1105 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1106 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1107 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1108 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1109 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1110 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1111 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1112 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1113 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1114 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1115 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1116 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1117 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1118 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1119 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1120 { 0, } 1121 }; 1122 1123 static int pci_quatech_amcc(u16 devid) 1124 { 1125 struct quatech_feature *qf = &quatech_cards[0]; 1126 while (qf->devid) { 1127 if (qf->devid == devid) 1128 return qf->amcc; 1129 qf++; 1130 } 1131 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1132 return 0; 1133 }; 1134 1135 static int pci_quatech_rqopr(struct uart_8250_port *port) 1136 { 1137 unsigned long base = port->port.iobase; 1138 u8 LCR, val; 1139 1140 LCR = inb(base + UART_LCR); 1141 outb(0xBF, base + UART_LCR); 1142 val = inb(base + UART_SCR); 1143 outb(LCR, base + UART_LCR); 1144 return val; 1145 } 1146 1147 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1148 { 1149 unsigned long base = port->port.iobase; 1150 u8 LCR; 1151 1152 LCR = inb(base + UART_LCR); 1153 outb(0xBF, base + UART_LCR); 1154 inb(base + UART_SCR); 1155 outb(qopr, base + UART_SCR); 1156 outb(LCR, base + UART_LCR); 1157 } 1158 1159 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1160 { 1161 unsigned long base = port->port.iobase; 1162 u8 LCR, val, qmcr; 1163 1164 LCR = inb(base + UART_LCR); 1165 outb(0xBF, base + UART_LCR); 1166 val = inb(base + UART_SCR); 1167 outb(val | 0x10, base + UART_SCR); 1168 qmcr = inb(base + UART_MCR); 1169 outb(val, base + UART_SCR); 1170 outb(LCR, base + UART_LCR); 1171 1172 return qmcr; 1173 } 1174 1175 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1176 { 1177 unsigned long base = port->port.iobase; 1178 u8 LCR, val; 1179 1180 LCR = inb(base + UART_LCR); 1181 outb(0xBF, base + UART_LCR); 1182 val = inb(base + UART_SCR); 1183 outb(val | 0x10, base + UART_SCR); 1184 outb(qmcr, base + UART_MCR); 1185 outb(val, base + UART_SCR); 1186 outb(LCR, base + UART_LCR); 1187 } 1188 1189 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1190 { 1191 unsigned long base = port->port.iobase; 1192 u8 LCR, val; 1193 1194 LCR = inb(base + UART_LCR); 1195 outb(0xBF, base + UART_LCR); 1196 val = inb(base + UART_SCR); 1197 if (val & 0x20) { 1198 outb(0x80, UART_LCR); 1199 if (!(inb(UART_SCR) & 0x20)) { 1200 outb(LCR, base + UART_LCR); 1201 return 1; 1202 } 1203 } 1204 return 0; 1205 } 1206 1207 static int pci_quatech_test(struct uart_8250_port *port) 1208 { 1209 u8 reg, qopr; 1210 1211 qopr = pci_quatech_rqopr(port); 1212 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1213 reg = pci_quatech_rqopr(port) & 0xC0; 1214 if (reg != QPCR_TEST_GET1) 1215 return -EINVAL; 1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1217 reg = pci_quatech_rqopr(port) & 0xC0; 1218 if (reg != QPCR_TEST_GET2) 1219 return -EINVAL; 1220 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1221 reg = pci_quatech_rqopr(port) & 0xC0; 1222 if (reg != QPCR_TEST_GET3) 1223 return -EINVAL; 1224 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1225 reg = pci_quatech_rqopr(port) & 0xC0; 1226 if (reg != QPCR_TEST_GET4) 1227 return -EINVAL; 1228 1229 pci_quatech_wqopr(port, qopr); 1230 return 0; 1231 } 1232 1233 static int pci_quatech_clock(struct uart_8250_port *port) 1234 { 1235 u8 qopr, reg, set; 1236 unsigned long clock; 1237 1238 if (pci_quatech_test(port) < 0) 1239 return 1843200; 1240 1241 qopr = pci_quatech_rqopr(port); 1242 1243 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1244 reg = pci_quatech_rqopr(port); 1245 if (reg & QOPR_CLOCK_X8) { 1246 clock = 1843200; 1247 goto out; 1248 } 1249 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1250 reg = pci_quatech_rqopr(port); 1251 if (!(reg & QOPR_CLOCK_X8)) { 1252 clock = 1843200; 1253 goto out; 1254 } 1255 reg &= QOPR_CLOCK_X8; 1256 if (reg == QOPR_CLOCK_X2) { 1257 clock = 3685400; 1258 set = QOPR_CLOCK_X2; 1259 } else if (reg == QOPR_CLOCK_X4) { 1260 clock = 7372800; 1261 set = QOPR_CLOCK_X4; 1262 } else if (reg == QOPR_CLOCK_X8) { 1263 clock = 14745600; 1264 set = QOPR_CLOCK_X8; 1265 } else { 1266 clock = 1843200; 1267 set = QOPR_CLOCK_X1; 1268 } 1269 qopr &= ~QOPR_CLOCK_RATE_MASK; 1270 qopr |= set; 1271 1272 out: 1273 pci_quatech_wqopr(port, qopr); 1274 return clock; 1275 } 1276 1277 static int pci_quatech_rs422(struct uart_8250_port *port) 1278 { 1279 u8 qmcr; 1280 int rs422 = 0; 1281 1282 if (!pci_quatech_has_qmcr(port)) 1283 return 0; 1284 qmcr = pci_quatech_rqmcr(port); 1285 pci_quatech_wqmcr(port, 0xFF); 1286 if (pci_quatech_rqmcr(port)) 1287 rs422 = 1; 1288 pci_quatech_wqmcr(port, qmcr); 1289 return rs422; 1290 } 1291 1292 static int pci_quatech_init(struct pci_dev *dev) 1293 { 1294 if (pci_quatech_amcc(dev->device)) { 1295 unsigned long base = pci_resource_start(dev, 0); 1296 if (base) { 1297 u32 tmp; 1298 1299 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1300 tmp = inl(base + 0x3c); 1301 outl(tmp | 0x01000000, base + 0x3c); 1302 outl(tmp &= ~0x01000000, base + 0x3c); 1303 } 1304 } 1305 return 0; 1306 } 1307 1308 static int pci_quatech_setup(struct serial_private *priv, 1309 const struct pciserial_board *board, 1310 struct uart_8250_port *port, int idx) 1311 { 1312 /* Needed by pci_quatech calls below */ 1313 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1314 /* Set up the clocking */ 1315 port->port.uartclk = pci_quatech_clock(port); 1316 /* For now just warn about RS422 */ 1317 if (pci_quatech_rs422(port)) 1318 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1319 return pci_default_setup(priv, board, port, idx); 1320 } 1321 1322 static void pci_quatech_exit(struct pci_dev *dev) 1323 { 1324 } 1325 1326 static int pci_default_setup(struct serial_private *priv, 1327 const struct pciserial_board *board, 1328 struct uart_8250_port *port, int idx) 1329 { 1330 unsigned int bar, offset = board->first_offset, maxnr; 1331 1332 bar = FL_GET_BASE(board->flags); 1333 if (board->flags & FL_BASE_BARS) 1334 bar += idx; 1335 else 1336 offset += idx * board->uart_offset; 1337 1338 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1339 (board->reg_shift + 3); 1340 1341 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1342 return 1; 1343 1344 return setup_port(priv, port, bar, offset, board->reg_shift); 1345 } 1346 static void 1347 pericom_do_set_divisor(struct uart_port *port, unsigned int baud, 1348 unsigned int quot, unsigned int quot_frac) 1349 { 1350 int scr; 1351 int lcr; 1352 int actual_baud; 1353 int tolerance; 1354 1355 for (scr = 5 ; scr <= 15 ; scr++) { 1356 actual_baud = 921600 * 16 / scr; 1357 tolerance = actual_baud / 50; 1358 1359 if ((baud < actual_baud + tolerance) && 1360 (baud > actual_baud - tolerance)) { 1361 1362 lcr = serial_port_in(port, UART_LCR); 1363 serial_port_out(port, UART_LCR, lcr | 0x80); 1364 1365 serial_port_out(port, UART_DLL, 1); 1366 serial_port_out(port, UART_DLM, 0); 1367 serial_port_out(port, 2, 16 - scr); 1368 serial_port_out(port, UART_LCR, lcr); 1369 return; 1370 } else if (baud > actual_baud) { 1371 break; 1372 } 1373 } 1374 serial8250_do_set_divisor(port, baud, quot, quot_frac); 1375 } 1376 static int pci_pericom_setup(struct serial_private *priv, 1377 const struct pciserial_board *board, 1378 struct uart_8250_port *port, int idx) 1379 { 1380 unsigned int bar, offset = board->first_offset, maxnr; 1381 1382 bar = FL_GET_BASE(board->flags); 1383 if (board->flags & FL_BASE_BARS) 1384 bar += idx; 1385 else 1386 offset += idx * board->uart_offset; 1387 1388 1389 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1390 (board->reg_shift + 3); 1391 1392 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1393 return 1; 1394 1395 port->port.set_divisor = pericom_do_set_divisor; 1396 1397 return setup_port(priv, port, bar, offset, board->reg_shift); 1398 } 1399 1400 static int pci_pericom_setup_four_at_eight(struct serial_private *priv, 1401 const struct pciserial_board *board, 1402 struct uart_8250_port *port, int idx) 1403 { 1404 unsigned int bar, offset = board->first_offset, maxnr; 1405 1406 bar = FL_GET_BASE(board->flags); 1407 if (board->flags & FL_BASE_BARS) 1408 bar += idx; 1409 else 1410 offset += idx * board->uart_offset; 1411 1412 if (idx==3) 1413 offset = 0x38; 1414 1415 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1416 (board->reg_shift + 3); 1417 1418 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1419 return 1; 1420 1421 port->port.set_divisor = pericom_do_set_divisor; 1422 1423 return setup_port(priv, port, bar, offset, board->reg_shift); 1424 } 1425 1426 static int 1427 ce4100_serial_setup(struct serial_private *priv, 1428 const struct pciserial_board *board, 1429 struct uart_8250_port *port, int idx) 1430 { 1431 int ret; 1432 1433 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1434 port->port.iotype = UPIO_MEM32; 1435 port->port.type = PORT_XSCALE; 1436 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1437 port->port.regshift = 2; 1438 1439 return ret; 1440 } 1441 1442 static int 1443 pci_omegapci_setup(struct serial_private *priv, 1444 const struct pciserial_board *board, 1445 struct uart_8250_port *port, int idx) 1446 { 1447 return setup_port(priv, port, 2, idx * 8, 0); 1448 } 1449 1450 static int 1451 pci_brcm_trumanage_setup(struct serial_private *priv, 1452 const struct pciserial_board *board, 1453 struct uart_8250_port *port, int idx) 1454 { 1455 int ret = pci_default_setup(priv, board, port, idx); 1456 1457 port->port.type = PORT_BRCM_TRUMANAGE; 1458 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1459 return ret; 1460 } 1461 1462 /* RTS will control by MCR if this bit is 0 */ 1463 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1464 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1465 #define FINTEK_RTS_INVERT BIT(5) 1466 1467 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1468 static int pci_fintek_rs485_config(struct uart_port *port, 1469 struct serial_rs485 *rs485) 1470 { 1471 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1472 u8 setting; 1473 u8 *index = (u8 *) port->private_data; 1474 1475 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1476 1477 if (!rs485) 1478 rs485 = &port->rs485; 1479 else if (rs485->flags & SER_RS485_ENABLED) 1480 memset(rs485->padding, 0, sizeof(rs485->padding)); 1481 else 1482 memset(rs485, 0, sizeof(*rs485)); 1483 1484 /* F81504/508/512 not support RTS delay before or after send */ 1485 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1486 1487 if (rs485->flags & SER_RS485_ENABLED) { 1488 /* Enable RTS H/W control mode */ 1489 setting |= FINTEK_RTS_CONTROL_BY_HW; 1490 1491 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1492 /* RTS driving high on TX */ 1493 setting &= ~FINTEK_RTS_INVERT; 1494 } else { 1495 /* RTS driving low on TX */ 1496 setting |= FINTEK_RTS_INVERT; 1497 } 1498 1499 rs485->delay_rts_after_send = 0; 1500 rs485->delay_rts_before_send = 0; 1501 } else { 1502 /* Disable RTS H/W control mode */ 1503 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1504 } 1505 1506 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1507 1508 if (rs485 != &port->rs485) 1509 port->rs485 = *rs485; 1510 1511 return 0; 1512 } 1513 1514 static int pci_fintek_setup(struct serial_private *priv, 1515 const struct pciserial_board *board, 1516 struct uart_8250_port *port, int idx) 1517 { 1518 struct pci_dev *pdev = priv->dev; 1519 u8 *data; 1520 u8 config_base; 1521 u16 iobase; 1522 1523 config_base = 0x40 + 0x08 * idx; 1524 1525 /* Get the io address from configuration space */ 1526 pci_read_config_word(pdev, config_base + 4, &iobase); 1527 1528 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1529 1530 port->port.iotype = UPIO_PORT; 1531 port->port.iobase = iobase; 1532 port->port.rs485_config = pci_fintek_rs485_config; 1533 1534 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1535 if (!data) 1536 return -ENOMEM; 1537 1538 /* preserve index in PCI configuration space */ 1539 *data = idx; 1540 port->port.private_data = data; 1541 1542 return 0; 1543 } 1544 1545 static int pci_fintek_init(struct pci_dev *dev) 1546 { 1547 unsigned long iobase; 1548 u32 max_port, i; 1549 resource_size_t bar_data[3]; 1550 u8 config_base; 1551 struct serial_private *priv = pci_get_drvdata(dev); 1552 struct uart_8250_port *port; 1553 1554 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1555 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1556 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1557 return -ENODEV; 1558 1559 switch (dev->device) { 1560 case 0x1104: /* 4 ports */ 1561 case 0x1108: /* 8 ports */ 1562 max_port = dev->device & 0xff; 1563 break; 1564 case 0x1112: /* 12 ports */ 1565 max_port = 12; 1566 break; 1567 default: 1568 return -EINVAL; 1569 } 1570 1571 /* Get the io address dispatch from the BIOS */ 1572 bar_data[0] = pci_resource_start(dev, 5); 1573 bar_data[1] = pci_resource_start(dev, 4); 1574 bar_data[2] = pci_resource_start(dev, 3); 1575 1576 for (i = 0; i < max_port; ++i) { 1577 /* UART0 configuration offset start from 0x40 */ 1578 config_base = 0x40 + 0x08 * i; 1579 1580 /* Calculate Real IO Port */ 1581 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1582 1583 /* Enable UART I/O port */ 1584 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1585 1586 /* Select 128-byte FIFO and 8x FIFO threshold */ 1587 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1588 1589 /* LSB UART */ 1590 pci_write_config_byte(dev, config_base + 0x04, 1591 (u8)(iobase & 0xff)); 1592 1593 /* MSB UART */ 1594 pci_write_config_byte(dev, config_base + 0x05, 1595 (u8)((iobase & 0xff00) >> 8)); 1596 1597 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1598 1599 if (priv) { 1600 /* re-apply RS232/485 mode when 1601 * pciserial_resume_ports() 1602 */ 1603 port = serial8250_get_port(priv->line[i]); 1604 pci_fintek_rs485_config(&port->port, NULL); 1605 } else { 1606 /* First init without port data 1607 * force init to RS232 Mode 1608 */ 1609 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1610 } 1611 } 1612 1613 return max_port; 1614 } 1615 1616 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1617 { 1618 struct f815xxa_data *data = p->private_data; 1619 unsigned long flags; 1620 1621 spin_lock_irqsave(&data->lock, flags); 1622 writeb(value, p->membase + offset); 1623 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1624 spin_unlock_irqrestore(&data->lock, flags); 1625 } 1626 1627 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1628 const struct pciserial_board *board, 1629 struct uart_8250_port *port, int idx) 1630 { 1631 struct pci_dev *pdev = priv->dev; 1632 struct f815xxa_data *data; 1633 1634 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1635 if (!data) 1636 return -ENOMEM; 1637 1638 data->idx = idx; 1639 spin_lock_init(&data->lock); 1640 1641 port->port.private_data = data; 1642 port->port.iotype = UPIO_MEM; 1643 port->port.flags |= UPF_IOREMAP; 1644 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1645 port->port.serial_out = f815xxa_mem_serial_out; 1646 1647 return 0; 1648 } 1649 1650 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1651 { 1652 u32 max_port, i; 1653 int config_base; 1654 1655 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1656 return -ENODEV; 1657 1658 switch (dev->device) { 1659 case 0x1204: /* 4 ports */ 1660 case 0x1208: /* 8 ports */ 1661 max_port = dev->device & 0xff; 1662 break; 1663 case 0x1212: /* 12 ports */ 1664 max_port = 12; 1665 break; 1666 default: 1667 return -EINVAL; 1668 } 1669 1670 /* Set to mmio decode */ 1671 pci_write_config_byte(dev, 0x209, 0x40); 1672 1673 for (i = 0; i < max_port; ++i) { 1674 /* UART0 configuration offset start from 0x2A0 */ 1675 config_base = 0x2A0 + 0x08 * i; 1676 1677 /* Select 128-byte FIFO and 8x FIFO threshold */ 1678 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1679 1680 /* Enable UART I/O port */ 1681 pci_write_config_byte(dev, config_base + 0, 0x01); 1682 } 1683 1684 return max_port; 1685 } 1686 1687 static int skip_tx_en_setup(struct serial_private *priv, 1688 const struct pciserial_board *board, 1689 struct uart_8250_port *port, int idx) 1690 { 1691 port->port.quirks |= UPQ_NO_TXEN_TEST; 1692 dev_dbg(&priv->dev->dev, 1693 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1694 priv->dev->vendor, priv->dev->device, 1695 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1696 1697 return pci_default_setup(priv, board, port, idx); 1698 } 1699 1700 static void kt_handle_break(struct uart_port *p) 1701 { 1702 struct uart_8250_port *up = up_to_u8250p(p); 1703 /* 1704 * On receipt of a BI, serial device in Intel ME (Intel 1705 * management engine) needs to have its fifos cleared for sane 1706 * SOL (Serial Over Lan) output. 1707 */ 1708 serial8250_clear_and_reinit_fifos(up); 1709 } 1710 1711 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1712 { 1713 struct uart_8250_port *up = up_to_u8250p(p); 1714 unsigned int val; 1715 1716 /* 1717 * When the Intel ME (management engine) gets reset its serial 1718 * port registers could return 0 momentarily. Functions like 1719 * serial8250_console_write, read and save the IER, perform 1720 * some operation and then restore it. In order to avoid 1721 * setting IER register inadvertently to 0, if the value read 1722 * is 0, double check with ier value in uart_8250_port and use 1723 * that instead. up->ier should be the same value as what is 1724 * currently configured. 1725 */ 1726 val = inb(p->iobase + offset); 1727 if (offset == UART_IER) { 1728 if (val == 0) 1729 val = up->ier; 1730 } 1731 return val; 1732 } 1733 1734 static int kt_serial_setup(struct serial_private *priv, 1735 const struct pciserial_board *board, 1736 struct uart_8250_port *port, int idx) 1737 { 1738 port->port.flags |= UPF_BUG_THRE; 1739 port->port.serial_in = kt_serial_in; 1740 port->port.handle_break = kt_handle_break; 1741 return skip_tx_en_setup(priv, board, port, idx); 1742 } 1743 1744 static int pci_eg20t_init(struct pci_dev *dev) 1745 { 1746 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1747 return -ENODEV; 1748 #else 1749 return 0; 1750 #endif 1751 } 1752 1753 static int 1754 pci_wch_ch353_setup(struct serial_private *priv, 1755 const struct pciserial_board *board, 1756 struct uart_8250_port *port, int idx) 1757 { 1758 port->port.flags |= UPF_FIXED_TYPE; 1759 port->port.type = PORT_16550A; 1760 return pci_default_setup(priv, board, port, idx); 1761 } 1762 1763 static int 1764 pci_wch_ch355_setup(struct serial_private *priv, 1765 const struct pciserial_board *board, 1766 struct uart_8250_port *port, int idx) 1767 { 1768 port->port.flags |= UPF_FIXED_TYPE; 1769 port->port.type = PORT_16550A; 1770 return pci_default_setup(priv, board, port, idx); 1771 } 1772 1773 static int 1774 pci_wch_ch38x_setup(struct serial_private *priv, 1775 const struct pciserial_board *board, 1776 struct uart_8250_port *port, int idx) 1777 { 1778 port->port.flags |= UPF_FIXED_TYPE; 1779 port->port.type = PORT_16850; 1780 return pci_default_setup(priv, board, port, idx); 1781 } 1782 1783 1784 #define CH384_XINT_ENABLE_REG 0xEB 1785 #define CH384_XINT_ENABLE_BIT 0x02 1786 1787 static int pci_wch_ch38x_init(struct pci_dev *dev) 1788 { 1789 int max_port; 1790 unsigned long iobase; 1791 1792 1793 switch (dev->device) { 1794 case 0x3853: /* 8 ports */ 1795 max_port = 8; 1796 break; 1797 default: 1798 return -EINVAL; 1799 } 1800 1801 iobase = pci_resource_start(dev, 0); 1802 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1803 1804 return max_port; 1805 } 1806 1807 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1808 { 1809 unsigned long iobase; 1810 1811 iobase = pci_resource_start(dev, 0); 1812 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1813 } 1814 1815 1816 static int 1817 pci_sunix_setup(struct serial_private *priv, 1818 const struct pciserial_board *board, 1819 struct uart_8250_port *port, int idx) 1820 { 1821 int bar; 1822 int offset; 1823 1824 port->port.flags |= UPF_FIXED_TYPE; 1825 port->port.type = PORT_SUNIX; 1826 1827 if (idx < 4) { 1828 bar = 0; 1829 offset = idx * board->uart_offset; 1830 } else { 1831 bar = 1; 1832 idx -= 4; 1833 idx = div_s64_rem(idx, 4, &offset); 1834 offset = idx * 64 + offset * board->uart_offset; 1835 } 1836 1837 return setup_port(priv, port, bar, offset, 0); 1838 } 1839 1840 static int 1841 pci_moxa_setup(struct serial_private *priv, 1842 const struct pciserial_board *board, 1843 struct uart_8250_port *port, int idx) 1844 { 1845 unsigned int bar = FL_GET_BASE(board->flags); 1846 int offset; 1847 1848 if (board->num_ports == 4 && idx == 3) 1849 offset = 7 * board->uart_offset; 1850 else 1851 offset = idx * board->uart_offset; 1852 1853 return setup_port(priv, port, bar, offset, 0); 1854 } 1855 1856 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1857 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1858 #define PCI_DEVICE_ID_OCTPRO 0x0001 1859 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1860 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1861 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1862 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1863 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1864 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1865 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1866 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1867 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1868 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1869 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1870 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1871 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1872 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1873 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1874 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1875 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1876 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1877 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1878 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1879 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1880 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1881 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1882 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1883 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1884 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1885 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1886 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1887 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1888 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1889 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1890 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1891 #define PCI_VENDOR_ID_WCH 0x4348 1892 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1893 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1894 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1895 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1896 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1897 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1898 #define PCI_VENDOR_ID_AGESTAR 0x5372 1899 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1900 #define PCI_VENDOR_ID_ASIX 0x9710 1901 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1902 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1903 1904 #define PCIE_VENDOR_ID_WCH 0x1c00 1905 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1906 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1907 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1908 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1909 1910 #define PCI_VENDOR_ID_ACCESIO 0x494f 1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1912 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1914 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1916 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1918 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1919 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1920 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1921 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1922 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1923 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1924 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1925 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1926 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1927 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1928 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1929 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1930 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1931 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1932 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1933 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1934 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1935 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1936 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1937 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1938 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1939 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1940 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1941 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1942 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1943 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1944 1945 1946 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1947 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1948 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1949 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1950 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1951 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1952 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1953 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1954 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1955 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1956 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1957 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1958 1959 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1960 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1961 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1962 1963 /* 1964 * Master list of serial port init/setup/exit quirks. 1965 * This does not describe the general nature of the port. 1966 * (ie, baud base, number and location of ports, etc) 1967 * 1968 * This list is ordered alphabetically by vendor then device. 1969 * Specific entries must come before more generic entries. 1970 */ 1971 static struct pci_serial_quirk pci_serial_quirks[] = { 1972 /* 1973 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1974 */ 1975 { 1976 .vendor = PCI_VENDOR_ID_AMCC, 1977 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1978 .subvendor = PCI_ANY_ID, 1979 .subdevice = PCI_ANY_ID, 1980 .setup = addidata_apci7800_setup, 1981 }, 1982 /* 1983 * AFAVLAB cards - these may be called via parport_serial 1984 * It is not clear whether this applies to all products. 1985 */ 1986 { 1987 .vendor = PCI_VENDOR_ID_AFAVLAB, 1988 .device = PCI_ANY_ID, 1989 .subvendor = PCI_ANY_ID, 1990 .subdevice = PCI_ANY_ID, 1991 .setup = afavlab_setup, 1992 }, 1993 /* 1994 * HP Diva 1995 */ 1996 { 1997 .vendor = PCI_VENDOR_ID_HP, 1998 .device = PCI_DEVICE_ID_HP_DIVA, 1999 .subvendor = PCI_ANY_ID, 2000 .subdevice = PCI_ANY_ID, 2001 .init = pci_hp_diva_init, 2002 .setup = pci_hp_diva_setup, 2003 }, 2004 /* 2005 * HPE PCI serial device 2006 */ 2007 { 2008 .vendor = PCI_VENDOR_ID_HP_3PAR, 2009 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2010 .subvendor = PCI_ANY_ID, 2011 .subdevice = PCI_ANY_ID, 2012 .setup = pci_hp_diva_setup, 2013 }, 2014 /* 2015 * Intel 2016 */ 2017 { 2018 .vendor = PCI_VENDOR_ID_INTEL, 2019 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2020 .subvendor = 0xe4bf, 2021 .subdevice = PCI_ANY_ID, 2022 .init = pci_inteli960ni_init, 2023 .setup = pci_default_setup, 2024 }, 2025 { 2026 .vendor = PCI_VENDOR_ID_INTEL, 2027 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2028 .subvendor = PCI_ANY_ID, 2029 .subdevice = PCI_ANY_ID, 2030 .setup = skip_tx_en_setup, 2031 }, 2032 { 2033 .vendor = PCI_VENDOR_ID_INTEL, 2034 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2035 .subvendor = PCI_ANY_ID, 2036 .subdevice = PCI_ANY_ID, 2037 .setup = skip_tx_en_setup, 2038 }, 2039 { 2040 .vendor = PCI_VENDOR_ID_INTEL, 2041 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2042 .subvendor = PCI_ANY_ID, 2043 .subdevice = PCI_ANY_ID, 2044 .setup = skip_tx_en_setup, 2045 }, 2046 { 2047 .vendor = PCI_VENDOR_ID_INTEL, 2048 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2049 .subvendor = PCI_ANY_ID, 2050 .subdevice = PCI_ANY_ID, 2051 .setup = ce4100_serial_setup, 2052 }, 2053 { 2054 .vendor = PCI_VENDOR_ID_INTEL, 2055 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2056 .subvendor = PCI_ANY_ID, 2057 .subdevice = PCI_ANY_ID, 2058 .setup = kt_serial_setup, 2059 }, 2060 /* 2061 * ITE 2062 */ 2063 { 2064 .vendor = PCI_VENDOR_ID_ITE, 2065 .device = PCI_DEVICE_ID_ITE_8872, 2066 .subvendor = PCI_ANY_ID, 2067 .subdevice = PCI_ANY_ID, 2068 .init = pci_ite887x_init, 2069 .setup = pci_default_setup, 2070 .exit = pci_ite887x_exit, 2071 }, 2072 /* 2073 * National Instruments 2074 */ 2075 { 2076 .vendor = PCI_VENDOR_ID_NI, 2077 .device = PCI_DEVICE_ID_NI_PCI23216, 2078 .subvendor = PCI_ANY_ID, 2079 .subdevice = PCI_ANY_ID, 2080 .init = pci_ni8420_init, 2081 .setup = pci_default_setup, 2082 .exit = pci_ni8420_exit, 2083 }, 2084 { 2085 .vendor = PCI_VENDOR_ID_NI, 2086 .device = PCI_DEVICE_ID_NI_PCI2328, 2087 .subvendor = PCI_ANY_ID, 2088 .subdevice = PCI_ANY_ID, 2089 .init = pci_ni8420_init, 2090 .setup = pci_default_setup, 2091 .exit = pci_ni8420_exit, 2092 }, 2093 { 2094 .vendor = PCI_VENDOR_ID_NI, 2095 .device = PCI_DEVICE_ID_NI_PCI2324, 2096 .subvendor = PCI_ANY_ID, 2097 .subdevice = PCI_ANY_ID, 2098 .init = pci_ni8420_init, 2099 .setup = pci_default_setup, 2100 .exit = pci_ni8420_exit, 2101 }, 2102 { 2103 .vendor = PCI_VENDOR_ID_NI, 2104 .device = PCI_DEVICE_ID_NI_PCI2322, 2105 .subvendor = PCI_ANY_ID, 2106 .subdevice = PCI_ANY_ID, 2107 .init = pci_ni8420_init, 2108 .setup = pci_default_setup, 2109 .exit = pci_ni8420_exit, 2110 }, 2111 { 2112 .vendor = PCI_VENDOR_ID_NI, 2113 .device = PCI_DEVICE_ID_NI_PCI2324I, 2114 .subvendor = PCI_ANY_ID, 2115 .subdevice = PCI_ANY_ID, 2116 .init = pci_ni8420_init, 2117 .setup = pci_default_setup, 2118 .exit = pci_ni8420_exit, 2119 }, 2120 { 2121 .vendor = PCI_VENDOR_ID_NI, 2122 .device = PCI_DEVICE_ID_NI_PCI2322I, 2123 .subvendor = PCI_ANY_ID, 2124 .subdevice = PCI_ANY_ID, 2125 .init = pci_ni8420_init, 2126 .setup = pci_default_setup, 2127 .exit = pci_ni8420_exit, 2128 }, 2129 { 2130 .vendor = PCI_VENDOR_ID_NI, 2131 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2132 .subvendor = PCI_ANY_ID, 2133 .subdevice = PCI_ANY_ID, 2134 .init = pci_ni8420_init, 2135 .setup = pci_default_setup, 2136 .exit = pci_ni8420_exit, 2137 }, 2138 { 2139 .vendor = PCI_VENDOR_ID_NI, 2140 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2141 .subvendor = PCI_ANY_ID, 2142 .subdevice = PCI_ANY_ID, 2143 .init = pci_ni8420_init, 2144 .setup = pci_default_setup, 2145 .exit = pci_ni8420_exit, 2146 }, 2147 { 2148 .vendor = PCI_VENDOR_ID_NI, 2149 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2150 .subvendor = PCI_ANY_ID, 2151 .subdevice = PCI_ANY_ID, 2152 .init = pci_ni8420_init, 2153 .setup = pci_default_setup, 2154 .exit = pci_ni8420_exit, 2155 }, 2156 { 2157 .vendor = PCI_VENDOR_ID_NI, 2158 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2159 .subvendor = PCI_ANY_ID, 2160 .subdevice = PCI_ANY_ID, 2161 .init = pci_ni8420_init, 2162 .setup = pci_default_setup, 2163 .exit = pci_ni8420_exit, 2164 }, 2165 { 2166 .vendor = PCI_VENDOR_ID_NI, 2167 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2168 .subvendor = PCI_ANY_ID, 2169 .subdevice = PCI_ANY_ID, 2170 .init = pci_ni8420_init, 2171 .setup = pci_default_setup, 2172 .exit = pci_ni8420_exit, 2173 }, 2174 { 2175 .vendor = PCI_VENDOR_ID_NI, 2176 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2177 .subvendor = PCI_ANY_ID, 2178 .subdevice = PCI_ANY_ID, 2179 .init = pci_ni8420_init, 2180 .setup = pci_default_setup, 2181 .exit = pci_ni8420_exit, 2182 }, 2183 { 2184 .vendor = PCI_VENDOR_ID_NI, 2185 .device = PCI_ANY_ID, 2186 .subvendor = PCI_ANY_ID, 2187 .subdevice = PCI_ANY_ID, 2188 .init = pci_ni8430_init, 2189 .setup = pci_ni8430_setup, 2190 .exit = pci_ni8430_exit, 2191 }, 2192 /* Quatech */ 2193 { 2194 .vendor = PCI_VENDOR_ID_QUATECH, 2195 .device = PCI_ANY_ID, 2196 .subvendor = PCI_ANY_ID, 2197 .subdevice = PCI_ANY_ID, 2198 .init = pci_quatech_init, 2199 .setup = pci_quatech_setup, 2200 .exit = pci_quatech_exit, 2201 }, 2202 /* 2203 * Panacom 2204 */ 2205 { 2206 .vendor = PCI_VENDOR_ID_PANACOM, 2207 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2208 .subvendor = PCI_ANY_ID, 2209 .subdevice = PCI_ANY_ID, 2210 .init = pci_plx9050_init, 2211 .setup = pci_default_setup, 2212 .exit = pci_plx9050_exit, 2213 }, 2214 { 2215 .vendor = PCI_VENDOR_ID_PANACOM, 2216 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2217 .subvendor = PCI_ANY_ID, 2218 .subdevice = PCI_ANY_ID, 2219 .init = pci_plx9050_init, 2220 .setup = pci_default_setup, 2221 .exit = pci_plx9050_exit, 2222 }, 2223 /* 2224 * Pericom (Only 7954 - It have a offset jump for port 4) 2225 */ 2226 { 2227 .vendor = PCI_VENDOR_ID_PERICOM, 2228 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 2229 .subvendor = PCI_ANY_ID, 2230 .subdevice = PCI_ANY_ID, 2231 .setup = pci_pericom_setup_four_at_eight, 2232 }, 2233 /* 2234 * PLX 2235 */ 2236 { 2237 .vendor = PCI_VENDOR_ID_PLX, 2238 .device = PCI_DEVICE_ID_PLX_9050, 2239 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2240 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2241 .init = pci_plx9050_init, 2242 .setup = pci_default_setup, 2243 .exit = pci_plx9050_exit, 2244 }, 2245 { 2246 .vendor = PCI_VENDOR_ID_PLX, 2247 .device = PCI_DEVICE_ID_PLX_9050, 2248 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2249 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2250 .init = pci_plx9050_init, 2251 .setup = pci_default_setup, 2252 .exit = pci_plx9050_exit, 2253 }, 2254 { 2255 .vendor = PCI_VENDOR_ID_PLX, 2256 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2257 .subvendor = PCI_VENDOR_ID_PLX, 2258 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2259 .init = pci_plx9050_init, 2260 .setup = pci_default_setup, 2261 .exit = pci_plx9050_exit, 2262 }, 2263 { 2264 .vendor = PCI_VENDOR_ID_ACCESIO, 2265 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 2266 .subvendor = PCI_ANY_ID, 2267 .subdevice = PCI_ANY_ID, 2268 .setup = pci_pericom_setup_four_at_eight, 2269 }, 2270 { 2271 .vendor = PCI_VENDOR_ID_ACCESIO, 2272 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 2273 .subvendor = PCI_ANY_ID, 2274 .subdevice = PCI_ANY_ID, 2275 .setup = pci_pericom_setup_four_at_eight, 2276 }, 2277 { 2278 .vendor = PCI_VENDOR_ID_ACCESIO, 2279 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .setup = pci_pericom_setup_four_at_eight, 2283 }, 2284 { 2285 .vendor = PCI_VENDOR_ID_ACCESIO, 2286 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 2287 .subvendor = PCI_ANY_ID, 2288 .subdevice = PCI_ANY_ID, 2289 .setup = pci_pericom_setup_four_at_eight, 2290 }, 2291 { 2292 .vendor = PCI_VENDOR_ID_ACCESIO, 2293 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 2294 .subvendor = PCI_ANY_ID, 2295 .subdevice = PCI_ANY_ID, 2296 .setup = pci_pericom_setup_four_at_eight, 2297 }, 2298 { 2299 .vendor = PCI_VENDOR_ID_ACCESIO, 2300 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 2301 .subvendor = PCI_ANY_ID, 2302 .subdevice = PCI_ANY_ID, 2303 .setup = pci_pericom_setup_four_at_eight, 2304 }, 2305 { 2306 .vendor = PCI_VENDOR_ID_ACCESIO, 2307 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 2308 .subvendor = PCI_ANY_ID, 2309 .subdevice = PCI_ANY_ID, 2310 .setup = pci_pericom_setup_four_at_eight, 2311 }, 2312 { 2313 .vendor = PCI_VENDOR_ID_ACCESIO, 2314 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 2315 .subvendor = PCI_ANY_ID, 2316 .subdevice = PCI_ANY_ID, 2317 .setup = pci_pericom_setup_four_at_eight, 2318 }, 2319 { 2320 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 2321 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 2322 .subvendor = PCI_ANY_ID, 2323 .subdevice = PCI_ANY_ID, 2324 .setup = pci_pericom_setup_four_at_eight, 2325 }, 2326 { 2327 .vendor = PCI_VENDOR_ID_ACCESIO, 2328 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 2329 .subvendor = PCI_ANY_ID, 2330 .subdevice = PCI_ANY_ID, 2331 .setup = pci_pericom_setup_four_at_eight, 2332 }, 2333 { 2334 .vendor = PCI_VENDOR_ID_ACCESIO, 2335 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 2336 .subvendor = PCI_ANY_ID, 2337 .subdevice = PCI_ANY_ID, 2338 .setup = pci_pericom_setup_four_at_eight, 2339 }, 2340 { 2341 .vendor = PCI_VENDOR_ID_ACCESIO, 2342 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 2343 .subvendor = PCI_ANY_ID, 2344 .subdevice = PCI_ANY_ID, 2345 .setup = pci_pericom_setup_four_at_eight, 2346 }, 2347 { 2348 .vendor = PCI_VENDOR_ID_ACCESIO, 2349 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 2350 .subvendor = PCI_ANY_ID, 2351 .subdevice = PCI_ANY_ID, 2352 .setup = pci_pericom_setup_four_at_eight, 2353 }, 2354 { 2355 .vendor = PCI_VENDOR_ID_ACCESIO, 2356 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 2357 .subvendor = PCI_ANY_ID, 2358 .subdevice = PCI_ANY_ID, 2359 .setup = pci_pericom_setup_four_at_eight, 2360 }, 2361 { 2362 .vendor = PCI_VENDOR_ID_ACCESIO, 2363 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 2364 .subvendor = PCI_ANY_ID, 2365 .subdevice = PCI_ANY_ID, 2366 .setup = pci_pericom_setup_four_at_eight, 2367 }, 2368 { 2369 .vendor = PCI_VENDOR_ID_ACCESIO, 2370 .device = PCI_ANY_ID, 2371 .subvendor = PCI_ANY_ID, 2372 .subdevice = PCI_ANY_ID, 2373 .setup = pci_pericom_setup, 2374 }, /* 2375 * SBS Technologies, Inc., PMC-OCTALPRO 232 2376 */ 2377 { 2378 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2379 .device = PCI_DEVICE_ID_OCTPRO, 2380 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2381 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2382 .init = sbs_init, 2383 .setup = sbs_setup, 2384 .exit = sbs_exit, 2385 }, 2386 /* 2387 * SBS Technologies, Inc., PMC-OCTALPRO 422 2388 */ 2389 { 2390 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2391 .device = PCI_DEVICE_ID_OCTPRO, 2392 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2393 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2394 .init = sbs_init, 2395 .setup = sbs_setup, 2396 .exit = sbs_exit, 2397 }, 2398 /* 2399 * SBS Technologies, Inc., P-Octal 232 2400 */ 2401 { 2402 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2403 .device = PCI_DEVICE_ID_OCTPRO, 2404 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2405 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2406 .init = sbs_init, 2407 .setup = sbs_setup, 2408 .exit = sbs_exit, 2409 }, 2410 /* 2411 * SBS Technologies, Inc., P-Octal 422 2412 */ 2413 { 2414 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2415 .device = PCI_DEVICE_ID_OCTPRO, 2416 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2417 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2418 .init = sbs_init, 2419 .setup = sbs_setup, 2420 .exit = sbs_exit, 2421 }, 2422 /* 2423 * SIIG cards - these may be called via parport_serial 2424 */ 2425 { 2426 .vendor = PCI_VENDOR_ID_SIIG, 2427 .device = PCI_ANY_ID, 2428 .subvendor = PCI_ANY_ID, 2429 .subdevice = PCI_ANY_ID, 2430 .init = pci_siig_init, 2431 .setup = pci_siig_setup, 2432 }, 2433 /* 2434 * Titan cards 2435 */ 2436 { 2437 .vendor = PCI_VENDOR_ID_TITAN, 2438 .device = PCI_DEVICE_ID_TITAN_400L, 2439 .subvendor = PCI_ANY_ID, 2440 .subdevice = PCI_ANY_ID, 2441 .setup = titan_400l_800l_setup, 2442 }, 2443 { 2444 .vendor = PCI_VENDOR_ID_TITAN, 2445 .device = PCI_DEVICE_ID_TITAN_800L, 2446 .subvendor = PCI_ANY_ID, 2447 .subdevice = PCI_ANY_ID, 2448 .setup = titan_400l_800l_setup, 2449 }, 2450 /* 2451 * Timedia cards 2452 */ 2453 { 2454 .vendor = PCI_VENDOR_ID_TIMEDIA, 2455 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2456 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2457 .subdevice = PCI_ANY_ID, 2458 .probe = pci_timedia_probe, 2459 .init = pci_timedia_init, 2460 .setup = pci_timedia_setup, 2461 }, 2462 { 2463 .vendor = PCI_VENDOR_ID_TIMEDIA, 2464 .device = PCI_ANY_ID, 2465 .subvendor = PCI_ANY_ID, 2466 .subdevice = PCI_ANY_ID, 2467 .setup = pci_timedia_setup, 2468 }, 2469 /* 2470 * Sunix PCI serial boards 2471 */ 2472 { 2473 .vendor = PCI_VENDOR_ID_SUNIX, 2474 .device = PCI_DEVICE_ID_SUNIX_1999, 2475 .subvendor = PCI_VENDOR_ID_SUNIX, 2476 .subdevice = PCI_ANY_ID, 2477 .setup = pci_sunix_setup, 2478 }, 2479 /* 2480 * Xircom cards 2481 */ 2482 { 2483 .vendor = PCI_VENDOR_ID_XIRCOM, 2484 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2485 .subvendor = PCI_ANY_ID, 2486 .subdevice = PCI_ANY_ID, 2487 .init = pci_xircom_init, 2488 .setup = pci_default_setup, 2489 }, 2490 /* 2491 * Netmos cards - these may be called via parport_serial 2492 */ 2493 { 2494 .vendor = PCI_VENDOR_ID_NETMOS, 2495 .device = PCI_ANY_ID, 2496 .subvendor = PCI_ANY_ID, 2497 .subdevice = PCI_ANY_ID, 2498 .init = pci_netmos_init, 2499 .setup = pci_netmos_9900_setup, 2500 }, 2501 /* 2502 * EndRun Technologies 2503 */ 2504 { 2505 .vendor = PCI_VENDOR_ID_ENDRUN, 2506 .device = PCI_ANY_ID, 2507 .subvendor = PCI_ANY_ID, 2508 .subdevice = PCI_ANY_ID, 2509 .init = pci_endrun_init, 2510 .setup = pci_default_setup, 2511 }, 2512 /* 2513 * For Oxford Semiconductor Tornado based devices 2514 */ 2515 { 2516 .vendor = PCI_VENDOR_ID_OXSEMI, 2517 .device = PCI_ANY_ID, 2518 .subvendor = PCI_ANY_ID, 2519 .subdevice = PCI_ANY_ID, 2520 .init = pci_oxsemi_tornado_init, 2521 .setup = pci_default_setup, 2522 }, 2523 { 2524 .vendor = PCI_VENDOR_ID_MAINPINE, 2525 .device = PCI_ANY_ID, 2526 .subvendor = PCI_ANY_ID, 2527 .subdevice = PCI_ANY_ID, 2528 .init = pci_oxsemi_tornado_init, 2529 .setup = pci_default_setup, 2530 }, 2531 { 2532 .vendor = PCI_VENDOR_ID_DIGI, 2533 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2534 .subvendor = PCI_SUBVENDOR_ID_IBM, 2535 .subdevice = PCI_ANY_ID, 2536 .init = pci_oxsemi_tornado_init, 2537 .setup = pci_default_setup, 2538 }, 2539 { 2540 .vendor = PCI_VENDOR_ID_INTEL, 2541 .device = 0x8811, 2542 .subvendor = PCI_ANY_ID, 2543 .subdevice = PCI_ANY_ID, 2544 .init = pci_eg20t_init, 2545 .setup = pci_default_setup, 2546 }, 2547 { 2548 .vendor = PCI_VENDOR_ID_INTEL, 2549 .device = 0x8812, 2550 .subvendor = PCI_ANY_ID, 2551 .subdevice = PCI_ANY_ID, 2552 .init = pci_eg20t_init, 2553 .setup = pci_default_setup, 2554 }, 2555 { 2556 .vendor = PCI_VENDOR_ID_INTEL, 2557 .device = 0x8813, 2558 .subvendor = PCI_ANY_ID, 2559 .subdevice = PCI_ANY_ID, 2560 .init = pci_eg20t_init, 2561 .setup = pci_default_setup, 2562 }, 2563 { 2564 .vendor = PCI_VENDOR_ID_INTEL, 2565 .device = 0x8814, 2566 .subvendor = PCI_ANY_ID, 2567 .subdevice = PCI_ANY_ID, 2568 .init = pci_eg20t_init, 2569 .setup = pci_default_setup, 2570 }, 2571 { 2572 .vendor = 0x10DB, 2573 .device = 0x8027, 2574 .subvendor = PCI_ANY_ID, 2575 .subdevice = PCI_ANY_ID, 2576 .init = pci_eg20t_init, 2577 .setup = pci_default_setup, 2578 }, 2579 { 2580 .vendor = 0x10DB, 2581 .device = 0x8028, 2582 .subvendor = PCI_ANY_ID, 2583 .subdevice = PCI_ANY_ID, 2584 .init = pci_eg20t_init, 2585 .setup = pci_default_setup, 2586 }, 2587 { 2588 .vendor = 0x10DB, 2589 .device = 0x8029, 2590 .subvendor = PCI_ANY_ID, 2591 .subdevice = PCI_ANY_ID, 2592 .init = pci_eg20t_init, 2593 .setup = pci_default_setup, 2594 }, 2595 { 2596 .vendor = 0x10DB, 2597 .device = 0x800C, 2598 .subvendor = PCI_ANY_ID, 2599 .subdevice = PCI_ANY_ID, 2600 .init = pci_eg20t_init, 2601 .setup = pci_default_setup, 2602 }, 2603 { 2604 .vendor = 0x10DB, 2605 .device = 0x800D, 2606 .subvendor = PCI_ANY_ID, 2607 .subdevice = PCI_ANY_ID, 2608 .init = pci_eg20t_init, 2609 .setup = pci_default_setup, 2610 }, 2611 /* 2612 * Cronyx Omega PCI (PLX-chip based) 2613 */ 2614 { 2615 .vendor = PCI_VENDOR_ID_PLX, 2616 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2617 .subvendor = PCI_ANY_ID, 2618 .subdevice = PCI_ANY_ID, 2619 .setup = pci_omegapci_setup, 2620 }, 2621 /* WCH CH353 1S1P card (16550 clone) */ 2622 { 2623 .vendor = PCI_VENDOR_ID_WCH, 2624 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2625 .subvendor = PCI_ANY_ID, 2626 .subdevice = PCI_ANY_ID, 2627 .setup = pci_wch_ch353_setup, 2628 }, 2629 /* WCH CH353 2S1P card (16550 clone) */ 2630 { 2631 .vendor = PCI_VENDOR_ID_WCH, 2632 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2633 .subvendor = PCI_ANY_ID, 2634 .subdevice = PCI_ANY_ID, 2635 .setup = pci_wch_ch353_setup, 2636 }, 2637 /* WCH CH353 4S card (16550 clone) */ 2638 { 2639 .vendor = PCI_VENDOR_ID_WCH, 2640 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2641 .subvendor = PCI_ANY_ID, 2642 .subdevice = PCI_ANY_ID, 2643 .setup = pci_wch_ch353_setup, 2644 }, 2645 /* WCH CH353 2S1PF card (16550 clone) */ 2646 { 2647 .vendor = PCI_VENDOR_ID_WCH, 2648 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2649 .subvendor = PCI_ANY_ID, 2650 .subdevice = PCI_ANY_ID, 2651 .setup = pci_wch_ch353_setup, 2652 }, 2653 /* WCH CH352 2S card (16550 clone) */ 2654 { 2655 .vendor = PCI_VENDOR_ID_WCH, 2656 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2657 .subvendor = PCI_ANY_ID, 2658 .subdevice = PCI_ANY_ID, 2659 .setup = pci_wch_ch353_setup, 2660 }, 2661 /* WCH CH355 4S card (16550 clone) */ 2662 { 2663 .vendor = PCI_VENDOR_ID_WCH, 2664 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2665 .subvendor = PCI_ANY_ID, 2666 .subdevice = PCI_ANY_ID, 2667 .setup = pci_wch_ch355_setup, 2668 }, 2669 /* WCH CH382 2S card (16850 clone) */ 2670 { 2671 .vendor = PCIE_VENDOR_ID_WCH, 2672 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2673 .subvendor = PCI_ANY_ID, 2674 .subdevice = PCI_ANY_ID, 2675 .setup = pci_wch_ch38x_setup, 2676 }, 2677 /* WCH CH382 2S1P card (16850 clone) */ 2678 { 2679 .vendor = PCIE_VENDOR_ID_WCH, 2680 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2681 .subvendor = PCI_ANY_ID, 2682 .subdevice = PCI_ANY_ID, 2683 .setup = pci_wch_ch38x_setup, 2684 }, 2685 /* WCH CH384 4S card (16850 clone) */ 2686 { 2687 .vendor = PCIE_VENDOR_ID_WCH, 2688 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2689 .subvendor = PCI_ANY_ID, 2690 .subdevice = PCI_ANY_ID, 2691 .setup = pci_wch_ch38x_setup, 2692 }, 2693 /* WCH CH384 8S card (16850 clone) */ 2694 { 2695 .vendor = PCIE_VENDOR_ID_WCH, 2696 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2697 .subvendor = PCI_ANY_ID, 2698 .subdevice = PCI_ANY_ID, 2699 .init = pci_wch_ch38x_init, 2700 .exit = pci_wch_ch38x_exit, 2701 .setup = pci_wch_ch38x_setup, 2702 }, 2703 /* 2704 * ASIX devices with FIFO bug 2705 */ 2706 { 2707 .vendor = PCI_VENDOR_ID_ASIX, 2708 .device = PCI_ANY_ID, 2709 .subvendor = PCI_ANY_ID, 2710 .subdevice = PCI_ANY_ID, 2711 .setup = pci_asix_setup, 2712 }, 2713 /* 2714 * Broadcom TruManage (NetXtreme) 2715 */ 2716 { 2717 .vendor = PCI_VENDOR_ID_BROADCOM, 2718 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2719 .subvendor = PCI_ANY_ID, 2720 .subdevice = PCI_ANY_ID, 2721 .setup = pci_brcm_trumanage_setup, 2722 }, 2723 { 2724 .vendor = 0x1c29, 2725 .device = 0x1104, 2726 .subvendor = PCI_ANY_ID, 2727 .subdevice = PCI_ANY_ID, 2728 .setup = pci_fintek_setup, 2729 .init = pci_fintek_init, 2730 }, 2731 { 2732 .vendor = 0x1c29, 2733 .device = 0x1108, 2734 .subvendor = PCI_ANY_ID, 2735 .subdevice = PCI_ANY_ID, 2736 .setup = pci_fintek_setup, 2737 .init = pci_fintek_init, 2738 }, 2739 { 2740 .vendor = 0x1c29, 2741 .device = 0x1112, 2742 .subvendor = PCI_ANY_ID, 2743 .subdevice = PCI_ANY_ID, 2744 .setup = pci_fintek_setup, 2745 .init = pci_fintek_init, 2746 }, 2747 /* 2748 * MOXA 2749 */ 2750 { 2751 .vendor = PCI_VENDOR_ID_MOXA, 2752 .device = PCI_ANY_ID, 2753 .subvendor = PCI_ANY_ID, 2754 .subdevice = PCI_ANY_ID, 2755 .setup = pci_moxa_setup, 2756 }, 2757 { 2758 .vendor = 0x1c29, 2759 .device = 0x1204, 2760 .subvendor = PCI_ANY_ID, 2761 .subdevice = PCI_ANY_ID, 2762 .setup = pci_fintek_f815xxa_setup, 2763 .init = pci_fintek_f815xxa_init, 2764 }, 2765 { 2766 .vendor = 0x1c29, 2767 .device = 0x1208, 2768 .subvendor = PCI_ANY_ID, 2769 .subdevice = PCI_ANY_ID, 2770 .setup = pci_fintek_f815xxa_setup, 2771 .init = pci_fintek_f815xxa_init, 2772 }, 2773 { 2774 .vendor = 0x1c29, 2775 .device = 0x1212, 2776 .subvendor = PCI_ANY_ID, 2777 .subdevice = PCI_ANY_ID, 2778 .setup = pci_fintek_f815xxa_setup, 2779 .init = pci_fintek_f815xxa_init, 2780 }, 2781 2782 /* 2783 * Default "match everything" terminator entry 2784 */ 2785 { 2786 .vendor = PCI_ANY_ID, 2787 .device = PCI_ANY_ID, 2788 .subvendor = PCI_ANY_ID, 2789 .subdevice = PCI_ANY_ID, 2790 .setup = pci_default_setup, 2791 } 2792 }; 2793 2794 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2795 { 2796 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2797 } 2798 2799 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2800 { 2801 struct pci_serial_quirk *quirk; 2802 2803 for (quirk = pci_serial_quirks; ; quirk++) 2804 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2805 quirk_id_matches(quirk->device, dev->device) && 2806 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2807 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2808 break; 2809 return quirk; 2810 } 2811 2812 /* 2813 * This is the configuration table for all of the PCI serial boards 2814 * which we support. It is directly indexed by the pci_board_num_t enum 2815 * value, which is encoded in the pci_device_id PCI probe table's 2816 * driver_data member. 2817 * 2818 * The makeup of these names are: 2819 * pbn_bn{_bt}_n_baud{_offsetinhex} 2820 * 2821 * bn = PCI BAR number 2822 * bt = Index using PCI BARs 2823 * n = number of serial ports 2824 * baud = baud rate 2825 * offsetinhex = offset for each sequential port (in hex) 2826 * 2827 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2828 * 2829 * Please note: in theory if n = 1, _bt infix should make no difference. 2830 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2831 */ 2832 enum pci_board_num_t { 2833 pbn_default = 0, 2834 2835 pbn_b0_1_115200, 2836 pbn_b0_2_115200, 2837 pbn_b0_4_115200, 2838 pbn_b0_5_115200, 2839 pbn_b0_8_115200, 2840 2841 pbn_b0_1_921600, 2842 pbn_b0_2_921600, 2843 pbn_b0_4_921600, 2844 2845 pbn_b0_2_1130000, 2846 2847 pbn_b0_4_1152000, 2848 2849 pbn_b0_4_1250000, 2850 2851 pbn_b0_2_1843200, 2852 pbn_b0_4_1843200, 2853 2854 pbn_b0_1_4000000, 2855 2856 pbn_b0_bt_1_115200, 2857 pbn_b0_bt_2_115200, 2858 pbn_b0_bt_4_115200, 2859 pbn_b0_bt_8_115200, 2860 2861 pbn_b0_bt_1_460800, 2862 pbn_b0_bt_2_460800, 2863 pbn_b0_bt_4_460800, 2864 2865 pbn_b0_bt_1_921600, 2866 pbn_b0_bt_2_921600, 2867 pbn_b0_bt_4_921600, 2868 pbn_b0_bt_8_921600, 2869 2870 pbn_b1_1_115200, 2871 pbn_b1_2_115200, 2872 pbn_b1_4_115200, 2873 pbn_b1_8_115200, 2874 pbn_b1_16_115200, 2875 2876 pbn_b1_1_921600, 2877 pbn_b1_2_921600, 2878 pbn_b1_4_921600, 2879 pbn_b1_8_921600, 2880 2881 pbn_b1_2_1250000, 2882 2883 pbn_b1_bt_1_115200, 2884 pbn_b1_bt_2_115200, 2885 pbn_b1_bt_4_115200, 2886 2887 pbn_b1_bt_2_921600, 2888 2889 pbn_b1_1_1382400, 2890 pbn_b1_2_1382400, 2891 pbn_b1_4_1382400, 2892 pbn_b1_8_1382400, 2893 2894 pbn_b2_1_115200, 2895 pbn_b2_2_115200, 2896 pbn_b2_4_115200, 2897 pbn_b2_8_115200, 2898 2899 pbn_b2_1_460800, 2900 pbn_b2_4_460800, 2901 pbn_b2_8_460800, 2902 pbn_b2_16_460800, 2903 2904 pbn_b2_1_921600, 2905 pbn_b2_4_921600, 2906 pbn_b2_8_921600, 2907 2908 pbn_b2_8_1152000, 2909 2910 pbn_b2_bt_1_115200, 2911 pbn_b2_bt_2_115200, 2912 pbn_b2_bt_4_115200, 2913 2914 pbn_b2_bt_2_921600, 2915 pbn_b2_bt_4_921600, 2916 2917 pbn_b3_2_115200, 2918 pbn_b3_4_115200, 2919 pbn_b3_8_115200, 2920 2921 pbn_b4_bt_2_921600, 2922 pbn_b4_bt_4_921600, 2923 pbn_b4_bt_8_921600, 2924 2925 /* 2926 * Board-specific versions. 2927 */ 2928 pbn_panacom, 2929 pbn_panacom2, 2930 pbn_panacom4, 2931 pbn_plx_romulus, 2932 pbn_endrun_2_4000000, 2933 pbn_oxsemi, 2934 pbn_oxsemi_1_4000000, 2935 pbn_oxsemi_2_4000000, 2936 pbn_oxsemi_4_4000000, 2937 pbn_oxsemi_8_4000000, 2938 pbn_intel_i960, 2939 pbn_sgi_ioc3, 2940 pbn_computone_4, 2941 pbn_computone_6, 2942 pbn_computone_8, 2943 pbn_sbsxrsio, 2944 pbn_pasemi_1682M, 2945 pbn_ni8430_2, 2946 pbn_ni8430_4, 2947 pbn_ni8430_8, 2948 pbn_ni8430_16, 2949 pbn_ADDIDATA_PCIe_1_3906250, 2950 pbn_ADDIDATA_PCIe_2_3906250, 2951 pbn_ADDIDATA_PCIe_4_3906250, 2952 pbn_ADDIDATA_PCIe_8_3906250, 2953 pbn_ce4100_1_115200, 2954 pbn_omegapci, 2955 pbn_NETMOS9900_2s_115200, 2956 pbn_brcm_trumanage, 2957 pbn_fintek_4, 2958 pbn_fintek_8, 2959 pbn_fintek_12, 2960 pbn_fintek_F81504A, 2961 pbn_fintek_F81508A, 2962 pbn_fintek_F81512A, 2963 pbn_wch382_2, 2964 pbn_wch384_4, 2965 pbn_wch384_8, 2966 pbn_pericom_PI7C9X7951, 2967 pbn_pericom_PI7C9X7952, 2968 pbn_pericom_PI7C9X7954, 2969 pbn_pericom_PI7C9X7958, 2970 pbn_sunix_pci_1s, 2971 pbn_sunix_pci_2s, 2972 pbn_sunix_pci_4s, 2973 pbn_sunix_pci_8s, 2974 pbn_sunix_pci_16s, 2975 pbn_moxa8250_2p, 2976 pbn_moxa8250_4p, 2977 pbn_moxa8250_8p, 2978 }; 2979 2980 /* 2981 * uart_offset - the space between channels 2982 * reg_shift - describes how the UART registers are mapped 2983 * to PCI memory by the card. 2984 * For example IER register on SBS, Inc. PMC-OctPro is located at 2985 * offset 0x10 from the UART base, while UART_IER is defined as 1 2986 * in include/linux/serial_reg.h, 2987 * see first lines of serial_in() and serial_out() in 8250.c 2988 */ 2989 2990 static struct pciserial_board pci_boards[] = { 2991 [pbn_default] = { 2992 .flags = FL_BASE0, 2993 .num_ports = 1, 2994 .base_baud = 115200, 2995 .uart_offset = 8, 2996 }, 2997 [pbn_b0_1_115200] = { 2998 .flags = FL_BASE0, 2999 .num_ports = 1, 3000 .base_baud = 115200, 3001 .uart_offset = 8, 3002 }, 3003 [pbn_b0_2_115200] = { 3004 .flags = FL_BASE0, 3005 .num_ports = 2, 3006 .base_baud = 115200, 3007 .uart_offset = 8, 3008 }, 3009 [pbn_b0_4_115200] = { 3010 .flags = FL_BASE0, 3011 .num_ports = 4, 3012 .base_baud = 115200, 3013 .uart_offset = 8, 3014 }, 3015 [pbn_b0_5_115200] = { 3016 .flags = FL_BASE0, 3017 .num_ports = 5, 3018 .base_baud = 115200, 3019 .uart_offset = 8, 3020 }, 3021 [pbn_b0_8_115200] = { 3022 .flags = FL_BASE0, 3023 .num_ports = 8, 3024 .base_baud = 115200, 3025 .uart_offset = 8, 3026 }, 3027 [pbn_b0_1_921600] = { 3028 .flags = FL_BASE0, 3029 .num_ports = 1, 3030 .base_baud = 921600, 3031 .uart_offset = 8, 3032 }, 3033 [pbn_b0_2_921600] = { 3034 .flags = FL_BASE0, 3035 .num_ports = 2, 3036 .base_baud = 921600, 3037 .uart_offset = 8, 3038 }, 3039 [pbn_b0_4_921600] = { 3040 .flags = FL_BASE0, 3041 .num_ports = 4, 3042 .base_baud = 921600, 3043 .uart_offset = 8, 3044 }, 3045 3046 [pbn_b0_2_1130000] = { 3047 .flags = FL_BASE0, 3048 .num_ports = 2, 3049 .base_baud = 1130000, 3050 .uart_offset = 8, 3051 }, 3052 3053 [pbn_b0_4_1152000] = { 3054 .flags = FL_BASE0, 3055 .num_ports = 4, 3056 .base_baud = 1152000, 3057 .uart_offset = 8, 3058 }, 3059 3060 [pbn_b0_4_1250000] = { 3061 .flags = FL_BASE0, 3062 .num_ports = 4, 3063 .base_baud = 1250000, 3064 .uart_offset = 8, 3065 }, 3066 3067 [pbn_b0_2_1843200] = { 3068 .flags = FL_BASE0, 3069 .num_ports = 2, 3070 .base_baud = 1843200, 3071 .uart_offset = 8, 3072 }, 3073 [pbn_b0_4_1843200] = { 3074 .flags = FL_BASE0, 3075 .num_ports = 4, 3076 .base_baud = 1843200, 3077 .uart_offset = 8, 3078 }, 3079 3080 [pbn_b0_1_4000000] = { 3081 .flags = FL_BASE0, 3082 .num_ports = 1, 3083 .base_baud = 4000000, 3084 .uart_offset = 8, 3085 }, 3086 3087 [pbn_b0_bt_1_115200] = { 3088 .flags = FL_BASE0|FL_BASE_BARS, 3089 .num_ports = 1, 3090 .base_baud = 115200, 3091 .uart_offset = 8, 3092 }, 3093 [pbn_b0_bt_2_115200] = { 3094 .flags = FL_BASE0|FL_BASE_BARS, 3095 .num_ports = 2, 3096 .base_baud = 115200, 3097 .uart_offset = 8, 3098 }, 3099 [pbn_b0_bt_4_115200] = { 3100 .flags = FL_BASE0|FL_BASE_BARS, 3101 .num_ports = 4, 3102 .base_baud = 115200, 3103 .uart_offset = 8, 3104 }, 3105 [pbn_b0_bt_8_115200] = { 3106 .flags = FL_BASE0|FL_BASE_BARS, 3107 .num_ports = 8, 3108 .base_baud = 115200, 3109 .uart_offset = 8, 3110 }, 3111 3112 [pbn_b0_bt_1_460800] = { 3113 .flags = FL_BASE0|FL_BASE_BARS, 3114 .num_ports = 1, 3115 .base_baud = 460800, 3116 .uart_offset = 8, 3117 }, 3118 [pbn_b0_bt_2_460800] = { 3119 .flags = FL_BASE0|FL_BASE_BARS, 3120 .num_ports = 2, 3121 .base_baud = 460800, 3122 .uart_offset = 8, 3123 }, 3124 [pbn_b0_bt_4_460800] = { 3125 .flags = FL_BASE0|FL_BASE_BARS, 3126 .num_ports = 4, 3127 .base_baud = 460800, 3128 .uart_offset = 8, 3129 }, 3130 3131 [pbn_b0_bt_1_921600] = { 3132 .flags = FL_BASE0|FL_BASE_BARS, 3133 .num_ports = 1, 3134 .base_baud = 921600, 3135 .uart_offset = 8, 3136 }, 3137 [pbn_b0_bt_2_921600] = { 3138 .flags = FL_BASE0|FL_BASE_BARS, 3139 .num_ports = 2, 3140 .base_baud = 921600, 3141 .uart_offset = 8, 3142 }, 3143 [pbn_b0_bt_4_921600] = { 3144 .flags = FL_BASE0|FL_BASE_BARS, 3145 .num_ports = 4, 3146 .base_baud = 921600, 3147 .uart_offset = 8, 3148 }, 3149 [pbn_b0_bt_8_921600] = { 3150 .flags = FL_BASE0|FL_BASE_BARS, 3151 .num_ports = 8, 3152 .base_baud = 921600, 3153 .uart_offset = 8, 3154 }, 3155 3156 [pbn_b1_1_115200] = { 3157 .flags = FL_BASE1, 3158 .num_ports = 1, 3159 .base_baud = 115200, 3160 .uart_offset = 8, 3161 }, 3162 [pbn_b1_2_115200] = { 3163 .flags = FL_BASE1, 3164 .num_ports = 2, 3165 .base_baud = 115200, 3166 .uart_offset = 8, 3167 }, 3168 [pbn_b1_4_115200] = { 3169 .flags = FL_BASE1, 3170 .num_ports = 4, 3171 .base_baud = 115200, 3172 .uart_offset = 8, 3173 }, 3174 [pbn_b1_8_115200] = { 3175 .flags = FL_BASE1, 3176 .num_ports = 8, 3177 .base_baud = 115200, 3178 .uart_offset = 8, 3179 }, 3180 [pbn_b1_16_115200] = { 3181 .flags = FL_BASE1, 3182 .num_ports = 16, 3183 .base_baud = 115200, 3184 .uart_offset = 8, 3185 }, 3186 3187 [pbn_b1_1_921600] = { 3188 .flags = FL_BASE1, 3189 .num_ports = 1, 3190 .base_baud = 921600, 3191 .uart_offset = 8, 3192 }, 3193 [pbn_b1_2_921600] = { 3194 .flags = FL_BASE1, 3195 .num_ports = 2, 3196 .base_baud = 921600, 3197 .uart_offset = 8, 3198 }, 3199 [pbn_b1_4_921600] = { 3200 .flags = FL_BASE1, 3201 .num_ports = 4, 3202 .base_baud = 921600, 3203 .uart_offset = 8, 3204 }, 3205 [pbn_b1_8_921600] = { 3206 .flags = FL_BASE1, 3207 .num_ports = 8, 3208 .base_baud = 921600, 3209 .uart_offset = 8, 3210 }, 3211 [pbn_b1_2_1250000] = { 3212 .flags = FL_BASE1, 3213 .num_ports = 2, 3214 .base_baud = 1250000, 3215 .uart_offset = 8, 3216 }, 3217 3218 [pbn_b1_bt_1_115200] = { 3219 .flags = FL_BASE1|FL_BASE_BARS, 3220 .num_ports = 1, 3221 .base_baud = 115200, 3222 .uart_offset = 8, 3223 }, 3224 [pbn_b1_bt_2_115200] = { 3225 .flags = FL_BASE1|FL_BASE_BARS, 3226 .num_ports = 2, 3227 .base_baud = 115200, 3228 .uart_offset = 8, 3229 }, 3230 [pbn_b1_bt_4_115200] = { 3231 .flags = FL_BASE1|FL_BASE_BARS, 3232 .num_ports = 4, 3233 .base_baud = 115200, 3234 .uart_offset = 8, 3235 }, 3236 3237 [pbn_b1_bt_2_921600] = { 3238 .flags = FL_BASE1|FL_BASE_BARS, 3239 .num_ports = 2, 3240 .base_baud = 921600, 3241 .uart_offset = 8, 3242 }, 3243 3244 [pbn_b1_1_1382400] = { 3245 .flags = FL_BASE1, 3246 .num_ports = 1, 3247 .base_baud = 1382400, 3248 .uart_offset = 8, 3249 }, 3250 [pbn_b1_2_1382400] = { 3251 .flags = FL_BASE1, 3252 .num_ports = 2, 3253 .base_baud = 1382400, 3254 .uart_offset = 8, 3255 }, 3256 [pbn_b1_4_1382400] = { 3257 .flags = FL_BASE1, 3258 .num_ports = 4, 3259 .base_baud = 1382400, 3260 .uart_offset = 8, 3261 }, 3262 [pbn_b1_8_1382400] = { 3263 .flags = FL_BASE1, 3264 .num_ports = 8, 3265 .base_baud = 1382400, 3266 .uart_offset = 8, 3267 }, 3268 3269 [pbn_b2_1_115200] = { 3270 .flags = FL_BASE2, 3271 .num_ports = 1, 3272 .base_baud = 115200, 3273 .uart_offset = 8, 3274 }, 3275 [pbn_b2_2_115200] = { 3276 .flags = FL_BASE2, 3277 .num_ports = 2, 3278 .base_baud = 115200, 3279 .uart_offset = 8, 3280 }, 3281 [pbn_b2_4_115200] = { 3282 .flags = FL_BASE2, 3283 .num_ports = 4, 3284 .base_baud = 115200, 3285 .uart_offset = 8, 3286 }, 3287 [pbn_b2_8_115200] = { 3288 .flags = FL_BASE2, 3289 .num_ports = 8, 3290 .base_baud = 115200, 3291 .uart_offset = 8, 3292 }, 3293 3294 [pbn_b2_1_460800] = { 3295 .flags = FL_BASE2, 3296 .num_ports = 1, 3297 .base_baud = 460800, 3298 .uart_offset = 8, 3299 }, 3300 [pbn_b2_4_460800] = { 3301 .flags = FL_BASE2, 3302 .num_ports = 4, 3303 .base_baud = 460800, 3304 .uart_offset = 8, 3305 }, 3306 [pbn_b2_8_460800] = { 3307 .flags = FL_BASE2, 3308 .num_ports = 8, 3309 .base_baud = 460800, 3310 .uart_offset = 8, 3311 }, 3312 [pbn_b2_16_460800] = { 3313 .flags = FL_BASE2, 3314 .num_ports = 16, 3315 .base_baud = 460800, 3316 .uart_offset = 8, 3317 }, 3318 3319 [pbn_b2_1_921600] = { 3320 .flags = FL_BASE2, 3321 .num_ports = 1, 3322 .base_baud = 921600, 3323 .uart_offset = 8, 3324 }, 3325 [pbn_b2_4_921600] = { 3326 .flags = FL_BASE2, 3327 .num_ports = 4, 3328 .base_baud = 921600, 3329 .uart_offset = 8, 3330 }, 3331 [pbn_b2_8_921600] = { 3332 .flags = FL_BASE2, 3333 .num_ports = 8, 3334 .base_baud = 921600, 3335 .uart_offset = 8, 3336 }, 3337 3338 [pbn_b2_8_1152000] = { 3339 .flags = FL_BASE2, 3340 .num_ports = 8, 3341 .base_baud = 1152000, 3342 .uart_offset = 8, 3343 }, 3344 3345 [pbn_b2_bt_1_115200] = { 3346 .flags = FL_BASE2|FL_BASE_BARS, 3347 .num_ports = 1, 3348 .base_baud = 115200, 3349 .uart_offset = 8, 3350 }, 3351 [pbn_b2_bt_2_115200] = { 3352 .flags = FL_BASE2|FL_BASE_BARS, 3353 .num_ports = 2, 3354 .base_baud = 115200, 3355 .uart_offset = 8, 3356 }, 3357 [pbn_b2_bt_4_115200] = { 3358 .flags = FL_BASE2|FL_BASE_BARS, 3359 .num_ports = 4, 3360 .base_baud = 115200, 3361 .uart_offset = 8, 3362 }, 3363 3364 [pbn_b2_bt_2_921600] = { 3365 .flags = FL_BASE2|FL_BASE_BARS, 3366 .num_ports = 2, 3367 .base_baud = 921600, 3368 .uart_offset = 8, 3369 }, 3370 [pbn_b2_bt_4_921600] = { 3371 .flags = FL_BASE2|FL_BASE_BARS, 3372 .num_ports = 4, 3373 .base_baud = 921600, 3374 .uart_offset = 8, 3375 }, 3376 3377 [pbn_b3_2_115200] = { 3378 .flags = FL_BASE3, 3379 .num_ports = 2, 3380 .base_baud = 115200, 3381 .uart_offset = 8, 3382 }, 3383 [pbn_b3_4_115200] = { 3384 .flags = FL_BASE3, 3385 .num_ports = 4, 3386 .base_baud = 115200, 3387 .uart_offset = 8, 3388 }, 3389 [pbn_b3_8_115200] = { 3390 .flags = FL_BASE3, 3391 .num_ports = 8, 3392 .base_baud = 115200, 3393 .uart_offset = 8, 3394 }, 3395 3396 [pbn_b4_bt_2_921600] = { 3397 .flags = FL_BASE4, 3398 .num_ports = 2, 3399 .base_baud = 921600, 3400 .uart_offset = 8, 3401 }, 3402 [pbn_b4_bt_4_921600] = { 3403 .flags = FL_BASE4, 3404 .num_ports = 4, 3405 .base_baud = 921600, 3406 .uart_offset = 8, 3407 }, 3408 [pbn_b4_bt_8_921600] = { 3409 .flags = FL_BASE4, 3410 .num_ports = 8, 3411 .base_baud = 921600, 3412 .uart_offset = 8, 3413 }, 3414 3415 /* 3416 * Entries following this are board-specific. 3417 */ 3418 3419 /* 3420 * Panacom - IOMEM 3421 */ 3422 [pbn_panacom] = { 3423 .flags = FL_BASE2, 3424 .num_ports = 2, 3425 .base_baud = 921600, 3426 .uart_offset = 0x400, 3427 .reg_shift = 7, 3428 }, 3429 [pbn_panacom2] = { 3430 .flags = FL_BASE2|FL_BASE_BARS, 3431 .num_ports = 2, 3432 .base_baud = 921600, 3433 .uart_offset = 0x400, 3434 .reg_shift = 7, 3435 }, 3436 [pbn_panacom4] = { 3437 .flags = FL_BASE2|FL_BASE_BARS, 3438 .num_ports = 4, 3439 .base_baud = 921600, 3440 .uart_offset = 0x400, 3441 .reg_shift = 7, 3442 }, 3443 3444 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3445 [pbn_plx_romulus] = { 3446 .flags = FL_BASE2, 3447 .num_ports = 4, 3448 .base_baud = 921600, 3449 .uart_offset = 8 << 2, 3450 .reg_shift = 2, 3451 .first_offset = 0x03, 3452 }, 3453 3454 /* 3455 * EndRun Technologies 3456 * Uses the size of PCI Base region 0 to 3457 * signal now many ports are available 3458 * 2 port 952 Uart support 3459 */ 3460 [pbn_endrun_2_4000000] = { 3461 .flags = FL_BASE0, 3462 .num_ports = 2, 3463 .base_baud = 4000000, 3464 .uart_offset = 0x200, 3465 .first_offset = 0x1000, 3466 }, 3467 3468 /* 3469 * This board uses the size of PCI Base region 0 to 3470 * signal now many ports are available 3471 */ 3472 [pbn_oxsemi] = { 3473 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3474 .num_ports = 32, 3475 .base_baud = 115200, 3476 .uart_offset = 8, 3477 }, 3478 [pbn_oxsemi_1_4000000] = { 3479 .flags = FL_BASE0, 3480 .num_ports = 1, 3481 .base_baud = 4000000, 3482 .uart_offset = 0x200, 3483 .first_offset = 0x1000, 3484 }, 3485 [pbn_oxsemi_2_4000000] = { 3486 .flags = FL_BASE0, 3487 .num_ports = 2, 3488 .base_baud = 4000000, 3489 .uart_offset = 0x200, 3490 .first_offset = 0x1000, 3491 }, 3492 [pbn_oxsemi_4_4000000] = { 3493 .flags = FL_BASE0, 3494 .num_ports = 4, 3495 .base_baud = 4000000, 3496 .uart_offset = 0x200, 3497 .first_offset = 0x1000, 3498 }, 3499 [pbn_oxsemi_8_4000000] = { 3500 .flags = FL_BASE0, 3501 .num_ports = 8, 3502 .base_baud = 4000000, 3503 .uart_offset = 0x200, 3504 .first_offset = 0x1000, 3505 }, 3506 3507 3508 /* 3509 * EKF addition for i960 Boards form EKF with serial port. 3510 * Max 256 ports. 3511 */ 3512 [pbn_intel_i960] = { 3513 .flags = FL_BASE0, 3514 .num_ports = 32, 3515 .base_baud = 921600, 3516 .uart_offset = 8 << 2, 3517 .reg_shift = 2, 3518 .first_offset = 0x10000, 3519 }, 3520 [pbn_sgi_ioc3] = { 3521 .flags = FL_BASE0|FL_NOIRQ, 3522 .num_ports = 1, 3523 .base_baud = 458333, 3524 .uart_offset = 8, 3525 .reg_shift = 0, 3526 .first_offset = 0x20178, 3527 }, 3528 3529 /* 3530 * Computone - uses IOMEM. 3531 */ 3532 [pbn_computone_4] = { 3533 .flags = FL_BASE0, 3534 .num_ports = 4, 3535 .base_baud = 921600, 3536 .uart_offset = 0x40, 3537 .reg_shift = 2, 3538 .first_offset = 0x200, 3539 }, 3540 [pbn_computone_6] = { 3541 .flags = FL_BASE0, 3542 .num_ports = 6, 3543 .base_baud = 921600, 3544 .uart_offset = 0x40, 3545 .reg_shift = 2, 3546 .first_offset = 0x200, 3547 }, 3548 [pbn_computone_8] = { 3549 .flags = FL_BASE0, 3550 .num_ports = 8, 3551 .base_baud = 921600, 3552 .uart_offset = 0x40, 3553 .reg_shift = 2, 3554 .first_offset = 0x200, 3555 }, 3556 [pbn_sbsxrsio] = { 3557 .flags = FL_BASE0, 3558 .num_ports = 8, 3559 .base_baud = 460800, 3560 .uart_offset = 256, 3561 .reg_shift = 4, 3562 }, 3563 /* 3564 * PA Semi PWRficient PA6T-1682M on-chip UART 3565 */ 3566 [pbn_pasemi_1682M] = { 3567 .flags = FL_BASE0, 3568 .num_ports = 1, 3569 .base_baud = 8333333, 3570 }, 3571 /* 3572 * National Instruments 843x 3573 */ 3574 [pbn_ni8430_16] = { 3575 .flags = FL_BASE0, 3576 .num_ports = 16, 3577 .base_baud = 3686400, 3578 .uart_offset = 0x10, 3579 .first_offset = 0x800, 3580 }, 3581 [pbn_ni8430_8] = { 3582 .flags = FL_BASE0, 3583 .num_ports = 8, 3584 .base_baud = 3686400, 3585 .uart_offset = 0x10, 3586 .first_offset = 0x800, 3587 }, 3588 [pbn_ni8430_4] = { 3589 .flags = FL_BASE0, 3590 .num_ports = 4, 3591 .base_baud = 3686400, 3592 .uart_offset = 0x10, 3593 .first_offset = 0x800, 3594 }, 3595 [pbn_ni8430_2] = { 3596 .flags = FL_BASE0, 3597 .num_ports = 2, 3598 .base_baud = 3686400, 3599 .uart_offset = 0x10, 3600 .first_offset = 0x800, 3601 }, 3602 /* 3603 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3604 */ 3605 [pbn_ADDIDATA_PCIe_1_3906250] = { 3606 .flags = FL_BASE0, 3607 .num_ports = 1, 3608 .base_baud = 3906250, 3609 .uart_offset = 0x200, 3610 .first_offset = 0x1000, 3611 }, 3612 [pbn_ADDIDATA_PCIe_2_3906250] = { 3613 .flags = FL_BASE0, 3614 .num_ports = 2, 3615 .base_baud = 3906250, 3616 .uart_offset = 0x200, 3617 .first_offset = 0x1000, 3618 }, 3619 [pbn_ADDIDATA_PCIe_4_3906250] = { 3620 .flags = FL_BASE0, 3621 .num_ports = 4, 3622 .base_baud = 3906250, 3623 .uart_offset = 0x200, 3624 .first_offset = 0x1000, 3625 }, 3626 [pbn_ADDIDATA_PCIe_8_3906250] = { 3627 .flags = FL_BASE0, 3628 .num_ports = 8, 3629 .base_baud = 3906250, 3630 .uart_offset = 0x200, 3631 .first_offset = 0x1000, 3632 }, 3633 [pbn_ce4100_1_115200] = { 3634 .flags = FL_BASE_BARS, 3635 .num_ports = 2, 3636 .base_baud = 921600, 3637 .reg_shift = 2, 3638 }, 3639 [pbn_omegapci] = { 3640 .flags = FL_BASE0, 3641 .num_ports = 8, 3642 .base_baud = 115200, 3643 .uart_offset = 0x200, 3644 }, 3645 [pbn_NETMOS9900_2s_115200] = { 3646 .flags = FL_BASE0, 3647 .num_ports = 2, 3648 .base_baud = 115200, 3649 }, 3650 [pbn_brcm_trumanage] = { 3651 .flags = FL_BASE0, 3652 .num_ports = 1, 3653 .reg_shift = 2, 3654 .base_baud = 115200, 3655 }, 3656 [pbn_fintek_4] = { 3657 .num_ports = 4, 3658 .uart_offset = 8, 3659 .base_baud = 115200, 3660 .first_offset = 0x40, 3661 }, 3662 [pbn_fintek_8] = { 3663 .num_ports = 8, 3664 .uart_offset = 8, 3665 .base_baud = 115200, 3666 .first_offset = 0x40, 3667 }, 3668 [pbn_fintek_12] = { 3669 .num_ports = 12, 3670 .uart_offset = 8, 3671 .base_baud = 115200, 3672 .first_offset = 0x40, 3673 }, 3674 [pbn_fintek_F81504A] = { 3675 .num_ports = 4, 3676 .uart_offset = 8, 3677 .base_baud = 115200, 3678 }, 3679 [pbn_fintek_F81508A] = { 3680 .num_ports = 8, 3681 .uart_offset = 8, 3682 .base_baud = 115200, 3683 }, 3684 [pbn_fintek_F81512A] = { 3685 .num_ports = 12, 3686 .uart_offset = 8, 3687 .base_baud = 115200, 3688 }, 3689 [pbn_wch382_2] = { 3690 .flags = FL_BASE0, 3691 .num_ports = 2, 3692 .base_baud = 115200, 3693 .uart_offset = 8, 3694 .first_offset = 0xC0, 3695 }, 3696 [pbn_wch384_4] = { 3697 .flags = FL_BASE0, 3698 .num_ports = 4, 3699 .base_baud = 115200, 3700 .uart_offset = 8, 3701 .first_offset = 0xC0, 3702 }, 3703 [pbn_wch384_8] = { 3704 .flags = FL_BASE0, 3705 .num_ports = 8, 3706 .base_baud = 115200, 3707 .uart_offset = 8, 3708 .first_offset = 0x00, 3709 }, 3710 /* 3711 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3712 */ 3713 [pbn_pericom_PI7C9X7951] = { 3714 .flags = FL_BASE0, 3715 .num_ports = 1, 3716 .base_baud = 921600, 3717 .uart_offset = 0x8, 3718 }, 3719 [pbn_pericom_PI7C9X7952] = { 3720 .flags = FL_BASE0, 3721 .num_ports = 2, 3722 .base_baud = 921600, 3723 .uart_offset = 0x8, 3724 }, 3725 [pbn_pericom_PI7C9X7954] = { 3726 .flags = FL_BASE0, 3727 .num_ports = 4, 3728 .base_baud = 921600, 3729 .uart_offset = 0x8, 3730 }, 3731 [pbn_pericom_PI7C9X7958] = { 3732 .flags = FL_BASE0, 3733 .num_ports = 8, 3734 .base_baud = 921600, 3735 .uart_offset = 0x8, 3736 }, 3737 [pbn_sunix_pci_1s] = { 3738 .num_ports = 1, 3739 .base_baud = 921600, 3740 .uart_offset = 0x8, 3741 }, 3742 [pbn_sunix_pci_2s] = { 3743 .num_ports = 2, 3744 .base_baud = 921600, 3745 .uart_offset = 0x8, 3746 }, 3747 [pbn_sunix_pci_4s] = { 3748 .num_ports = 4, 3749 .base_baud = 921600, 3750 .uart_offset = 0x8, 3751 }, 3752 [pbn_sunix_pci_8s] = { 3753 .num_ports = 8, 3754 .base_baud = 921600, 3755 .uart_offset = 0x8, 3756 }, 3757 [pbn_sunix_pci_16s] = { 3758 .num_ports = 16, 3759 .base_baud = 921600, 3760 .uart_offset = 0x8, 3761 }, 3762 [pbn_moxa8250_2p] = { 3763 .flags = FL_BASE1, 3764 .num_ports = 2, 3765 .base_baud = 921600, 3766 .uart_offset = 0x200, 3767 }, 3768 [pbn_moxa8250_4p] = { 3769 .flags = FL_BASE1, 3770 .num_ports = 4, 3771 .base_baud = 921600, 3772 .uart_offset = 0x200, 3773 }, 3774 [pbn_moxa8250_8p] = { 3775 .flags = FL_BASE1, 3776 .num_ports = 8, 3777 .base_baud = 921600, 3778 .uart_offset = 0x200, 3779 }, 3780 }; 3781 3782 static const struct pci_device_id blacklist[] = { 3783 /* softmodems */ 3784 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3785 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3786 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3787 3788 /* multi-io cards handled by parport_serial */ 3789 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3790 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3791 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3792 3793 /* Intel platforms with MID UART */ 3794 { PCI_VDEVICE(INTEL, 0x081b), }, 3795 { PCI_VDEVICE(INTEL, 0x081c), }, 3796 { PCI_VDEVICE(INTEL, 0x081d), }, 3797 { PCI_VDEVICE(INTEL, 0x1191), }, 3798 { PCI_VDEVICE(INTEL, 0x18d8), }, 3799 { PCI_VDEVICE(INTEL, 0x19d8), }, 3800 3801 /* Intel platforms with DesignWare UART */ 3802 { PCI_VDEVICE(INTEL, 0x0936), }, 3803 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3804 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3805 { PCI_VDEVICE(INTEL, 0x228a), }, 3806 { PCI_VDEVICE(INTEL, 0x228c), }, 3807 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3808 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3809 3810 /* Exar devices */ 3811 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3812 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3813 3814 /* End of the black list */ 3815 { } 3816 }; 3817 3818 static int serial_pci_is_class_communication(struct pci_dev *dev) 3819 { 3820 /* 3821 * If it is not a communications device or the programming 3822 * interface is greater than 6, give up. 3823 */ 3824 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3825 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3826 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3827 (dev->class & 0xff) > 6) 3828 return -ENODEV; 3829 3830 return 0; 3831 } 3832 3833 /* 3834 * Given a complete unknown PCI device, try to use some heuristics to 3835 * guess what the configuration might be, based on the pitiful PCI 3836 * serial specs. Returns 0 on success, -ENODEV on failure. 3837 */ 3838 static int 3839 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3840 { 3841 int num_iomem, num_port, first_port = -1, i; 3842 int rc; 3843 3844 rc = serial_pci_is_class_communication(dev); 3845 if (rc) 3846 return rc; 3847 3848 /* 3849 * Should we try to make guesses for multiport serial devices later? 3850 */ 3851 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3852 return -ENODEV; 3853 3854 num_iomem = num_port = 0; 3855 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3856 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3857 num_port++; 3858 if (first_port == -1) 3859 first_port = i; 3860 } 3861 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3862 num_iomem++; 3863 } 3864 3865 /* 3866 * If there is 1 or 0 iomem regions, and exactly one port, 3867 * use it. We guess the number of ports based on the IO 3868 * region size. 3869 */ 3870 if (num_iomem <= 1 && num_port == 1) { 3871 board->flags = first_port; 3872 board->num_ports = pci_resource_len(dev, first_port) / 8; 3873 return 0; 3874 } 3875 3876 /* 3877 * Now guess if we've got a board which indexes by BARs. 3878 * Each IO BAR should be 8 bytes, and they should follow 3879 * consecutively. 3880 */ 3881 first_port = -1; 3882 num_port = 0; 3883 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3884 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3885 pci_resource_len(dev, i) == 8 && 3886 (first_port == -1 || (first_port + num_port) == i)) { 3887 num_port++; 3888 if (first_port == -1) 3889 first_port = i; 3890 } 3891 } 3892 3893 if (num_port > 1) { 3894 board->flags = first_port | FL_BASE_BARS; 3895 board->num_ports = num_port; 3896 return 0; 3897 } 3898 3899 return -ENODEV; 3900 } 3901 3902 static inline int 3903 serial_pci_matches(const struct pciserial_board *board, 3904 const struct pciserial_board *guessed) 3905 { 3906 return 3907 board->num_ports == guessed->num_ports && 3908 board->base_baud == guessed->base_baud && 3909 board->uart_offset == guessed->uart_offset && 3910 board->reg_shift == guessed->reg_shift && 3911 board->first_offset == guessed->first_offset; 3912 } 3913 3914 struct serial_private * 3915 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3916 { 3917 struct uart_8250_port uart; 3918 struct serial_private *priv; 3919 struct pci_serial_quirk *quirk; 3920 int rc, nr_ports, i; 3921 3922 nr_ports = board->num_ports; 3923 3924 /* 3925 * Find an init and setup quirks. 3926 */ 3927 quirk = find_quirk(dev); 3928 3929 /* 3930 * Run the new-style initialization function. 3931 * The initialization function returns: 3932 * <0 - error 3933 * 0 - use board->num_ports 3934 * >0 - number of ports 3935 */ 3936 if (quirk->init) { 3937 rc = quirk->init(dev); 3938 if (rc < 0) { 3939 priv = ERR_PTR(rc); 3940 goto err_out; 3941 } 3942 if (rc) 3943 nr_ports = rc; 3944 } 3945 3946 priv = kzalloc(sizeof(struct serial_private) + 3947 sizeof(unsigned int) * nr_ports, 3948 GFP_KERNEL); 3949 if (!priv) { 3950 priv = ERR_PTR(-ENOMEM); 3951 goto err_deinit; 3952 } 3953 3954 priv->dev = dev; 3955 priv->quirk = quirk; 3956 3957 memset(&uart, 0, sizeof(uart)); 3958 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3959 uart.port.uartclk = board->base_baud * 16; 3960 3961 if (board->flags & FL_NOIRQ) { 3962 uart.port.irq = 0; 3963 } else { 3964 if (pci_match_id(pci_use_msi, dev)) { 3965 dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n"); 3966 pci_set_master(dev); 3967 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3968 } else { 3969 dev_dbg(&dev->dev, "Using legacy interrupts\n"); 3970 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3971 } 3972 if (rc < 0) { 3973 kfree(priv); 3974 priv = ERR_PTR(rc); 3975 goto err_deinit; 3976 } 3977 3978 uart.port.irq = pci_irq_vector(dev, 0); 3979 } 3980 3981 uart.port.dev = &dev->dev; 3982 3983 for (i = 0; i < nr_ports; i++) { 3984 if (quirk->setup(priv, board, &uart, i)) 3985 break; 3986 3987 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3988 uart.port.iobase, uart.port.irq, uart.port.iotype); 3989 3990 priv->line[i] = serial8250_register_8250_port(&uart); 3991 if (priv->line[i] < 0) { 3992 dev_err(&dev->dev, 3993 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3994 uart.port.iobase, uart.port.irq, 3995 uart.port.iotype, priv->line[i]); 3996 break; 3997 } 3998 } 3999 priv->nr = i; 4000 priv->board = board; 4001 return priv; 4002 4003 err_deinit: 4004 if (quirk->exit) 4005 quirk->exit(dev); 4006 err_out: 4007 return priv; 4008 } 4009 EXPORT_SYMBOL_GPL(pciserial_init_ports); 4010 4011 static void pciserial_detach_ports(struct serial_private *priv) 4012 { 4013 struct pci_serial_quirk *quirk; 4014 int i; 4015 4016 for (i = 0; i < priv->nr; i++) 4017 serial8250_unregister_port(priv->line[i]); 4018 4019 /* 4020 * Find the exit quirks. 4021 */ 4022 quirk = find_quirk(priv->dev); 4023 if (quirk->exit) 4024 quirk->exit(priv->dev); 4025 } 4026 4027 void pciserial_remove_ports(struct serial_private *priv) 4028 { 4029 pciserial_detach_ports(priv); 4030 kfree(priv); 4031 } 4032 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4033 4034 void pciserial_suspend_ports(struct serial_private *priv) 4035 { 4036 int i; 4037 4038 for (i = 0; i < priv->nr; i++) 4039 if (priv->line[i] >= 0) 4040 serial8250_suspend_port(priv->line[i]); 4041 4042 /* 4043 * Ensure that every init quirk is properly torn down 4044 */ 4045 if (priv->quirk->exit) 4046 priv->quirk->exit(priv->dev); 4047 } 4048 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4049 4050 void pciserial_resume_ports(struct serial_private *priv) 4051 { 4052 int i; 4053 4054 /* 4055 * Ensure that the board is correctly configured. 4056 */ 4057 if (priv->quirk->init) 4058 priv->quirk->init(priv->dev); 4059 4060 for (i = 0; i < priv->nr; i++) 4061 if (priv->line[i] >= 0) 4062 serial8250_resume_port(priv->line[i]); 4063 } 4064 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4065 4066 /* 4067 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4068 * to the arrangement of serial ports on a PCI card. 4069 */ 4070 static int 4071 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4072 { 4073 struct pci_serial_quirk *quirk; 4074 struct serial_private *priv; 4075 const struct pciserial_board *board; 4076 const struct pci_device_id *exclude; 4077 struct pciserial_board tmp; 4078 int rc; 4079 4080 quirk = find_quirk(dev); 4081 if (quirk->probe) { 4082 rc = quirk->probe(dev); 4083 if (rc) 4084 return rc; 4085 } 4086 4087 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4088 dev_err(&dev->dev, "invalid driver_data: %ld\n", 4089 ent->driver_data); 4090 return -EINVAL; 4091 } 4092 4093 board = &pci_boards[ent->driver_data]; 4094 4095 exclude = pci_match_id(blacklist, dev); 4096 if (exclude) 4097 return -ENODEV; 4098 4099 rc = pcim_enable_device(dev); 4100 pci_save_state(dev); 4101 if (rc) 4102 return rc; 4103 4104 if (ent->driver_data == pbn_default) { 4105 /* 4106 * Use a copy of the pci_board entry for this; 4107 * avoid changing entries in the table. 4108 */ 4109 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4110 board = &tmp; 4111 4112 /* 4113 * We matched one of our class entries. Try to 4114 * determine the parameters of this board. 4115 */ 4116 rc = serial_pci_guess_board(dev, &tmp); 4117 if (rc) 4118 return rc; 4119 } else { 4120 /* 4121 * We matched an explicit entry. If we are able to 4122 * detect this boards settings with our heuristic, 4123 * then we no longer need this entry. 4124 */ 4125 memcpy(&tmp, &pci_boards[pbn_default], 4126 sizeof(struct pciserial_board)); 4127 rc = serial_pci_guess_board(dev, &tmp); 4128 if (rc == 0 && serial_pci_matches(board, &tmp)) 4129 moan_device("Redundant entry in serial pci_table.", 4130 dev); 4131 } 4132 4133 priv = pciserial_init_ports(dev, board); 4134 if (IS_ERR(priv)) 4135 return PTR_ERR(priv); 4136 4137 pci_set_drvdata(dev, priv); 4138 return 0; 4139 } 4140 4141 static void pciserial_remove_one(struct pci_dev *dev) 4142 { 4143 struct serial_private *priv = pci_get_drvdata(dev); 4144 4145 pciserial_remove_ports(priv); 4146 } 4147 4148 #ifdef CONFIG_PM_SLEEP 4149 static int pciserial_suspend_one(struct device *dev) 4150 { 4151 struct serial_private *priv = dev_get_drvdata(dev); 4152 4153 if (priv) 4154 pciserial_suspend_ports(priv); 4155 4156 return 0; 4157 } 4158 4159 static int pciserial_resume_one(struct device *dev) 4160 { 4161 struct pci_dev *pdev = to_pci_dev(dev); 4162 struct serial_private *priv = pci_get_drvdata(pdev); 4163 int err; 4164 4165 if (priv) { 4166 /* 4167 * The device may have been disabled. Re-enable it. 4168 */ 4169 err = pci_enable_device(pdev); 4170 /* FIXME: We cannot simply error out here */ 4171 if (err) 4172 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 4173 pciserial_resume_ports(priv); 4174 } 4175 return 0; 4176 } 4177 #endif 4178 4179 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4180 pciserial_resume_one); 4181 4182 static const struct pci_device_id serial_pci_tbl[] = { 4183 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4184 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4185 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4186 pbn_b2_8_921600 }, 4187 /* Advantech also use 0x3618 and 0xf618 */ 4188 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4189 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4190 pbn_b0_4_921600 }, 4191 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4192 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4193 pbn_b0_4_921600 }, 4194 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4195 PCI_SUBVENDOR_ID_CONNECT_TECH, 4196 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4197 pbn_b1_8_1382400 }, 4198 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4199 PCI_SUBVENDOR_ID_CONNECT_TECH, 4200 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4201 pbn_b1_4_1382400 }, 4202 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4203 PCI_SUBVENDOR_ID_CONNECT_TECH, 4204 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4205 pbn_b1_2_1382400 }, 4206 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4207 PCI_SUBVENDOR_ID_CONNECT_TECH, 4208 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4209 pbn_b1_8_1382400 }, 4210 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4211 PCI_SUBVENDOR_ID_CONNECT_TECH, 4212 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4213 pbn_b1_4_1382400 }, 4214 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4215 PCI_SUBVENDOR_ID_CONNECT_TECH, 4216 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4217 pbn_b1_2_1382400 }, 4218 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4219 PCI_SUBVENDOR_ID_CONNECT_TECH, 4220 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4221 pbn_b1_8_921600 }, 4222 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4223 PCI_SUBVENDOR_ID_CONNECT_TECH, 4224 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4225 pbn_b1_8_921600 }, 4226 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4227 PCI_SUBVENDOR_ID_CONNECT_TECH, 4228 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4229 pbn_b1_4_921600 }, 4230 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4231 PCI_SUBVENDOR_ID_CONNECT_TECH, 4232 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4233 pbn_b1_4_921600 }, 4234 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4235 PCI_SUBVENDOR_ID_CONNECT_TECH, 4236 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4237 pbn_b1_2_921600 }, 4238 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4239 PCI_SUBVENDOR_ID_CONNECT_TECH, 4240 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4241 pbn_b1_8_921600 }, 4242 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4243 PCI_SUBVENDOR_ID_CONNECT_TECH, 4244 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4245 pbn_b1_8_921600 }, 4246 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4247 PCI_SUBVENDOR_ID_CONNECT_TECH, 4248 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4249 pbn_b1_4_921600 }, 4250 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4251 PCI_SUBVENDOR_ID_CONNECT_TECH, 4252 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4253 pbn_b1_2_1250000 }, 4254 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4255 PCI_SUBVENDOR_ID_CONNECT_TECH, 4256 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4257 pbn_b0_2_1843200 }, 4258 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4259 PCI_SUBVENDOR_ID_CONNECT_TECH, 4260 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4261 pbn_b0_4_1843200 }, 4262 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4263 PCI_VENDOR_ID_AFAVLAB, 4264 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4265 pbn_b0_4_1152000 }, 4266 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4268 pbn_b2_bt_1_115200 }, 4269 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4271 pbn_b2_bt_2_115200 }, 4272 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4274 pbn_b2_bt_4_115200 }, 4275 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4277 pbn_b2_bt_2_115200 }, 4278 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4280 pbn_b2_bt_4_115200 }, 4281 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4283 pbn_b2_8_115200 }, 4284 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4286 pbn_b2_8_460800 }, 4287 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4289 pbn_b2_8_115200 }, 4290 4291 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4293 pbn_b2_bt_2_115200 }, 4294 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4296 pbn_b2_bt_2_921600 }, 4297 /* 4298 * VScom SPCOM800, from sl@s.pl 4299 */ 4300 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4302 pbn_b2_8_921600 }, 4303 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4305 pbn_b2_4_921600 }, 4306 /* Unknown card - subdevice 0x1584 */ 4307 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4308 PCI_VENDOR_ID_PLX, 4309 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4310 pbn_b2_4_115200 }, 4311 /* Unknown card - subdevice 0x1588 */ 4312 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4313 PCI_VENDOR_ID_PLX, 4314 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4315 pbn_b2_8_115200 }, 4316 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4317 PCI_SUBVENDOR_ID_KEYSPAN, 4318 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4319 pbn_panacom }, 4320 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4322 pbn_panacom4 }, 4323 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4325 pbn_panacom2 }, 4326 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4327 PCI_VENDOR_ID_ESDGMBH, 4328 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4329 pbn_b2_4_115200 }, 4330 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4331 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4332 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4333 pbn_b2_4_460800 }, 4334 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4335 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4336 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4337 pbn_b2_8_460800 }, 4338 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4339 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4340 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4341 pbn_b2_16_460800 }, 4342 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4343 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4344 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4345 pbn_b2_16_460800 }, 4346 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4347 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4348 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4349 pbn_b2_4_460800 }, 4350 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4351 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4352 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4353 pbn_b2_8_460800 }, 4354 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4355 PCI_SUBVENDOR_ID_EXSYS, 4356 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4357 pbn_b2_4_115200 }, 4358 /* 4359 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4360 * (Exoray@isys.ca) 4361 */ 4362 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4363 0x10b5, 0x106a, 0, 0, 4364 pbn_plx_romulus }, 4365 /* 4366 * EndRun Technologies. PCI express device range. 4367 * EndRun PTP/1588 has 2 Native UARTs. 4368 */ 4369 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4371 pbn_endrun_2_4000000 }, 4372 /* 4373 * Quatech cards. These actually have configurable clocks but for 4374 * now we just use the default. 4375 * 4376 * 100 series are RS232, 200 series RS422, 4377 */ 4378 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4380 pbn_b1_4_115200 }, 4381 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4383 pbn_b1_2_115200 }, 4384 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4386 pbn_b2_2_115200 }, 4387 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4389 pbn_b1_2_115200 }, 4390 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4392 pbn_b2_2_115200 }, 4393 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4395 pbn_b1_4_115200 }, 4396 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4398 pbn_b1_8_115200 }, 4399 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4401 pbn_b1_8_115200 }, 4402 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4404 pbn_b1_4_115200 }, 4405 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4407 pbn_b1_2_115200 }, 4408 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4410 pbn_b1_4_115200 }, 4411 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4413 pbn_b1_2_115200 }, 4414 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4416 pbn_b2_4_115200 }, 4417 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4419 pbn_b2_2_115200 }, 4420 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4422 pbn_b2_1_115200 }, 4423 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4425 pbn_b2_4_115200 }, 4426 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4428 pbn_b2_2_115200 }, 4429 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4431 pbn_b2_1_115200 }, 4432 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4434 pbn_b0_8_115200 }, 4435 4436 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4437 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4438 0, 0, 4439 pbn_b0_4_921600 }, 4440 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4441 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4442 0, 0, 4443 pbn_b0_4_1152000 }, 4444 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4446 pbn_b0_bt_2_921600 }, 4447 4448 /* 4449 * The below card is a little controversial since it is the 4450 * subject of a PCI vendor/device ID clash. (See 4451 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4452 * For now just used the hex ID 0x950a. 4453 */ 4454 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4455 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4456 0, 0, pbn_b0_2_115200 }, 4457 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4458 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4459 0, 0, pbn_b0_2_115200 }, 4460 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4462 pbn_b0_2_1130000 }, 4463 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4464 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4465 pbn_b0_1_921600 }, 4466 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_b0_4_115200 }, 4469 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_b0_bt_2_921600 }, 4472 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_b2_8_1152000 }, 4475 4476 /* 4477 * Oxford Semiconductor Inc. Tornado PCI express device range. 4478 */ 4479 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4481 pbn_b0_1_4000000 }, 4482 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4484 pbn_b0_1_4000000 }, 4485 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4487 pbn_oxsemi_1_4000000 }, 4488 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4490 pbn_oxsemi_1_4000000 }, 4491 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4493 pbn_b0_1_4000000 }, 4494 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4496 pbn_b0_1_4000000 }, 4497 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4499 pbn_oxsemi_1_4000000 }, 4500 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_oxsemi_1_4000000 }, 4503 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4505 pbn_b0_1_4000000 }, 4506 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4508 pbn_b0_1_4000000 }, 4509 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4511 pbn_b0_1_4000000 }, 4512 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4514 pbn_b0_1_4000000 }, 4515 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4517 pbn_oxsemi_2_4000000 }, 4518 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4520 pbn_oxsemi_2_4000000 }, 4521 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4523 pbn_oxsemi_4_4000000 }, 4524 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4526 pbn_oxsemi_4_4000000 }, 4527 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4529 pbn_oxsemi_8_4000000 }, 4530 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4532 pbn_oxsemi_8_4000000 }, 4533 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4535 pbn_oxsemi_1_4000000 }, 4536 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4538 pbn_oxsemi_1_4000000 }, 4539 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4541 pbn_oxsemi_1_4000000 }, 4542 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4544 pbn_oxsemi_1_4000000 }, 4545 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4547 pbn_oxsemi_1_4000000 }, 4548 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4550 pbn_oxsemi_1_4000000 }, 4551 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4553 pbn_oxsemi_1_4000000 }, 4554 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4556 pbn_oxsemi_1_4000000 }, 4557 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4559 pbn_oxsemi_1_4000000 }, 4560 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4562 pbn_oxsemi_1_4000000 }, 4563 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4565 pbn_oxsemi_1_4000000 }, 4566 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4568 pbn_oxsemi_1_4000000 }, 4569 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4571 pbn_oxsemi_1_4000000 }, 4572 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4574 pbn_oxsemi_1_4000000 }, 4575 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4577 pbn_oxsemi_1_4000000 }, 4578 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4580 pbn_oxsemi_1_4000000 }, 4581 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4583 pbn_oxsemi_1_4000000 }, 4584 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4586 pbn_oxsemi_1_4000000 }, 4587 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4589 pbn_oxsemi_1_4000000 }, 4590 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4592 pbn_oxsemi_1_4000000 }, 4593 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4595 pbn_oxsemi_1_4000000 }, 4596 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4598 pbn_oxsemi_1_4000000 }, 4599 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4601 pbn_oxsemi_1_4000000 }, 4602 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4604 pbn_oxsemi_1_4000000 }, 4605 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_oxsemi_1_4000000 }, 4608 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_oxsemi_1_4000000 }, 4611 /* 4612 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4613 */ 4614 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4615 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4616 pbn_oxsemi_1_4000000 }, 4617 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4618 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4619 pbn_oxsemi_2_4000000 }, 4620 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4621 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4622 pbn_oxsemi_4_4000000 }, 4623 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4624 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4625 pbn_oxsemi_8_4000000 }, 4626 4627 /* 4628 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4629 */ 4630 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4631 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4632 pbn_oxsemi_2_4000000 }, 4633 4634 /* 4635 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4636 * from skokodyn@yahoo.com 4637 */ 4638 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4639 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4640 pbn_sbsxrsio }, 4641 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4642 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4643 pbn_sbsxrsio }, 4644 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4645 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4646 pbn_sbsxrsio }, 4647 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4648 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4649 pbn_sbsxrsio }, 4650 4651 /* 4652 * Digitan DS560-558, from jimd@esoft.com 4653 */ 4654 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4656 pbn_b1_1_115200 }, 4657 4658 /* 4659 * Titan Electronic cards 4660 * The 400L and 800L have a custom setup quirk. 4661 */ 4662 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4664 pbn_b0_1_921600 }, 4665 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4667 pbn_b0_2_921600 }, 4668 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4670 pbn_b0_4_921600 }, 4671 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4673 pbn_b0_4_921600 }, 4674 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4676 pbn_b1_1_921600 }, 4677 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4679 pbn_b1_bt_2_921600 }, 4680 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4682 pbn_b0_bt_4_921600 }, 4683 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_b0_bt_8_921600 }, 4686 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_b4_bt_2_921600 }, 4689 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_b4_bt_4_921600 }, 4692 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4694 pbn_b4_bt_8_921600 }, 4695 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4697 pbn_b0_4_921600 }, 4698 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4700 pbn_b0_4_921600 }, 4701 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4703 pbn_b0_4_921600 }, 4704 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4706 pbn_oxsemi_1_4000000 }, 4707 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4709 pbn_oxsemi_2_4000000 }, 4710 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4712 pbn_oxsemi_4_4000000 }, 4713 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4715 pbn_oxsemi_8_4000000 }, 4716 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4718 pbn_oxsemi_2_4000000 }, 4719 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4721 pbn_oxsemi_2_4000000 }, 4722 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4724 pbn_b0_bt_2_921600 }, 4725 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_b0_4_921600 }, 4728 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4730 pbn_b0_4_921600 }, 4731 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4733 pbn_b0_4_921600 }, 4734 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4736 pbn_b0_4_921600 }, 4737 4738 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4740 pbn_b2_1_460800 }, 4741 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4743 pbn_b2_1_460800 }, 4744 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4746 pbn_b2_1_460800 }, 4747 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4749 pbn_b2_bt_2_921600 }, 4750 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4752 pbn_b2_bt_2_921600 }, 4753 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4755 pbn_b2_bt_2_921600 }, 4756 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4758 pbn_b2_bt_4_921600 }, 4759 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4761 pbn_b2_bt_4_921600 }, 4762 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4764 pbn_b2_bt_4_921600 }, 4765 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4767 pbn_b0_1_921600 }, 4768 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4770 pbn_b0_1_921600 }, 4771 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4773 pbn_b0_1_921600 }, 4774 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4776 pbn_b0_bt_2_921600 }, 4777 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4779 pbn_b0_bt_2_921600 }, 4780 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4782 pbn_b0_bt_2_921600 }, 4783 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4785 pbn_b0_bt_4_921600 }, 4786 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4788 pbn_b0_bt_4_921600 }, 4789 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4791 pbn_b0_bt_4_921600 }, 4792 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4794 pbn_b0_bt_8_921600 }, 4795 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4797 pbn_b0_bt_8_921600 }, 4798 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4800 pbn_b0_bt_8_921600 }, 4801 4802 /* 4803 * Computone devices submitted by Doug McNash dmcnash@computone.com 4804 */ 4805 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4806 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4807 0, 0, pbn_computone_4 }, 4808 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4809 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4810 0, 0, pbn_computone_8 }, 4811 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4812 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4813 0, 0, pbn_computone_6 }, 4814 4815 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4817 pbn_oxsemi }, 4818 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4819 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4820 pbn_b0_bt_1_921600 }, 4821 4822 /* 4823 * Sunix PCI serial boards 4824 */ 4825 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4826 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4827 pbn_sunix_pci_1s }, 4828 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4829 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4830 pbn_sunix_pci_2s }, 4831 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4832 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4833 pbn_sunix_pci_4s }, 4834 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4835 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4836 pbn_sunix_pci_4s }, 4837 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4838 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4839 pbn_sunix_pci_8s }, 4840 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4841 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4842 pbn_sunix_pci_8s }, 4843 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4844 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4845 pbn_sunix_pci_16s }, 4846 4847 /* 4848 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4849 */ 4850 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4851 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4852 pbn_b0_bt_8_115200 }, 4853 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4855 pbn_b0_bt_8_115200 }, 4856 4857 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4859 pbn_b0_bt_2_115200 }, 4860 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b0_bt_2_115200 }, 4863 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4865 pbn_b0_bt_2_115200 }, 4866 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4868 pbn_b0_bt_2_115200 }, 4869 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4871 pbn_b0_bt_2_115200 }, 4872 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4874 pbn_b0_bt_4_460800 }, 4875 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4877 pbn_b0_bt_4_460800 }, 4878 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4880 pbn_b0_bt_2_460800 }, 4881 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4883 pbn_b0_bt_2_460800 }, 4884 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4886 pbn_b0_bt_2_460800 }, 4887 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4889 pbn_b0_bt_1_115200 }, 4890 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4892 pbn_b0_bt_1_460800 }, 4893 4894 /* 4895 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4896 * Cards are identified by their subsystem vendor IDs, which 4897 * (in hex) match the model number. 4898 * 4899 * Note that JC140x are RS422/485 cards which require ox950 4900 * ACR = 0x10, and as such are not currently fully supported. 4901 */ 4902 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4903 0x1204, 0x0004, 0, 0, 4904 pbn_b0_4_921600 }, 4905 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4906 0x1208, 0x0004, 0, 0, 4907 pbn_b0_4_921600 }, 4908 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4909 0x1402, 0x0002, 0, 0, 4910 pbn_b0_2_921600 }, */ 4911 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4912 0x1404, 0x0004, 0, 0, 4913 pbn_b0_4_921600 }, */ 4914 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4915 0x1208, 0x0004, 0, 0, 4916 pbn_b0_4_921600 }, 4917 4918 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4919 0x1204, 0x0004, 0, 0, 4920 pbn_b0_4_921600 }, 4921 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4922 0x1208, 0x0004, 0, 0, 4923 pbn_b0_4_921600 }, 4924 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4925 0x1208, 0x0004, 0, 0, 4926 pbn_b0_4_921600 }, 4927 /* 4928 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4929 */ 4930 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4932 pbn_b1_1_1382400 }, 4933 4934 /* 4935 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4936 */ 4937 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4939 pbn_b1_1_1382400 }, 4940 4941 /* 4942 * RAStel 2 port modem, gerg@moreton.com.au 4943 */ 4944 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4946 pbn_b2_bt_2_115200 }, 4947 4948 /* 4949 * EKF addition for i960 Boards form EKF with serial port 4950 */ 4951 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4952 0xE4BF, PCI_ANY_ID, 0, 0, 4953 pbn_intel_i960 }, 4954 4955 /* 4956 * Xircom Cardbus/Ethernet combos 4957 */ 4958 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4960 pbn_b0_1_115200 }, 4961 /* 4962 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4963 */ 4964 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4966 pbn_b0_1_115200 }, 4967 4968 /* 4969 * Untested PCI modems, sent in from various folks... 4970 */ 4971 4972 /* 4973 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4974 */ 4975 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4976 0x1048, 0x1500, 0, 0, 4977 pbn_b1_1_115200 }, 4978 4979 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4980 0xFF00, 0, 0, 0, 4981 pbn_sgi_ioc3 }, 4982 4983 /* 4984 * HP Diva card 4985 */ 4986 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4987 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4988 pbn_b1_1_115200 }, 4989 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4990 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4991 pbn_b0_5_115200 }, 4992 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4993 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4994 pbn_b2_1_115200 }, 4995 /* HPE PCI serial device */ 4996 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4998 pbn_b1_1_115200 }, 4999 5000 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5002 pbn_b3_2_115200 }, 5003 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5005 pbn_b3_4_115200 }, 5006 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5008 pbn_b3_8_115200 }, 5009 /* 5010 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 5011 */ 5012 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 5013 PCI_ANY_ID, PCI_ANY_ID, 5014 0, 5015 0, pbn_pericom_PI7C9X7951 }, 5016 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 5017 PCI_ANY_ID, PCI_ANY_ID, 5018 0, 5019 0, pbn_pericom_PI7C9X7952 }, 5020 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 5021 PCI_ANY_ID, PCI_ANY_ID, 5022 0, 5023 0, pbn_pericom_PI7C9X7954 }, 5024 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 5025 PCI_ANY_ID, PCI_ANY_ID, 5026 0, 5027 0, pbn_pericom_PI7C9X7958 }, 5028 /* 5029 * ACCES I/O Products quad 5030 */ 5031 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5033 pbn_pericom_PI7C9X7952 }, 5034 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5036 pbn_pericom_PI7C9X7952 }, 5037 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 5038 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5039 pbn_pericom_PI7C9X7954 }, 5040 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5042 pbn_pericom_PI7C9X7954 }, 5043 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 5044 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5045 pbn_pericom_PI7C9X7952 }, 5046 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5048 pbn_pericom_PI7C9X7952 }, 5049 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5051 pbn_pericom_PI7C9X7954 }, 5052 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5054 pbn_pericom_PI7C9X7954 }, 5055 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5057 pbn_pericom_PI7C9X7952 }, 5058 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5060 pbn_pericom_PI7C9X7952 }, 5061 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5063 pbn_pericom_PI7C9X7954 }, 5064 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5066 pbn_pericom_PI7C9X7954 }, 5067 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5069 pbn_pericom_PI7C9X7951 }, 5070 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5072 pbn_pericom_PI7C9X7952 }, 5073 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5075 pbn_pericom_PI7C9X7952 }, 5076 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5078 pbn_pericom_PI7C9X7954 }, 5079 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5081 pbn_pericom_PI7C9X7954 }, 5082 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5084 pbn_pericom_PI7C9X7952 }, 5085 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5087 pbn_pericom_PI7C9X7954 }, 5088 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5090 pbn_pericom_PI7C9X7952 }, 5091 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5093 pbn_pericom_PI7C9X7952 }, 5094 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 5095 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5096 pbn_pericom_PI7C9X7954 }, 5097 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5099 pbn_pericom_PI7C9X7954 }, 5100 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5102 pbn_pericom_PI7C9X7952 }, 5103 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5105 pbn_pericom_PI7C9X7954 }, 5106 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5108 pbn_pericom_PI7C9X7954 }, 5109 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5111 pbn_pericom_PI7C9X7958 }, 5112 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5114 pbn_pericom_PI7C9X7958 }, 5115 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5117 pbn_pericom_PI7C9X7954 }, 5118 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5120 pbn_pericom_PI7C9X7958 }, 5121 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 5122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5123 pbn_pericom_PI7C9X7954 }, 5124 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5126 pbn_pericom_PI7C9X7958 }, 5127 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 5128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5129 pbn_pericom_PI7C9X7954 }, 5130 /* 5131 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5132 */ 5133 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5135 pbn_b0_1_115200 }, 5136 /* 5137 * ITE 5138 */ 5139 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5140 PCI_ANY_ID, PCI_ANY_ID, 5141 0, 0, 5142 pbn_b1_bt_1_115200 }, 5143 5144 /* 5145 * IntaShield IS-200 5146 */ 5147 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5149 pbn_b2_2_115200 }, 5150 /* 5151 * IntaShield IS-400 5152 */ 5153 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5155 pbn_b2_4_115200 }, 5156 /* 5157 * BrainBoxes UC-260 5158 */ 5159 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5160 PCI_ANY_ID, PCI_ANY_ID, 5161 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5162 pbn_b2_4_115200 }, 5163 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5164 PCI_ANY_ID, PCI_ANY_ID, 5165 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5166 pbn_b2_4_115200 }, 5167 /* 5168 * Perle PCI-RAS cards 5169 */ 5170 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5171 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5172 0, 0, pbn_b2_4_921600 }, 5173 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5174 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5175 0, 0, pbn_b2_8_921600 }, 5176 5177 /* 5178 * Mainpine series cards: Fairly standard layout but fools 5179 * parts of the autodetect in some cases and uses otherwise 5180 * unmatched communications subclasses in the PCI Express case 5181 */ 5182 5183 { /* RockForceDUO */ 5184 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5185 PCI_VENDOR_ID_MAINPINE, 0x0200, 5186 0, 0, pbn_b0_2_115200 }, 5187 { /* RockForceQUATRO */ 5188 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5189 PCI_VENDOR_ID_MAINPINE, 0x0300, 5190 0, 0, pbn_b0_4_115200 }, 5191 { /* RockForceDUO+ */ 5192 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5193 PCI_VENDOR_ID_MAINPINE, 0x0400, 5194 0, 0, pbn_b0_2_115200 }, 5195 { /* RockForceQUATRO+ */ 5196 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5197 PCI_VENDOR_ID_MAINPINE, 0x0500, 5198 0, 0, pbn_b0_4_115200 }, 5199 { /* RockForce+ */ 5200 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5201 PCI_VENDOR_ID_MAINPINE, 0x0600, 5202 0, 0, pbn_b0_2_115200 }, 5203 { /* RockForce+ */ 5204 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5205 PCI_VENDOR_ID_MAINPINE, 0x0700, 5206 0, 0, pbn_b0_4_115200 }, 5207 { /* RockForceOCTO+ */ 5208 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5209 PCI_VENDOR_ID_MAINPINE, 0x0800, 5210 0, 0, pbn_b0_8_115200 }, 5211 { /* RockForceDUO+ */ 5212 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5213 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5214 0, 0, pbn_b0_2_115200 }, 5215 { /* RockForceQUARTRO+ */ 5216 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5217 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5218 0, 0, pbn_b0_4_115200 }, 5219 { /* RockForceOCTO+ */ 5220 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5221 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5222 0, 0, pbn_b0_8_115200 }, 5223 { /* RockForceD1 */ 5224 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5225 PCI_VENDOR_ID_MAINPINE, 0x2000, 5226 0, 0, pbn_b0_1_115200 }, 5227 { /* RockForceF1 */ 5228 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5229 PCI_VENDOR_ID_MAINPINE, 0x2100, 5230 0, 0, pbn_b0_1_115200 }, 5231 { /* RockForceD2 */ 5232 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5233 PCI_VENDOR_ID_MAINPINE, 0x2200, 5234 0, 0, pbn_b0_2_115200 }, 5235 { /* RockForceF2 */ 5236 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5237 PCI_VENDOR_ID_MAINPINE, 0x2300, 5238 0, 0, pbn_b0_2_115200 }, 5239 { /* RockForceD4 */ 5240 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5241 PCI_VENDOR_ID_MAINPINE, 0x2400, 5242 0, 0, pbn_b0_4_115200 }, 5243 { /* RockForceF4 */ 5244 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5245 PCI_VENDOR_ID_MAINPINE, 0x2500, 5246 0, 0, pbn_b0_4_115200 }, 5247 { /* RockForceD8 */ 5248 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5249 PCI_VENDOR_ID_MAINPINE, 0x2600, 5250 0, 0, pbn_b0_8_115200 }, 5251 { /* RockForceF8 */ 5252 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5253 PCI_VENDOR_ID_MAINPINE, 0x2700, 5254 0, 0, pbn_b0_8_115200 }, 5255 { /* IQ Express D1 */ 5256 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5257 PCI_VENDOR_ID_MAINPINE, 0x3000, 5258 0, 0, pbn_b0_1_115200 }, 5259 { /* IQ Express F1 */ 5260 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5261 PCI_VENDOR_ID_MAINPINE, 0x3100, 5262 0, 0, pbn_b0_1_115200 }, 5263 { /* IQ Express D2 */ 5264 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5265 PCI_VENDOR_ID_MAINPINE, 0x3200, 5266 0, 0, pbn_b0_2_115200 }, 5267 { /* IQ Express F2 */ 5268 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5269 PCI_VENDOR_ID_MAINPINE, 0x3300, 5270 0, 0, pbn_b0_2_115200 }, 5271 { /* IQ Express D4 */ 5272 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5273 PCI_VENDOR_ID_MAINPINE, 0x3400, 5274 0, 0, pbn_b0_4_115200 }, 5275 { /* IQ Express F4 */ 5276 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5277 PCI_VENDOR_ID_MAINPINE, 0x3500, 5278 0, 0, pbn_b0_4_115200 }, 5279 { /* IQ Express D8 */ 5280 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5281 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5282 0, 0, pbn_b0_8_115200 }, 5283 { /* IQ Express F8 */ 5284 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5285 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5286 0, 0, pbn_b0_8_115200 }, 5287 5288 5289 /* 5290 * PA Semi PA6T-1682M on-chip UART 5291 */ 5292 { PCI_VENDOR_ID_PASEMI, 0xa004, 5293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5294 pbn_pasemi_1682M }, 5295 5296 /* 5297 * National Instruments 5298 */ 5299 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5301 pbn_b1_16_115200 }, 5302 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5304 pbn_b1_8_115200 }, 5305 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5307 pbn_b1_bt_4_115200 }, 5308 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5310 pbn_b1_bt_2_115200 }, 5311 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5313 pbn_b1_bt_4_115200 }, 5314 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5316 pbn_b1_bt_2_115200 }, 5317 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5319 pbn_b1_16_115200 }, 5320 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5322 pbn_b1_8_115200 }, 5323 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5325 pbn_b1_bt_4_115200 }, 5326 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5328 pbn_b1_bt_2_115200 }, 5329 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5331 pbn_b1_bt_4_115200 }, 5332 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5334 pbn_b1_bt_2_115200 }, 5335 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5337 pbn_ni8430_2 }, 5338 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5340 pbn_ni8430_2 }, 5341 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5343 pbn_ni8430_4 }, 5344 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5346 pbn_ni8430_4 }, 5347 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5349 pbn_ni8430_8 }, 5350 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5352 pbn_ni8430_8 }, 5353 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5355 pbn_ni8430_16 }, 5356 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5358 pbn_ni8430_16 }, 5359 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5361 pbn_ni8430_2 }, 5362 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5364 pbn_ni8430_2 }, 5365 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5367 pbn_ni8430_4 }, 5368 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5370 pbn_ni8430_4 }, 5371 5372 /* 5373 * MOXA 5374 */ 5375 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5377 pbn_moxa8250_2p }, 5378 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5380 pbn_moxa8250_2p }, 5381 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5383 pbn_moxa8250_4p }, 5384 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5386 pbn_moxa8250_4p }, 5387 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5389 pbn_moxa8250_8p }, 5390 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5392 pbn_moxa8250_8p }, 5393 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5395 pbn_moxa8250_8p }, 5396 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5398 pbn_moxa8250_8p }, 5399 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5401 pbn_moxa8250_2p }, 5402 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5404 pbn_moxa8250_4p }, 5405 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5407 pbn_moxa8250_8p }, 5408 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5410 pbn_moxa8250_8p }, 5411 5412 /* 5413 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5414 */ 5415 { PCI_VENDOR_ID_ADDIDATA, 5416 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5417 PCI_ANY_ID, 5418 PCI_ANY_ID, 5419 0, 5420 0, 5421 pbn_b0_4_115200 }, 5422 5423 { PCI_VENDOR_ID_ADDIDATA, 5424 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5425 PCI_ANY_ID, 5426 PCI_ANY_ID, 5427 0, 5428 0, 5429 pbn_b0_2_115200 }, 5430 5431 { PCI_VENDOR_ID_ADDIDATA, 5432 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5433 PCI_ANY_ID, 5434 PCI_ANY_ID, 5435 0, 5436 0, 5437 pbn_b0_1_115200 }, 5438 5439 { PCI_VENDOR_ID_AMCC, 5440 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5441 PCI_ANY_ID, 5442 PCI_ANY_ID, 5443 0, 5444 0, 5445 pbn_b1_8_115200 }, 5446 5447 { PCI_VENDOR_ID_ADDIDATA, 5448 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5449 PCI_ANY_ID, 5450 PCI_ANY_ID, 5451 0, 5452 0, 5453 pbn_b0_4_115200 }, 5454 5455 { PCI_VENDOR_ID_ADDIDATA, 5456 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5457 PCI_ANY_ID, 5458 PCI_ANY_ID, 5459 0, 5460 0, 5461 pbn_b0_2_115200 }, 5462 5463 { PCI_VENDOR_ID_ADDIDATA, 5464 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5465 PCI_ANY_ID, 5466 PCI_ANY_ID, 5467 0, 5468 0, 5469 pbn_b0_1_115200 }, 5470 5471 { PCI_VENDOR_ID_ADDIDATA, 5472 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5473 PCI_ANY_ID, 5474 PCI_ANY_ID, 5475 0, 5476 0, 5477 pbn_b0_4_115200 }, 5478 5479 { PCI_VENDOR_ID_ADDIDATA, 5480 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5481 PCI_ANY_ID, 5482 PCI_ANY_ID, 5483 0, 5484 0, 5485 pbn_b0_2_115200 }, 5486 5487 { PCI_VENDOR_ID_ADDIDATA, 5488 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5489 PCI_ANY_ID, 5490 PCI_ANY_ID, 5491 0, 5492 0, 5493 pbn_b0_1_115200 }, 5494 5495 { PCI_VENDOR_ID_ADDIDATA, 5496 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5497 PCI_ANY_ID, 5498 PCI_ANY_ID, 5499 0, 5500 0, 5501 pbn_b0_8_115200 }, 5502 5503 { PCI_VENDOR_ID_ADDIDATA, 5504 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5505 PCI_ANY_ID, 5506 PCI_ANY_ID, 5507 0, 5508 0, 5509 pbn_ADDIDATA_PCIe_4_3906250 }, 5510 5511 { PCI_VENDOR_ID_ADDIDATA, 5512 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5513 PCI_ANY_ID, 5514 PCI_ANY_ID, 5515 0, 5516 0, 5517 pbn_ADDIDATA_PCIe_2_3906250 }, 5518 5519 { PCI_VENDOR_ID_ADDIDATA, 5520 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5521 PCI_ANY_ID, 5522 PCI_ANY_ID, 5523 0, 5524 0, 5525 pbn_ADDIDATA_PCIe_1_3906250 }, 5526 5527 { PCI_VENDOR_ID_ADDIDATA, 5528 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5529 PCI_ANY_ID, 5530 PCI_ANY_ID, 5531 0, 5532 0, 5533 pbn_ADDIDATA_PCIe_8_3906250 }, 5534 5535 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5536 PCI_VENDOR_ID_IBM, 0x0299, 5537 0, 0, pbn_b0_bt_2_115200 }, 5538 5539 /* 5540 * other NetMos 9835 devices are most likely handled by the 5541 * parport_serial driver, check drivers/parport/parport_serial.c 5542 * before adding them here. 5543 */ 5544 5545 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5546 0xA000, 0x1000, 5547 0, 0, pbn_b0_1_115200 }, 5548 5549 /* the 9901 is a rebranded 9912 */ 5550 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5551 0xA000, 0x1000, 5552 0, 0, pbn_b0_1_115200 }, 5553 5554 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5555 0xA000, 0x1000, 5556 0, 0, pbn_b0_1_115200 }, 5557 5558 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5559 0xA000, 0x1000, 5560 0, 0, pbn_b0_1_115200 }, 5561 5562 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5563 0xA000, 0x1000, 5564 0, 0, pbn_b0_1_115200 }, 5565 5566 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5567 0xA000, 0x3002, 5568 0, 0, pbn_NETMOS9900_2s_115200 }, 5569 5570 /* 5571 * Best Connectivity and Rosewill PCI Multi I/O cards 5572 */ 5573 5574 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5575 0xA000, 0x1000, 5576 0, 0, pbn_b0_1_115200 }, 5577 5578 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5579 0xA000, 0x3002, 5580 0, 0, pbn_b0_bt_2_115200 }, 5581 5582 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5583 0xA000, 0x3004, 5584 0, 0, pbn_b0_bt_4_115200 }, 5585 /* Intel CE4100 */ 5586 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5587 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5588 pbn_ce4100_1_115200 }, 5589 5590 /* 5591 * Cronyx Omega PCI 5592 */ 5593 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5594 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5595 pbn_omegapci }, 5596 5597 /* 5598 * Broadcom TruManage 5599 */ 5600 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5602 pbn_brcm_trumanage }, 5603 5604 /* 5605 * AgeStar as-prs2-009 5606 */ 5607 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5608 PCI_ANY_ID, PCI_ANY_ID, 5609 0, 0, pbn_b0_bt_2_115200 }, 5610 5611 /* 5612 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5613 * so not listed here. 5614 */ 5615 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5616 PCI_ANY_ID, PCI_ANY_ID, 5617 0, 0, pbn_b0_bt_4_115200 }, 5618 5619 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5620 PCI_ANY_ID, PCI_ANY_ID, 5621 0, 0, pbn_b0_bt_2_115200 }, 5622 5623 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5624 PCI_ANY_ID, PCI_ANY_ID, 5625 0, 0, pbn_b0_bt_4_115200 }, 5626 5627 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5628 PCI_ANY_ID, PCI_ANY_ID, 5629 0, 0, pbn_wch382_2 }, 5630 5631 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5632 PCI_ANY_ID, PCI_ANY_ID, 5633 0, 0, pbn_wch384_4 }, 5634 5635 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5636 PCI_ANY_ID, PCI_ANY_ID, 5637 0, 0, pbn_wch384_8 }, 5638 /* 5639 * Realtek RealManage 5640 */ 5641 { PCI_VENDOR_ID_REALTEK, 0x816a, 5642 PCI_ANY_ID, PCI_ANY_ID, 5643 0, 0, pbn_b0_1_115200 }, 5644 5645 { PCI_VENDOR_ID_REALTEK, 0x816b, 5646 PCI_ANY_ID, PCI_ANY_ID, 5647 0, 0, pbn_b0_1_115200 }, 5648 5649 /* Fintek PCI serial cards */ 5650 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5651 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5652 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5653 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5654 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5655 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5656 5657 /* MKS Tenta SCOM-080x serial cards */ 5658 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5659 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5660 5661 /* Amazon PCI serial device */ 5662 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5663 5664 /* 5665 * These entries match devices with class COMMUNICATION_SERIAL, 5666 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5667 */ 5668 { PCI_ANY_ID, PCI_ANY_ID, 5669 PCI_ANY_ID, PCI_ANY_ID, 5670 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5671 0xffff00, pbn_default }, 5672 { PCI_ANY_ID, PCI_ANY_ID, 5673 PCI_ANY_ID, PCI_ANY_ID, 5674 PCI_CLASS_COMMUNICATION_MODEM << 8, 5675 0xffff00, pbn_default }, 5676 { PCI_ANY_ID, PCI_ANY_ID, 5677 PCI_ANY_ID, PCI_ANY_ID, 5678 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5679 0xffff00, pbn_default }, 5680 { 0, } 5681 }; 5682 5683 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5684 pci_channel_state_t state) 5685 { 5686 struct serial_private *priv = pci_get_drvdata(dev); 5687 5688 if (state == pci_channel_io_perm_failure) 5689 return PCI_ERS_RESULT_DISCONNECT; 5690 5691 if (priv) 5692 pciserial_detach_ports(priv); 5693 5694 pci_disable_device(dev); 5695 5696 return PCI_ERS_RESULT_NEED_RESET; 5697 } 5698 5699 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5700 { 5701 int rc; 5702 5703 rc = pci_enable_device(dev); 5704 5705 if (rc) 5706 return PCI_ERS_RESULT_DISCONNECT; 5707 5708 pci_restore_state(dev); 5709 pci_save_state(dev); 5710 5711 return PCI_ERS_RESULT_RECOVERED; 5712 } 5713 5714 static void serial8250_io_resume(struct pci_dev *dev) 5715 { 5716 struct serial_private *priv = pci_get_drvdata(dev); 5717 struct serial_private *new; 5718 5719 if (!priv) 5720 return; 5721 5722 new = pciserial_init_ports(dev, priv->board); 5723 if (!IS_ERR(new)) { 5724 pci_set_drvdata(dev, new); 5725 kfree(priv); 5726 } 5727 } 5728 5729 static const struct pci_error_handlers serial8250_err_handler = { 5730 .error_detected = serial8250_io_error_detected, 5731 .slot_reset = serial8250_io_slot_reset, 5732 .resume = serial8250_io_resume, 5733 }; 5734 5735 static struct pci_driver serial_pci_driver = { 5736 .name = "serial", 5737 .probe = pciserial_init_one, 5738 .remove = pciserial_remove_one, 5739 .driver = { 5740 .pm = &pciserial_pm_ops, 5741 }, 5742 .id_table = serial_pci_tbl, 5743 .err_handler = &serial8250_err_handler, 5744 }; 5745 5746 module_pci_driver(serial_pci_driver); 5747 5748 MODULE_LICENSE("GPL"); 5749 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5750 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5751