1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 #include <linux/bitfield.h> 23 24 #include <asm/byteorder.h> 25 #include <asm/io.h> 26 27 #include "8250.h" 28 #include "8250_pcilib.h" 29 30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 32 #define PCI_DEVICE_ID_OCTPRO 0x0001 33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 46 #define PCI_DEVICE_ID_TITAN_200I 0x8028 47 #define PCI_DEVICE_ID_TITAN_400I 0x8048 48 #define PCI_DEVICE_ID_TITAN_800I 0x8088 49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 52 #define PCI_DEVICE_ID_TITAN_100E 0xA010 53 #define PCI_DEVICE_ID_TITAN_200E 0xA012 54 #define PCI_DEVICE_ID_TITAN_400E 0xA013 55 #define PCI_DEVICE_ID_TITAN_800E 0xA014 56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 67 #define PCI_VENDOR_ID_WCH 0x4348 68 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 69 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 70 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 71 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 72 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 73 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 74 #define PCI_VENDOR_ID_AGESTAR 0x5372 75 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 76 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 77 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 78 79 #define PCIE_VENDOR_ID_WCH 0x1c00 80 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 81 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 82 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 83 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 84 85 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 86 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 87 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027 88 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 89 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046 90 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121 91 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 92 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145 93 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 94 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 95 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 96 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 97 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 98 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323 99 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 100 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343 101 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 102 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 103 104 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 106 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 107 108 /* 109 * init function returns: 110 * > 0 - number of ports 111 * = 0 - use board->num_ports 112 * < 0 - error 113 */ 114 struct pci_serial_quirk { 115 u32 vendor; 116 u32 device; 117 u32 subvendor; 118 u32 subdevice; 119 int (*probe)(struct pci_dev *dev); 120 int (*init)(struct pci_dev *dev); 121 int (*setup)(struct serial_private *, 122 const struct pciserial_board *, 123 struct uart_8250_port *, int); 124 void (*exit)(struct pci_dev *dev); 125 }; 126 127 struct f815xxa_data { 128 spinlock_t lock; 129 int idx; 130 }; 131 132 struct serial_private { 133 struct pci_dev *dev; 134 unsigned int nr; 135 struct pci_serial_quirk *quirk; 136 const struct pciserial_board *board; 137 int line[]; 138 }; 139 140 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 141 142 static const struct pci_device_id pci_use_msi[] = { 143 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 144 0xA000, 0x1000) }, 145 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 146 0xA000, 0x1000) }, 147 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 148 0xA000, 0x1000) }, 149 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 150 0xA000, 0x1000) }, 151 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 152 PCI_ANY_ID, PCI_ANY_ID) }, 153 { } 154 }; 155 156 static int pci_default_setup(struct serial_private*, 157 const struct pciserial_board*, struct uart_8250_port *, int); 158 159 static void moan_device(const char *str, struct pci_dev *dev) 160 { 161 pci_err(dev, "%s\n" 162 "Please send the output of lspci -vv, this\n" 163 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 164 "manufacturer and name of serial board or\n" 165 "modem board to <linux-serial@vger.kernel.org>.\n", 166 str, dev->vendor, dev->device, 167 dev->subsystem_vendor, dev->subsystem_device); 168 } 169 170 static int 171 setup_port(struct serial_private *priv, struct uart_8250_port *port, 172 u8 bar, unsigned int offset, int regshift) 173 { 174 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); 175 } 176 177 /* 178 * ADDI-DATA GmbH communication cards <info@addi-data.com> 179 */ 180 static int addidata_apci7800_setup(struct serial_private *priv, 181 const struct pciserial_board *board, 182 struct uart_8250_port *port, int idx) 183 { 184 unsigned int bar = 0, offset = board->first_offset; 185 bar = FL_GET_BASE(board->flags); 186 187 if (idx < 2) { 188 offset += idx * board->uart_offset; 189 } else if ((idx >= 2) && (idx < 4)) { 190 bar += 1; 191 offset += ((idx - 2) * board->uart_offset); 192 } else if ((idx >= 4) && (idx < 6)) { 193 bar += 2; 194 offset += ((idx - 4) * board->uart_offset); 195 } else if (idx >= 6) { 196 bar += 3; 197 offset += ((idx - 6) * board->uart_offset); 198 } 199 200 return setup_port(priv, port, bar, offset, board->reg_shift); 201 } 202 203 /* 204 * AFAVLAB uses a different mixture of BARs and offsets 205 * Not that ugly ;) -- HW 206 */ 207 static int 208 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 209 struct uart_8250_port *port, int idx) 210 { 211 unsigned int bar, offset = board->first_offset; 212 213 bar = FL_GET_BASE(board->flags); 214 if (idx < 4) 215 bar += idx; 216 else { 217 bar = 4; 218 offset += (idx - 4) * board->uart_offset; 219 } 220 221 return setup_port(priv, port, bar, offset, board->reg_shift); 222 } 223 224 /* 225 * HP's Remote Management Console. The Diva chip came in several 226 * different versions. N-class, L2000 and A500 have two Diva chips, each 227 * with 3 UARTs (the third UART on the second chip is unused). Superdome 228 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 229 * one Diva chip, but it has been expanded to 5 UARTs. 230 */ 231 static int pci_hp_diva_init(struct pci_dev *dev) 232 { 233 int rc = 0; 234 235 switch (dev->subsystem_device) { 236 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 237 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 238 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 239 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 240 rc = 3; 241 break; 242 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 243 rc = 2; 244 break; 245 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 246 rc = 4; 247 break; 248 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 249 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 250 rc = 1; 251 break; 252 } 253 254 return rc; 255 } 256 257 /* 258 * HP's Diva chip puts the 4th/5th serial port further out, and 259 * some serial ports are supposed to be hidden on certain models. 260 */ 261 static int 262 pci_hp_diva_setup(struct serial_private *priv, 263 const struct pciserial_board *board, 264 struct uart_8250_port *port, int idx) 265 { 266 unsigned int offset = board->first_offset; 267 unsigned int bar = FL_GET_BASE(board->flags); 268 269 switch (priv->dev->subsystem_device) { 270 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 271 if (idx == 3) 272 idx++; 273 break; 274 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 275 if (idx > 0) 276 idx++; 277 if (idx > 2) 278 idx++; 279 break; 280 } 281 if (idx > 2) 282 offset = 0x18; 283 284 offset += idx * board->uart_offset; 285 286 return setup_port(priv, port, bar, offset, board->reg_shift); 287 } 288 289 /* 290 * Added for EKF Intel i960 serial boards 291 */ 292 static int pci_inteli960ni_init(struct pci_dev *dev) 293 { 294 u32 oldval; 295 296 if (!(dev->subsystem_device & 0x1000)) 297 return -ENODEV; 298 299 /* is firmware started? */ 300 pci_read_config_dword(dev, 0x44, &oldval); 301 if (oldval == 0x00001000L) { /* RESET value */ 302 pci_dbg(dev, "Local i960 firmware missing\n"); 303 return -ENODEV; 304 } 305 return 0; 306 } 307 308 /* 309 * Some PCI serial cards using the PLX 9050 PCI interface chip require 310 * that the card interrupt be explicitly enabled or disabled. This 311 * seems to be mainly needed on card using the PLX which also use I/O 312 * mapped memory. 313 */ 314 static int pci_plx9050_init(struct pci_dev *dev) 315 { 316 u8 irq_config; 317 void __iomem *p; 318 319 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 320 moan_device("no memory in bar 0", dev); 321 return 0; 322 } 323 324 irq_config = 0x41; 325 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 326 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 327 irq_config = 0x43; 328 329 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 330 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 331 /* 332 * As the megawolf cards have the int pins active 333 * high, and have 2 UART chips, both ints must be 334 * enabled on the 9050. Also, the UARTS are set in 335 * 16450 mode by default, so we have to enable the 336 * 16C950 'enhanced' mode so that we can use the 337 * deep FIFOs 338 */ 339 irq_config = 0x5b; 340 /* 341 * enable/disable interrupts 342 */ 343 p = ioremap(pci_resource_start(dev, 0), 0x80); 344 if (p == NULL) 345 return -ENOMEM; 346 writel(irq_config, p + 0x4c); 347 348 /* 349 * Read the register back to ensure that it took effect. 350 */ 351 readl(p + 0x4c); 352 iounmap(p); 353 354 return 0; 355 } 356 357 static void pci_plx9050_exit(struct pci_dev *dev) 358 { 359 u8 __iomem *p; 360 361 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 362 return; 363 364 /* 365 * disable interrupts 366 */ 367 p = ioremap(pci_resource_start(dev, 0), 0x80); 368 if (p != NULL) { 369 writel(0, p + 0x4c); 370 371 /* 372 * Read the register back to ensure that it took effect. 373 */ 374 readl(p + 0x4c); 375 iounmap(p); 376 } 377 } 378 379 #define NI8420_INT_ENABLE_REG 0x38 380 #define NI8420_INT_ENABLE_BIT 0x2000 381 382 static void pci_ni8420_exit(struct pci_dev *dev) 383 { 384 void __iomem *p; 385 unsigned int bar = 0; 386 387 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 388 moan_device("no memory in bar", dev); 389 return; 390 } 391 392 p = pci_ioremap_bar(dev, bar); 393 if (p == NULL) 394 return; 395 396 /* Disable the CPU Interrupt */ 397 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 398 p + NI8420_INT_ENABLE_REG); 399 iounmap(p); 400 } 401 402 403 /* MITE registers */ 404 #define MITE_IOWBSR1 0xc4 405 #define MITE_IOWCR1 0xf4 406 #define MITE_LCIMR1 0x08 407 #define MITE_LCIMR2 0x10 408 409 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 410 411 static void pci_ni8430_exit(struct pci_dev *dev) 412 { 413 void __iomem *p; 414 unsigned int bar = 0; 415 416 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 417 moan_device("no memory in bar", dev); 418 return; 419 } 420 421 p = pci_ioremap_bar(dev, bar); 422 if (p == NULL) 423 return; 424 425 /* Disable the CPU Interrupt */ 426 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 427 iounmap(p); 428 } 429 430 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 431 static int 432 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 433 struct uart_8250_port *port, int idx) 434 { 435 unsigned int bar, offset = board->first_offset; 436 437 bar = 0; 438 439 if (idx < 4) { 440 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 441 offset += idx * board->uart_offset; 442 } else if (idx < 8) { 443 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 444 offset += idx * board->uart_offset + 0xC00; 445 } else /* we have only 8 ports on PMC-OCTALPRO */ 446 return 1; 447 448 return setup_port(priv, port, bar, offset, board->reg_shift); 449 } 450 451 /* 452 * This does initialization for PMC OCTALPRO cards: 453 * maps the device memory, resets the UARTs (needed, bc 454 * if the module is removed and inserted again, the card 455 * is in the sleep mode) and enables global interrupt. 456 */ 457 458 /* global control register offset for SBS PMC-OctalPro */ 459 #define OCT_REG_CR_OFF 0x500 460 461 static int sbs_init(struct pci_dev *dev) 462 { 463 u8 __iomem *p; 464 465 p = pci_ioremap_bar(dev, 0); 466 467 if (p == NULL) 468 return -ENOMEM; 469 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 470 writeb(0x10, p + OCT_REG_CR_OFF); 471 udelay(50); 472 writeb(0x0, p + OCT_REG_CR_OFF); 473 474 /* Set bit-2 (INTENABLE) of Control Register */ 475 writeb(0x4, p + OCT_REG_CR_OFF); 476 iounmap(p); 477 478 return 0; 479 } 480 481 /* 482 * Disables the global interrupt of PMC-OctalPro 483 */ 484 485 static void sbs_exit(struct pci_dev *dev) 486 { 487 u8 __iomem *p; 488 489 p = pci_ioremap_bar(dev, 0); 490 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 491 if (p != NULL) 492 writeb(0, p + OCT_REG_CR_OFF); 493 iounmap(p); 494 } 495 496 /* 497 * SIIG serial cards have an PCI interface chip which also controls 498 * the UART clocking frequency. Each UART can be clocked independently 499 * (except cards equipped with 4 UARTs) and initial clocking settings 500 * are stored in the EEPROM chip. It can cause problems because this 501 * version of serial driver doesn't support differently clocked UART's 502 * on single PCI card. To prevent this, initialization functions set 503 * high frequency clocking for all UART's on given card. It is safe (I 504 * hope) because it doesn't touch EEPROM settings to prevent conflicts 505 * with other OSes (like M$ DOS). 506 * 507 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 508 * 509 * There is two family of SIIG serial cards with different PCI 510 * interface chip and different configuration methods: 511 * - 10x cards have control registers in IO and/or memory space; 512 * - 20x cards have control registers in standard PCI configuration space. 513 * 514 * Note: all 10x cards have PCI device ids 0x10.. 515 * all 20x cards have PCI device ids 0x20.. 516 * 517 * There are also Quartet Serial cards which use Oxford Semiconductor 518 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 519 * 520 * Note: some SIIG cards are probed by the parport_serial object. 521 */ 522 523 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 524 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 525 526 static int pci_siig10x_init(struct pci_dev *dev) 527 { 528 u16 data; 529 void __iomem *p; 530 531 switch (dev->device & 0xfff8) { 532 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 533 data = 0xffdf; 534 break; 535 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 536 data = 0xf7ff; 537 break; 538 default: /* 1S1P, 4S */ 539 data = 0xfffb; 540 break; 541 } 542 543 p = ioremap(pci_resource_start(dev, 0), 0x80); 544 if (p == NULL) 545 return -ENOMEM; 546 547 writew(readw(p + 0x28) & data, p + 0x28); 548 readw(p + 0x28); 549 iounmap(p); 550 return 0; 551 } 552 553 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 554 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 555 556 static int pci_siig20x_init(struct pci_dev *dev) 557 { 558 u8 data; 559 560 /* Change clock frequency for the first UART. */ 561 pci_read_config_byte(dev, 0x6f, &data); 562 pci_write_config_byte(dev, 0x6f, data & 0xef); 563 564 /* If this card has 2 UART, we have to do the same with second UART. */ 565 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 566 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 567 pci_read_config_byte(dev, 0x73, &data); 568 pci_write_config_byte(dev, 0x73, data & 0xef); 569 } 570 return 0; 571 } 572 573 static int pci_siig_init(struct pci_dev *dev) 574 { 575 unsigned int type = dev->device & 0xff00; 576 577 if (type == 0x1000) 578 return pci_siig10x_init(dev); 579 if (type == 0x2000) 580 return pci_siig20x_init(dev); 581 582 moan_device("Unknown SIIG card", dev); 583 return -ENODEV; 584 } 585 586 static int pci_siig_setup(struct serial_private *priv, 587 const struct pciserial_board *board, 588 struct uart_8250_port *port, int idx) 589 { 590 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 591 592 if (idx > 3) { 593 bar = 4; 594 offset = (idx - 4) * 8; 595 } 596 597 return setup_port(priv, port, bar, offset, 0); 598 } 599 600 /* 601 * Timedia has an explosion of boards, and to avoid the PCI table from 602 * growing *huge*, we use this function to collapse some 70 entries 603 * in the PCI table into one, for sanity's and compactness's sake. 604 */ 605 static const unsigned short timedia_single_port[] = { 606 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 607 }; 608 609 static const unsigned short timedia_dual_port[] = { 610 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 611 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 612 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 613 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 614 0xD079, 0 615 }; 616 617 static const unsigned short timedia_quad_port[] = { 618 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 619 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 620 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 621 0xB157, 0 622 }; 623 624 static const unsigned short timedia_eight_port[] = { 625 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 626 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 627 }; 628 629 static const struct timedia_struct { 630 int num; 631 const unsigned short *ids; 632 } timedia_data[] = { 633 { 1, timedia_single_port }, 634 { 2, timedia_dual_port }, 635 { 4, timedia_quad_port }, 636 { 8, timedia_eight_port } 637 }; 638 639 /* 640 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 641 * listing them individually, this driver merely grabs them all with 642 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 643 * and should be left free to be claimed by parport_serial instead. 644 */ 645 static int pci_timedia_probe(struct pci_dev *dev) 646 { 647 /* 648 * Check the third digit of the subdevice ID 649 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 650 */ 651 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 652 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 653 dev->subsystem_device); 654 return -ENODEV; 655 } 656 657 return 0; 658 } 659 660 static int pci_timedia_init(struct pci_dev *dev) 661 { 662 const unsigned short *ids; 663 int i, j; 664 665 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 666 ids = timedia_data[i].ids; 667 for (j = 0; ids[j]; j++) 668 if (dev->subsystem_device == ids[j]) 669 return timedia_data[i].num; 670 } 671 return 0; 672 } 673 674 /* 675 * Timedia/SUNIX uses a mixture of BARs and offsets 676 * Ugh, this is ugly as all hell --- TYT 677 */ 678 static int 679 pci_timedia_setup(struct serial_private *priv, 680 const struct pciserial_board *board, 681 struct uart_8250_port *port, int idx) 682 { 683 unsigned int bar = 0, offset = board->first_offset; 684 685 switch (idx) { 686 case 0: 687 bar = 0; 688 break; 689 case 1: 690 offset = board->uart_offset; 691 bar = 0; 692 break; 693 case 2: 694 bar = 1; 695 break; 696 case 3: 697 offset = board->uart_offset; 698 fallthrough; 699 case 4: /* BAR 2 */ 700 case 5: /* BAR 3 */ 701 case 6: /* BAR 4 */ 702 case 7: /* BAR 5 */ 703 bar = idx - 2; 704 } 705 706 return setup_port(priv, port, bar, offset, board->reg_shift); 707 } 708 709 /* 710 * Some Titan cards are also a little weird 711 */ 712 static int 713 titan_400l_800l_setup(struct serial_private *priv, 714 const struct pciserial_board *board, 715 struct uart_8250_port *port, int idx) 716 { 717 unsigned int bar, offset = board->first_offset; 718 719 switch (idx) { 720 case 0: 721 bar = 1; 722 break; 723 case 1: 724 bar = 2; 725 break; 726 default: 727 bar = 4; 728 offset = (idx - 2) * board->uart_offset; 729 } 730 731 return setup_port(priv, port, bar, offset, board->reg_shift); 732 } 733 734 static int pci_xircom_init(struct pci_dev *dev) 735 { 736 msleep(100); 737 return 0; 738 } 739 740 static int pci_ni8420_init(struct pci_dev *dev) 741 { 742 void __iomem *p; 743 unsigned int bar = 0; 744 745 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 746 moan_device("no memory in bar", dev); 747 return 0; 748 } 749 750 p = pci_ioremap_bar(dev, bar); 751 if (p == NULL) 752 return -ENOMEM; 753 754 /* Enable CPU Interrupt */ 755 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 756 p + NI8420_INT_ENABLE_REG); 757 758 iounmap(p); 759 return 0; 760 } 761 762 #define MITE_IOWBSR1_WSIZE 0xa 763 #define MITE_IOWBSR1_WIN_OFFSET 0x800 764 #define MITE_IOWBSR1_WENAB (1 << 7) 765 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 766 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 767 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 768 769 static int pci_ni8430_init(struct pci_dev *dev) 770 { 771 void __iomem *p; 772 struct pci_bus_region region; 773 u32 device_window; 774 unsigned int bar = 0; 775 776 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 777 moan_device("no memory in bar", dev); 778 return 0; 779 } 780 781 p = pci_ioremap_bar(dev, bar); 782 if (p == NULL) 783 return -ENOMEM; 784 785 /* 786 * Set device window address and size in BAR0, while acknowledging that 787 * the resource structure may contain a translated address that differs 788 * from the address the device responds to. 789 */ 790 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 791 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 792 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 793 writel(device_window, p + MITE_IOWBSR1); 794 795 /* Set window access to go to RAMSEL IO address space */ 796 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 797 p + MITE_IOWCR1); 798 799 /* Enable IO Bus Interrupt 0 */ 800 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 801 802 /* Enable CPU Interrupt */ 803 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 804 805 iounmap(p); 806 return 0; 807 } 808 809 /* UART Port Control Register */ 810 #define NI8430_PORTCON 0x0f 811 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 812 813 static int 814 pci_ni8430_setup(struct serial_private *priv, 815 const struct pciserial_board *board, 816 struct uart_8250_port *port, int idx) 817 { 818 struct pci_dev *dev = priv->dev; 819 void __iomem *p; 820 unsigned int bar, offset = board->first_offset; 821 822 if (idx >= board->num_ports) 823 return 1; 824 825 bar = FL_GET_BASE(board->flags); 826 offset += idx * board->uart_offset; 827 828 p = pci_ioremap_bar(dev, bar); 829 if (!p) 830 return -ENOMEM; 831 832 /* enable the transceiver */ 833 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 834 p + offset + NI8430_PORTCON); 835 836 iounmap(p); 837 838 return setup_port(priv, port, bar, offset, board->reg_shift); 839 } 840 841 static int pci_netmos_9900_setup(struct serial_private *priv, 842 const struct pciserial_board *board, 843 struct uart_8250_port *port, int idx) 844 { 845 unsigned int bar; 846 847 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 848 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 849 /* netmos apparently orders BARs by datasheet layout, so serial 850 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 851 */ 852 bar = 3 * idx; 853 854 return setup_port(priv, port, bar, 0, board->reg_shift); 855 } 856 857 return pci_default_setup(priv, board, port, idx); 858 } 859 860 /* the 99xx series comes with a range of device IDs and a variety 861 * of capabilities: 862 * 863 * 9900 has varying capabilities and can cascade to sub-controllers 864 * (cascading should be purely internal) 865 * 9904 is hardwired with 4 serial ports 866 * 9912 and 9922 are hardwired with 2 serial ports 867 */ 868 static int pci_netmos_9900_numports(struct pci_dev *dev) 869 { 870 unsigned int c = dev->class; 871 unsigned int pi; 872 unsigned short sub_serports; 873 874 pi = c & 0xff; 875 876 if (pi == 2) 877 return 1; 878 879 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 880 /* two possibilities: 0x30ps encodes number of parallel and 881 * serial ports, or 0x1000 indicates *something*. This is not 882 * immediately obvious, since the 2s1p+4s configuration seems 883 * to offer all functionality on functions 0..2, while still 884 * advertising the same function 3 as the 4s+2s1p config. 885 */ 886 sub_serports = dev->subsystem_device & 0xf; 887 if (sub_serports > 0) 888 return sub_serports; 889 890 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 891 return 0; 892 } 893 894 moan_device("unknown NetMos/Mostech program interface", dev); 895 return 0; 896 } 897 898 static int pci_netmos_init(struct pci_dev *dev) 899 { 900 /* subdevice 0x00PS means <P> parallel, <S> serial */ 901 unsigned int num_serial = dev->subsystem_device & 0xf; 902 903 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 904 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 905 return 0; 906 907 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 908 dev->subsystem_device == 0x0299) 909 return 0; 910 911 switch (dev->device) { /* FALLTHROUGH on all */ 912 case PCI_DEVICE_ID_NETMOS_9904: 913 case PCI_DEVICE_ID_NETMOS_9912: 914 case PCI_DEVICE_ID_NETMOS_9922: 915 case PCI_DEVICE_ID_NETMOS_9900: 916 num_serial = pci_netmos_9900_numports(dev); 917 break; 918 919 default: 920 break; 921 } 922 923 if (num_serial == 0) { 924 moan_device("unknown NetMos/Mostech device", dev); 925 return -ENODEV; 926 } 927 928 return num_serial; 929 } 930 931 /* 932 * These chips are available with optionally one parallel port and up to 933 * two serial ports. Unfortunately they all have the same product id. 934 * 935 * Basic configuration is done over a region of 32 I/O ports. The base 936 * ioport is called INTA or INTC, depending on docs/other drivers. 937 * 938 * The region of the 32 I/O ports is configured in POSIO0R... 939 */ 940 941 /* registers */ 942 #define ITE_887x_MISCR 0x9c 943 #define ITE_887x_INTCBAR 0x78 944 #define ITE_887x_UARTBAR 0x7c 945 #define ITE_887x_PS0BAR 0x10 946 #define ITE_887x_POSIO0 0x60 947 948 /* I/O space size */ 949 #define ITE_887x_IOSIZE 32 950 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 951 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 952 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 953 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 954 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 955 #define ITE_887x_POSIO_SPEED (3 << 29) 956 /* enable IO_Space bit */ 957 #define ITE_887x_POSIO_ENABLE (1 << 31) 958 959 /* inta_addr are the configuration addresses of the ITE */ 960 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 961 static int pci_ite887x_init(struct pci_dev *dev) 962 { 963 int ret, i, type; 964 struct resource *iobase = NULL; 965 u32 miscr, uartbar, ioport; 966 967 /* search for the base-ioport */ 968 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 969 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 970 "ite887x"); 971 if (iobase != NULL) { 972 /* write POSIO0R - speed | size | ioport */ 973 pci_write_config_dword(dev, ITE_887x_POSIO0, 974 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 975 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 976 /* write INTCBAR - ioport */ 977 pci_write_config_dword(dev, ITE_887x_INTCBAR, 978 inta_addr[i]); 979 ret = inb(inta_addr[i]); 980 if (ret != 0xff) { 981 /* ioport connected */ 982 break; 983 } 984 release_region(iobase->start, ITE_887x_IOSIZE); 985 } 986 } 987 988 if (i == ARRAY_SIZE(inta_addr)) { 989 pci_err(dev, "could not find iobase\n"); 990 return -ENODEV; 991 } 992 993 /* start of undocumented type checking (see parport_pc.c) */ 994 type = inb(iobase->start + 0x18) & 0x0f; 995 996 switch (type) { 997 case 0x2: /* ITE8871 (1P) */ 998 case 0xa: /* ITE8875 (1P) */ 999 ret = 0; 1000 break; 1001 case 0xe: /* ITE8872 (2S1P) */ 1002 ret = 2; 1003 break; 1004 case 0x6: /* ITE8873 (1S) */ 1005 ret = 1; 1006 break; 1007 case 0x8: /* ITE8874 (2S) */ 1008 ret = 2; 1009 break; 1010 default: 1011 moan_device("Unknown ITE887x", dev); 1012 ret = -ENODEV; 1013 } 1014 1015 /* configure all serial ports */ 1016 for (i = 0; i < ret; i++) { 1017 /* read the I/O port from the device */ 1018 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 1019 &ioport); 1020 ioport &= 0x0000FF00; /* the actual base address */ 1021 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 1022 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 1023 ITE_887x_POSIO_IOSIZE_8 | ioport); 1024 1025 /* write the ioport to the UARTBAR */ 1026 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 1027 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 1028 uartbar |= (ioport << (16 * i)); /* set the ioport */ 1029 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 1030 1031 /* get current config */ 1032 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 1033 /* disable interrupts (UARTx_Routing[3:0]) */ 1034 miscr &= ~(0xf << (12 - 4 * i)); 1035 /* activate the UART (UARTx_En) */ 1036 miscr |= 1 << (23 - i); 1037 /* write new config with activated UART */ 1038 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 1039 } 1040 1041 if (ret <= 0) { 1042 /* the device has no UARTs if we get here */ 1043 release_region(iobase->start, ITE_887x_IOSIZE); 1044 } 1045 1046 return ret; 1047 } 1048 1049 static void pci_ite887x_exit(struct pci_dev *dev) 1050 { 1051 u32 ioport; 1052 /* the ioport is bit 0-15 in POSIO0R */ 1053 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 1054 ioport &= 0xffff; 1055 release_region(ioport, ITE_887x_IOSIZE); 1056 } 1057 1058 /* 1059 * Oxford Semiconductor Inc. 1060 * Check if an OxSemi device is part of the Tornado range of devices. 1061 */ 1062 #define PCI_VENDOR_ID_ENDRUN 0x7401 1063 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1064 1065 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1066 { 1067 /* OxSemi Tornado devices are all 0xCxxx */ 1068 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1069 (dev->device & 0xf000) != 0xc000) 1070 return false; 1071 1072 /* EndRun devices are all 0xExxx */ 1073 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1074 (dev->device & 0xf000) != 0xe000) 1075 return false; 1076 1077 return true; 1078 } 1079 1080 /* 1081 * Determine the number of ports available on a Tornado device. 1082 */ 1083 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1084 { 1085 u8 __iomem *p; 1086 unsigned long deviceID; 1087 unsigned int number_uarts = 0; 1088 1089 if (!pci_oxsemi_tornado_p(dev)) 1090 return 0; 1091 1092 p = pci_iomap(dev, 0, 5); 1093 if (p == NULL) 1094 return -ENOMEM; 1095 1096 deviceID = ioread32(p); 1097 /* Tornado device */ 1098 if (deviceID == 0x07000200) { 1099 number_uarts = ioread8(p + 4); 1100 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1101 number_uarts, 1102 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1103 "EndRun" : "Oxford"); 1104 } 1105 pci_iounmap(dev, p); 1106 return number_uarts; 1107 } 1108 1109 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1110 #define OXSEMI_TORNADO_TCR_MASK 0xf 1111 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1112 #define OXSEMI_TORNADO_CPR_MIN 0x008 1113 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1114 1115 /* 1116 * Determine the oversampling rate, the clock prescaler, and the clock 1117 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1118 * which is four times the baud base, and the prescaler increments in 1119 * steps of 1/8. Therefore to make calculations on integers we need 1120 * to use a scaled clock rate, which is the baud base multiplied by 32 1121 * (or our assumed UART clock rate multiplied by 2). 1122 * 1123 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1124 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1125 * values between 1.000 and 63.875 inclusive (operation for values from 1126 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1127 * unsigned 16-bit integer. 1128 * 1129 * For the most accurate baud rate we use a table of predetermined 1130 * oversampling rates and clock prescalers that records all possible 1131 * products of the two parameters in the range from 4 up to 255 inclusive, 1132 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1133 * by 8. The table is sorted by the decreasing value of the oversampling 1134 * rate and ties are resolved by sorting by the decreasing value of the 1135 * product. This way preference is given to higher oversampling rates. 1136 * 1137 * We iterate over the table and choose the product of an oversampling 1138 * rate and a clock prescaler that gives the lowest integer division 1139 * result deviation, or if an exact integer divider is found we stop 1140 * looking for it right away. We do some fixup if the resulting clock 1141 * divisor required would be out of its unsigned 16-bit integer range. 1142 * 1143 * Finally we abuse the supposed fractional part returned to encode the 1144 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1145 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1146 */ 1147 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1148 unsigned int baud, 1149 unsigned int *frac) 1150 { 1151 static u8 p[][2] = { 1152 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1153 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1154 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1155 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1156 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1157 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1158 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1159 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1160 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1161 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1162 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1163 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1164 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1165 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1166 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1167 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1168 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1169 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1170 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1171 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1172 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1173 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1174 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1175 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1176 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1177 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1178 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1179 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1180 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1181 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1182 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1183 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1184 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1185 { 4, 9, }, { 4, 8, }, 1186 }; 1187 /* Scale the quotient for comparison to get the fractional part. */ 1188 const unsigned int quot_scale = 65536; 1189 unsigned int sclk = port->uartclk * 2; 1190 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1191 unsigned int best_squot; 1192 unsigned int squot; 1193 unsigned int quot; 1194 u16 cpr; 1195 u8 tcr; 1196 int i; 1197 1198 /* Old custom speed handling. */ 1199 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1200 unsigned int cust_div = port->custom_divisor; 1201 1202 quot = cust_div & UART_DIV_MAX; 1203 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1204 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1205 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1206 cpr = OXSEMI_TORNADO_CPR_DEF; 1207 } else { 1208 best_squot = quot_scale; 1209 for (i = 0; i < ARRAY_SIZE(p); i++) { 1210 unsigned int spre; 1211 unsigned int srem; 1212 u8 cp; 1213 u8 tc; 1214 1215 tc = p[i][0]; 1216 cp = p[i][1]; 1217 spre = tc * cp; 1218 1219 srem = sdiv % spre; 1220 if (srem > spre / 2) 1221 srem = spre - srem; 1222 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1223 1224 if (srem == 0) { 1225 tcr = tc; 1226 cpr = cp; 1227 quot = sdiv / spre; 1228 break; 1229 } else if (squot < best_squot) { 1230 best_squot = squot; 1231 tcr = tc; 1232 cpr = cp; 1233 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1234 } 1235 } 1236 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1237 quot % 2 == 0) { 1238 quot >>= 1; 1239 tcr <<= 1; 1240 } 1241 while (quot > UART_DIV_MAX) { 1242 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1243 quot >>= 1; 1244 tcr <<= 1; 1245 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1246 quot >>= 1; 1247 cpr <<= 1; 1248 } else { 1249 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1250 cpr = OXSEMI_TORNADO_CPR_MASK; 1251 } 1252 } 1253 } 1254 1255 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1256 return quot; 1257 } 1258 1259 /* 1260 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1261 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1262 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1263 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1264 * has to be written first, followed by CPR2, which occupies the location 1265 * of CKS used with earlier UART designs. 1266 */ 1267 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1268 unsigned int baud, 1269 unsigned int quot, 1270 unsigned int quot_frac) 1271 { 1272 struct uart_8250_port *up = up_to_u8250p(port); 1273 u8 cpr2 = quot_frac >> 16; 1274 u8 cpr = quot_frac >> 8; 1275 u8 tcr = quot_frac; 1276 1277 serial_icr_write(up, UART_TCR, tcr); 1278 serial_icr_write(up, UART_CPR, cpr); 1279 serial_icr_write(up, UART_CKS, cpr2); 1280 serial8250_do_set_divisor(port, baud, quot, 0); 1281 } 1282 1283 /* 1284 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1285 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1286 */ 1287 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1288 unsigned int mctrl) 1289 { 1290 struct uart_8250_port *up = up_to_u8250p(port); 1291 1292 up->mcr |= UART_MCR_CLKSEL; 1293 serial8250_do_set_mctrl(port, mctrl); 1294 } 1295 1296 /* 1297 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1298 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1299 */ 1300 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1301 const struct pciserial_board *board, 1302 struct uart_8250_port *up, int idx) 1303 { 1304 struct pci_dev *dev = priv->dev; 1305 1306 if (pci_oxsemi_tornado_p(dev)) { 1307 up->port.flags |= UPF_FULL_PROBE; 1308 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1309 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1310 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1311 } 1312 1313 return pci_default_setup(priv, board, up, idx); 1314 } 1315 1316 #define QPCR_TEST_FOR1 0x3F 1317 #define QPCR_TEST_GET1 0x00 1318 #define QPCR_TEST_FOR2 0x40 1319 #define QPCR_TEST_GET2 0x40 1320 #define QPCR_TEST_FOR3 0x80 1321 #define QPCR_TEST_GET3 0x40 1322 #define QPCR_TEST_FOR4 0xC0 1323 #define QPCR_TEST_GET4 0x80 1324 1325 #define QOPR_CLOCK_X1 0x0000 1326 #define QOPR_CLOCK_X2 0x0001 1327 #define QOPR_CLOCK_X4 0x0002 1328 #define QOPR_CLOCK_X8 0x0003 1329 #define QOPR_CLOCK_RATE_MASK 0x0003 1330 1331 /* Quatech devices have their own extra interface features */ 1332 static struct pci_device_id quatech_cards[] = { 1333 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1334 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1335 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1336 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1337 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1338 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1339 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1340 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1341 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1342 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1343 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1344 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1345 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1346 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1347 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1348 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1349 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1350 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1351 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1352 { 0, } 1353 }; 1354 1355 static int pci_quatech_rqopr(struct uart_8250_port *port) 1356 { 1357 unsigned long base = port->port.iobase; 1358 u8 LCR, val; 1359 1360 LCR = inb(base + UART_LCR); 1361 outb(0xBF, base + UART_LCR); 1362 val = inb(base + UART_SCR); 1363 outb(LCR, base + UART_LCR); 1364 return val; 1365 } 1366 1367 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1368 { 1369 unsigned long base = port->port.iobase; 1370 u8 LCR; 1371 1372 LCR = inb(base + UART_LCR); 1373 outb(0xBF, base + UART_LCR); 1374 inb(base + UART_SCR); 1375 outb(qopr, base + UART_SCR); 1376 outb(LCR, base + UART_LCR); 1377 } 1378 1379 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1380 { 1381 unsigned long base = port->port.iobase; 1382 u8 LCR, val, qmcr; 1383 1384 LCR = inb(base + UART_LCR); 1385 outb(0xBF, base + UART_LCR); 1386 val = inb(base + UART_SCR); 1387 outb(val | 0x10, base + UART_SCR); 1388 qmcr = inb(base + UART_MCR); 1389 outb(val, base + UART_SCR); 1390 outb(LCR, base + UART_LCR); 1391 1392 return qmcr; 1393 } 1394 1395 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1396 { 1397 unsigned long base = port->port.iobase; 1398 u8 LCR, val; 1399 1400 LCR = inb(base + UART_LCR); 1401 outb(0xBF, base + UART_LCR); 1402 val = inb(base + UART_SCR); 1403 outb(val | 0x10, base + UART_SCR); 1404 outb(qmcr, base + UART_MCR); 1405 outb(val, base + UART_SCR); 1406 outb(LCR, base + UART_LCR); 1407 } 1408 1409 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1410 { 1411 unsigned long base = port->port.iobase; 1412 u8 LCR, val; 1413 1414 LCR = inb(base + UART_LCR); 1415 outb(0xBF, base + UART_LCR); 1416 val = inb(base + UART_SCR); 1417 if (val & 0x20) { 1418 outb(0x80, UART_LCR); 1419 if (!(inb(UART_SCR) & 0x20)) { 1420 outb(LCR, base + UART_LCR); 1421 return 1; 1422 } 1423 } 1424 return 0; 1425 } 1426 1427 static int pci_quatech_test(struct uart_8250_port *port) 1428 { 1429 u8 reg, qopr; 1430 1431 qopr = pci_quatech_rqopr(port); 1432 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1433 reg = pci_quatech_rqopr(port) & 0xC0; 1434 if (reg != QPCR_TEST_GET1) 1435 return -EINVAL; 1436 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1437 reg = pci_quatech_rqopr(port) & 0xC0; 1438 if (reg != QPCR_TEST_GET2) 1439 return -EINVAL; 1440 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1441 reg = pci_quatech_rqopr(port) & 0xC0; 1442 if (reg != QPCR_TEST_GET3) 1443 return -EINVAL; 1444 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1445 reg = pci_quatech_rqopr(port) & 0xC0; 1446 if (reg != QPCR_TEST_GET4) 1447 return -EINVAL; 1448 1449 pci_quatech_wqopr(port, qopr); 1450 return 0; 1451 } 1452 1453 static int pci_quatech_clock(struct uart_8250_port *port) 1454 { 1455 u8 qopr, reg, set; 1456 unsigned long clock; 1457 1458 if (pci_quatech_test(port) < 0) 1459 return 1843200; 1460 1461 qopr = pci_quatech_rqopr(port); 1462 1463 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1464 reg = pci_quatech_rqopr(port); 1465 if (reg & QOPR_CLOCK_X8) { 1466 clock = 1843200; 1467 goto out; 1468 } 1469 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1470 reg = pci_quatech_rqopr(port); 1471 if (!(reg & QOPR_CLOCK_X8)) { 1472 clock = 1843200; 1473 goto out; 1474 } 1475 reg &= QOPR_CLOCK_X8; 1476 if (reg == QOPR_CLOCK_X2) { 1477 clock = 3685400; 1478 set = QOPR_CLOCK_X2; 1479 } else if (reg == QOPR_CLOCK_X4) { 1480 clock = 7372800; 1481 set = QOPR_CLOCK_X4; 1482 } else if (reg == QOPR_CLOCK_X8) { 1483 clock = 14745600; 1484 set = QOPR_CLOCK_X8; 1485 } else { 1486 clock = 1843200; 1487 set = QOPR_CLOCK_X1; 1488 } 1489 qopr &= ~QOPR_CLOCK_RATE_MASK; 1490 qopr |= set; 1491 1492 out: 1493 pci_quatech_wqopr(port, qopr); 1494 return clock; 1495 } 1496 1497 static int pci_quatech_rs422(struct uart_8250_port *port) 1498 { 1499 u8 qmcr; 1500 int rs422 = 0; 1501 1502 if (!pci_quatech_has_qmcr(port)) 1503 return 0; 1504 qmcr = pci_quatech_rqmcr(port); 1505 pci_quatech_wqmcr(port, 0xFF); 1506 if (pci_quatech_rqmcr(port)) 1507 rs422 = 1; 1508 pci_quatech_wqmcr(port, qmcr); 1509 return rs422; 1510 } 1511 1512 static int pci_quatech_init(struct pci_dev *dev) 1513 { 1514 const struct pci_device_id *match; 1515 bool amcc = false; 1516 1517 match = pci_match_id(quatech_cards, dev); 1518 if (match) 1519 amcc = match->driver_data; 1520 else 1521 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1522 1523 if (amcc) { 1524 unsigned long base = pci_resource_start(dev, 0); 1525 if (base) { 1526 u32 tmp; 1527 1528 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1529 tmp = inl(base + 0x3c); 1530 outl(tmp | 0x01000000, base + 0x3c); 1531 outl(tmp & ~0x01000000, base + 0x3c); 1532 } 1533 } 1534 return 0; 1535 } 1536 1537 static int pci_quatech_setup(struct serial_private *priv, 1538 const struct pciserial_board *board, 1539 struct uart_8250_port *port, int idx) 1540 { 1541 /* Needed by pci_quatech calls below */ 1542 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1543 /* Set up the clocking */ 1544 port->port.uartclk = pci_quatech_clock(port); 1545 /* For now just warn about RS422 */ 1546 if (pci_quatech_rs422(port)) 1547 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1548 return pci_default_setup(priv, board, port, idx); 1549 } 1550 1551 static int pci_default_setup(struct serial_private *priv, 1552 const struct pciserial_board *board, 1553 struct uart_8250_port *port, int idx) 1554 { 1555 unsigned int bar, offset = board->first_offset, maxnr; 1556 1557 bar = FL_GET_BASE(board->flags); 1558 if (board->flags & FL_BASE_BARS) 1559 bar += idx; 1560 else 1561 offset += idx * board->uart_offset; 1562 1563 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1564 (board->reg_shift + 3); 1565 1566 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1567 return 1; 1568 1569 return setup_port(priv, port, bar, offset, board->reg_shift); 1570 } 1571 1572 static int 1573 ce4100_serial_setup(struct serial_private *priv, 1574 const struct pciserial_board *board, 1575 struct uart_8250_port *port, int idx) 1576 { 1577 int ret; 1578 1579 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1580 port->port.iotype = UPIO_MEM32; 1581 port->port.type = PORT_XSCALE; 1582 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1583 port->port.regshift = 2; 1584 1585 return ret; 1586 } 1587 1588 static int 1589 pci_omegapci_setup(struct serial_private *priv, 1590 const struct pciserial_board *board, 1591 struct uart_8250_port *port, int idx) 1592 { 1593 return setup_port(priv, port, 2, idx * 8, 0); 1594 } 1595 1596 static int 1597 pci_brcm_trumanage_setup(struct serial_private *priv, 1598 const struct pciserial_board *board, 1599 struct uart_8250_port *port, int idx) 1600 { 1601 int ret = pci_default_setup(priv, board, port, idx); 1602 1603 port->port.type = PORT_BRCM_TRUMANAGE; 1604 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1605 return ret; 1606 } 1607 1608 /* RTS will control by MCR if this bit is 0 */ 1609 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1610 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1611 #define FINTEK_RTS_INVERT BIT(5) 1612 1613 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1614 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1615 struct serial_rs485 *rs485) 1616 { 1617 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1618 u8 setting; 1619 u8 *index = (u8 *) port->private_data; 1620 1621 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1622 1623 if (rs485->flags & SER_RS485_ENABLED) { 1624 /* Enable RTS H/W control mode */ 1625 setting |= FINTEK_RTS_CONTROL_BY_HW; 1626 1627 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1628 /* RTS driving high on TX */ 1629 setting &= ~FINTEK_RTS_INVERT; 1630 } else { 1631 /* RTS driving low on TX */ 1632 setting |= FINTEK_RTS_INVERT; 1633 } 1634 } else { 1635 /* Disable RTS H/W control mode */ 1636 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1637 } 1638 1639 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1640 1641 return 0; 1642 } 1643 1644 static const struct serial_rs485 pci_fintek_rs485_supported = { 1645 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 1646 /* F81504/508/512 does not support RTS delay before or after send */ 1647 }; 1648 1649 static int pci_fintek_setup(struct serial_private *priv, 1650 const struct pciserial_board *board, 1651 struct uart_8250_port *port, int idx) 1652 { 1653 struct pci_dev *pdev = priv->dev; 1654 u8 *data; 1655 u8 config_base; 1656 u16 iobase; 1657 1658 config_base = 0x40 + 0x08 * idx; 1659 1660 /* Get the io address from configuration space */ 1661 pci_read_config_word(pdev, config_base + 4, &iobase); 1662 1663 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1664 1665 port->port.iotype = UPIO_PORT; 1666 port->port.iobase = iobase; 1667 port->port.rs485_config = pci_fintek_rs485_config; 1668 port->port.rs485_supported = pci_fintek_rs485_supported; 1669 1670 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1671 if (!data) 1672 return -ENOMEM; 1673 1674 /* preserve index in PCI configuration space */ 1675 *data = idx; 1676 port->port.private_data = data; 1677 1678 return 0; 1679 } 1680 1681 static int pci_fintek_init(struct pci_dev *dev) 1682 { 1683 unsigned long iobase; 1684 u32 max_port, i; 1685 resource_size_t bar_data[3]; 1686 u8 config_base; 1687 struct serial_private *priv = pci_get_drvdata(dev); 1688 1689 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1690 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1691 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1692 return -ENODEV; 1693 1694 switch (dev->device) { 1695 case 0x1104: /* 4 ports */ 1696 case 0x1108: /* 8 ports */ 1697 max_port = dev->device & 0xff; 1698 break; 1699 case 0x1112: /* 12 ports */ 1700 max_port = 12; 1701 break; 1702 default: 1703 return -EINVAL; 1704 } 1705 1706 /* Get the io address dispatch from the BIOS */ 1707 bar_data[0] = pci_resource_start(dev, 5); 1708 bar_data[1] = pci_resource_start(dev, 4); 1709 bar_data[2] = pci_resource_start(dev, 3); 1710 1711 for (i = 0; i < max_port; ++i) { 1712 /* UART0 configuration offset start from 0x40 */ 1713 config_base = 0x40 + 0x08 * i; 1714 1715 /* Calculate Real IO Port */ 1716 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1717 1718 /* Enable UART I/O port */ 1719 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1720 1721 /* Select 128-byte FIFO and 8x FIFO threshold */ 1722 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1723 1724 /* LSB UART */ 1725 pci_write_config_byte(dev, config_base + 0x04, 1726 (u8)(iobase & 0xff)); 1727 1728 /* MSB UART */ 1729 pci_write_config_byte(dev, config_base + 0x05, 1730 (u8)((iobase & 0xff00) >> 8)); 1731 1732 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1733 1734 if (!priv) { 1735 /* First init without port data 1736 * force init to RS232 Mode 1737 */ 1738 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1739 } 1740 } 1741 1742 return max_port; 1743 } 1744 1745 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1746 { 1747 struct f815xxa_data *data = p->private_data; 1748 unsigned long flags; 1749 1750 spin_lock_irqsave(&data->lock, flags); 1751 writeb(value, p->membase + offset); 1752 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1753 spin_unlock_irqrestore(&data->lock, flags); 1754 } 1755 1756 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1757 const struct pciserial_board *board, 1758 struct uart_8250_port *port, int idx) 1759 { 1760 struct pci_dev *pdev = priv->dev; 1761 struct f815xxa_data *data; 1762 1763 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1764 if (!data) 1765 return -ENOMEM; 1766 1767 data->idx = idx; 1768 spin_lock_init(&data->lock); 1769 1770 port->port.private_data = data; 1771 port->port.iotype = UPIO_MEM; 1772 port->port.flags |= UPF_IOREMAP; 1773 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1774 port->port.serial_out = f815xxa_mem_serial_out; 1775 1776 return 0; 1777 } 1778 1779 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1780 { 1781 u32 max_port, i; 1782 int config_base; 1783 1784 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1785 return -ENODEV; 1786 1787 switch (dev->device) { 1788 case 0x1204: /* 4 ports */ 1789 case 0x1208: /* 8 ports */ 1790 max_port = dev->device & 0xff; 1791 break; 1792 case 0x1212: /* 12 ports */ 1793 max_port = 12; 1794 break; 1795 default: 1796 return -EINVAL; 1797 } 1798 1799 /* Set to mmio decode */ 1800 pci_write_config_byte(dev, 0x209, 0x40); 1801 1802 for (i = 0; i < max_port; ++i) { 1803 /* UART0 configuration offset start from 0x2A0 */ 1804 config_base = 0x2A0 + 0x08 * i; 1805 1806 /* Select 128-byte FIFO and 8x FIFO threshold */ 1807 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1808 1809 /* Enable UART I/O port */ 1810 pci_write_config_byte(dev, config_base + 0, 0x01); 1811 } 1812 1813 return max_port; 1814 } 1815 1816 static int skip_tx_en_setup(struct serial_private *priv, 1817 const struct pciserial_board *board, 1818 struct uart_8250_port *port, int idx) 1819 { 1820 port->port.quirks |= UPQ_NO_TXEN_TEST; 1821 pci_dbg(priv->dev, 1822 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1823 priv->dev->vendor, priv->dev->device, 1824 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1825 1826 return pci_default_setup(priv, board, port, idx); 1827 } 1828 1829 static void kt_handle_break(struct uart_port *p) 1830 { 1831 struct uart_8250_port *up = up_to_u8250p(p); 1832 /* 1833 * On receipt of a BI, serial device in Intel ME (Intel 1834 * management engine) needs to have its fifos cleared for sane 1835 * SOL (Serial Over Lan) output. 1836 */ 1837 serial8250_clear_and_reinit_fifos(up); 1838 } 1839 1840 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1841 { 1842 struct uart_8250_port *up = up_to_u8250p(p); 1843 unsigned int val; 1844 1845 /* 1846 * When the Intel ME (management engine) gets reset its serial 1847 * port registers could return 0 momentarily. Functions like 1848 * serial8250_console_write, read and save the IER, perform 1849 * some operation and then restore it. In order to avoid 1850 * setting IER register inadvertently to 0, if the value read 1851 * is 0, double check with ier value in uart_8250_port and use 1852 * that instead. up->ier should be the same value as what is 1853 * currently configured. 1854 */ 1855 val = inb(p->iobase + offset); 1856 if (offset == UART_IER) { 1857 if (val == 0) 1858 val = up->ier; 1859 } 1860 return val; 1861 } 1862 1863 static int kt_serial_setup(struct serial_private *priv, 1864 const struct pciserial_board *board, 1865 struct uart_8250_port *port, int idx) 1866 { 1867 port->port.flags |= UPF_BUG_THRE; 1868 port->port.serial_in = kt_serial_in; 1869 port->port.handle_break = kt_handle_break; 1870 return skip_tx_en_setup(priv, board, port, idx); 1871 } 1872 1873 static int pci_eg20t_init(struct pci_dev *dev) 1874 { 1875 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1876 return -ENODEV; 1877 #else 1878 return 0; 1879 #endif 1880 } 1881 1882 static int 1883 pci_wch_ch353_setup(struct serial_private *priv, 1884 const struct pciserial_board *board, 1885 struct uart_8250_port *port, int idx) 1886 { 1887 port->port.flags |= UPF_FIXED_TYPE; 1888 port->port.type = PORT_16550A; 1889 return pci_default_setup(priv, board, port, idx); 1890 } 1891 1892 static int 1893 pci_wch_ch355_setup(struct serial_private *priv, 1894 const struct pciserial_board *board, 1895 struct uart_8250_port *port, int idx) 1896 { 1897 port->port.flags |= UPF_FIXED_TYPE; 1898 port->port.type = PORT_16550A; 1899 return pci_default_setup(priv, board, port, idx); 1900 } 1901 1902 static int 1903 pci_wch_ch38x_setup(struct serial_private *priv, 1904 const struct pciserial_board *board, 1905 struct uart_8250_port *port, int idx) 1906 { 1907 port->port.flags |= UPF_FIXED_TYPE; 1908 port->port.type = PORT_16850; 1909 return pci_default_setup(priv, board, port, idx); 1910 } 1911 1912 1913 #define CH384_XINT_ENABLE_REG 0xEB 1914 #define CH384_XINT_ENABLE_BIT 0x02 1915 1916 static int pci_wch_ch38x_init(struct pci_dev *dev) 1917 { 1918 int max_port; 1919 unsigned long iobase; 1920 1921 1922 switch (dev->device) { 1923 case 0x3853: /* 8 ports */ 1924 max_port = 8; 1925 break; 1926 default: 1927 return -EINVAL; 1928 } 1929 1930 iobase = pci_resource_start(dev, 0); 1931 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1932 1933 return max_port; 1934 } 1935 1936 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1937 { 1938 unsigned long iobase; 1939 1940 iobase = pci_resource_start(dev, 0); 1941 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1942 } 1943 1944 1945 static int 1946 pci_sunix_setup(struct serial_private *priv, 1947 const struct pciserial_board *board, 1948 struct uart_8250_port *port, int idx) 1949 { 1950 int bar; 1951 int offset; 1952 1953 port->port.flags |= UPF_FIXED_TYPE; 1954 port->port.type = PORT_SUNIX; 1955 1956 if (idx < 4) { 1957 bar = 0; 1958 offset = idx * board->uart_offset; 1959 } else { 1960 bar = 1; 1961 idx -= 4; 1962 idx = div_s64_rem(idx, 4, &offset); 1963 offset = idx * 64 + offset * board->uart_offset; 1964 } 1965 1966 return setup_port(priv, port, bar, offset, 0); 1967 } 1968 1969 #define MOXA_PUART_GPIO_EN 0x09 1970 #define MOXA_PUART_GPIO_OUT 0x0A 1971 1972 #define MOXA_GPIO_PIN2 BIT(2) 1973 1974 #define MOXA_RS232 0x00 1975 #define MOXA_RS422 0x01 1976 #define MOXA_RS485_4W 0x0B 1977 #define MOXA_RS485_2W 0x0F 1978 #define MOXA_UIR_OFFSET 0x04 1979 #define MOXA_EVEN_RS_MASK GENMASK(3, 0) 1980 #define MOXA_ODD_RS_MASK GENMASK(7, 4) 1981 1982 enum { 1983 MOXA_SUPP_RS232 = BIT(0), 1984 MOXA_SUPP_RS422 = BIT(1), 1985 MOXA_SUPP_RS485 = BIT(2), 1986 }; 1987 1988 static bool pci_moxa_is_mini_pcie(unsigned short device) 1989 { 1990 if (device == PCI_DEVICE_ID_MOXA_CP102N || 1991 device == PCI_DEVICE_ID_MOXA_CP104N || 1992 device == PCI_DEVICE_ID_MOXA_CP112N || 1993 device == PCI_DEVICE_ID_MOXA_CP114N || 1994 device == PCI_DEVICE_ID_MOXA_CP132N || 1995 device == PCI_DEVICE_ID_MOXA_CP134N) 1996 return true; 1997 1998 return false; 1999 } 2000 2001 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev) 2002 { 2003 switch (dev->device & 0x0F00) { 2004 case 0x0000: 2005 case 0x0600: 2006 return MOXA_SUPP_RS232; 2007 case 0x0100: 2008 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 2009 case 0x0300: 2010 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 2011 } 2012 return 0; 2013 } 2014 2015 static int pci_moxa_set_interface(const struct pci_dev *dev, 2016 unsigned int port_idx, 2017 u8 mode) 2018 { 2019 resource_size_t iobar_addr = pci_resource_start(dev, 2); 2020 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2; 2021 u8 val; 2022 2023 val = inb(UIR_addr); 2024 2025 if (port_idx % 2) { 2026 val &= ~MOXA_ODD_RS_MASK; 2027 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode); 2028 } else { 2029 val &= ~MOXA_EVEN_RS_MASK; 2030 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode); 2031 } 2032 outb(val, UIR_addr); 2033 2034 return 0; 2035 } 2036 2037 static int pci_moxa_init(struct pci_dev *dev) 2038 { 2039 unsigned short device = dev->device; 2040 resource_size_t iobar_addr = pci_resource_start(dev, 2); 2041 unsigned int num_ports = (device & 0x00F0) >> 4, i; 2042 u8 val, init_mode = MOXA_RS232; 2043 2044 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) { 2045 init_mode = MOXA_RS422; 2046 } 2047 for (i = 0; i < num_ports; ++i) 2048 pci_moxa_set_interface(dev, i, init_mode); 2049 2050 /* 2051 * Enable hardware buffer to prevent break signal output when system boots up. 2052 * This hardware buffer is only supported on Mini PCIe series. 2053 */ 2054 if (pci_moxa_is_mini_pcie(device)) { 2055 /* Set GPIO direction */ 2056 val = inb(iobar_addr + MOXA_PUART_GPIO_EN); 2057 val |= MOXA_GPIO_PIN2; 2058 outb(val, iobar_addr + MOXA_PUART_GPIO_EN); 2059 /* Enable low GPIO */ 2060 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT); 2061 val &= ~MOXA_GPIO_PIN2; 2062 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT); 2063 } 2064 2065 return num_ports; 2066 } 2067 2068 static int 2069 pci_moxa_setup(struct serial_private *priv, 2070 const struct pciserial_board *board, 2071 struct uart_8250_port *port, int idx) 2072 { 2073 unsigned int bar = FL_GET_BASE(board->flags); 2074 int offset; 2075 2076 if (board->num_ports == 4 && idx == 3) 2077 offset = 7 * board->uart_offset; 2078 else 2079 offset = idx * board->uart_offset; 2080 2081 return setup_port(priv, port, bar, offset, 0); 2082 } 2083 2084 /* 2085 * Master list of serial port init/setup/exit quirks. 2086 * This does not describe the general nature of the port. 2087 * (ie, baud base, number and location of ports, etc) 2088 * 2089 * This list is ordered alphabetically by vendor then device. 2090 * Specific entries must come before more generic entries. 2091 */ 2092 static struct pci_serial_quirk pci_serial_quirks[] = { 2093 /* 2094 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2095 */ 2096 { 2097 .vendor = PCI_VENDOR_ID_AMCC, 2098 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2099 .subvendor = PCI_ANY_ID, 2100 .subdevice = PCI_ANY_ID, 2101 .setup = addidata_apci7800_setup, 2102 }, 2103 /* 2104 * AFAVLAB cards - these may be called via parport_serial 2105 * It is not clear whether this applies to all products. 2106 */ 2107 { 2108 .vendor = PCI_VENDOR_ID_AFAVLAB, 2109 .device = PCI_ANY_ID, 2110 .subvendor = PCI_ANY_ID, 2111 .subdevice = PCI_ANY_ID, 2112 .setup = afavlab_setup, 2113 }, 2114 /* 2115 * HP Diva 2116 */ 2117 { 2118 .vendor = PCI_VENDOR_ID_HP, 2119 .device = PCI_DEVICE_ID_HP_DIVA, 2120 .subvendor = PCI_ANY_ID, 2121 .subdevice = PCI_ANY_ID, 2122 .init = pci_hp_diva_init, 2123 .setup = pci_hp_diva_setup, 2124 }, 2125 /* 2126 * HPE PCI serial device 2127 */ 2128 { 2129 .vendor = PCI_VENDOR_ID_HP_3PAR, 2130 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2131 .subvendor = PCI_ANY_ID, 2132 .subdevice = PCI_ANY_ID, 2133 .setup = pci_hp_diva_setup, 2134 }, 2135 /* 2136 * Intel 2137 */ 2138 { 2139 .vendor = PCI_VENDOR_ID_INTEL, 2140 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2141 .subvendor = 0xe4bf, 2142 .subdevice = PCI_ANY_ID, 2143 .init = pci_inteli960ni_init, 2144 .setup = pci_default_setup, 2145 }, 2146 { 2147 .vendor = PCI_VENDOR_ID_INTEL, 2148 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2149 .subvendor = PCI_ANY_ID, 2150 .subdevice = PCI_ANY_ID, 2151 .setup = skip_tx_en_setup, 2152 }, 2153 { 2154 .vendor = PCI_VENDOR_ID_INTEL, 2155 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2156 .subvendor = PCI_ANY_ID, 2157 .subdevice = PCI_ANY_ID, 2158 .setup = skip_tx_en_setup, 2159 }, 2160 { 2161 .vendor = PCI_VENDOR_ID_INTEL, 2162 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2163 .subvendor = PCI_ANY_ID, 2164 .subdevice = PCI_ANY_ID, 2165 .setup = skip_tx_en_setup, 2166 }, 2167 { 2168 .vendor = PCI_VENDOR_ID_INTEL, 2169 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2170 .subvendor = PCI_ANY_ID, 2171 .subdevice = PCI_ANY_ID, 2172 .setup = ce4100_serial_setup, 2173 }, 2174 { 2175 .vendor = PCI_VENDOR_ID_INTEL, 2176 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2177 .subvendor = PCI_ANY_ID, 2178 .subdevice = PCI_ANY_ID, 2179 .setup = kt_serial_setup, 2180 }, 2181 /* 2182 * ITE 2183 */ 2184 { 2185 .vendor = PCI_VENDOR_ID_ITE, 2186 .device = PCI_DEVICE_ID_ITE_8872, 2187 .subvendor = PCI_ANY_ID, 2188 .subdevice = PCI_ANY_ID, 2189 .init = pci_ite887x_init, 2190 .setup = pci_default_setup, 2191 .exit = pci_ite887x_exit, 2192 }, 2193 /* 2194 * National Instruments 2195 */ 2196 { 2197 .vendor = PCI_VENDOR_ID_NI, 2198 .device = PCI_DEVICE_ID_NI_PCI23216, 2199 .subvendor = PCI_ANY_ID, 2200 .subdevice = PCI_ANY_ID, 2201 .init = pci_ni8420_init, 2202 .setup = pci_default_setup, 2203 .exit = pci_ni8420_exit, 2204 }, 2205 { 2206 .vendor = PCI_VENDOR_ID_NI, 2207 .device = PCI_DEVICE_ID_NI_PCI2328, 2208 .subvendor = PCI_ANY_ID, 2209 .subdevice = PCI_ANY_ID, 2210 .init = pci_ni8420_init, 2211 .setup = pci_default_setup, 2212 .exit = pci_ni8420_exit, 2213 }, 2214 { 2215 .vendor = PCI_VENDOR_ID_NI, 2216 .device = PCI_DEVICE_ID_NI_PCI2324, 2217 .subvendor = PCI_ANY_ID, 2218 .subdevice = PCI_ANY_ID, 2219 .init = pci_ni8420_init, 2220 .setup = pci_default_setup, 2221 .exit = pci_ni8420_exit, 2222 }, 2223 { 2224 .vendor = PCI_VENDOR_ID_NI, 2225 .device = PCI_DEVICE_ID_NI_PCI2322, 2226 .subvendor = PCI_ANY_ID, 2227 .subdevice = PCI_ANY_ID, 2228 .init = pci_ni8420_init, 2229 .setup = pci_default_setup, 2230 .exit = pci_ni8420_exit, 2231 }, 2232 { 2233 .vendor = PCI_VENDOR_ID_NI, 2234 .device = PCI_DEVICE_ID_NI_PCI2324I, 2235 .subvendor = PCI_ANY_ID, 2236 .subdevice = PCI_ANY_ID, 2237 .init = pci_ni8420_init, 2238 .setup = pci_default_setup, 2239 .exit = pci_ni8420_exit, 2240 }, 2241 { 2242 .vendor = PCI_VENDOR_ID_NI, 2243 .device = PCI_DEVICE_ID_NI_PCI2322I, 2244 .subvendor = PCI_ANY_ID, 2245 .subdevice = PCI_ANY_ID, 2246 .init = pci_ni8420_init, 2247 .setup = pci_default_setup, 2248 .exit = pci_ni8420_exit, 2249 }, 2250 { 2251 .vendor = PCI_VENDOR_ID_NI, 2252 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2253 .subvendor = PCI_ANY_ID, 2254 .subdevice = PCI_ANY_ID, 2255 .init = pci_ni8420_init, 2256 .setup = pci_default_setup, 2257 .exit = pci_ni8420_exit, 2258 }, 2259 { 2260 .vendor = PCI_VENDOR_ID_NI, 2261 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2262 .subvendor = PCI_ANY_ID, 2263 .subdevice = PCI_ANY_ID, 2264 .init = pci_ni8420_init, 2265 .setup = pci_default_setup, 2266 .exit = pci_ni8420_exit, 2267 }, 2268 { 2269 .vendor = PCI_VENDOR_ID_NI, 2270 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2271 .subvendor = PCI_ANY_ID, 2272 .subdevice = PCI_ANY_ID, 2273 .init = pci_ni8420_init, 2274 .setup = pci_default_setup, 2275 .exit = pci_ni8420_exit, 2276 }, 2277 { 2278 .vendor = PCI_VENDOR_ID_NI, 2279 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .init = pci_ni8420_init, 2283 .setup = pci_default_setup, 2284 .exit = pci_ni8420_exit, 2285 }, 2286 { 2287 .vendor = PCI_VENDOR_ID_NI, 2288 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2289 .subvendor = PCI_ANY_ID, 2290 .subdevice = PCI_ANY_ID, 2291 .init = pci_ni8420_init, 2292 .setup = pci_default_setup, 2293 .exit = pci_ni8420_exit, 2294 }, 2295 { 2296 .vendor = PCI_VENDOR_ID_NI, 2297 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2298 .subvendor = PCI_ANY_ID, 2299 .subdevice = PCI_ANY_ID, 2300 .init = pci_ni8420_init, 2301 .setup = pci_default_setup, 2302 .exit = pci_ni8420_exit, 2303 }, 2304 { 2305 .vendor = PCI_VENDOR_ID_NI, 2306 .device = PCI_ANY_ID, 2307 .subvendor = PCI_ANY_ID, 2308 .subdevice = PCI_ANY_ID, 2309 .init = pci_ni8430_init, 2310 .setup = pci_ni8430_setup, 2311 .exit = pci_ni8430_exit, 2312 }, 2313 /* Quatech */ 2314 { 2315 .vendor = PCI_VENDOR_ID_QUATECH, 2316 .device = PCI_ANY_ID, 2317 .subvendor = PCI_ANY_ID, 2318 .subdevice = PCI_ANY_ID, 2319 .init = pci_quatech_init, 2320 .setup = pci_quatech_setup, 2321 }, 2322 /* 2323 * Panacom 2324 */ 2325 { 2326 .vendor = PCI_VENDOR_ID_PANACOM, 2327 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2328 .subvendor = PCI_ANY_ID, 2329 .subdevice = PCI_ANY_ID, 2330 .init = pci_plx9050_init, 2331 .setup = pci_default_setup, 2332 .exit = pci_plx9050_exit, 2333 }, 2334 { 2335 .vendor = PCI_VENDOR_ID_PANACOM, 2336 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2337 .subvendor = PCI_ANY_ID, 2338 .subdevice = PCI_ANY_ID, 2339 .init = pci_plx9050_init, 2340 .setup = pci_default_setup, 2341 .exit = pci_plx9050_exit, 2342 }, 2343 /* 2344 * PLX 2345 */ 2346 { 2347 .vendor = PCI_VENDOR_ID_PLX, 2348 .device = PCI_DEVICE_ID_PLX_9050, 2349 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2350 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2351 .init = pci_plx9050_init, 2352 .setup = pci_default_setup, 2353 .exit = pci_plx9050_exit, 2354 }, 2355 { 2356 .vendor = PCI_VENDOR_ID_PLX, 2357 .device = PCI_DEVICE_ID_PLX_9050, 2358 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2359 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2360 .init = pci_plx9050_init, 2361 .setup = pci_default_setup, 2362 .exit = pci_plx9050_exit, 2363 }, 2364 { 2365 .vendor = PCI_VENDOR_ID_PLX, 2366 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2367 .subvendor = PCI_VENDOR_ID_PLX, 2368 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2369 .init = pci_plx9050_init, 2370 .setup = pci_default_setup, 2371 .exit = pci_plx9050_exit, 2372 }, 2373 /* 2374 * SBS Technologies, Inc., PMC-OCTALPRO 232 2375 */ 2376 { 2377 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2378 .device = PCI_DEVICE_ID_OCTPRO, 2379 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2380 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2381 .init = sbs_init, 2382 .setup = sbs_setup, 2383 .exit = sbs_exit, 2384 }, 2385 /* 2386 * SBS Technologies, Inc., PMC-OCTALPRO 422 2387 */ 2388 { 2389 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2390 .device = PCI_DEVICE_ID_OCTPRO, 2391 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2392 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2393 .init = sbs_init, 2394 .setup = sbs_setup, 2395 .exit = sbs_exit, 2396 }, 2397 /* 2398 * SBS Technologies, Inc., P-Octal 232 2399 */ 2400 { 2401 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2402 .device = PCI_DEVICE_ID_OCTPRO, 2403 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2404 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2405 .init = sbs_init, 2406 .setup = sbs_setup, 2407 .exit = sbs_exit, 2408 }, 2409 /* 2410 * SBS Technologies, Inc., P-Octal 422 2411 */ 2412 { 2413 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2414 .device = PCI_DEVICE_ID_OCTPRO, 2415 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2416 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2417 .init = sbs_init, 2418 .setup = sbs_setup, 2419 .exit = sbs_exit, 2420 }, 2421 /* 2422 * SIIG cards - these may be called via parport_serial 2423 */ 2424 { 2425 .vendor = PCI_VENDOR_ID_SIIG, 2426 .device = PCI_ANY_ID, 2427 .subvendor = PCI_ANY_ID, 2428 .subdevice = PCI_ANY_ID, 2429 .init = pci_siig_init, 2430 .setup = pci_siig_setup, 2431 }, 2432 /* 2433 * Titan cards 2434 */ 2435 { 2436 .vendor = PCI_VENDOR_ID_TITAN, 2437 .device = PCI_DEVICE_ID_TITAN_400L, 2438 .subvendor = PCI_ANY_ID, 2439 .subdevice = PCI_ANY_ID, 2440 .setup = titan_400l_800l_setup, 2441 }, 2442 { 2443 .vendor = PCI_VENDOR_ID_TITAN, 2444 .device = PCI_DEVICE_ID_TITAN_800L, 2445 .subvendor = PCI_ANY_ID, 2446 .subdevice = PCI_ANY_ID, 2447 .setup = titan_400l_800l_setup, 2448 }, 2449 /* 2450 * Timedia cards 2451 */ 2452 { 2453 .vendor = PCI_VENDOR_ID_TIMEDIA, 2454 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2455 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2456 .subdevice = PCI_ANY_ID, 2457 .probe = pci_timedia_probe, 2458 .init = pci_timedia_init, 2459 .setup = pci_timedia_setup, 2460 }, 2461 { 2462 .vendor = PCI_VENDOR_ID_TIMEDIA, 2463 .device = PCI_ANY_ID, 2464 .subvendor = PCI_ANY_ID, 2465 .subdevice = PCI_ANY_ID, 2466 .setup = pci_timedia_setup, 2467 }, 2468 /* 2469 * Sunix PCI serial boards 2470 */ 2471 { 2472 .vendor = PCI_VENDOR_ID_SUNIX, 2473 .device = PCI_DEVICE_ID_SUNIX_1999, 2474 .subvendor = PCI_VENDOR_ID_SUNIX, 2475 .subdevice = PCI_ANY_ID, 2476 .setup = pci_sunix_setup, 2477 }, 2478 /* 2479 * Xircom cards 2480 */ 2481 { 2482 .vendor = PCI_VENDOR_ID_XIRCOM, 2483 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2484 .subvendor = PCI_ANY_ID, 2485 .subdevice = PCI_ANY_ID, 2486 .init = pci_xircom_init, 2487 .setup = pci_default_setup, 2488 }, 2489 /* 2490 * Netmos cards - these may be called via parport_serial 2491 */ 2492 { 2493 .vendor = PCI_VENDOR_ID_NETMOS, 2494 .device = PCI_ANY_ID, 2495 .subvendor = PCI_ANY_ID, 2496 .subdevice = PCI_ANY_ID, 2497 .init = pci_netmos_init, 2498 .setup = pci_netmos_9900_setup, 2499 }, 2500 /* 2501 * EndRun Technologies 2502 */ 2503 { 2504 .vendor = PCI_VENDOR_ID_ENDRUN, 2505 .device = PCI_ANY_ID, 2506 .subvendor = PCI_ANY_ID, 2507 .subdevice = PCI_ANY_ID, 2508 .init = pci_oxsemi_tornado_init, 2509 .setup = pci_default_setup, 2510 }, 2511 /* 2512 * For Oxford Semiconductor Tornado based devices 2513 */ 2514 { 2515 .vendor = PCI_VENDOR_ID_OXSEMI, 2516 .device = PCI_ANY_ID, 2517 .subvendor = PCI_ANY_ID, 2518 .subdevice = PCI_ANY_ID, 2519 .init = pci_oxsemi_tornado_init, 2520 .setup = pci_oxsemi_tornado_setup, 2521 }, 2522 { 2523 .vendor = PCI_VENDOR_ID_MAINPINE, 2524 .device = PCI_ANY_ID, 2525 .subvendor = PCI_ANY_ID, 2526 .subdevice = PCI_ANY_ID, 2527 .init = pci_oxsemi_tornado_init, 2528 .setup = pci_oxsemi_tornado_setup, 2529 }, 2530 { 2531 .vendor = PCI_VENDOR_ID_DIGI, 2532 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2533 .subvendor = PCI_SUBVENDOR_ID_IBM, 2534 .subdevice = PCI_ANY_ID, 2535 .init = pci_oxsemi_tornado_init, 2536 .setup = pci_oxsemi_tornado_setup, 2537 }, 2538 /* 2539 * Brainboxes devices - all Oxsemi based 2540 */ 2541 { 2542 .vendor = PCI_VENDOR_ID_INTASHIELD, 2543 .device = 0x4027, 2544 .subvendor = PCI_ANY_ID, 2545 .subdevice = PCI_ANY_ID, 2546 .init = pci_oxsemi_tornado_init, 2547 .setup = pci_oxsemi_tornado_setup, 2548 }, 2549 { 2550 .vendor = PCI_VENDOR_ID_INTASHIELD, 2551 .device = 0x4028, 2552 .subvendor = PCI_ANY_ID, 2553 .subdevice = PCI_ANY_ID, 2554 .init = pci_oxsemi_tornado_init, 2555 .setup = pci_oxsemi_tornado_setup, 2556 }, 2557 { 2558 .vendor = PCI_VENDOR_ID_INTASHIELD, 2559 .device = 0x4029, 2560 .subvendor = PCI_ANY_ID, 2561 .subdevice = PCI_ANY_ID, 2562 .init = pci_oxsemi_tornado_init, 2563 .setup = pci_oxsemi_tornado_setup, 2564 }, 2565 { 2566 .vendor = PCI_VENDOR_ID_INTASHIELD, 2567 .device = 0x4019, 2568 .subvendor = PCI_ANY_ID, 2569 .subdevice = PCI_ANY_ID, 2570 .init = pci_oxsemi_tornado_init, 2571 .setup = pci_oxsemi_tornado_setup, 2572 }, 2573 { 2574 .vendor = PCI_VENDOR_ID_INTASHIELD, 2575 .device = 0x4016, 2576 .subvendor = PCI_ANY_ID, 2577 .subdevice = PCI_ANY_ID, 2578 .init = pci_oxsemi_tornado_init, 2579 .setup = pci_oxsemi_tornado_setup, 2580 }, 2581 { 2582 .vendor = PCI_VENDOR_ID_INTASHIELD, 2583 .device = 0x4015, 2584 .subvendor = PCI_ANY_ID, 2585 .subdevice = PCI_ANY_ID, 2586 .init = pci_oxsemi_tornado_init, 2587 .setup = pci_oxsemi_tornado_setup, 2588 }, 2589 { 2590 .vendor = PCI_VENDOR_ID_INTASHIELD, 2591 .device = 0x400A, 2592 .subvendor = PCI_ANY_ID, 2593 .subdevice = PCI_ANY_ID, 2594 .init = pci_oxsemi_tornado_init, 2595 .setup = pci_oxsemi_tornado_setup, 2596 }, 2597 { 2598 .vendor = PCI_VENDOR_ID_INTASHIELD, 2599 .device = 0x400E, 2600 .subvendor = PCI_ANY_ID, 2601 .subdevice = PCI_ANY_ID, 2602 .init = pci_oxsemi_tornado_init, 2603 .setup = pci_oxsemi_tornado_setup, 2604 }, 2605 { 2606 .vendor = PCI_VENDOR_ID_INTASHIELD, 2607 .device = 0x400C, 2608 .subvendor = PCI_ANY_ID, 2609 .subdevice = PCI_ANY_ID, 2610 .init = pci_oxsemi_tornado_init, 2611 .setup = pci_oxsemi_tornado_setup, 2612 }, 2613 { 2614 .vendor = PCI_VENDOR_ID_INTASHIELD, 2615 .device = 0x400B, 2616 .subvendor = PCI_ANY_ID, 2617 .subdevice = PCI_ANY_ID, 2618 .init = pci_oxsemi_tornado_init, 2619 .setup = pci_oxsemi_tornado_setup, 2620 }, 2621 { 2622 .vendor = PCI_VENDOR_ID_INTASHIELD, 2623 .device = 0x400F, 2624 .subvendor = PCI_ANY_ID, 2625 .subdevice = PCI_ANY_ID, 2626 .init = pci_oxsemi_tornado_init, 2627 .setup = pci_oxsemi_tornado_setup, 2628 }, 2629 { 2630 .vendor = PCI_VENDOR_ID_INTASHIELD, 2631 .device = 0x4010, 2632 .subvendor = PCI_ANY_ID, 2633 .subdevice = PCI_ANY_ID, 2634 .init = pci_oxsemi_tornado_init, 2635 .setup = pci_oxsemi_tornado_setup, 2636 }, 2637 { 2638 .vendor = PCI_VENDOR_ID_INTASHIELD, 2639 .device = 0x4011, 2640 .subvendor = PCI_ANY_ID, 2641 .subdevice = PCI_ANY_ID, 2642 .init = pci_oxsemi_tornado_init, 2643 .setup = pci_oxsemi_tornado_setup, 2644 }, 2645 { 2646 .vendor = PCI_VENDOR_ID_INTASHIELD, 2647 .device = 0x401D, 2648 .subvendor = PCI_ANY_ID, 2649 .subdevice = PCI_ANY_ID, 2650 .init = pci_oxsemi_tornado_init, 2651 .setup = pci_oxsemi_tornado_setup, 2652 }, 2653 { 2654 .vendor = PCI_VENDOR_ID_INTASHIELD, 2655 .device = 0x401E, 2656 .subvendor = PCI_ANY_ID, 2657 .subdevice = PCI_ANY_ID, 2658 .init = pci_oxsemi_tornado_init, 2659 .setup = pci_oxsemi_tornado_setup, 2660 }, 2661 { 2662 .vendor = PCI_VENDOR_ID_INTASHIELD, 2663 .device = 0x4013, 2664 .subvendor = PCI_ANY_ID, 2665 .subdevice = PCI_ANY_ID, 2666 .init = pci_oxsemi_tornado_init, 2667 .setup = pci_oxsemi_tornado_setup, 2668 }, 2669 { 2670 .vendor = PCI_VENDOR_ID_INTASHIELD, 2671 .device = 0x4017, 2672 .subvendor = PCI_ANY_ID, 2673 .subdevice = PCI_ANY_ID, 2674 .init = pci_oxsemi_tornado_init, 2675 .setup = pci_oxsemi_tornado_setup, 2676 }, 2677 { 2678 .vendor = PCI_VENDOR_ID_INTASHIELD, 2679 .device = 0x4018, 2680 .subvendor = PCI_ANY_ID, 2681 .subdevice = PCI_ANY_ID, 2682 .init = pci_oxsemi_tornado_init, 2683 .setup = pci_oxsemi_tornado_setup, 2684 }, 2685 { 2686 .vendor = PCI_VENDOR_ID_INTEL, 2687 .device = 0x8811, 2688 .subvendor = PCI_ANY_ID, 2689 .subdevice = PCI_ANY_ID, 2690 .init = pci_eg20t_init, 2691 .setup = pci_default_setup, 2692 }, 2693 { 2694 .vendor = PCI_VENDOR_ID_INTEL, 2695 .device = 0x8812, 2696 .subvendor = PCI_ANY_ID, 2697 .subdevice = PCI_ANY_ID, 2698 .init = pci_eg20t_init, 2699 .setup = pci_default_setup, 2700 }, 2701 { 2702 .vendor = PCI_VENDOR_ID_INTEL, 2703 .device = 0x8813, 2704 .subvendor = PCI_ANY_ID, 2705 .subdevice = PCI_ANY_ID, 2706 .init = pci_eg20t_init, 2707 .setup = pci_default_setup, 2708 }, 2709 { 2710 .vendor = PCI_VENDOR_ID_INTEL, 2711 .device = 0x8814, 2712 .subvendor = PCI_ANY_ID, 2713 .subdevice = PCI_ANY_ID, 2714 .init = pci_eg20t_init, 2715 .setup = pci_default_setup, 2716 }, 2717 { 2718 .vendor = 0x10DB, 2719 .device = 0x8027, 2720 .subvendor = PCI_ANY_ID, 2721 .subdevice = PCI_ANY_ID, 2722 .init = pci_eg20t_init, 2723 .setup = pci_default_setup, 2724 }, 2725 { 2726 .vendor = 0x10DB, 2727 .device = 0x8028, 2728 .subvendor = PCI_ANY_ID, 2729 .subdevice = PCI_ANY_ID, 2730 .init = pci_eg20t_init, 2731 .setup = pci_default_setup, 2732 }, 2733 { 2734 .vendor = 0x10DB, 2735 .device = 0x8029, 2736 .subvendor = PCI_ANY_ID, 2737 .subdevice = PCI_ANY_ID, 2738 .init = pci_eg20t_init, 2739 .setup = pci_default_setup, 2740 }, 2741 { 2742 .vendor = 0x10DB, 2743 .device = 0x800C, 2744 .subvendor = PCI_ANY_ID, 2745 .subdevice = PCI_ANY_ID, 2746 .init = pci_eg20t_init, 2747 .setup = pci_default_setup, 2748 }, 2749 { 2750 .vendor = 0x10DB, 2751 .device = 0x800D, 2752 .subvendor = PCI_ANY_ID, 2753 .subdevice = PCI_ANY_ID, 2754 .init = pci_eg20t_init, 2755 .setup = pci_default_setup, 2756 }, 2757 /* 2758 * Cronyx Omega PCI (PLX-chip based) 2759 */ 2760 { 2761 .vendor = PCI_VENDOR_ID_PLX, 2762 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2763 .subvendor = PCI_ANY_ID, 2764 .subdevice = PCI_ANY_ID, 2765 .setup = pci_omegapci_setup, 2766 }, 2767 /* WCH CH353 1S1P card (16550 clone) */ 2768 { 2769 .vendor = PCI_VENDOR_ID_WCH, 2770 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2771 .subvendor = PCI_ANY_ID, 2772 .subdevice = PCI_ANY_ID, 2773 .setup = pci_wch_ch353_setup, 2774 }, 2775 /* WCH CH353 2S1P card (16550 clone) */ 2776 { 2777 .vendor = PCI_VENDOR_ID_WCH, 2778 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2779 .subvendor = PCI_ANY_ID, 2780 .subdevice = PCI_ANY_ID, 2781 .setup = pci_wch_ch353_setup, 2782 }, 2783 /* WCH CH353 4S card (16550 clone) */ 2784 { 2785 .vendor = PCI_VENDOR_ID_WCH, 2786 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2787 .subvendor = PCI_ANY_ID, 2788 .subdevice = PCI_ANY_ID, 2789 .setup = pci_wch_ch353_setup, 2790 }, 2791 /* WCH CH353 2S1PF card (16550 clone) */ 2792 { 2793 .vendor = PCI_VENDOR_ID_WCH, 2794 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2795 .subvendor = PCI_ANY_ID, 2796 .subdevice = PCI_ANY_ID, 2797 .setup = pci_wch_ch353_setup, 2798 }, 2799 /* WCH CH352 2S card (16550 clone) */ 2800 { 2801 .vendor = PCI_VENDOR_ID_WCH, 2802 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2803 .subvendor = PCI_ANY_ID, 2804 .subdevice = PCI_ANY_ID, 2805 .setup = pci_wch_ch353_setup, 2806 }, 2807 /* WCH CH355 4S card (16550 clone) */ 2808 { 2809 .vendor = PCI_VENDOR_ID_WCH, 2810 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2811 .subvendor = PCI_ANY_ID, 2812 .subdevice = PCI_ANY_ID, 2813 .setup = pci_wch_ch355_setup, 2814 }, 2815 /* WCH CH382 2S card (16850 clone) */ 2816 { 2817 .vendor = PCIE_VENDOR_ID_WCH, 2818 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2819 .subvendor = PCI_ANY_ID, 2820 .subdevice = PCI_ANY_ID, 2821 .setup = pci_wch_ch38x_setup, 2822 }, 2823 /* WCH CH382 2S1P card (16850 clone) */ 2824 { 2825 .vendor = PCIE_VENDOR_ID_WCH, 2826 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2827 .subvendor = PCI_ANY_ID, 2828 .subdevice = PCI_ANY_ID, 2829 .setup = pci_wch_ch38x_setup, 2830 }, 2831 /* WCH CH384 4S card (16850 clone) */ 2832 { 2833 .vendor = PCIE_VENDOR_ID_WCH, 2834 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2835 .subvendor = PCI_ANY_ID, 2836 .subdevice = PCI_ANY_ID, 2837 .setup = pci_wch_ch38x_setup, 2838 }, 2839 /* WCH CH384 8S card (16850 clone) */ 2840 { 2841 .vendor = PCIE_VENDOR_ID_WCH, 2842 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2843 .subvendor = PCI_ANY_ID, 2844 .subdevice = PCI_ANY_ID, 2845 .init = pci_wch_ch38x_init, 2846 .exit = pci_wch_ch38x_exit, 2847 .setup = pci_wch_ch38x_setup, 2848 }, 2849 /* 2850 * Broadcom TruManage (NetXtreme) 2851 */ 2852 { 2853 .vendor = PCI_VENDOR_ID_BROADCOM, 2854 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2855 .subvendor = PCI_ANY_ID, 2856 .subdevice = PCI_ANY_ID, 2857 .setup = pci_brcm_trumanage_setup, 2858 }, 2859 { 2860 .vendor = 0x1c29, 2861 .device = 0x1104, 2862 .subvendor = PCI_ANY_ID, 2863 .subdevice = PCI_ANY_ID, 2864 .setup = pci_fintek_setup, 2865 .init = pci_fintek_init, 2866 }, 2867 { 2868 .vendor = 0x1c29, 2869 .device = 0x1108, 2870 .subvendor = PCI_ANY_ID, 2871 .subdevice = PCI_ANY_ID, 2872 .setup = pci_fintek_setup, 2873 .init = pci_fintek_init, 2874 }, 2875 { 2876 .vendor = 0x1c29, 2877 .device = 0x1112, 2878 .subvendor = PCI_ANY_ID, 2879 .subdevice = PCI_ANY_ID, 2880 .setup = pci_fintek_setup, 2881 .init = pci_fintek_init, 2882 }, 2883 /* 2884 * MOXA 2885 */ 2886 { 2887 .vendor = PCI_VENDOR_ID_MOXA, 2888 .device = PCI_ANY_ID, 2889 .subvendor = PCI_ANY_ID, 2890 .subdevice = PCI_ANY_ID, 2891 .init = pci_moxa_init, 2892 .setup = pci_moxa_setup, 2893 }, 2894 { 2895 .vendor = 0x1c29, 2896 .device = 0x1204, 2897 .subvendor = PCI_ANY_ID, 2898 .subdevice = PCI_ANY_ID, 2899 .setup = pci_fintek_f815xxa_setup, 2900 .init = pci_fintek_f815xxa_init, 2901 }, 2902 { 2903 .vendor = 0x1c29, 2904 .device = 0x1208, 2905 .subvendor = PCI_ANY_ID, 2906 .subdevice = PCI_ANY_ID, 2907 .setup = pci_fintek_f815xxa_setup, 2908 .init = pci_fintek_f815xxa_init, 2909 }, 2910 { 2911 .vendor = 0x1c29, 2912 .device = 0x1212, 2913 .subvendor = PCI_ANY_ID, 2914 .subdevice = PCI_ANY_ID, 2915 .setup = pci_fintek_f815xxa_setup, 2916 .init = pci_fintek_f815xxa_init, 2917 }, 2918 2919 /* 2920 * Default "match everything" terminator entry 2921 */ 2922 { 2923 .vendor = PCI_ANY_ID, 2924 .device = PCI_ANY_ID, 2925 .subvendor = PCI_ANY_ID, 2926 .subdevice = PCI_ANY_ID, 2927 .setup = pci_default_setup, 2928 } 2929 }; 2930 2931 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2932 { 2933 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2934 } 2935 2936 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2937 { 2938 struct pci_serial_quirk *quirk; 2939 2940 for (quirk = pci_serial_quirks; ; quirk++) 2941 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2942 quirk_id_matches(quirk->device, dev->device) && 2943 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2944 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2945 break; 2946 return quirk; 2947 } 2948 2949 /* 2950 * This is the configuration table for all of the PCI serial boards 2951 * which we support. It is directly indexed by the pci_board_num_t enum 2952 * value, which is encoded in the pci_device_id PCI probe table's 2953 * driver_data member. 2954 * 2955 * The makeup of these names are: 2956 * pbn_bn{_bt}_n_baud{_offsetinhex} 2957 * 2958 * bn = PCI BAR number 2959 * bt = Index using PCI BARs 2960 * n = number of serial ports 2961 * baud = baud rate 2962 * offsetinhex = offset for each sequential port (in hex) 2963 * 2964 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2965 * 2966 * Please note: in theory if n = 1, _bt infix should make no difference. 2967 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2968 */ 2969 enum pci_board_num_t { 2970 pbn_default = 0, 2971 2972 pbn_b0_1_115200, 2973 pbn_b0_2_115200, 2974 pbn_b0_4_115200, 2975 pbn_b0_5_115200, 2976 pbn_b0_8_115200, 2977 2978 pbn_b0_1_921600, 2979 pbn_b0_2_921600, 2980 pbn_b0_4_921600, 2981 2982 pbn_b0_2_1130000, 2983 2984 pbn_b0_4_1152000, 2985 2986 pbn_b0_4_1250000, 2987 2988 pbn_b0_2_1843200, 2989 pbn_b0_4_1843200, 2990 2991 pbn_b0_1_15625000, 2992 2993 pbn_b0_bt_1_115200, 2994 pbn_b0_bt_2_115200, 2995 pbn_b0_bt_4_115200, 2996 pbn_b0_bt_8_115200, 2997 2998 pbn_b0_bt_1_460800, 2999 pbn_b0_bt_2_460800, 3000 pbn_b0_bt_4_460800, 3001 3002 pbn_b0_bt_1_921600, 3003 pbn_b0_bt_2_921600, 3004 pbn_b0_bt_4_921600, 3005 pbn_b0_bt_8_921600, 3006 3007 pbn_b1_1_115200, 3008 pbn_b1_2_115200, 3009 pbn_b1_4_115200, 3010 pbn_b1_8_115200, 3011 pbn_b1_16_115200, 3012 3013 pbn_b1_1_921600, 3014 pbn_b1_2_921600, 3015 pbn_b1_4_921600, 3016 pbn_b1_8_921600, 3017 3018 pbn_b1_2_1250000, 3019 3020 pbn_b1_bt_1_115200, 3021 pbn_b1_bt_2_115200, 3022 pbn_b1_bt_4_115200, 3023 3024 pbn_b1_bt_2_921600, 3025 3026 pbn_b1_1_1382400, 3027 pbn_b1_2_1382400, 3028 pbn_b1_4_1382400, 3029 pbn_b1_8_1382400, 3030 3031 pbn_b2_1_115200, 3032 pbn_b2_2_115200, 3033 pbn_b2_4_115200, 3034 pbn_b2_8_115200, 3035 3036 pbn_b2_1_460800, 3037 pbn_b2_4_460800, 3038 pbn_b2_8_460800, 3039 pbn_b2_16_460800, 3040 3041 pbn_b2_1_921600, 3042 pbn_b2_4_921600, 3043 pbn_b2_8_921600, 3044 3045 pbn_b2_8_1152000, 3046 3047 pbn_b2_bt_1_115200, 3048 pbn_b2_bt_2_115200, 3049 pbn_b2_bt_4_115200, 3050 3051 pbn_b2_bt_2_921600, 3052 pbn_b2_bt_4_921600, 3053 3054 pbn_b3_2_115200, 3055 pbn_b3_4_115200, 3056 pbn_b3_8_115200, 3057 3058 pbn_b4_bt_2_921600, 3059 pbn_b4_bt_4_921600, 3060 pbn_b4_bt_8_921600, 3061 3062 /* 3063 * Board-specific versions. 3064 */ 3065 pbn_panacom, 3066 pbn_panacom2, 3067 pbn_panacom4, 3068 pbn_plx_romulus, 3069 pbn_oxsemi, 3070 pbn_oxsemi_1_15625000, 3071 pbn_oxsemi_2_15625000, 3072 pbn_oxsemi_4_15625000, 3073 pbn_oxsemi_8_15625000, 3074 pbn_intel_i960, 3075 pbn_sgi_ioc3, 3076 pbn_computone_4, 3077 pbn_computone_6, 3078 pbn_computone_8, 3079 pbn_sbsxrsio, 3080 pbn_pasemi_1682M, 3081 pbn_ni8430_2, 3082 pbn_ni8430_4, 3083 pbn_ni8430_8, 3084 pbn_ni8430_16, 3085 pbn_ADDIDATA_PCIe_1_3906250, 3086 pbn_ADDIDATA_PCIe_2_3906250, 3087 pbn_ADDIDATA_PCIe_4_3906250, 3088 pbn_ADDIDATA_PCIe_8_3906250, 3089 pbn_ce4100_1_115200, 3090 pbn_omegapci, 3091 pbn_NETMOS9900_2s_115200, 3092 pbn_brcm_trumanage, 3093 pbn_fintek_4, 3094 pbn_fintek_8, 3095 pbn_fintek_12, 3096 pbn_fintek_F81504A, 3097 pbn_fintek_F81508A, 3098 pbn_fintek_F81512A, 3099 pbn_wch382_2, 3100 pbn_wch384_4, 3101 pbn_wch384_8, 3102 pbn_sunix_pci_1s, 3103 pbn_sunix_pci_2s, 3104 pbn_sunix_pci_4s, 3105 pbn_sunix_pci_8s, 3106 pbn_sunix_pci_16s, 3107 pbn_titan_1_4000000, 3108 pbn_titan_2_4000000, 3109 pbn_titan_4_4000000, 3110 pbn_titan_8_4000000, 3111 pbn_moxa_2, 3112 pbn_moxa_4, 3113 pbn_moxa_8, 3114 }; 3115 3116 /* 3117 * uart_offset - the space between channels 3118 * reg_shift - describes how the UART registers are mapped 3119 * to PCI memory by the card. 3120 * For example IER register on SBS, Inc. PMC-OctPro is located at 3121 * offset 0x10 from the UART base, while UART_IER is defined as 1 3122 * in include/linux/serial_reg.h, 3123 * see first lines of serial_in() and serial_out() in 8250.c 3124 */ 3125 3126 static struct pciserial_board pci_boards[] = { 3127 [pbn_default] = { 3128 .flags = FL_BASE0, 3129 .num_ports = 1, 3130 .base_baud = 115200, 3131 .uart_offset = 8, 3132 }, 3133 [pbn_b0_1_115200] = { 3134 .flags = FL_BASE0, 3135 .num_ports = 1, 3136 .base_baud = 115200, 3137 .uart_offset = 8, 3138 }, 3139 [pbn_b0_2_115200] = { 3140 .flags = FL_BASE0, 3141 .num_ports = 2, 3142 .base_baud = 115200, 3143 .uart_offset = 8, 3144 }, 3145 [pbn_b0_4_115200] = { 3146 .flags = FL_BASE0, 3147 .num_ports = 4, 3148 .base_baud = 115200, 3149 .uart_offset = 8, 3150 }, 3151 [pbn_b0_5_115200] = { 3152 .flags = FL_BASE0, 3153 .num_ports = 5, 3154 .base_baud = 115200, 3155 .uart_offset = 8, 3156 }, 3157 [pbn_b0_8_115200] = { 3158 .flags = FL_BASE0, 3159 .num_ports = 8, 3160 .base_baud = 115200, 3161 .uart_offset = 8, 3162 }, 3163 [pbn_b0_1_921600] = { 3164 .flags = FL_BASE0, 3165 .num_ports = 1, 3166 .base_baud = 921600, 3167 .uart_offset = 8, 3168 }, 3169 [pbn_b0_2_921600] = { 3170 .flags = FL_BASE0, 3171 .num_ports = 2, 3172 .base_baud = 921600, 3173 .uart_offset = 8, 3174 }, 3175 [pbn_b0_4_921600] = { 3176 .flags = FL_BASE0, 3177 .num_ports = 4, 3178 .base_baud = 921600, 3179 .uart_offset = 8, 3180 }, 3181 3182 [pbn_b0_2_1130000] = { 3183 .flags = FL_BASE0, 3184 .num_ports = 2, 3185 .base_baud = 1130000, 3186 .uart_offset = 8, 3187 }, 3188 3189 [pbn_b0_4_1152000] = { 3190 .flags = FL_BASE0, 3191 .num_ports = 4, 3192 .base_baud = 1152000, 3193 .uart_offset = 8, 3194 }, 3195 3196 [pbn_b0_4_1250000] = { 3197 .flags = FL_BASE0, 3198 .num_ports = 4, 3199 .base_baud = 1250000, 3200 .uart_offset = 8, 3201 }, 3202 3203 [pbn_b0_2_1843200] = { 3204 .flags = FL_BASE0, 3205 .num_ports = 2, 3206 .base_baud = 1843200, 3207 .uart_offset = 8, 3208 }, 3209 [pbn_b0_4_1843200] = { 3210 .flags = FL_BASE0, 3211 .num_ports = 4, 3212 .base_baud = 1843200, 3213 .uart_offset = 8, 3214 }, 3215 3216 [pbn_b0_1_15625000] = { 3217 .flags = FL_BASE0, 3218 .num_ports = 1, 3219 .base_baud = 15625000, 3220 .uart_offset = 8, 3221 }, 3222 3223 [pbn_b0_bt_1_115200] = { 3224 .flags = FL_BASE0|FL_BASE_BARS, 3225 .num_ports = 1, 3226 .base_baud = 115200, 3227 .uart_offset = 8, 3228 }, 3229 [pbn_b0_bt_2_115200] = { 3230 .flags = FL_BASE0|FL_BASE_BARS, 3231 .num_ports = 2, 3232 .base_baud = 115200, 3233 .uart_offset = 8, 3234 }, 3235 [pbn_b0_bt_4_115200] = { 3236 .flags = FL_BASE0|FL_BASE_BARS, 3237 .num_ports = 4, 3238 .base_baud = 115200, 3239 .uart_offset = 8, 3240 }, 3241 [pbn_b0_bt_8_115200] = { 3242 .flags = FL_BASE0|FL_BASE_BARS, 3243 .num_ports = 8, 3244 .base_baud = 115200, 3245 .uart_offset = 8, 3246 }, 3247 3248 [pbn_b0_bt_1_460800] = { 3249 .flags = FL_BASE0|FL_BASE_BARS, 3250 .num_ports = 1, 3251 .base_baud = 460800, 3252 .uart_offset = 8, 3253 }, 3254 [pbn_b0_bt_2_460800] = { 3255 .flags = FL_BASE0|FL_BASE_BARS, 3256 .num_ports = 2, 3257 .base_baud = 460800, 3258 .uart_offset = 8, 3259 }, 3260 [pbn_b0_bt_4_460800] = { 3261 .flags = FL_BASE0|FL_BASE_BARS, 3262 .num_ports = 4, 3263 .base_baud = 460800, 3264 .uart_offset = 8, 3265 }, 3266 3267 [pbn_b0_bt_1_921600] = { 3268 .flags = FL_BASE0|FL_BASE_BARS, 3269 .num_ports = 1, 3270 .base_baud = 921600, 3271 .uart_offset = 8, 3272 }, 3273 [pbn_b0_bt_2_921600] = { 3274 .flags = FL_BASE0|FL_BASE_BARS, 3275 .num_ports = 2, 3276 .base_baud = 921600, 3277 .uart_offset = 8, 3278 }, 3279 [pbn_b0_bt_4_921600] = { 3280 .flags = FL_BASE0|FL_BASE_BARS, 3281 .num_ports = 4, 3282 .base_baud = 921600, 3283 .uart_offset = 8, 3284 }, 3285 [pbn_b0_bt_8_921600] = { 3286 .flags = FL_BASE0|FL_BASE_BARS, 3287 .num_ports = 8, 3288 .base_baud = 921600, 3289 .uart_offset = 8, 3290 }, 3291 3292 [pbn_b1_1_115200] = { 3293 .flags = FL_BASE1, 3294 .num_ports = 1, 3295 .base_baud = 115200, 3296 .uart_offset = 8, 3297 }, 3298 [pbn_b1_2_115200] = { 3299 .flags = FL_BASE1, 3300 .num_ports = 2, 3301 .base_baud = 115200, 3302 .uart_offset = 8, 3303 }, 3304 [pbn_b1_4_115200] = { 3305 .flags = FL_BASE1, 3306 .num_ports = 4, 3307 .base_baud = 115200, 3308 .uart_offset = 8, 3309 }, 3310 [pbn_b1_8_115200] = { 3311 .flags = FL_BASE1, 3312 .num_ports = 8, 3313 .base_baud = 115200, 3314 .uart_offset = 8, 3315 }, 3316 [pbn_b1_16_115200] = { 3317 .flags = FL_BASE1, 3318 .num_ports = 16, 3319 .base_baud = 115200, 3320 .uart_offset = 8, 3321 }, 3322 3323 [pbn_b1_1_921600] = { 3324 .flags = FL_BASE1, 3325 .num_ports = 1, 3326 .base_baud = 921600, 3327 .uart_offset = 8, 3328 }, 3329 [pbn_b1_2_921600] = { 3330 .flags = FL_BASE1, 3331 .num_ports = 2, 3332 .base_baud = 921600, 3333 .uart_offset = 8, 3334 }, 3335 [pbn_b1_4_921600] = { 3336 .flags = FL_BASE1, 3337 .num_ports = 4, 3338 .base_baud = 921600, 3339 .uart_offset = 8, 3340 }, 3341 [pbn_b1_8_921600] = { 3342 .flags = FL_BASE1, 3343 .num_ports = 8, 3344 .base_baud = 921600, 3345 .uart_offset = 8, 3346 }, 3347 [pbn_b1_2_1250000] = { 3348 .flags = FL_BASE1, 3349 .num_ports = 2, 3350 .base_baud = 1250000, 3351 .uart_offset = 8, 3352 }, 3353 3354 [pbn_b1_bt_1_115200] = { 3355 .flags = FL_BASE1|FL_BASE_BARS, 3356 .num_ports = 1, 3357 .base_baud = 115200, 3358 .uart_offset = 8, 3359 }, 3360 [pbn_b1_bt_2_115200] = { 3361 .flags = FL_BASE1|FL_BASE_BARS, 3362 .num_ports = 2, 3363 .base_baud = 115200, 3364 .uart_offset = 8, 3365 }, 3366 [pbn_b1_bt_4_115200] = { 3367 .flags = FL_BASE1|FL_BASE_BARS, 3368 .num_ports = 4, 3369 .base_baud = 115200, 3370 .uart_offset = 8, 3371 }, 3372 3373 [pbn_b1_bt_2_921600] = { 3374 .flags = FL_BASE1|FL_BASE_BARS, 3375 .num_ports = 2, 3376 .base_baud = 921600, 3377 .uart_offset = 8, 3378 }, 3379 3380 [pbn_b1_1_1382400] = { 3381 .flags = FL_BASE1, 3382 .num_ports = 1, 3383 .base_baud = 1382400, 3384 .uart_offset = 8, 3385 }, 3386 [pbn_b1_2_1382400] = { 3387 .flags = FL_BASE1, 3388 .num_ports = 2, 3389 .base_baud = 1382400, 3390 .uart_offset = 8, 3391 }, 3392 [pbn_b1_4_1382400] = { 3393 .flags = FL_BASE1, 3394 .num_ports = 4, 3395 .base_baud = 1382400, 3396 .uart_offset = 8, 3397 }, 3398 [pbn_b1_8_1382400] = { 3399 .flags = FL_BASE1, 3400 .num_ports = 8, 3401 .base_baud = 1382400, 3402 .uart_offset = 8, 3403 }, 3404 3405 [pbn_b2_1_115200] = { 3406 .flags = FL_BASE2, 3407 .num_ports = 1, 3408 .base_baud = 115200, 3409 .uart_offset = 8, 3410 }, 3411 [pbn_b2_2_115200] = { 3412 .flags = FL_BASE2, 3413 .num_ports = 2, 3414 .base_baud = 115200, 3415 .uart_offset = 8, 3416 }, 3417 [pbn_b2_4_115200] = { 3418 .flags = FL_BASE2, 3419 .num_ports = 4, 3420 .base_baud = 115200, 3421 .uart_offset = 8, 3422 }, 3423 [pbn_b2_8_115200] = { 3424 .flags = FL_BASE2, 3425 .num_ports = 8, 3426 .base_baud = 115200, 3427 .uart_offset = 8, 3428 }, 3429 3430 [pbn_b2_1_460800] = { 3431 .flags = FL_BASE2, 3432 .num_ports = 1, 3433 .base_baud = 460800, 3434 .uart_offset = 8, 3435 }, 3436 [pbn_b2_4_460800] = { 3437 .flags = FL_BASE2, 3438 .num_ports = 4, 3439 .base_baud = 460800, 3440 .uart_offset = 8, 3441 }, 3442 [pbn_b2_8_460800] = { 3443 .flags = FL_BASE2, 3444 .num_ports = 8, 3445 .base_baud = 460800, 3446 .uart_offset = 8, 3447 }, 3448 [pbn_b2_16_460800] = { 3449 .flags = FL_BASE2, 3450 .num_ports = 16, 3451 .base_baud = 460800, 3452 .uart_offset = 8, 3453 }, 3454 3455 [pbn_b2_1_921600] = { 3456 .flags = FL_BASE2, 3457 .num_ports = 1, 3458 .base_baud = 921600, 3459 .uart_offset = 8, 3460 }, 3461 [pbn_b2_4_921600] = { 3462 .flags = FL_BASE2, 3463 .num_ports = 4, 3464 .base_baud = 921600, 3465 .uart_offset = 8, 3466 }, 3467 [pbn_b2_8_921600] = { 3468 .flags = FL_BASE2, 3469 .num_ports = 8, 3470 .base_baud = 921600, 3471 .uart_offset = 8, 3472 }, 3473 3474 [pbn_b2_8_1152000] = { 3475 .flags = FL_BASE2, 3476 .num_ports = 8, 3477 .base_baud = 1152000, 3478 .uart_offset = 8, 3479 }, 3480 3481 [pbn_b2_bt_1_115200] = { 3482 .flags = FL_BASE2|FL_BASE_BARS, 3483 .num_ports = 1, 3484 .base_baud = 115200, 3485 .uart_offset = 8, 3486 }, 3487 [pbn_b2_bt_2_115200] = { 3488 .flags = FL_BASE2|FL_BASE_BARS, 3489 .num_ports = 2, 3490 .base_baud = 115200, 3491 .uart_offset = 8, 3492 }, 3493 [pbn_b2_bt_4_115200] = { 3494 .flags = FL_BASE2|FL_BASE_BARS, 3495 .num_ports = 4, 3496 .base_baud = 115200, 3497 .uart_offset = 8, 3498 }, 3499 3500 [pbn_b2_bt_2_921600] = { 3501 .flags = FL_BASE2|FL_BASE_BARS, 3502 .num_ports = 2, 3503 .base_baud = 921600, 3504 .uart_offset = 8, 3505 }, 3506 [pbn_b2_bt_4_921600] = { 3507 .flags = FL_BASE2|FL_BASE_BARS, 3508 .num_ports = 4, 3509 .base_baud = 921600, 3510 .uart_offset = 8, 3511 }, 3512 3513 [pbn_b3_2_115200] = { 3514 .flags = FL_BASE3, 3515 .num_ports = 2, 3516 .base_baud = 115200, 3517 .uart_offset = 8, 3518 }, 3519 [pbn_b3_4_115200] = { 3520 .flags = FL_BASE3, 3521 .num_ports = 4, 3522 .base_baud = 115200, 3523 .uart_offset = 8, 3524 }, 3525 [pbn_b3_8_115200] = { 3526 .flags = FL_BASE3, 3527 .num_ports = 8, 3528 .base_baud = 115200, 3529 .uart_offset = 8, 3530 }, 3531 3532 [pbn_b4_bt_2_921600] = { 3533 .flags = FL_BASE4, 3534 .num_ports = 2, 3535 .base_baud = 921600, 3536 .uart_offset = 8, 3537 }, 3538 [pbn_b4_bt_4_921600] = { 3539 .flags = FL_BASE4, 3540 .num_ports = 4, 3541 .base_baud = 921600, 3542 .uart_offset = 8, 3543 }, 3544 [pbn_b4_bt_8_921600] = { 3545 .flags = FL_BASE4, 3546 .num_ports = 8, 3547 .base_baud = 921600, 3548 .uart_offset = 8, 3549 }, 3550 3551 /* 3552 * Entries following this are board-specific. 3553 */ 3554 3555 /* 3556 * Panacom - IOMEM 3557 */ 3558 [pbn_panacom] = { 3559 .flags = FL_BASE2, 3560 .num_ports = 2, 3561 .base_baud = 921600, 3562 .uart_offset = 0x400, 3563 .reg_shift = 7, 3564 }, 3565 [pbn_panacom2] = { 3566 .flags = FL_BASE2|FL_BASE_BARS, 3567 .num_ports = 2, 3568 .base_baud = 921600, 3569 .uart_offset = 0x400, 3570 .reg_shift = 7, 3571 }, 3572 [pbn_panacom4] = { 3573 .flags = FL_BASE2|FL_BASE_BARS, 3574 .num_ports = 4, 3575 .base_baud = 921600, 3576 .uart_offset = 0x400, 3577 .reg_shift = 7, 3578 }, 3579 3580 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3581 [pbn_plx_romulus] = { 3582 .flags = FL_BASE2, 3583 .num_ports = 4, 3584 .base_baud = 921600, 3585 .uart_offset = 8 << 2, 3586 .reg_shift = 2, 3587 .first_offset = 0x03, 3588 }, 3589 3590 /* 3591 * This board uses the size of PCI Base region 0 to 3592 * signal now many ports are available 3593 */ 3594 [pbn_oxsemi] = { 3595 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3596 .num_ports = 32, 3597 .base_baud = 115200, 3598 .uart_offset = 8, 3599 }, 3600 [pbn_oxsemi_1_15625000] = { 3601 .flags = FL_BASE0, 3602 .num_ports = 1, 3603 .base_baud = 15625000, 3604 .uart_offset = 0x200, 3605 .first_offset = 0x1000, 3606 }, 3607 [pbn_oxsemi_2_15625000] = { 3608 .flags = FL_BASE0, 3609 .num_ports = 2, 3610 .base_baud = 15625000, 3611 .uart_offset = 0x200, 3612 .first_offset = 0x1000, 3613 }, 3614 [pbn_oxsemi_4_15625000] = { 3615 .flags = FL_BASE0, 3616 .num_ports = 4, 3617 .base_baud = 15625000, 3618 .uart_offset = 0x200, 3619 .first_offset = 0x1000, 3620 }, 3621 [pbn_oxsemi_8_15625000] = { 3622 .flags = FL_BASE0, 3623 .num_ports = 8, 3624 .base_baud = 15625000, 3625 .uart_offset = 0x200, 3626 .first_offset = 0x1000, 3627 }, 3628 3629 3630 /* 3631 * EKF addition for i960 Boards form EKF with serial port. 3632 * Max 256 ports. 3633 */ 3634 [pbn_intel_i960] = { 3635 .flags = FL_BASE0, 3636 .num_ports = 32, 3637 .base_baud = 921600, 3638 .uart_offset = 8 << 2, 3639 .reg_shift = 2, 3640 .first_offset = 0x10000, 3641 }, 3642 [pbn_sgi_ioc3] = { 3643 .flags = FL_BASE0|FL_NOIRQ, 3644 .num_ports = 1, 3645 .base_baud = 458333, 3646 .uart_offset = 8, 3647 .reg_shift = 0, 3648 .first_offset = 0x20178, 3649 }, 3650 3651 /* 3652 * Computone - uses IOMEM. 3653 */ 3654 [pbn_computone_4] = { 3655 .flags = FL_BASE0, 3656 .num_ports = 4, 3657 .base_baud = 921600, 3658 .uart_offset = 0x40, 3659 .reg_shift = 2, 3660 .first_offset = 0x200, 3661 }, 3662 [pbn_computone_6] = { 3663 .flags = FL_BASE0, 3664 .num_ports = 6, 3665 .base_baud = 921600, 3666 .uart_offset = 0x40, 3667 .reg_shift = 2, 3668 .first_offset = 0x200, 3669 }, 3670 [pbn_computone_8] = { 3671 .flags = FL_BASE0, 3672 .num_ports = 8, 3673 .base_baud = 921600, 3674 .uart_offset = 0x40, 3675 .reg_shift = 2, 3676 .first_offset = 0x200, 3677 }, 3678 [pbn_sbsxrsio] = { 3679 .flags = FL_BASE0, 3680 .num_ports = 8, 3681 .base_baud = 460800, 3682 .uart_offset = 256, 3683 .reg_shift = 4, 3684 }, 3685 /* 3686 * PA Semi PWRficient PA6T-1682M on-chip UART 3687 */ 3688 [pbn_pasemi_1682M] = { 3689 .flags = FL_BASE0, 3690 .num_ports = 1, 3691 .base_baud = 8333333, 3692 }, 3693 /* 3694 * National Instruments 843x 3695 */ 3696 [pbn_ni8430_16] = { 3697 .flags = FL_BASE0, 3698 .num_ports = 16, 3699 .base_baud = 3686400, 3700 .uart_offset = 0x10, 3701 .first_offset = 0x800, 3702 }, 3703 [pbn_ni8430_8] = { 3704 .flags = FL_BASE0, 3705 .num_ports = 8, 3706 .base_baud = 3686400, 3707 .uart_offset = 0x10, 3708 .first_offset = 0x800, 3709 }, 3710 [pbn_ni8430_4] = { 3711 .flags = FL_BASE0, 3712 .num_ports = 4, 3713 .base_baud = 3686400, 3714 .uart_offset = 0x10, 3715 .first_offset = 0x800, 3716 }, 3717 [pbn_ni8430_2] = { 3718 .flags = FL_BASE0, 3719 .num_ports = 2, 3720 .base_baud = 3686400, 3721 .uart_offset = 0x10, 3722 .first_offset = 0x800, 3723 }, 3724 /* 3725 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3726 */ 3727 [pbn_ADDIDATA_PCIe_1_3906250] = { 3728 .flags = FL_BASE0, 3729 .num_ports = 1, 3730 .base_baud = 3906250, 3731 .uart_offset = 0x200, 3732 .first_offset = 0x1000, 3733 }, 3734 [pbn_ADDIDATA_PCIe_2_3906250] = { 3735 .flags = FL_BASE0, 3736 .num_ports = 2, 3737 .base_baud = 3906250, 3738 .uart_offset = 0x200, 3739 .first_offset = 0x1000, 3740 }, 3741 [pbn_ADDIDATA_PCIe_4_3906250] = { 3742 .flags = FL_BASE0, 3743 .num_ports = 4, 3744 .base_baud = 3906250, 3745 .uart_offset = 0x200, 3746 .first_offset = 0x1000, 3747 }, 3748 [pbn_ADDIDATA_PCIe_8_3906250] = { 3749 .flags = FL_BASE0, 3750 .num_ports = 8, 3751 .base_baud = 3906250, 3752 .uart_offset = 0x200, 3753 .first_offset = 0x1000, 3754 }, 3755 [pbn_ce4100_1_115200] = { 3756 .flags = FL_BASE_BARS, 3757 .num_ports = 2, 3758 .base_baud = 921600, 3759 .reg_shift = 2, 3760 }, 3761 [pbn_omegapci] = { 3762 .flags = FL_BASE0, 3763 .num_ports = 8, 3764 .base_baud = 115200, 3765 .uart_offset = 0x200, 3766 }, 3767 [pbn_NETMOS9900_2s_115200] = { 3768 .flags = FL_BASE0, 3769 .num_ports = 2, 3770 .base_baud = 115200, 3771 }, 3772 [pbn_brcm_trumanage] = { 3773 .flags = FL_BASE0, 3774 .num_ports = 1, 3775 .reg_shift = 2, 3776 .base_baud = 115200, 3777 }, 3778 [pbn_fintek_4] = { 3779 .num_ports = 4, 3780 .uart_offset = 8, 3781 .base_baud = 115200, 3782 .first_offset = 0x40, 3783 }, 3784 [pbn_fintek_8] = { 3785 .num_ports = 8, 3786 .uart_offset = 8, 3787 .base_baud = 115200, 3788 .first_offset = 0x40, 3789 }, 3790 [pbn_fintek_12] = { 3791 .num_ports = 12, 3792 .uart_offset = 8, 3793 .base_baud = 115200, 3794 .first_offset = 0x40, 3795 }, 3796 [pbn_fintek_F81504A] = { 3797 .num_ports = 4, 3798 .uart_offset = 8, 3799 .base_baud = 115200, 3800 }, 3801 [pbn_fintek_F81508A] = { 3802 .num_ports = 8, 3803 .uart_offset = 8, 3804 .base_baud = 115200, 3805 }, 3806 [pbn_fintek_F81512A] = { 3807 .num_ports = 12, 3808 .uart_offset = 8, 3809 .base_baud = 115200, 3810 }, 3811 [pbn_wch382_2] = { 3812 .flags = FL_BASE0, 3813 .num_ports = 2, 3814 .base_baud = 115200, 3815 .uart_offset = 8, 3816 .first_offset = 0xC0, 3817 }, 3818 [pbn_wch384_4] = { 3819 .flags = FL_BASE0, 3820 .num_ports = 4, 3821 .base_baud = 115200, 3822 .uart_offset = 8, 3823 .first_offset = 0xC0, 3824 }, 3825 [pbn_wch384_8] = { 3826 .flags = FL_BASE0, 3827 .num_ports = 8, 3828 .base_baud = 115200, 3829 .uart_offset = 8, 3830 .first_offset = 0x00, 3831 }, 3832 [pbn_sunix_pci_1s] = { 3833 .num_ports = 1, 3834 .base_baud = 921600, 3835 .uart_offset = 0x8, 3836 }, 3837 [pbn_sunix_pci_2s] = { 3838 .num_ports = 2, 3839 .base_baud = 921600, 3840 .uart_offset = 0x8, 3841 }, 3842 [pbn_sunix_pci_4s] = { 3843 .num_ports = 4, 3844 .base_baud = 921600, 3845 .uart_offset = 0x8, 3846 }, 3847 [pbn_sunix_pci_8s] = { 3848 .num_ports = 8, 3849 .base_baud = 921600, 3850 .uart_offset = 0x8, 3851 }, 3852 [pbn_sunix_pci_16s] = { 3853 .num_ports = 16, 3854 .base_baud = 921600, 3855 .uart_offset = 0x8, 3856 }, 3857 [pbn_titan_1_4000000] = { 3858 .flags = FL_BASE0, 3859 .num_ports = 1, 3860 .base_baud = 4000000, 3861 .uart_offset = 0x200, 3862 .first_offset = 0x1000, 3863 }, 3864 [pbn_titan_2_4000000] = { 3865 .flags = FL_BASE0, 3866 .num_ports = 2, 3867 .base_baud = 4000000, 3868 .uart_offset = 0x200, 3869 .first_offset = 0x1000, 3870 }, 3871 [pbn_titan_4_4000000] = { 3872 .flags = FL_BASE0, 3873 .num_ports = 4, 3874 .base_baud = 4000000, 3875 .uart_offset = 0x200, 3876 .first_offset = 0x1000, 3877 }, 3878 [pbn_titan_8_4000000] = { 3879 .flags = FL_BASE0, 3880 .num_ports = 8, 3881 .base_baud = 4000000, 3882 .uart_offset = 0x200, 3883 .first_offset = 0x1000, 3884 }, 3885 [pbn_moxa_2] = { 3886 .flags = FL_BASE1, 3887 .num_ports = 2, 3888 .base_baud = 921600, 3889 .uart_offset = 0x200, 3890 }, 3891 [pbn_moxa_4] = { 3892 .flags = FL_BASE1, 3893 .num_ports = 4, 3894 .base_baud = 921600, 3895 .uart_offset = 0x200, 3896 }, 3897 [pbn_moxa_8] = { 3898 .flags = FL_BASE1, 3899 .num_ports = 8, 3900 .base_baud = 921600, 3901 .uart_offset = 0x200, 3902 }, 3903 }; 3904 3905 #define REPORT_CONFIG(option) \ 3906 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3907 #define REPORT_8250_CONFIG(option) \ 3908 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3909 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3910 3911 static const struct pci_device_id blacklist[] = { 3912 /* softmodems */ 3913 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3914 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3915 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3916 3917 /* multi-io cards handled by parport_serial */ 3918 /* WCH CH353 2S1P */ 3919 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3920 /* WCH CH353 1S1P */ 3921 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3922 /* WCH CH382 2S1P */ 3923 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3924 3925 /* Intel platforms with MID UART */ 3926 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3927 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3928 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3929 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3930 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3931 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3932 3933 /* Intel platforms with DesignWare UART */ 3934 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3935 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3936 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3937 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3938 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3939 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3940 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3941 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3942 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3943 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3944 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3945 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3946 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3947 3948 /* Exar devices */ 3949 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3950 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3951 3952 /* Pericom devices */ 3953 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3954 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3955 3956 /* End of the black list */ 3957 { } 3958 }; 3959 3960 static int serial_pci_is_class_communication(struct pci_dev *dev) 3961 { 3962 /* 3963 * If it is not a communications device or the programming 3964 * interface is greater than 6, give up. 3965 */ 3966 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3967 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3968 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3969 (dev->class & 0xff) > 6) 3970 return -ENODEV; 3971 3972 return 0; 3973 } 3974 3975 /* 3976 * Given a complete unknown PCI device, try to use some heuristics to 3977 * guess what the configuration might be, based on the pitiful PCI 3978 * serial specs. Returns 0 on success, -ENODEV on failure. 3979 */ 3980 static int 3981 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3982 { 3983 int num_iomem, num_port, first_port = -1, i; 3984 int rc; 3985 3986 rc = serial_pci_is_class_communication(dev); 3987 if (rc) 3988 return rc; 3989 3990 /* 3991 * Should we try to make guesses for multiport serial devices later? 3992 */ 3993 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3994 return -ENODEV; 3995 3996 num_iomem = num_port = 0; 3997 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3998 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3999 num_port++; 4000 if (first_port == -1) 4001 first_port = i; 4002 } 4003 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 4004 num_iomem++; 4005 } 4006 4007 /* 4008 * If there is 1 or 0 iomem regions, and exactly one port, 4009 * use it. We guess the number of ports based on the IO 4010 * region size. 4011 */ 4012 if (num_iomem <= 1 && num_port == 1) { 4013 board->flags = first_port; 4014 board->num_ports = pci_resource_len(dev, first_port) / 8; 4015 return 0; 4016 } 4017 4018 /* 4019 * Now guess if we've got a board which indexes by BARs. 4020 * Each IO BAR should be 8 bytes, and they should follow 4021 * consecutively. 4022 */ 4023 first_port = -1; 4024 num_port = 0; 4025 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 4026 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 4027 pci_resource_len(dev, i) == 8 && 4028 (first_port == -1 || (first_port + num_port) == i)) { 4029 num_port++; 4030 if (first_port == -1) 4031 first_port = i; 4032 } 4033 } 4034 4035 if (num_port > 1) { 4036 board->flags = first_port | FL_BASE_BARS; 4037 board->num_ports = num_port; 4038 return 0; 4039 } 4040 4041 return -ENODEV; 4042 } 4043 4044 static inline int 4045 serial_pci_matches(const struct pciserial_board *board, 4046 const struct pciserial_board *guessed) 4047 { 4048 return 4049 board->num_ports == guessed->num_ports && 4050 board->base_baud == guessed->base_baud && 4051 board->uart_offset == guessed->uart_offset && 4052 board->reg_shift == guessed->reg_shift && 4053 board->first_offset == guessed->first_offset; 4054 } 4055 4056 struct serial_private * 4057 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 4058 { 4059 struct uart_8250_port uart; 4060 struct serial_private *priv; 4061 struct pci_serial_quirk *quirk; 4062 int rc, nr_ports, i; 4063 4064 nr_ports = board->num_ports; 4065 4066 /* 4067 * Find an init and setup quirks. 4068 */ 4069 quirk = find_quirk(dev); 4070 4071 /* 4072 * Run the new-style initialization function. 4073 * The initialization function returns: 4074 * <0 - error 4075 * 0 - use board->num_ports 4076 * >0 - number of ports 4077 */ 4078 if (quirk->init) { 4079 rc = quirk->init(dev); 4080 if (rc < 0) { 4081 priv = ERR_PTR(rc); 4082 goto err_out; 4083 } 4084 if (rc) 4085 nr_ports = rc; 4086 } 4087 4088 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 4089 if (!priv) { 4090 priv = ERR_PTR(-ENOMEM); 4091 goto err_deinit; 4092 } 4093 4094 priv->dev = dev; 4095 priv->quirk = quirk; 4096 4097 memset(&uart, 0, sizeof(uart)); 4098 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 4099 uart.port.uartclk = board->base_baud * 16; 4100 4101 if (board->flags & FL_NOIRQ) { 4102 uart.port.irq = 0; 4103 } else { 4104 if (pci_match_id(pci_use_msi, dev)) { 4105 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 4106 pci_set_master(dev); 4107 uart.port.flags &= ~UPF_SHARE_IRQ; 4108 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 4109 } else { 4110 pci_dbg(dev, "Using legacy interrupts\n"); 4111 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 4112 } 4113 if (rc < 0) { 4114 kfree(priv); 4115 priv = ERR_PTR(rc); 4116 goto err_deinit; 4117 } 4118 4119 uart.port.irq = pci_irq_vector(dev, 0); 4120 } 4121 4122 uart.port.dev = &dev->dev; 4123 4124 for (i = 0; i < nr_ports; i++) { 4125 if (quirk->setup(priv, board, &uart, i)) 4126 break; 4127 4128 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 4129 uart.port.iobase, uart.port.irq, uart.port.iotype); 4130 4131 priv->line[i] = serial8250_register_8250_port(&uart); 4132 if (priv->line[i] < 0) { 4133 pci_err(dev, 4134 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4135 uart.port.iobase, uart.port.irq, 4136 uart.port.iotype, priv->line[i]); 4137 break; 4138 } 4139 } 4140 priv->nr = i; 4141 priv->board = board; 4142 return priv; 4143 4144 err_deinit: 4145 if (quirk->exit) 4146 quirk->exit(dev); 4147 err_out: 4148 return priv; 4149 } 4150 EXPORT_SYMBOL_GPL(pciserial_init_ports); 4151 4152 static void pciserial_detach_ports(struct serial_private *priv) 4153 { 4154 struct pci_serial_quirk *quirk; 4155 int i; 4156 4157 for (i = 0; i < priv->nr; i++) 4158 serial8250_unregister_port(priv->line[i]); 4159 4160 /* 4161 * Find the exit quirks. 4162 */ 4163 quirk = find_quirk(priv->dev); 4164 if (quirk->exit) 4165 quirk->exit(priv->dev); 4166 } 4167 4168 void pciserial_remove_ports(struct serial_private *priv) 4169 { 4170 pciserial_detach_ports(priv); 4171 kfree(priv); 4172 } 4173 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4174 4175 void pciserial_suspend_ports(struct serial_private *priv) 4176 { 4177 int i; 4178 4179 for (i = 0; i < priv->nr; i++) 4180 if (priv->line[i] >= 0) 4181 serial8250_suspend_port(priv->line[i]); 4182 4183 /* 4184 * Ensure that every init quirk is properly torn down 4185 */ 4186 if (priv->quirk->exit) 4187 priv->quirk->exit(priv->dev); 4188 } 4189 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4190 4191 void pciserial_resume_ports(struct serial_private *priv) 4192 { 4193 int i; 4194 4195 /* 4196 * Ensure that the board is correctly configured. 4197 */ 4198 if (priv->quirk->init) 4199 priv->quirk->init(priv->dev); 4200 4201 for (i = 0; i < priv->nr; i++) 4202 if (priv->line[i] >= 0) 4203 serial8250_resume_port(priv->line[i]); 4204 } 4205 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4206 4207 /* 4208 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4209 * to the arrangement of serial ports on a PCI card. 4210 */ 4211 static int 4212 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4213 { 4214 struct pci_serial_quirk *quirk; 4215 struct serial_private *priv; 4216 const struct pciserial_board *board; 4217 const struct pci_device_id *exclude; 4218 struct pciserial_board tmp; 4219 int rc; 4220 4221 quirk = find_quirk(dev); 4222 if (quirk->probe) { 4223 rc = quirk->probe(dev); 4224 if (rc) 4225 return rc; 4226 } 4227 4228 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4229 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4230 return -EINVAL; 4231 } 4232 4233 board = &pci_boards[ent->driver_data]; 4234 4235 exclude = pci_match_id(blacklist, dev); 4236 if (exclude) { 4237 if (exclude->driver_data) 4238 pci_warn(dev, "ignoring port, enable %s to handle\n", 4239 (const char *)exclude->driver_data); 4240 return -ENODEV; 4241 } 4242 4243 rc = pcim_enable_device(dev); 4244 pci_save_state(dev); 4245 if (rc) 4246 return rc; 4247 4248 if (ent->driver_data == pbn_default) { 4249 /* 4250 * Use a copy of the pci_board entry for this; 4251 * avoid changing entries in the table. 4252 */ 4253 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4254 board = &tmp; 4255 4256 /* 4257 * We matched one of our class entries. Try to 4258 * determine the parameters of this board. 4259 */ 4260 rc = serial_pci_guess_board(dev, &tmp); 4261 if (rc) 4262 return rc; 4263 } else { 4264 /* 4265 * We matched an explicit entry. If we are able to 4266 * detect this boards settings with our heuristic, 4267 * then we no longer need this entry. 4268 */ 4269 memcpy(&tmp, &pci_boards[pbn_default], 4270 sizeof(struct pciserial_board)); 4271 rc = serial_pci_guess_board(dev, &tmp); 4272 if (rc == 0 && serial_pci_matches(board, &tmp)) 4273 moan_device("Redundant entry in serial pci_table.", 4274 dev); 4275 } 4276 4277 priv = pciserial_init_ports(dev, board); 4278 if (IS_ERR(priv)) 4279 return PTR_ERR(priv); 4280 4281 pci_set_drvdata(dev, priv); 4282 return 0; 4283 } 4284 4285 static void pciserial_remove_one(struct pci_dev *dev) 4286 { 4287 struct serial_private *priv = pci_get_drvdata(dev); 4288 4289 pciserial_remove_ports(priv); 4290 } 4291 4292 #ifdef CONFIG_PM_SLEEP 4293 static int pciserial_suspend_one(struct device *dev) 4294 { 4295 struct serial_private *priv = dev_get_drvdata(dev); 4296 4297 if (priv) 4298 pciserial_suspend_ports(priv); 4299 4300 return 0; 4301 } 4302 4303 static int pciserial_resume_one(struct device *dev) 4304 { 4305 struct pci_dev *pdev = to_pci_dev(dev); 4306 struct serial_private *priv = pci_get_drvdata(pdev); 4307 int err; 4308 4309 if (priv) { 4310 /* 4311 * The device may have been disabled. Re-enable it. 4312 */ 4313 err = pci_enable_device(pdev); 4314 /* FIXME: We cannot simply error out here */ 4315 if (err) 4316 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4317 pciserial_resume_ports(priv); 4318 } 4319 return 0; 4320 } 4321 #endif 4322 4323 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4324 pciserial_resume_one); 4325 4326 static const struct pci_device_id serial_pci_tbl[] = { 4327 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4328 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, 4329 pbn_b0_4_921600 }, 4330 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4331 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4332 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4333 pbn_b2_8_921600 }, 4334 /* Advantech also use 0x3618 and 0xf618 */ 4335 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4336 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4337 pbn_b0_4_921600 }, 4338 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4339 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4340 pbn_b0_4_921600 }, 4341 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4342 PCI_SUBVENDOR_ID_CONNECT_TECH, 4343 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4344 pbn_b1_8_1382400 }, 4345 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4346 PCI_SUBVENDOR_ID_CONNECT_TECH, 4347 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4348 pbn_b1_4_1382400 }, 4349 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4350 PCI_SUBVENDOR_ID_CONNECT_TECH, 4351 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4352 pbn_b1_2_1382400 }, 4353 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4354 PCI_SUBVENDOR_ID_CONNECT_TECH, 4355 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4356 pbn_b1_8_1382400 }, 4357 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4358 PCI_SUBVENDOR_ID_CONNECT_TECH, 4359 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4360 pbn_b1_4_1382400 }, 4361 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4362 PCI_SUBVENDOR_ID_CONNECT_TECH, 4363 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4364 pbn_b1_2_1382400 }, 4365 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4366 PCI_SUBVENDOR_ID_CONNECT_TECH, 4367 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4368 pbn_b1_8_921600 }, 4369 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4370 PCI_SUBVENDOR_ID_CONNECT_TECH, 4371 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4372 pbn_b1_8_921600 }, 4373 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4374 PCI_SUBVENDOR_ID_CONNECT_TECH, 4375 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4376 pbn_b1_4_921600 }, 4377 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4378 PCI_SUBVENDOR_ID_CONNECT_TECH, 4379 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4380 pbn_b1_4_921600 }, 4381 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4382 PCI_SUBVENDOR_ID_CONNECT_TECH, 4383 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4384 pbn_b1_2_921600 }, 4385 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4386 PCI_SUBVENDOR_ID_CONNECT_TECH, 4387 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4388 pbn_b1_8_921600 }, 4389 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4390 PCI_SUBVENDOR_ID_CONNECT_TECH, 4391 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4392 pbn_b1_8_921600 }, 4393 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4394 PCI_SUBVENDOR_ID_CONNECT_TECH, 4395 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4396 pbn_b1_4_921600 }, 4397 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4398 PCI_SUBVENDOR_ID_CONNECT_TECH, 4399 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4400 pbn_b1_2_1250000 }, 4401 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4402 PCI_SUBVENDOR_ID_CONNECT_TECH, 4403 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4404 pbn_b0_2_1843200 }, 4405 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4406 PCI_SUBVENDOR_ID_CONNECT_TECH, 4407 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4408 pbn_b0_4_1843200 }, 4409 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4410 PCI_VENDOR_ID_AFAVLAB, 4411 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4412 pbn_b0_4_1152000 }, 4413 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_b2_bt_1_115200 }, 4416 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4418 pbn_b2_bt_2_115200 }, 4419 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4421 pbn_b2_bt_4_115200 }, 4422 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4424 pbn_b2_bt_2_115200 }, 4425 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4427 pbn_b2_bt_4_115200 }, 4428 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4430 pbn_b2_8_115200 }, 4431 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4433 pbn_b2_8_460800 }, 4434 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4436 pbn_b2_8_115200 }, 4437 4438 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4440 pbn_b2_bt_2_115200 }, 4441 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4443 pbn_b2_bt_2_921600 }, 4444 /* 4445 * VScom SPCOM800, from sl@s.pl 4446 */ 4447 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4449 pbn_b2_8_921600 }, 4450 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_b2_4_921600 }, 4453 /* Unknown card - subdevice 0x1584 */ 4454 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4455 PCI_VENDOR_ID_PLX, 4456 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4457 pbn_b2_4_115200 }, 4458 /* Unknown card - subdevice 0x1588 */ 4459 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4460 PCI_VENDOR_ID_PLX, 4461 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4462 pbn_b2_8_115200 }, 4463 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4464 PCI_SUBVENDOR_ID_KEYSPAN, 4465 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4466 pbn_panacom }, 4467 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4469 pbn_panacom4 }, 4470 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4472 pbn_panacom2 }, 4473 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4474 PCI_VENDOR_ID_ESDGMBH, 4475 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4476 pbn_b2_4_115200 }, 4477 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4478 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4479 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4480 pbn_b2_4_460800 }, 4481 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4482 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4483 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4484 pbn_b2_8_460800 }, 4485 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4486 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4487 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4488 pbn_b2_16_460800 }, 4489 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4490 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4491 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4492 pbn_b2_16_460800 }, 4493 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4494 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4495 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4496 pbn_b2_4_460800 }, 4497 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4498 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4499 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4500 pbn_b2_8_460800 }, 4501 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4502 PCI_SUBVENDOR_ID_EXSYS, 4503 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4504 pbn_b2_4_115200 }, 4505 /* 4506 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4507 * (Exoray@isys.ca) 4508 */ 4509 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4510 0x10b5, 0x106a, 0, 0, 4511 pbn_plx_romulus }, 4512 /* 4513 * Quatech cards. These actually have configurable clocks but for 4514 * now we just use the default. 4515 * 4516 * 100 series are RS232, 200 series RS422, 4517 */ 4518 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4520 pbn_b1_4_115200 }, 4521 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4523 pbn_b1_2_115200 }, 4524 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4526 pbn_b2_2_115200 }, 4527 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4529 pbn_b1_2_115200 }, 4530 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4532 pbn_b2_2_115200 }, 4533 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4535 pbn_b1_4_115200 }, 4536 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4538 pbn_b1_8_115200 }, 4539 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4541 pbn_b1_8_115200 }, 4542 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4544 pbn_b1_4_115200 }, 4545 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4547 pbn_b1_2_115200 }, 4548 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4550 pbn_b1_4_115200 }, 4551 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4553 pbn_b1_2_115200 }, 4554 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4556 pbn_b2_4_115200 }, 4557 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4559 pbn_b2_2_115200 }, 4560 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4562 pbn_b2_1_115200 }, 4563 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4565 pbn_b2_4_115200 }, 4566 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4568 pbn_b2_2_115200 }, 4569 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4571 pbn_b2_1_115200 }, 4572 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4574 pbn_b0_8_115200 }, 4575 4576 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4577 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4578 0, 0, 4579 pbn_b0_4_921600 }, 4580 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4581 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4582 0, 0, 4583 pbn_b0_4_1152000 }, 4584 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4586 pbn_b0_bt_2_921600 }, 4587 4588 /* 4589 * The below card is a little controversial since it is the 4590 * subject of a PCI vendor/device ID clash. (See 4591 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4592 * For now just used the hex ID 0x950a. 4593 */ 4594 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4595 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4596 0, 0, pbn_b0_2_115200 }, 4597 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4598 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4599 0, 0, pbn_b0_2_115200 }, 4600 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4602 pbn_b0_2_1130000 }, 4603 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4604 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4605 pbn_b0_1_921600 }, 4606 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4608 pbn_b0_4_115200 }, 4609 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4611 pbn_b0_bt_2_921600 }, 4612 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4614 pbn_b2_8_1152000 }, 4615 4616 /* 4617 * Oxford Semiconductor Inc. Tornado PCI express device range. 4618 */ 4619 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4621 pbn_b0_1_15625000 }, 4622 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4624 pbn_b0_1_15625000 }, 4625 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4627 pbn_oxsemi_1_15625000 }, 4628 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_oxsemi_1_15625000 }, 4631 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4633 pbn_b0_1_15625000 }, 4634 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4636 pbn_b0_1_15625000 }, 4637 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_oxsemi_1_15625000 }, 4640 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4642 pbn_oxsemi_1_15625000 }, 4643 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4645 pbn_b0_1_15625000 }, 4646 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4648 pbn_b0_1_15625000 }, 4649 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4651 pbn_b0_1_15625000 }, 4652 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_b0_1_15625000 }, 4655 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4657 pbn_oxsemi_2_15625000 }, 4658 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_oxsemi_2_15625000 }, 4661 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4663 pbn_oxsemi_4_15625000 }, 4664 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_oxsemi_4_15625000 }, 4667 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4669 pbn_oxsemi_8_15625000 }, 4670 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4672 pbn_oxsemi_8_15625000 }, 4673 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4675 pbn_oxsemi_1_15625000 }, 4676 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_oxsemi_1_15625000 }, 4679 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4681 pbn_oxsemi_1_15625000 }, 4682 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4684 pbn_oxsemi_1_15625000 }, 4685 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4687 pbn_oxsemi_1_15625000 }, 4688 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4690 pbn_oxsemi_1_15625000 }, 4691 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4693 pbn_oxsemi_1_15625000 }, 4694 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4696 pbn_oxsemi_1_15625000 }, 4697 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4699 pbn_oxsemi_1_15625000 }, 4700 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4702 pbn_oxsemi_1_15625000 }, 4703 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4705 pbn_oxsemi_1_15625000 }, 4706 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4708 pbn_oxsemi_1_15625000 }, 4709 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4711 pbn_oxsemi_1_15625000 }, 4712 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4714 pbn_oxsemi_1_15625000 }, 4715 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4717 pbn_oxsemi_1_15625000 }, 4718 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4720 pbn_oxsemi_1_15625000 }, 4721 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4723 pbn_oxsemi_1_15625000 }, 4724 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4726 pbn_oxsemi_1_15625000 }, 4727 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4729 pbn_oxsemi_1_15625000 }, 4730 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4732 pbn_oxsemi_1_15625000 }, 4733 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4735 pbn_oxsemi_1_15625000 }, 4736 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4738 pbn_oxsemi_1_15625000 }, 4739 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4741 pbn_oxsemi_1_15625000 }, 4742 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4744 pbn_oxsemi_1_15625000 }, 4745 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4747 pbn_oxsemi_1_15625000 }, 4748 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4750 pbn_oxsemi_1_15625000 }, 4751 /* 4752 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4753 */ 4754 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4755 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4756 pbn_oxsemi_1_15625000 }, 4757 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4758 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4759 pbn_oxsemi_2_15625000 }, 4760 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4761 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4762 pbn_oxsemi_4_15625000 }, 4763 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4764 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4765 pbn_oxsemi_8_15625000 }, 4766 4767 /* 4768 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4769 */ 4770 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4771 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4772 pbn_oxsemi_2_15625000 }, 4773 /* 4774 * EndRun Technologies. PCI express device range. 4775 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4776 */ 4777 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4779 pbn_oxsemi_2_15625000 }, 4780 4781 /* 4782 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4783 * from skokodyn@yahoo.com 4784 */ 4785 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4786 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4787 pbn_sbsxrsio }, 4788 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4789 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4790 pbn_sbsxrsio }, 4791 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4792 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4793 pbn_sbsxrsio }, 4794 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4795 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4796 pbn_sbsxrsio }, 4797 4798 /* 4799 * Digitan DS560-558, from jimd@esoft.com 4800 */ 4801 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4803 pbn_b1_1_115200 }, 4804 4805 /* 4806 * Titan Electronic cards 4807 * The 400L and 800L have a custom setup quirk. 4808 */ 4809 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4811 pbn_b0_1_921600 }, 4812 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4814 pbn_b0_2_921600 }, 4815 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4817 pbn_b0_4_921600 }, 4818 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4820 pbn_b0_4_921600 }, 4821 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4823 pbn_b1_1_921600 }, 4824 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4826 pbn_b1_bt_2_921600 }, 4827 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4829 pbn_b0_bt_4_921600 }, 4830 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4831 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4832 pbn_b0_bt_8_921600 }, 4833 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4835 pbn_b4_bt_2_921600 }, 4836 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4838 pbn_b4_bt_4_921600 }, 4839 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4841 pbn_b4_bt_8_921600 }, 4842 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4844 pbn_b0_4_921600 }, 4845 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4847 pbn_b0_4_921600 }, 4848 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4849 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4850 pbn_b0_4_921600 }, 4851 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4853 pbn_titan_1_4000000 }, 4854 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4856 pbn_titan_2_4000000 }, 4857 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4859 pbn_titan_4_4000000 }, 4860 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_titan_8_4000000 }, 4863 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4865 pbn_titan_2_4000000 }, 4866 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4868 pbn_titan_2_4000000 }, 4869 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4871 pbn_b0_bt_2_921600 }, 4872 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4874 pbn_b0_4_921600 }, 4875 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4877 pbn_b0_4_921600 }, 4878 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4880 pbn_b0_4_921600 }, 4881 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4883 pbn_b0_4_921600 }, 4884 4885 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4887 pbn_b2_1_460800 }, 4888 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4890 pbn_b2_1_460800 }, 4891 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4893 pbn_b2_1_460800 }, 4894 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4896 pbn_b2_bt_2_921600 }, 4897 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4899 pbn_b2_bt_2_921600 }, 4900 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4902 pbn_b2_bt_2_921600 }, 4903 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4905 pbn_b2_bt_4_921600 }, 4906 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4908 pbn_b2_bt_4_921600 }, 4909 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4911 pbn_b2_bt_4_921600 }, 4912 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4914 pbn_b0_1_921600 }, 4915 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4917 pbn_b0_1_921600 }, 4918 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4920 pbn_b0_1_921600 }, 4921 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4923 pbn_b0_bt_2_921600 }, 4924 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4926 pbn_b0_bt_2_921600 }, 4927 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4929 pbn_b0_bt_2_921600 }, 4930 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4932 pbn_b0_bt_4_921600 }, 4933 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4935 pbn_b0_bt_4_921600 }, 4936 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4938 pbn_b0_bt_4_921600 }, 4939 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4941 pbn_b0_bt_8_921600 }, 4942 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4944 pbn_b0_bt_8_921600 }, 4945 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4947 pbn_b0_bt_8_921600 }, 4948 4949 /* 4950 * Computone devices submitted by Doug McNash dmcnash@computone.com 4951 */ 4952 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4953 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4954 0, 0, pbn_computone_4 }, 4955 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4956 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4957 0, 0, pbn_computone_8 }, 4958 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4959 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4960 0, 0, pbn_computone_6 }, 4961 4962 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4964 pbn_oxsemi }, 4965 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4966 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4967 pbn_b0_bt_1_921600 }, 4968 4969 /* 4970 * Sunix PCI serial boards 4971 */ 4972 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4973 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4974 pbn_sunix_pci_1s }, 4975 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4976 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4977 pbn_sunix_pci_2s }, 4978 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4979 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4980 pbn_sunix_pci_4s }, 4981 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4982 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4983 pbn_sunix_pci_4s }, 4984 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4985 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4986 pbn_sunix_pci_8s }, 4987 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4988 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4989 pbn_sunix_pci_8s }, 4990 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4991 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4992 pbn_sunix_pci_16s }, 4993 4994 /* 4995 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4996 */ 4997 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4999 pbn_b0_bt_8_115200 }, 5000 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5002 pbn_b0_bt_8_115200 }, 5003 5004 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5006 pbn_b0_bt_2_115200 }, 5007 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5009 pbn_b0_bt_2_115200 }, 5010 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5012 pbn_b0_bt_2_115200 }, 5013 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5015 pbn_b0_bt_4_460800 }, 5016 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5018 pbn_b0_bt_4_460800 }, 5019 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5021 pbn_b0_bt_2_460800 }, 5022 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 5023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5024 pbn_b0_bt_2_460800 }, 5025 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5027 pbn_b0_bt_2_460800 }, 5028 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5030 pbn_b0_bt_1_115200 }, 5031 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5033 pbn_b0_bt_1_460800 }, 5034 5035 /* 5036 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 5037 * Cards are identified by their subsystem vendor IDs, which 5038 * (in hex) match the model number. 5039 * 5040 * Note that JC140x are RS422/485 cards which require ox950 5041 * ACR = 0x10, and as such are not currently fully supported. 5042 */ 5043 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5044 0x1204, 0x0004, 0, 0, 5045 pbn_b0_4_921600 }, 5046 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5047 0x1208, 0x0004, 0, 0, 5048 pbn_b0_4_921600 }, 5049 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5050 0x1402, 0x0002, 0, 0, 5051 pbn_b0_2_921600 }, */ 5052 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5053 0x1404, 0x0004, 0, 0, 5054 pbn_b0_4_921600 }, */ 5055 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 5056 0x1208, 0x0004, 0, 0, 5057 pbn_b0_4_921600 }, 5058 5059 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5060 0x1204, 0x0004, 0, 0, 5061 pbn_b0_4_921600 }, 5062 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5063 0x1208, 0x0004, 0, 0, 5064 pbn_b0_4_921600 }, 5065 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 5066 0x1208, 0x0004, 0, 0, 5067 pbn_b0_4_921600 }, 5068 /* 5069 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 5070 */ 5071 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5073 pbn_b1_1_1382400 }, 5074 5075 /* 5076 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 5077 */ 5078 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 5079 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5080 pbn_b1_1_1382400 }, 5081 5082 /* 5083 * RAStel 2 port modem, gerg@moreton.com.au 5084 */ 5085 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5087 pbn_b2_bt_2_115200 }, 5088 5089 /* 5090 * EKF addition for i960 Boards form EKF with serial port 5091 */ 5092 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 5093 0xE4BF, PCI_ANY_ID, 0, 0, 5094 pbn_intel_i960 }, 5095 5096 /* 5097 * Xircom Cardbus/Ethernet combos 5098 */ 5099 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 5100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5101 pbn_b0_1_115200 }, 5102 /* 5103 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 5104 */ 5105 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 5106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5107 pbn_b0_1_115200 }, 5108 5109 /* 5110 * Untested PCI modems, sent in from various folks... 5111 */ 5112 5113 /* 5114 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 5115 */ 5116 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 5117 0x1048, 0x1500, 0, 0, 5118 pbn_b1_1_115200 }, 5119 5120 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 5121 0xFF00, 0, 0, 0, 5122 pbn_sgi_ioc3 }, 5123 5124 /* 5125 * HP Diva card 5126 */ 5127 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5128 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 5129 pbn_b1_1_115200 }, 5130 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5132 pbn_b0_5_115200 }, 5133 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 5134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5135 pbn_b2_1_115200 }, 5136 /* HPE PCI serial device */ 5137 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5139 pbn_b1_1_115200 }, 5140 5141 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5143 pbn_b3_2_115200 }, 5144 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5146 pbn_b3_4_115200 }, 5147 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5149 pbn_b3_8_115200 }, 5150 /* 5151 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5152 */ 5153 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5155 pbn_b0_1_115200 }, 5156 /* 5157 * ITE 5158 */ 5159 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5160 PCI_ANY_ID, PCI_ANY_ID, 5161 0, 0, 5162 pbn_b1_bt_1_115200 }, 5163 5164 /* 5165 * IntaShield IS-100 5166 */ 5167 { PCI_VENDOR_ID_INTASHIELD, 0x0D60, 5168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5169 pbn_b2_1_115200 }, 5170 /* 5171 * IntaShield IS-200 5172 */ 5173 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */ 5175 pbn_b2_2_115200 }, 5176 /* 5177 * IntaShield IS-400 5178 */ 5179 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5181 pbn_b2_4_115200 }, 5182 /* 5183 * IntaShield IX-100 5184 */ 5185 { PCI_VENDOR_ID_INTASHIELD, 0x4027, 5186 PCI_ANY_ID, PCI_ANY_ID, 5187 0, 0, 5188 pbn_oxsemi_1_15625000 }, 5189 /* 5190 * IntaShield IX-200 5191 */ 5192 { PCI_VENDOR_ID_INTASHIELD, 0x4028, 5193 PCI_ANY_ID, PCI_ANY_ID, 5194 0, 0, 5195 pbn_oxsemi_2_15625000 }, 5196 /* 5197 * IntaShield IX-400 5198 */ 5199 { PCI_VENDOR_ID_INTASHIELD, 0x4029, 5200 PCI_ANY_ID, PCI_ANY_ID, 5201 0, 0, 5202 pbn_oxsemi_4_15625000 }, 5203 /* Brainboxes Devices */ 5204 /* 5205 * Brainboxes UC-101 5206 */ 5207 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 5208 PCI_ANY_ID, PCI_ANY_ID, 5209 0, 0, 5210 pbn_b2_2_115200 }, 5211 /* 5212 * Brainboxes UC-235/246 5213 */ 5214 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 5215 PCI_ANY_ID, PCI_ANY_ID, 5216 0, 0, 5217 pbn_b2_1_115200 }, 5218 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2, 5219 PCI_ANY_ID, PCI_ANY_ID, 5220 0, 0, 5221 pbn_b2_1_115200 }, 5222 /* 5223 * Brainboxes UC-253/UC-734 5224 */ 5225 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1, 5226 PCI_ANY_ID, PCI_ANY_ID, 5227 0, 0, 5228 pbn_b2_2_115200 }, 5229 /* 5230 * Brainboxes UC-260/271/701/756 5231 */ 5232 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5233 PCI_ANY_ID, PCI_ANY_ID, 5234 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5235 pbn_b2_4_115200 }, 5236 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5237 PCI_ANY_ID, PCI_ANY_ID, 5238 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5239 pbn_b2_4_115200 }, 5240 /* 5241 * Brainboxes UC-268 5242 */ 5243 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 5244 PCI_ANY_ID, PCI_ANY_ID, 5245 0, 0, 5246 pbn_b2_4_115200 }, 5247 /* 5248 * Brainboxes UC-275/279 5249 */ 5250 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 5251 PCI_ANY_ID, PCI_ANY_ID, 5252 0, 0, 5253 pbn_b2_8_115200 }, 5254 /* 5255 * Brainboxes UC-302 5256 */ 5257 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 5258 PCI_ANY_ID, PCI_ANY_ID, 5259 0, 0, 5260 pbn_b2_2_115200 }, 5261 { PCI_VENDOR_ID_INTASHIELD, 0x08E2, 5262 PCI_ANY_ID, PCI_ANY_ID, 5263 0, 0, 5264 pbn_b2_2_115200 }, 5265 { PCI_VENDOR_ID_INTASHIELD, 0x08E3, 5266 PCI_ANY_ID, PCI_ANY_ID, 5267 0, 0, 5268 pbn_b2_2_115200 }, 5269 /* 5270 * Brainboxes UC-310 5271 */ 5272 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5273 PCI_ANY_ID, PCI_ANY_ID, 5274 0, 0, 5275 pbn_b2_2_115200 }, 5276 /* 5277 * Brainboxes UC-313 5278 */ 5279 { PCI_VENDOR_ID_INTASHIELD, 0x08A1, 5280 PCI_ANY_ID, PCI_ANY_ID, 5281 0, 0, 5282 pbn_b2_2_115200 }, 5283 { PCI_VENDOR_ID_INTASHIELD, 0x08A2, 5284 PCI_ANY_ID, PCI_ANY_ID, 5285 0, 0, 5286 pbn_b2_2_115200 }, 5287 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5288 PCI_ANY_ID, PCI_ANY_ID, 5289 0, 0, 5290 pbn_b2_2_115200 }, 5291 /* 5292 * Brainboxes UC-320/324 5293 */ 5294 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5295 PCI_ANY_ID, PCI_ANY_ID, 5296 0, 0, 5297 pbn_b2_1_115200 }, 5298 /* 5299 * Brainboxes UC-346 5300 */ 5301 { PCI_VENDOR_ID_INTASHIELD, 0x0B01, 5302 PCI_ANY_ID, PCI_ANY_ID, 5303 0, 0, 5304 pbn_b2_4_115200 }, 5305 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5306 PCI_ANY_ID, PCI_ANY_ID, 5307 0, 0, 5308 pbn_b2_4_115200 }, 5309 /* 5310 * Brainboxes UC-357 5311 */ 5312 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5313 PCI_ANY_ID, PCI_ANY_ID, 5314 0, 0, 5315 pbn_b2_2_115200 }, 5316 { PCI_VENDOR_ID_INTASHIELD, 0x0A82, 5317 PCI_ANY_ID, PCI_ANY_ID, 5318 0, 0, 5319 pbn_b2_2_115200 }, 5320 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5321 PCI_ANY_ID, PCI_ANY_ID, 5322 0, 0, 5323 pbn_b2_2_115200 }, 5324 /* 5325 * Brainboxes UC-368 5326 */ 5327 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5328 PCI_ANY_ID, PCI_ANY_ID, 5329 0, 0, 5330 pbn_b2_4_115200 }, 5331 /* 5332 * Brainboxes UC-420 5333 */ 5334 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5335 PCI_ANY_ID, PCI_ANY_ID, 5336 0, 0, 5337 pbn_b2_4_115200 }, 5338 /* 5339 * Brainboxes UC-607 5340 */ 5341 { PCI_VENDOR_ID_INTASHIELD, 0x09A1, 5342 PCI_ANY_ID, PCI_ANY_ID, 5343 0, 0, 5344 pbn_b2_2_115200 }, 5345 { PCI_VENDOR_ID_INTASHIELD, 0x09A2, 5346 PCI_ANY_ID, PCI_ANY_ID, 5347 0, 0, 5348 pbn_b2_2_115200 }, 5349 { PCI_VENDOR_ID_INTASHIELD, 0x09A3, 5350 PCI_ANY_ID, PCI_ANY_ID, 5351 0, 0, 5352 pbn_b2_2_115200 }, 5353 /* 5354 * Brainboxes UC-836 5355 */ 5356 { PCI_VENDOR_ID_INTASHIELD, 0x0D41, 5357 PCI_ANY_ID, PCI_ANY_ID, 5358 0, 0, 5359 pbn_b2_4_115200 }, 5360 /* 5361 * Brainboxes UP-189 5362 */ 5363 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1, 5364 PCI_ANY_ID, PCI_ANY_ID, 5365 0, 0, 5366 pbn_b2_2_115200 }, 5367 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2, 5368 PCI_ANY_ID, PCI_ANY_ID, 5369 0, 0, 5370 pbn_b2_2_115200 }, 5371 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3, 5372 PCI_ANY_ID, PCI_ANY_ID, 5373 0, 0, 5374 pbn_b2_2_115200 }, 5375 /* 5376 * Brainboxes UP-200 5377 */ 5378 { PCI_VENDOR_ID_INTASHIELD, 0x0B21, 5379 PCI_ANY_ID, PCI_ANY_ID, 5380 0, 0, 5381 pbn_b2_2_115200 }, 5382 { PCI_VENDOR_ID_INTASHIELD, 0x0B22, 5383 PCI_ANY_ID, PCI_ANY_ID, 5384 0, 0, 5385 pbn_b2_2_115200 }, 5386 { PCI_VENDOR_ID_INTASHIELD, 0x0B23, 5387 PCI_ANY_ID, PCI_ANY_ID, 5388 0, 0, 5389 pbn_b2_2_115200 }, 5390 /* 5391 * Brainboxes UP-869 5392 */ 5393 { PCI_VENDOR_ID_INTASHIELD, 0x0C01, 5394 PCI_ANY_ID, PCI_ANY_ID, 5395 0, 0, 5396 pbn_b2_2_115200 }, 5397 { PCI_VENDOR_ID_INTASHIELD, 0x0C02, 5398 PCI_ANY_ID, PCI_ANY_ID, 5399 0, 0, 5400 pbn_b2_2_115200 }, 5401 { PCI_VENDOR_ID_INTASHIELD, 0x0C03, 5402 PCI_ANY_ID, PCI_ANY_ID, 5403 0, 0, 5404 pbn_b2_2_115200 }, 5405 /* 5406 * Brainboxes UP-880 5407 */ 5408 { PCI_VENDOR_ID_INTASHIELD, 0x0C21, 5409 PCI_ANY_ID, PCI_ANY_ID, 5410 0, 0, 5411 pbn_b2_2_115200 }, 5412 { PCI_VENDOR_ID_INTASHIELD, 0x0C22, 5413 PCI_ANY_ID, PCI_ANY_ID, 5414 0, 0, 5415 pbn_b2_2_115200 }, 5416 { PCI_VENDOR_ID_INTASHIELD, 0x0C23, 5417 PCI_ANY_ID, PCI_ANY_ID, 5418 0, 0, 5419 pbn_b2_2_115200 }, 5420 /* 5421 * Brainboxes PX-101 5422 */ 5423 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5424 PCI_ANY_ID, PCI_ANY_ID, 5425 0, 0, 5426 pbn_b0_2_115200 }, 5427 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5428 PCI_ANY_ID, PCI_ANY_ID, 5429 0, 0, 5430 pbn_oxsemi_2_15625000 }, 5431 /* 5432 * Brainboxes PX-235/246 5433 */ 5434 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5435 PCI_ANY_ID, PCI_ANY_ID, 5436 0, 0, 5437 pbn_b0_1_115200 }, 5438 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5439 PCI_ANY_ID, PCI_ANY_ID, 5440 0, 0, 5441 pbn_oxsemi_1_15625000 }, 5442 /* 5443 * Brainboxes PX-203/PX-257 5444 */ 5445 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5446 PCI_ANY_ID, PCI_ANY_ID, 5447 0, 0, 5448 pbn_b0_2_115200 }, 5449 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5450 PCI_ANY_ID, PCI_ANY_ID, 5451 0, 0, 5452 pbn_oxsemi_2_15625000 }, 5453 /* 5454 * Brainboxes PX-260/PX-701 5455 */ 5456 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5457 PCI_ANY_ID, PCI_ANY_ID, 5458 0, 0, 5459 pbn_oxsemi_4_15625000 }, 5460 /* 5461 * Brainboxes PX-275/279 5462 */ 5463 { PCI_VENDOR_ID_INTASHIELD, 0x0E41, 5464 PCI_ANY_ID, PCI_ANY_ID, 5465 0, 0, 5466 pbn_b2_8_115200 }, 5467 /* 5468 * Brainboxes PX-310 5469 */ 5470 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5471 PCI_ANY_ID, PCI_ANY_ID, 5472 0, 0, 5473 pbn_oxsemi_2_15625000 }, 5474 /* 5475 * Brainboxes PX-313 5476 */ 5477 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5478 PCI_ANY_ID, PCI_ANY_ID, 5479 0, 0, 5480 pbn_oxsemi_2_15625000 }, 5481 /* 5482 * Brainboxes PX-320/324/PX-376/PX-387 5483 */ 5484 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5485 PCI_ANY_ID, PCI_ANY_ID, 5486 0, 0, 5487 pbn_oxsemi_1_15625000 }, 5488 /* 5489 * Brainboxes PX-335/346 5490 */ 5491 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5492 PCI_ANY_ID, PCI_ANY_ID, 5493 0, 0, 5494 pbn_oxsemi_4_15625000 }, 5495 /* 5496 * Brainboxes PX-368 5497 */ 5498 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5499 PCI_ANY_ID, PCI_ANY_ID, 5500 0, 0, 5501 pbn_oxsemi_4_15625000 }, 5502 /* 5503 * Brainboxes PX-420 5504 */ 5505 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5506 PCI_ANY_ID, PCI_ANY_ID, 5507 0, 0, 5508 pbn_b0_4_115200 }, 5509 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5510 PCI_ANY_ID, PCI_ANY_ID, 5511 0, 0, 5512 pbn_oxsemi_4_15625000 }, 5513 /* 5514 * Brainboxes PX-475 5515 */ 5516 { PCI_VENDOR_ID_INTASHIELD, 0x401D, 5517 PCI_ANY_ID, PCI_ANY_ID, 5518 0, 0, 5519 pbn_oxsemi_1_15625000 }, 5520 /* 5521 * Brainboxes PX-803/PX-857 5522 */ 5523 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5524 PCI_ANY_ID, PCI_ANY_ID, 5525 0, 0, 5526 pbn_b0_2_115200 }, 5527 { PCI_VENDOR_ID_INTASHIELD, 0x4018, 5528 PCI_ANY_ID, PCI_ANY_ID, 5529 0, 0, 5530 pbn_oxsemi_2_15625000 }, 5531 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5532 PCI_ANY_ID, PCI_ANY_ID, 5533 0, 0, 5534 pbn_oxsemi_2_15625000 }, 5535 /* 5536 * Brainboxes PX-820 5537 */ 5538 { PCI_VENDOR_ID_INTASHIELD, 0x4002, 5539 PCI_ANY_ID, PCI_ANY_ID, 5540 0, 0, 5541 pbn_b0_4_115200 }, 5542 { PCI_VENDOR_ID_INTASHIELD, 0x4013, 5543 PCI_ANY_ID, PCI_ANY_ID, 5544 0, 0, 5545 pbn_oxsemi_4_15625000 }, 5546 /* 5547 * Brainboxes PX-835/PX-846 5548 */ 5549 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5550 PCI_ANY_ID, PCI_ANY_ID, 5551 0, 0, 5552 pbn_b0_1_115200 }, 5553 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5554 PCI_ANY_ID, PCI_ANY_ID, 5555 0, 0, 5556 pbn_oxsemi_1_15625000 }, 5557 5558 /* 5559 * Perle PCI-RAS cards 5560 */ 5561 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5562 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5563 0, 0, pbn_b2_4_921600 }, 5564 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5565 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5566 0, 0, pbn_b2_8_921600 }, 5567 5568 /* 5569 * Mainpine series cards: Fairly standard layout but fools 5570 * parts of the autodetect in some cases and uses otherwise 5571 * unmatched communications subclasses in the PCI Express case 5572 */ 5573 5574 { /* RockForceDUO */ 5575 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5576 PCI_VENDOR_ID_MAINPINE, 0x0200, 5577 0, 0, pbn_b0_2_115200 }, 5578 { /* RockForceQUATRO */ 5579 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5580 PCI_VENDOR_ID_MAINPINE, 0x0300, 5581 0, 0, pbn_b0_4_115200 }, 5582 { /* RockForceDUO+ */ 5583 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5584 PCI_VENDOR_ID_MAINPINE, 0x0400, 5585 0, 0, pbn_b0_2_115200 }, 5586 { /* RockForceQUATRO+ */ 5587 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5588 PCI_VENDOR_ID_MAINPINE, 0x0500, 5589 0, 0, pbn_b0_4_115200 }, 5590 { /* RockForce+ */ 5591 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5592 PCI_VENDOR_ID_MAINPINE, 0x0600, 5593 0, 0, pbn_b0_2_115200 }, 5594 { /* RockForce+ */ 5595 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5596 PCI_VENDOR_ID_MAINPINE, 0x0700, 5597 0, 0, pbn_b0_4_115200 }, 5598 { /* RockForceOCTO+ */ 5599 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5600 PCI_VENDOR_ID_MAINPINE, 0x0800, 5601 0, 0, pbn_b0_8_115200 }, 5602 { /* RockForceDUO+ */ 5603 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5604 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5605 0, 0, pbn_b0_2_115200 }, 5606 { /* RockForceQUARTRO+ */ 5607 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5608 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5609 0, 0, pbn_b0_4_115200 }, 5610 { /* RockForceOCTO+ */ 5611 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5612 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5613 0, 0, pbn_b0_8_115200 }, 5614 { /* RockForceD1 */ 5615 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5616 PCI_VENDOR_ID_MAINPINE, 0x2000, 5617 0, 0, pbn_b0_1_115200 }, 5618 { /* RockForceF1 */ 5619 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5620 PCI_VENDOR_ID_MAINPINE, 0x2100, 5621 0, 0, pbn_b0_1_115200 }, 5622 { /* RockForceD2 */ 5623 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5624 PCI_VENDOR_ID_MAINPINE, 0x2200, 5625 0, 0, pbn_b0_2_115200 }, 5626 { /* RockForceF2 */ 5627 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5628 PCI_VENDOR_ID_MAINPINE, 0x2300, 5629 0, 0, pbn_b0_2_115200 }, 5630 { /* RockForceD4 */ 5631 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5632 PCI_VENDOR_ID_MAINPINE, 0x2400, 5633 0, 0, pbn_b0_4_115200 }, 5634 { /* RockForceF4 */ 5635 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5636 PCI_VENDOR_ID_MAINPINE, 0x2500, 5637 0, 0, pbn_b0_4_115200 }, 5638 { /* RockForceD8 */ 5639 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5640 PCI_VENDOR_ID_MAINPINE, 0x2600, 5641 0, 0, pbn_b0_8_115200 }, 5642 { /* RockForceF8 */ 5643 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5644 PCI_VENDOR_ID_MAINPINE, 0x2700, 5645 0, 0, pbn_b0_8_115200 }, 5646 { /* IQ Express D1 */ 5647 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5648 PCI_VENDOR_ID_MAINPINE, 0x3000, 5649 0, 0, pbn_b0_1_115200 }, 5650 { /* IQ Express F1 */ 5651 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5652 PCI_VENDOR_ID_MAINPINE, 0x3100, 5653 0, 0, pbn_b0_1_115200 }, 5654 { /* IQ Express D2 */ 5655 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5656 PCI_VENDOR_ID_MAINPINE, 0x3200, 5657 0, 0, pbn_b0_2_115200 }, 5658 { /* IQ Express F2 */ 5659 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5660 PCI_VENDOR_ID_MAINPINE, 0x3300, 5661 0, 0, pbn_b0_2_115200 }, 5662 { /* IQ Express D4 */ 5663 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5664 PCI_VENDOR_ID_MAINPINE, 0x3400, 5665 0, 0, pbn_b0_4_115200 }, 5666 { /* IQ Express F4 */ 5667 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5668 PCI_VENDOR_ID_MAINPINE, 0x3500, 5669 0, 0, pbn_b0_4_115200 }, 5670 { /* IQ Express D8 */ 5671 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5672 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5673 0, 0, pbn_b0_8_115200 }, 5674 { /* IQ Express F8 */ 5675 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5676 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5677 0, 0, pbn_b0_8_115200 }, 5678 5679 5680 /* 5681 * PA Semi PA6T-1682M on-chip UART 5682 */ 5683 { PCI_VENDOR_ID_PASEMI, 0xa004, 5684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5685 pbn_pasemi_1682M }, 5686 5687 /* 5688 * National Instruments 5689 */ 5690 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5692 pbn_b1_16_115200 }, 5693 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5695 pbn_b1_8_115200 }, 5696 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5698 pbn_b1_bt_4_115200 }, 5699 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5701 pbn_b1_bt_2_115200 }, 5702 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5704 pbn_b1_bt_4_115200 }, 5705 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5707 pbn_b1_bt_2_115200 }, 5708 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5709 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5710 pbn_b1_16_115200 }, 5711 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5713 pbn_b1_8_115200 }, 5714 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5715 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5716 pbn_b1_bt_4_115200 }, 5717 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5719 pbn_b1_bt_2_115200 }, 5720 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5721 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5722 pbn_b1_bt_4_115200 }, 5723 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5725 pbn_b1_bt_2_115200 }, 5726 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5727 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5728 pbn_ni8430_2 }, 5729 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5731 pbn_ni8430_2 }, 5732 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5733 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5734 pbn_ni8430_4 }, 5735 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5737 pbn_ni8430_4 }, 5738 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5740 pbn_ni8430_8 }, 5741 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5743 pbn_ni8430_8 }, 5744 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5746 pbn_ni8430_16 }, 5747 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5749 pbn_ni8430_16 }, 5750 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5752 pbn_ni8430_2 }, 5753 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5755 pbn_ni8430_2 }, 5756 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5758 pbn_ni8430_4 }, 5759 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5761 pbn_ni8430_4 }, 5762 5763 /* 5764 * MOXA 5765 */ 5766 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 }, 5767 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 }, 5768 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 }, 5769 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 }, 5770 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 }, 5771 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 }, 5772 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 }, 5773 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 }, 5774 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 }, 5775 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 }, 5776 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 }, 5777 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 }, 5778 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 }, 5779 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 }, 5780 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 }, 5781 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 }, 5782 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 }, 5783 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 }, 5784 5785 /* 5786 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5787 */ 5788 { PCI_VENDOR_ID_ADDIDATA, 5789 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5790 PCI_ANY_ID, 5791 PCI_ANY_ID, 5792 0, 5793 0, 5794 pbn_b0_4_115200 }, 5795 5796 { PCI_VENDOR_ID_ADDIDATA, 5797 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5798 PCI_ANY_ID, 5799 PCI_ANY_ID, 5800 0, 5801 0, 5802 pbn_b0_2_115200 }, 5803 5804 { PCI_VENDOR_ID_ADDIDATA, 5805 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5806 PCI_ANY_ID, 5807 PCI_ANY_ID, 5808 0, 5809 0, 5810 pbn_b0_1_115200 }, 5811 5812 { PCI_VENDOR_ID_AMCC, 5813 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5814 PCI_ANY_ID, 5815 PCI_ANY_ID, 5816 0, 5817 0, 5818 pbn_b1_8_115200 }, 5819 5820 { PCI_VENDOR_ID_ADDIDATA, 5821 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5822 PCI_ANY_ID, 5823 PCI_ANY_ID, 5824 0, 5825 0, 5826 pbn_b0_4_115200 }, 5827 5828 { PCI_VENDOR_ID_ADDIDATA, 5829 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5830 PCI_ANY_ID, 5831 PCI_ANY_ID, 5832 0, 5833 0, 5834 pbn_b0_2_115200 }, 5835 5836 { PCI_VENDOR_ID_ADDIDATA, 5837 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5838 PCI_ANY_ID, 5839 PCI_ANY_ID, 5840 0, 5841 0, 5842 pbn_b0_1_115200 }, 5843 5844 { PCI_VENDOR_ID_ADDIDATA, 5845 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5846 PCI_ANY_ID, 5847 PCI_ANY_ID, 5848 0, 5849 0, 5850 pbn_b0_4_115200 }, 5851 5852 { PCI_VENDOR_ID_ADDIDATA, 5853 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5854 PCI_ANY_ID, 5855 PCI_ANY_ID, 5856 0, 5857 0, 5858 pbn_b0_2_115200 }, 5859 5860 { PCI_VENDOR_ID_ADDIDATA, 5861 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5862 PCI_ANY_ID, 5863 PCI_ANY_ID, 5864 0, 5865 0, 5866 pbn_b0_1_115200 }, 5867 5868 { PCI_VENDOR_ID_ADDIDATA, 5869 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5870 PCI_ANY_ID, 5871 PCI_ANY_ID, 5872 0, 5873 0, 5874 pbn_b0_8_115200 }, 5875 5876 { PCI_VENDOR_ID_ADDIDATA, 5877 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5878 PCI_ANY_ID, 5879 PCI_ANY_ID, 5880 0, 5881 0, 5882 pbn_ADDIDATA_PCIe_4_3906250 }, 5883 5884 { PCI_VENDOR_ID_ADDIDATA, 5885 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5886 PCI_ANY_ID, 5887 PCI_ANY_ID, 5888 0, 5889 0, 5890 pbn_ADDIDATA_PCIe_2_3906250 }, 5891 5892 { PCI_VENDOR_ID_ADDIDATA, 5893 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5894 PCI_ANY_ID, 5895 PCI_ANY_ID, 5896 0, 5897 0, 5898 pbn_ADDIDATA_PCIe_1_3906250 }, 5899 5900 { PCI_VENDOR_ID_ADDIDATA, 5901 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5902 PCI_ANY_ID, 5903 PCI_ANY_ID, 5904 0, 5905 0, 5906 pbn_ADDIDATA_PCIe_8_3906250 }, 5907 5908 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5909 PCI_VENDOR_ID_IBM, 0x0299, 5910 0, 0, pbn_b0_bt_2_115200 }, 5911 5912 /* 5913 * other NetMos 9835 devices are most likely handled by the 5914 * parport_serial driver, check drivers/parport/parport_serial.c 5915 * before adding them here. 5916 */ 5917 5918 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5919 0xA000, 0x1000, 5920 0, 0, pbn_b0_1_115200 }, 5921 5922 /* the 9901 is a rebranded 9912 */ 5923 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5924 0xA000, 0x1000, 5925 0, 0, pbn_b0_1_115200 }, 5926 5927 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5928 0xA000, 0x1000, 5929 0, 0, pbn_b0_1_115200 }, 5930 5931 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5932 0xA000, 0x1000, 5933 0, 0, pbn_b0_1_115200 }, 5934 5935 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5936 0xA000, 0x1000, 5937 0, 0, pbn_b0_1_115200 }, 5938 5939 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5940 0xA000, 0x3002, 5941 0, 0, pbn_NETMOS9900_2s_115200 }, 5942 5943 /* 5944 * Best Connectivity and Rosewill PCI Multi I/O cards 5945 */ 5946 5947 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5948 0xA000, 0x1000, 5949 0, 0, pbn_b0_1_115200 }, 5950 5951 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5952 0xA000, 0x3002, 5953 0, 0, pbn_b0_bt_2_115200 }, 5954 5955 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5956 0xA000, 0x3004, 5957 0, 0, pbn_b0_bt_4_115200 }, 5958 5959 /* 5960 * ASIX AX99100 PCIe to Multi I/O Controller 5961 */ 5962 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 5963 0xA000, 0x1000, 5964 0, 0, pbn_b0_1_115200 }, 5965 5966 /* Intel CE4100 */ 5967 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5968 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5969 pbn_ce4100_1_115200 }, 5970 5971 /* 5972 * Cronyx Omega PCI 5973 */ 5974 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5975 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5976 pbn_omegapci }, 5977 5978 /* 5979 * Broadcom TruManage 5980 */ 5981 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5982 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5983 pbn_brcm_trumanage }, 5984 5985 /* 5986 * AgeStar as-prs2-009 5987 */ 5988 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5989 PCI_ANY_ID, PCI_ANY_ID, 5990 0, 0, pbn_b0_bt_2_115200 }, 5991 5992 /* 5993 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5994 * so not listed here. 5995 */ 5996 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5997 PCI_ANY_ID, PCI_ANY_ID, 5998 0, 0, pbn_b0_bt_4_115200 }, 5999 6000 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 6001 PCI_ANY_ID, PCI_ANY_ID, 6002 0, 0, pbn_b0_bt_2_115200 }, 6003 6004 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 6005 PCI_ANY_ID, PCI_ANY_ID, 6006 0, 0, pbn_b0_bt_4_115200 }, 6007 6008 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 6009 PCI_ANY_ID, PCI_ANY_ID, 6010 0, 0, pbn_wch382_2 }, 6011 6012 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 6013 PCI_ANY_ID, PCI_ANY_ID, 6014 0, 0, pbn_wch384_4 }, 6015 6016 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 6017 PCI_ANY_ID, PCI_ANY_ID, 6018 0, 0, pbn_wch384_8 }, 6019 /* 6020 * Realtek RealManage 6021 */ 6022 { PCI_VENDOR_ID_REALTEK, 0x816a, 6023 PCI_ANY_ID, PCI_ANY_ID, 6024 0, 0, pbn_b0_1_115200 }, 6025 6026 { PCI_VENDOR_ID_REALTEK, 0x816b, 6027 PCI_ANY_ID, PCI_ANY_ID, 6028 0, 0, pbn_b0_1_115200 }, 6029 6030 /* Fintek PCI serial cards */ 6031 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 6032 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 6033 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 6034 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 6035 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 6036 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 6037 6038 /* MKS Tenta SCOM-080x serial cards */ 6039 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 6040 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 6041 6042 /* Amazon PCI serial device */ 6043 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 6044 6045 /* 6046 * These entries match devices with class COMMUNICATION_SERIAL, 6047 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 6048 */ 6049 { PCI_ANY_ID, PCI_ANY_ID, 6050 PCI_ANY_ID, PCI_ANY_ID, 6051 PCI_CLASS_COMMUNICATION_SERIAL << 8, 6052 0xffff00, pbn_default }, 6053 { PCI_ANY_ID, PCI_ANY_ID, 6054 PCI_ANY_ID, PCI_ANY_ID, 6055 PCI_CLASS_COMMUNICATION_MODEM << 8, 6056 0xffff00, pbn_default }, 6057 { PCI_ANY_ID, PCI_ANY_ID, 6058 PCI_ANY_ID, PCI_ANY_ID, 6059 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 6060 0xffff00, pbn_default }, 6061 { 0, } 6062 }; 6063 6064 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 6065 pci_channel_state_t state) 6066 { 6067 struct serial_private *priv = pci_get_drvdata(dev); 6068 6069 if (state == pci_channel_io_perm_failure) 6070 return PCI_ERS_RESULT_DISCONNECT; 6071 6072 if (priv) 6073 pciserial_detach_ports(priv); 6074 6075 pci_disable_device(dev); 6076 6077 return PCI_ERS_RESULT_NEED_RESET; 6078 } 6079 6080 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 6081 { 6082 int rc; 6083 6084 rc = pci_enable_device(dev); 6085 6086 if (rc) 6087 return PCI_ERS_RESULT_DISCONNECT; 6088 6089 pci_restore_state(dev); 6090 pci_save_state(dev); 6091 6092 return PCI_ERS_RESULT_RECOVERED; 6093 } 6094 6095 static void serial8250_io_resume(struct pci_dev *dev) 6096 { 6097 struct serial_private *priv = pci_get_drvdata(dev); 6098 struct serial_private *new; 6099 6100 if (!priv) 6101 return; 6102 6103 new = pciserial_init_ports(dev, priv->board); 6104 if (!IS_ERR(new)) { 6105 pci_set_drvdata(dev, new); 6106 kfree(priv); 6107 } 6108 } 6109 6110 static const struct pci_error_handlers serial8250_err_handler = { 6111 .error_detected = serial8250_io_error_detected, 6112 .slot_reset = serial8250_io_slot_reset, 6113 .resume = serial8250_io_resume, 6114 }; 6115 6116 static struct pci_driver serial_pci_driver = { 6117 .name = "serial", 6118 .probe = pciserial_init_one, 6119 .remove = pciserial_remove_one, 6120 .driver = { 6121 .pm = &pciserial_pm_ops, 6122 }, 6123 .id_table = serial_pci_tbl, 6124 .err_handler = &serial8250_err_handler, 6125 }; 6126 6127 module_pci_driver(serial_pci_driver); 6128 6129 MODULE_LICENSE("GPL"); 6130 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 6131 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 6132 MODULE_IMPORT_NS(SERIAL_8250_PCI); 6133