1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 23 #include <asm/byteorder.h> 24 #include <asm/io.h> 25 26 #include "8250.h" 27 #include "8250_pcilib.h" 28 29 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 30 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 31 #define PCI_DEVICE_ID_OCTPRO 0x0001 32 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 33 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 34 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 35 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 36 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 38 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 39 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 40 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 42 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 43 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 44 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 45 #define PCI_DEVICE_ID_TITAN_200I 0x8028 46 #define PCI_DEVICE_ID_TITAN_400I 0x8048 47 #define PCI_DEVICE_ID_TITAN_800I 0x8088 48 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 49 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 50 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 51 #define PCI_DEVICE_ID_TITAN_100E 0xA010 52 #define PCI_DEVICE_ID_TITAN_200E 0xA012 53 #define PCI_DEVICE_ID_TITAN_400E 0xA013 54 #define PCI_DEVICE_ID_TITAN_800E 0xA014 55 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 56 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 57 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 58 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 59 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 60 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 61 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 62 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 63 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 64 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 65 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 66 #define PCI_VENDOR_ID_WCH 0x4348 67 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 68 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 69 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 70 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 71 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 72 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 73 #define PCI_VENDOR_ID_AGESTAR 0x5372 74 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 75 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 76 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 77 78 #define PCIE_VENDOR_ID_WCH 0x1c00 79 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 80 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 81 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 82 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 83 84 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 85 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 86 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027 87 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 88 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046 89 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121 90 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 91 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145 92 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 93 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 94 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 95 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 96 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 97 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323 98 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 99 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343 100 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 101 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 102 103 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 104 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 106 107 /* 108 * init function returns: 109 * > 0 - number of ports 110 * = 0 - use board->num_ports 111 * < 0 - error 112 */ 113 struct pci_serial_quirk { 114 u32 vendor; 115 u32 device; 116 u32 subvendor; 117 u32 subdevice; 118 int (*probe)(struct pci_dev *dev); 119 int (*init)(struct pci_dev *dev); 120 int (*setup)(struct serial_private *, 121 const struct pciserial_board *, 122 struct uart_8250_port *, int); 123 void (*exit)(struct pci_dev *dev); 124 }; 125 126 struct f815xxa_data { 127 spinlock_t lock; 128 int idx; 129 }; 130 131 struct serial_private { 132 struct pci_dev *dev; 133 unsigned int nr; 134 struct pci_serial_quirk *quirk; 135 const struct pciserial_board *board; 136 int line[]; 137 }; 138 139 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 140 141 static const struct pci_device_id pci_use_msi[] = { 142 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 143 0xA000, 0x1000) }, 144 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 145 0xA000, 0x1000) }, 146 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 147 0xA000, 0x1000) }, 148 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 149 0xA000, 0x1000) }, 150 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 151 PCI_ANY_ID, PCI_ANY_ID) }, 152 { } 153 }; 154 155 static int pci_default_setup(struct serial_private*, 156 const struct pciserial_board*, struct uart_8250_port *, int); 157 158 static void moan_device(const char *str, struct pci_dev *dev) 159 { 160 pci_err(dev, "%s\n" 161 "Please send the output of lspci -vv, this\n" 162 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 163 "manufacturer and name of serial board or\n" 164 "modem board to <linux-serial@vger.kernel.org>.\n", 165 str, dev->vendor, dev->device, 166 dev->subsystem_vendor, dev->subsystem_device); 167 } 168 169 static int 170 setup_port(struct serial_private *priv, struct uart_8250_port *port, 171 u8 bar, unsigned int offset, int regshift) 172 { 173 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); 174 } 175 176 /* 177 * ADDI-DATA GmbH communication cards <info@addi-data.com> 178 */ 179 static int addidata_apci7800_setup(struct serial_private *priv, 180 const struct pciserial_board *board, 181 struct uart_8250_port *port, int idx) 182 { 183 unsigned int bar = 0, offset = board->first_offset; 184 bar = FL_GET_BASE(board->flags); 185 186 if (idx < 2) { 187 offset += idx * board->uart_offset; 188 } else if ((idx >= 2) && (idx < 4)) { 189 bar += 1; 190 offset += ((idx - 2) * board->uart_offset); 191 } else if ((idx >= 4) && (idx < 6)) { 192 bar += 2; 193 offset += ((idx - 4) * board->uart_offset); 194 } else if (idx >= 6) { 195 bar += 3; 196 offset += ((idx - 6) * board->uart_offset); 197 } 198 199 return setup_port(priv, port, bar, offset, board->reg_shift); 200 } 201 202 /* 203 * AFAVLAB uses a different mixture of BARs and offsets 204 * Not that ugly ;) -- HW 205 */ 206 static int 207 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 208 struct uart_8250_port *port, int idx) 209 { 210 unsigned int bar, offset = board->first_offset; 211 212 bar = FL_GET_BASE(board->flags); 213 if (idx < 4) 214 bar += idx; 215 else { 216 bar = 4; 217 offset += (idx - 4) * board->uart_offset; 218 } 219 220 return setup_port(priv, port, bar, offset, board->reg_shift); 221 } 222 223 /* 224 * HP's Remote Management Console. The Diva chip came in several 225 * different versions. N-class, L2000 and A500 have two Diva chips, each 226 * with 3 UARTs (the third UART on the second chip is unused). Superdome 227 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 228 * one Diva chip, but it has been expanded to 5 UARTs. 229 */ 230 static int pci_hp_diva_init(struct pci_dev *dev) 231 { 232 int rc = 0; 233 234 switch (dev->subsystem_device) { 235 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 236 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 237 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 238 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 239 rc = 3; 240 break; 241 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 242 rc = 2; 243 break; 244 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 245 rc = 4; 246 break; 247 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 248 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 249 rc = 1; 250 break; 251 } 252 253 return rc; 254 } 255 256 /* 257 * HP's Diva chip puts the 4th/5th serial port further out, and 258 * some serial ports are supposed to be hidden on certain models. 259 */ 260 static int 261 pci_hp_diva_setup(struct serial_private *priv, 262 const struct pciserial_board *board, 263 struct uart_8250_port *port, int idx) 264 { 265 unsigned int offset = board->first_offset; 266 unsigned int bar = FL_GET_BASE(board->flags); 267 268 switch (priv->dev->subsystem_device) { 269 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 270 if (idx == 3) 271 idx++; 272 break; 273 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 274 if (idx > 0) 275 idx++; 276 if (idx > 2) 277 idx++; 278 break; 279 } 280 if (idx > 2) 281 offset = 0x18; 282 283 offset += idx * board->uart_offset; 284 285 return setup_port(priv, port, bar, offset, board->reg_shift); 286 } 287 288 /* 289 * Added for EKF Intel i960 serial boards 290 */ 291 static int pci_inteli960ni_init(struct pci_dev *dev) 292 { 293 u32 oldval; 294 295 if (!(dev->subsystem_device & 0x1000)) 296 return -ENODEV; 297 298 /* is firmware started? */ 299 pci_read_config_dword(dev, 0x44, &oldval); 300 if (oldval == 0x00001000L) { /* RESET value */ 301 pci_dbg(dev, "Local i960 firmware missing\n"); 302 return -ENODEV; 303 } 304 return 0; 305 } 306 307 /* 308 * Some PCI serial cards using the PLX 9050 PCI interface chip require 309 * that the card interrupt be explicitly enabled or disabled. This 310 * seems to be mainly needed on card using the PLX which also use I/O 311 * mapped memory. 312 */ 313 static int pci_plx9050_init(struct pci_dev *dev) 314 { 315 u8 irq_config; 316 void __iomem *p; 317 318 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 319 moan_device("no memory in bar 0", dev); 320 return 0; 321 } 322 323 irq_config = 0x41; 324 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 325 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 326 irq_config = 0x43; 327 328 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 329 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 330 /* 331 * As the megawolf cards have the int pins active 332 * high, and have 2 UART chips, both ints must be 333 * enabled on the 9050. Also, the UARTS are set in 334 * 16450 mode by default, so we have to enable the 335 * 16C950 'enhanced' mode so that we can use the 336 * deep FIFOs 337 */ 338 irq_config = 0x5b; 339 /* 340 * enable/disable interrupts 341 */ 342 p = ioremap(pci_resource_start(dev, 0), 0x80); 343 if (p == NULL) 344 return -ENOMEM; 345 writel(irq_config, p + 0x4c); 346 347 /* 348 * Read the register back to ensure that it took effect. 349 */ 350 readl(p + 0x4c); 351 iounmap(p); 352 353 return 0; 354 } 355 356 static void pci_plx9050_exit(struct pci_dev *dev) 357 { 358 u8 __iomem *p; 359 360 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 361 return; 362 363 /* 364 * disable interrupts 365 */ 366 p = ioremap(pci_resource_start(dev, 0), 0x80); 367 if (p != NULL) { 368 writel(0, p + 0x4c); 369 370 /* 371 * Read the register back to ensure that it took effect. 372 */ 373 readl(p + 0x4c); 374 iounmap(p); 375 } 376 } 377 378 #define NI8420_INT_ENABLE_REG 0x38 379 #define NI8420_INT_ENABLE_BIT 0x2000 380 381 static void pci_ni8420_exit(struct pci_dev *dev) 382 { 383 void __iomem *p; 384 unsigned int bar = 0; 385 386 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 387 moan_device("no memory in bar", dev); 388 return; 389 } 390 391 p = pci_ioremap_bar(dev, bar); 392 if (p == NULL) 393 return; 394 395 /* Disable the CPU Interrupt */ 396 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 397 p + NI8420_INT_ENABLE_REG); 398 iounmap(p); 399 } 400 401 402 /* MITE registers */ 403 #define MITE_IOWBSR1 0xc4 404 #define MITE_IOWCR1 0xf4 405 #define MITE_LCIMR1 0x08 406 #define MITE_LCIMR2 0x10 407 408 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 409 410 static void pci_ni8430_exit(struct pci_dev *dev) 411 { 412 void __iomem *p; 413 unsigned int bar = 0; 414 415 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 416 moan_device("no memory in bar", dev); 417 return; 418 } 419 420 p = pci_ioremap_bar(dev, bar); 421 if (p == NULL) 422 return; 423 424 /* Disable the CPU Interrupt */ 425 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 426 iounmap(p); 427 } 428 429 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 430 static int 431 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 432 struct uart_8250_port *port, int idx) 433 { 434 unsigned int bar, offset = board->first_offset; 435 436 bar = 0; 437 438 if (idx < 4) { 439 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 440 offset += idx * board->uart_offset; 441 } else if (idx < 8) { 442 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 443 offset += idx * board->uart_offset + 0xC00; 444 } else /* we have only 8 ports on PMC-OCTALPRO */ 445 return 1; 446 447 return setup_port(priv, port, bar, offset, board->reg_shift); 448 } 449 450 /* 451 * This does initialization for PMC OCTALPRO cards: 452 * maps the device memory, resets the UARTs (needed, bc 453 * if the module is removed and inserted again, the card 454 * is in the sleep mode) and enables global interrupt. 455 */ 456 457 /* global control register offset for SBS PMC-OctalPro */ 458 #define OCT_REG_CR_OFF 0x500 459 460 static int sbs_init(struct pci_dev *dev) 461 { 462 u8 __iomem *p; 463 464 p = pci_ioremap_bar(dev, 0); 465 466 if (p == NULL) 467 return -ENOMEM; 468 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 469 writeb(0x10, p + OCT_REG_CR_OFF); 470 udelay(50); 471 writeb(0x0, p + OCT_REG_CR_OFF); 472 473 /* Set bit-2 (INTENABLE) of Control Register */ 474 writeb(0x4, p + OCT_REG_CR_OFF); 475 iounmap(p); 476 477 return 0; 478 } 479 480 /* 481 * Disables the global interrupt of PMC-OctalPro 482 */ 483 484 static void sbs_exit(struct pci_dev *dev) 485 { 486 u8 __iomem *p; 487 488 p = pci_ioremap_bar(dev, 0); 489 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 490 if (p != NULL) 491 writeb(0, p + OCT_REG_CR_OFF); 492 iounmap(p); 493 } 494 495 /* 496 * SIIG serial cards have an PCI interface chip which also controls 497 * the UART clocking frequency. Each UART can be clocked independently 498 * (except cards equipped with 4 UARTs) and initial clocking settings 499 * are stored in the EEPROM chip. It can cause problems because this 500 * version of serial driver doesn't support differently clocked UART's 501 * on single PCI card. To prevent this, initialization functions set 502 * high frequency clocking for all UART's on given card. It is safe (I 503 * hope) because it doesn't touch EEPROM settings to prevent conflicts 504 * with other OSes (like M$ DOS). 505 * 506 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 507 * 508 * There is two family of SIIG serial cards with different PCI 509 * interface chip and different configuration methods: 510 * - 10x cards have control registers in IO and/or memory space; 511 * - 20x cards have control registers in standard PCI configuration space. 512 * 513 * Note: all 10x cards have PCI device ids 0x10.. 514 * all 20x cards have PCI device ids 0x20.. 515 * 516 * There are also Quartet Serial cards which use Oxford Semiconductor 517 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 518 * 519 * Note: some SIIG cards are probed by the parport_serial object. 520 */ 521 522 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 523 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 524 525 static int pci_siig10x_init(struct pci_dev *dev) 526 { 527 u16 data; 528 void __iomem *p; 529 530 switch (dev->device & 0xfff8) { 531 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 532 data = 0xffdf; 533 break; 534 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 535 data = 0xf7ff; 536 break; 537 default: /* 1S1P, 4S */ 538 data = 0xfffb; 539 break; 540 } 541 542 p = ioremap(pci_resource_start(dev, 0), 0x80); 543 if (p == NULL) 544 return -ENOMEM; 545 546 writew(readw(p + 0x28) & data, p + 0x28); 547 readw(p + 0x28); 548 iounmap(p); 549 return 0; 550 } 551 552 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 553 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 554 555 static int pci_siig20x_init(struct pci_dev *dev) 556 { 557 u8 data; 558 559 /* Change clock frequency for the first UART. */ 560 pci_read_config_byte(dev, 0x6f, &data); 561 pci_write_config_byte(dev, 0x6f, data & 0xef); 562 563 /* If this card has 2 UART, we have to do the same with second UART. */ 564 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 565 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 566 pci_read_config_byte(dev, 0x73, &data); 567 pci_write_config_byte(dev, 0x73, data & 0xef); 568 } 569 return 0; 570 } 571 572 static int pci_siig_init(struct pci_dev *dev) 573 { 574 unsigned int type = dev->device & 0xff00; 575 576 if (type == 0x1000) 577 return pci_siig10x_init(dev); 578 if (type == 0x2000) 579 return pci_siig20x_init(dev); 580 581 moan_device("Unknown SIIG card", dev); 582 return -ENODEV; 583 } 584 585 static int pci_siig_setup(struct serial_private *priv, 586 const struct pciserial_board *board, 587 struct uart_8250_port *port, int idx) 588 { 589 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 590 591 if (idx > 3) { 592 bar = 4; 593 offset = (idx - 4) * 8; 594 } 595 596 return setup_port(priv, port, bar, offset, 0); 597 } 598 599 /* 600 * Timedia has an explosion of boards, and to avoid the PCI table from 601 * growing *huge*, we use this function to collapse some 70 entries 602 * in the PCI table into one, for sanity's and compactness's sake. 603 */ 604 static const unsigned short timedia_single_port[] = { 605 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 606 }; 607 608 static const unsigned short timedia_dual_port[] = { 609 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 610 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 611 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 612 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 613 0xD079, 0 614 }; 615 616 static const unsigned short timedia_quad_port[] = { 617 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 618 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 619 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 620 0xB157, 0 621 }; 622 623 static const unsigned short timedia_eight_port[] = { 624 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 625 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 626 }; 627 628 static const struct timedia_struct { 629 int num; 630 const unsigned short *ids; 631 } timedia_data[] = { 632 { 1, timedia_single_port }, 633 { 2, timedia_dual_port }, 634 { 4, timedia_quad_port }, 635 { 8, timedia_eight_port } 636 }; 637 638 /* 639 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 640 * listing them individually, this driver merely grabs them all with 641 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 642 * and should be left free to be claimed by parport_serial instead. 643 */ 644 static int pci_timedia_probe(struct pci_dev *dev) 645 { 646 /* 647 * Check the third digit of the subdevice ID 648 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 649 */ 650 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 651 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 652 dev->subsystem_device); 653 return -ENODEV; 654 } 655 656 return 0; 657 } 658 659 static int pci_timedia_init(struct pci_dev *dev) 660 { 661 const unsigned short *ids; 662 int i, j; 663 664 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 665 ids = timedia_data[i].ids; 666 for (j = 0; ids[j]; j++) 667 if (dev->subsystem_device == ids[j]) 668 return timedia_data[i].num; 669 } 670 return 0; 671 } 672 673 /* 674 * Timedia/SUNIX uses a mixture of BARs and offsets 675 * Ugh, this is ugly as all hell --- TYT 676 */ 677 static int 678 pci_timedia_setup(struct serial_private *priv, 679 const struct pciserial_board *board, 680 struct uart_8250_port *port, int idx) 681 { 682 unsigned int bar = 0, offset = board->first_offset; 683 684 switch (idx) { 685 case 0: 686 bar = 0; 687 break; 688 case 1: 689 offset = board->uart_offset; 690 bar = 0; 691 break; 692 case 2: 693 bar = 1; 694 break; 695 case 3: 696 offset = board->uart_offset; 697 fallthrough; 698 case 4: /* BAR 2 */ 699 case 5: /* BAR 3 */ 700 case 6: /* BAR 4 */ 701 case 7: /* BAR 5 */ 702 bar = idx - 2; 703 } 704 705 return setup_port(priv, port, bar, offset, board->reg_shift); 706 } 707 708 /* 709 * Some Titan cards are also a little weird 710 */ 711 static int 712 titan_400l_800l_setup(struct serial_private *priv, 713 const struct pciserial_board *board, 714 struct uart_8250_port *port, int idx) 715 { 716 unsigned int bar, offset = board->first_offset; 717 718 switch (idx) { 719 case 0: 720 bar = 1; 721 break; 722 case 1: 723 bar = 2; 724 break; 725 default: 726 bar = 4; 727 offset = (idx - 2) * board->uart_offset; 728 } 729 730 return setup_port(priv, port, bar, offset, board->reg_shift); 731 } 732 733 static int pci_xircom_init(struct pci_dev *dev) 734 { 735 msleep(100); 736 return 0; 737 } 738 739 static int pci_ni8420_init(struct pci_dev *dev) 740 { 741 void __iomem *p; 742 unsigned int bar = 0; 743 744 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 745 moan_device("no memory in bar", dev); 746 return 0; 747 } 748 749 p = pci_ioremap_bar(dev, bar); 750 if (p == NULL) 751 return -ENOMEM; 752 753 /* Enable CPU Interrupt */ 754 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 755 p + NI8420_INT_ENABLE_REG); 756 757 iounmap(p); 758 return 0; 759 } 760 761 #define MITE_IOWBSR1_WSIZE 0xa 762 #define MITE_IOWBSR1_WIN_OFFSET 0x800 763 #define MITE_IOWBSR1_WENAB (1 << 7) 764 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 765 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 766 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 767 768 static int pci_ni8430_init(struct pci_dev *dev) 769 { 770 void __iomem *p; 771 struct pci_bus_region region; 772 u32 device_window; 773 unsigned int bar = 0; 774 775 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 776 moan_device("no memory in bar", dev); 777 return 0; 778 } 779 780 p = pci_ioremap_bar(dev, bar); 781 if (p == NULL) 782 return -ENOMEM; 783 784 /* 785 * Set device window address and size in BAR0, while acknowledging that 786 * the resource structure may contain a translated address that differs 787 * from the address the device responds to. 788 */ 789 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 790 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 791 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 792 writel(device_window, p + MITE_IOWBSR1); 793 794 /* Set window access to go to RAMSEL IO address space */ 795 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 796 p + MITE_IOWCR1); 797 798 /* Enable IO Bus Interrupt 0 */ 799 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 800 801 /* Enable CPU Interrupt */ 802 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 803 804 iounmap(p); 805 return 0; 806 } 807 808 /* UART Port Control Register */ 809 #define NI8430_PORTCON 0x0f 810 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 811 812 static int 813 pci_ni8430_setup(struct serial_private *priv, 814 const struct pciserial_board *board, 815 struct uart_8250_port *port, int idx) 816 { 817 struct pci_dev *dev = priv->dev; 818 void __iomem *p; 819 unsigned int bar, offset = board->first_offset; 820 821 if (idx >= board->num_ports) 822 return 1; 823 824 bar = FL_GET_BASE(board->flags); 825 offset += idx * board->uart_offset; 826 827 p = pci_ioremap_bar(dev, bar); 828 if (!p) 829 return -ENOMEM; 830 831 /* enable the transceiver */ 832 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 833 p + offset + NI8430_PORTCON); 834 835 iounmap(p); 836 837 return setup_port(priv, port, bar, offset, board->reg_shift); 838 } 839 840 static int pci_netmos_9900_setup(struct serial_private *priv, 841 const struct pciserial_board *board, 842 struct uart_8250_port *port, int idx) 843 { 844 unsigned int bar; 845 846 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 847 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 848 /* netmos apparently orders BARs by datasheet layout, so serial 849 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 850 */ 851 bar = 3 * idx; 852 853 return setup_port(priv, port, bar, 0, board->reg_shift); 854 } 855 856 return pci_default_setup(priv, board, port, idx); 857 } 858 859 /* the 99xx series comes with a range of device IDs and a variety 860 * of capabilities: 861 * 862 * 9900 has varying capabilities and can cascade to sub-controllers 863 * (cascading should be purely internal) 864 * 9904 is hardwired with 4 serial ports 865 * 9912 and 9922 are hardwired with 2 serial ports 866 */ 867 static int pci_netmos_9900_numports(struct pci_dev *dev) 868 { 869 unsigned int c = dev->class; 870 unsigned int pi; 871 unsigned short sub_serports; 872 873 pi = c & 0xff; 874 875 if (pi == 2) 876 return 1; 877 878 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 879 /* two possibilities: 0x30ps encodes number of parallel and 880 * serial ports, or 0x1000 indicates *something*. This is not 881 * immediately obvious, since the 2s1p+4s configuration seems 882 * to offer all functionality on functions 0..2, while still 883 * advertising the same function 3 as the 4s+2s1p config. 884 */ 885 sub_serports = dev->subsystem_device & 0xf; 886 if (sub_serports > 0) 887 return sub_serports; 888 889 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 890 return 0; 891 } 892 893 moan_device("unknown NetMos/Mostech program interface", dev); 894 return 0; 895 } 896 897 static int pci_netmos_init(struct pci_dev *dev) 898 { 899 /* subdevice 0x00PS means <P> parallel, <S> serial */ 900 unsigned int num_serial = dev->subsystem_device & 0xf; 901 902 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 903 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 904 return 0; 905 906 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 907 dev->subsystem_device == 0x0299) 908 return 0; 909 910 switch (dev->device) { /* FALLTHROUGH on all */ 911 case PCI_DEVICE_ID_NETMOS_9904: 912 case PCI_DEVICE_ID_NETMOS_9912: 913 case PCI_DEVICE_ID_NETMOS_9922: 914 case PCI_DEVICE_ID_NETMOS_9900: 915 num_serial = pci_netmos_9900_numports(dev); 916 break; 917 918 default: 919 break; 920 } 921 922 if (num_serial == 0) { 923 moan_device("unknown NetMos/Mostech device", dev); 924 return -ENODEV; 925 } 926 927 return num_serial; 928 } 929 930 /* 931 * These chips are available with optionally one parallel port and up to 932 * two serial ports. Unfortunately they all have the same product id. 933 * 934 * Basic configuration is done over a region of 32 I/O ports. The base 935 * ioport is called INTA or INTC, depending on docs/other drivers. 936 * 937 * The region of the 32 I/O ports is configured in POSIO0R... 938 */ 939 940 /* registers */ 941 #define ITE_887x_MISCR 0x9c 942 #define ITE_887x_INTCBAR 0x78 943 #define ITE_887x_UARTBAR 0x7c 944 #define ITE_887x_PS0BAR 0x10 945 #define ITE_887x_POSIO0 0x60 946 947 /* I/O space size */ 948 #define ITE_887x_IOSIZE 32 949 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 950 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 951 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 952 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 953 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 954 #define ITE_887x_POSIO_SPEED (3 << 29) 955 /* enable IO_Space bit */ 956 #define ITE_887x_POSIO_ENABLE (1 << 31) 957 958 /* inta_addr are the configuration addresses of the ITE */ 959 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 960 static int pci_ite887x_init(struct pci_dev *dev) 961 { 962 int ret, i, type; 963 struct resource *iobase = NULL; 964 u32 miscr, uartbar, ioport; 965 966 /* search for the base-ioport */ 967 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 968 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 969 "ite887x"); 970 if (iobase != NULL) { 971 /* write POSIO0R - speed | size | ioport */ 972 pci_write_config_dword(dev, ITE_887x_POSIO0, 973 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 974 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 975 /* write INTCBAR - ioport */ 976 pci_write_config_dword(dev, ITE_887x_INTCBAR, 977 inta_addr[i]); 978 ret = inb(inta_addr[i]); 979 if (ret != 0xff) { 980 /* ioport connected */ 981 break; 982 } 983 release_region(iobase->start, ITE_887x_IOSIZE); 984 } 985 } 986 987 if (i == ARRAY_SIZE(inta_addr)) { 988 pci_err(dev, "could not find iobase\n"); 989 return -ENODEV; 990 } 991 992 /* start of undocumented type checking (see parport_pc.c) */ 993 type = inb(iobase->start + 0x18) & 0x0f; 994 995 switch (type) { 996 case 0x2: /* ITE8871 (1P) */ 997 case 0xa: /* ITE8875 (1P) */ 998 ret = 0; 999 break; 1000 case 0xe: /* ITE8872 (2S1P) */ 1001 ret = 2; 1002 break; 1003 case 0x6: /* ITE8873 (1S) */ 1004 ret = 1; 1005 break; 1006 case 0x8: /* ITE8874 (2S) */ 1007 ret = 2; 1008 break; 1009 default: 1010 moan_device("Unknown ITE887x", dev); 1011 ret = -ENODEV; 1012 } 1013 1014 /* configure all serial ports */ 1015 for (i = 0; i < ret; i++) { 1016 /* read the I/O port from the device */ 1017 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 1018 &ioport); 1019 ioport &= 0x0000FF00; /* the actual base address */ 1020 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 1021 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 1022 ITE_887x_POSIO_IOSIZE_8 | ioport); 1023 1024 /* write the ioport to the UARTBAR */ 1025 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 1026 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 1027 uartbar |= (ioport << (16 * i)); /* set the ioport */ 1028 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 1029 1030 /* get current config */ 1031 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 1032 /* disable interrupts (UARTx_Routing[3:0]) */ 1033 miscr &= ~(0xf << (12 - 4 * i)); 1034 /* activate the UART (UARTx_En) */ 1035 miscr |= 1 << (23 - i); 1036 /* write new config with activated UART */ 1037 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 1038 } 1039 1040 if (ret <= 0) { 1041 /* the device has no UARTs if we get here */ 1042 release_region(iobase->start, ITE_887x_IOSIZE); 1043 } 1044 1045 return ret; 1046 } 1047 1048 static void pci_ite887x_exit(struct pci_dev *dev) 1049 { 1050 u32 ioport; 1051 /* the ioport is bit 0-15 in POSIO0R */ 1052 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 1053 ioport &= 0xffff; 1054 release_region(ioport, ITE_887x_IOSIZE); 1055 } 1056 1057 /* 1058 * Oxford Semiconductor Inc. 1059 * Check if an OxSemi device is part of the Tornado range of devices. 1060 */ 1061 #define PCI_VENDOR_ID_ENDRUN 0x7401 1062 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1063 1064 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1065 { 1066 /* OxSemi Tornado devices are all 0xCxxx */ 1067 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1068 (dev->device & 0xf000) != 0xc000) 1069 return false; 1070 1071 /* EndRun devices are all 0xExxx */ 1072 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1073 (dev->device & 0xf000) != 0xe000) 1074 return false; 1075 1076 return true; 1077 } 1078 1079 /* 1080 * Determine the number of ports available on a Tornado device. 1081 */ 1082 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1083 { 1084 u8 __iomem *p; 1085 unsigned long deviceID; 1086 unsigned int number_uarts = 0; 1087 1088 if (!pci_oxsemi_tornado_p(dev)) 1089 return 0; 1090 1091 p = pci_iomap(dev, 0, 5); 1092 if (p == NULL) 1093 return -ENOMEM; 1094 1095 deviceID = ioread32(p); 1096 /* Tornado device */ 1097 if (deviceID == 0x07000200) { 1098 number_uarts = ioread8(p + 4); 1099 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1100 number_uarts, 1101 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1102 "EndRun" : "Oxford"); 1103 } 1104 pci_iounmap(dev, p); 1105 return number_uarts; 1106 } 1107 1108 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1109 #define OXSEMI_TORNADO_TCR_MASK 0xf 1110 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1111 #define OXSEMI_TORNADO_CPR_MIN 0x008 1112 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1113 1114 /* 1115 * Determine the oversampling rate, the clock prescaler, and the clock 1116 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1117 * which is four times the baud base, and the prescaler increments in 1118 * steps of 1/8. Therefore to make calculations on integers we need 1119 * to use a scaled clock rate, which is the baud base multiplied by 32 1120 * (or our assumed UART clock rate multiplied by 2). 1121 * 1122 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1123 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1124 * values between 1.000 and 63.875 inclusive (operation for values from 1125 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1126 * unsigned 16-bit integer. 1127 * 1128 * For the most accurate baud rate we use a table of predetermined 1129 * oversampling rates and clock prescalers that records all possible 1130 * products of the two parameters in the range from 4 up to 255 inclusive, 1131 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1132 * by 8. The table is sorted by the decreasing value of the oversampling 1133 * rate and ties are resolved by sorting by the decreasing value of the 1134 * product. This way preference is given to higher oversampling rates. 1135 * 1136 * We iterate over the table and choose the product of an oversampling 1137 * rate and a clock prescaler that gives the lowest integer division 1138 * result deviation, or if an exact integer divider is found we stop 1139 * looking for it right away. We do some fixup if the resulting clock 1140 * divisor required would be out of its unsigned 16-bit integer range. 1141 * 1142 * Finally we abuse the supposed fractional part returned to encode the 1143 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1144 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1145 */ 1146 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1147 unsigned int baud, 1148 unsigned int *frac) 1149 { 1150 static u8 p[][2] = { 1151 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1152 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1153 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1154 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1155 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1156 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1157 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1158 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1159 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1160 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1161 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1162 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1163 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1164 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1165 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1166 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1167 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1168 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1169 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1170 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1171 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1172 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1173 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1174 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1175 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1176 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1177 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1178 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1179 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1180 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1181 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1182 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1183 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1184 { 4, 9, }, { 4, 8, }, 1185 }; 1186 /* Scale the quotient for comparison to get the fractional part. */ 1187 const unsigned int quot_scale = 65536; 1188 unsigned int sclk = port->uartclk * 2; 1189 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1190 unsigned int best_squot; 1191 unsigned int squot; 1192 unsigned int quot; 1193 u16 cpr; 1194 u8 tcr; 1195 int i; 1196 1197 /* Old custom speed handling. */ 1198 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1199 unsigned int cust_div = port->custom_divisor; 1200 1201 quot = cust_div & UART_DIV_MAX; 1202 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1203 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1204 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1205 cpr = OXSEMI_TORNADO_CPR_DEF; 1206 } else { 1207 best_squot = quot_scale; 1208 for (i = 0; i < ARRAY_SIZE(p); i++) { 1209 unsigned int spre; 1210 unsigned int srem; 1211 u8 cp; 1212 u8 tc; 1213 1214 tc = p[i][0]; 1215 cp = p[i][1]; 1216 spre = tc * cp; 1217 1218 srem = sdiv % spre; 1219 if (srem > spre / 2) 1220 srem = spre - srem; 1221 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1222 1223 if (srem == 0) { 1224 tcr = tc; 1225 cpr = cp; 1226 quot = sdiv / spre; 1227 break; 1228 } else if (squot < best_squot) { 1229 best_squot = squot; 1230 tcr = tc; 1231 cpr = cp; 1232 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1233 } 1234 } 1235 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1236 quot % 2 == 0) { 1237 quot >>= 1; 1238 tcr <<= 1; 1239 } 1240 while (quot > UART_DIV_MAX) { 1241 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1242 quot >>= 1; 1243 tcr <<= 1; 1244 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1245 quot >>= 1; 1246 cpr <<= 1; 1247 } else { 1248 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1249 cpr = OXSEMI_TORNADO_CPR_MASK; 1250 } 1251 } 1252 } 1253 1254 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1255 return quot; 1256 } 1257 1258 /* 1259 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1260 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1261 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1262 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1263 * has to be written first, followed by CPR2, which occupies the location 1264 * of CKS used with earlier UART designs. 1265 */ 1266 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1267 unsigned int baud, 1268 unsigned int quot, 1269 unsigned int quot_frac) 1270 { 1271 struct uart_8250_port *up = up_to_u8250p(port); 1272 u8 cpr2 = quot_frac >> 16; 1273 u8 cpr = quot_frac >> 8; 1274 u8 tcr = quot_frac; 1275 1276 serial_icr_write(up, UART_TCR, tcr); 1277 serial_icr_write(up, UART_CPR, cpr); 1278 serial_icr_write(up, UART_CKS, cpr2); 1279 serial8250_do_set_divisor(port, baud, quot, 0); 1280 } 1281 1282 /* 1283 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1284 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1285 */ 1286 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1287 unsigned int mctrl) 1288 { 1289 struct uart_8250_port *up = up_to_u8250p(port); 1290 1291 up->mcr |= UART_MCR_CLKSEL; 1292 serial8250_do_set_mctrl(port, mctrl); 1293 } 1294 1295 /* 1296 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1297 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1298 */ 1299 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1300 const struct pciserial_board *board, 1301 struct uart_8250_port *up, int idx) 1302 { 1303 struct pci_dev *dev = priv->dev; 1304 1305 if (pci_oxsemi_tornado_p(dev)) { 1306 up->port.flags |= UPF_FULL_PROBE; 1307 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1308 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1309 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1310 } 1311 1312 return pci_default_setup(priv, board, up, idx); 1313 } 1314 1315 #define QPCR_TEST_FOR1 0x3F 1316 #define QPCR_TEST_GET1 0x00 1317 #define QPCR_TEST_FOR2 0x40 1318 #define QPCR_TEST_GET2 0x40 1319 #define QPCR_TEST_FOR3 0x80 1320 #define QPCR_TEST_GET3 0x40 1321 #define QPCR_TEST_FOR4 0xC0 1322 #define QPCR_TEST_GET4 0x80 1323 1324 #define QOPR_CLOCK_X1 0x0000 1325 #define QOPR_CLOCK_X2 0x0001 1326 #define QOPR_CLOCK_X4 0x0002 1327 #define QOPR_CLOCK_X8 0x0003 1328 #define QOPR_CLOCK_RATE_MASK 0x0003 1329 1330 /* Quatech devices have their own extra interface features */ 1331 static struct pci_device_id quatech_cards[] = { 1332 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1333 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1334 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1335 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1336 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1337 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1338 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1339 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1340 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1341 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1342 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1343 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1344 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1345 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1346 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1347 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1348 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1349 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1350 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1351 { 0, } 1352 }; 1353 1354 static int pci_quatech_rqopr(struct uart_8250_port *port) 1355 { 1356 unsigned long base = port->port.iobase; 1357 u8 LCR, val; 1358 1359 LCR = inb(base + UART_LCR); 1360 outb(0xBF, base + UART_LCR); 1361 val = inb(base + UART_SCR); 1362 outb(LCR, base + UART_LCR); 1363 return val; 1364 } 1365 1366 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1367 { 1368 unsigned long base = port->port.iobase; 1369 u8 LCR; 1370 1371 LCR = inb(base + UART_LCR); 1372 outb(0xBF, base + UART_LCR); 1373 inb(base + UART_SCR); 1374 outb(qopr, base + UART_SCR); 1375 outb(LCR, base + UART_LCR); 1376 } 1377 1378 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1379 { 1380 unsigned long base = port->port.iobase; 1381 u8 LCR, val, qmcr; 1382 1383 LCR = inb(base + UART_LCR); 1384 outb(0xBF, base + UART_LCR); 1385 val = inb(base + UART_SCR); 1386 outb(val | 0x10, base + UART_SCR); 1387 qmcr = inb(base + UART_MCR); 1388 outb(val, base + UART_SCR); 1389 outb(LCR, base + UART_LCR); 1390 1391 return qmcr; 1392 } 1393 1394 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1395 { 1396 unsigned long base = port->port.iobase; 1397 u8 LCR, val; 1398 1399 LCR = inb(base + UART_LCR); 1400 outb(0xBF, base + UART_LCR); 1401 val = inb(base + UART_SCR); 1402 outb(val | 0x10, base + UART_SCR); 1403 outb(qmcr, base + UART_MCR); 1404 outb(val, base + UART_SCR); 1405 outb(LCR, base + UART_LCR); 1406 } 1407 1408 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1409 { 1410 unsigned long base = port->port.iobase; 1411 u8 LCR, val; 1412 1413 LCR = inb(base + UART_LCR); 1414 outb(0xBF, base + UART_LCR); 1415 val = inb(base + UART_SCR); 1416 if (val & 0x20) { 1417 outb(0x80, UART_LCR); 1418 if (!(inb(UART_SCR) & 0x20)) { 1419 outb(LCR, base + UART_LCR); 1420 return 1; 1421 } 1422 } 1423 return 0; 1424 } 1425 1426 static int pci_quatech_test(struct uart_8250_port *port) 1427 { 1428 u8 reg, qopr; 1429 1430 qopr = pci_quatech_rqopr(port); 1431 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1432 reg = pci_quatech_rqopr(port) & 0xC0; 1433 if (reg != QPCR_TEST_GET1) 1434 return -EINVAL; 1435 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1436 reg = pci_quatech_rqopr(port) & 0xC0; 1437 if (reg != QPCR_TEST_GET2) 1438 return -EINVAL; 1439 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1440 reg = pci_quatech_rqopr(port) & 0xC0; 1441 if (reg != QPCR_TEST_GET3) 1442 return -EINVAL; 1443 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1444 reg = pci_quatech_rqopr(port) & 0xC0; 1445 if (reg != QPCR_TEST_GET4) 1446 return -EINVAL; 1447 1448 pci_quatech_wqopr(port, qopr); 1449 return 0; 1450 } 1451 1452 static int pci_quatech_clock(struct uart_8250_port *port) 1453 { 1454 u8 qopr, reg, set; 1455 unsigned long clock; 1456 1457 if (pci_quatech_test(port) < 0) 1458 return 1843200; 1459 1460 qopr = pci_quatech_rqopr(port); 1461 1462 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1463 reg = pci_quatech_rqopr(port); 1464 if (reg & QOPR_CLOCK_X8) { 1465 clock = 1843200; 1466 goto out; 1467 } 1468 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1469 reg = pci_quatech_rqopr(port); 1470 if (!(reg & QOPR_CLOCK_X8)) { 1471 clock = 1843200; 1472 goto out; 1473 } 1474 reg &= QOPR_CLOCK_X8; 1475 if (reg == QOPR_CLOCK_X2) { 1476 clock = 3685400; 1477 set = QOPR_CLOCK_X2; 1478 } else if (reg == QOPR_CLOCK_X4) { 1479 clock = 7372800; 1480 set = QOPR_CLOCK_X4; 1481 } else if (reg == QOPR_CLOCK_X8) { 1482 clock = 14745600; 1483 set = QOPR_CLOCK_X8; 1484 } else { 1485 clock = 1843200; 1486 set = QOPR_CLOCK_X1; 1487 } 1488 qopr &= ~QOPR_CLOCK_RATE_MASK; 1489 qopr |= set; 1490 1491 out: 1492 pci_quatech_wqopr(port, qopr); 1493 return clock; 1494 } 1495 1496 static int pci_quatech_rs422(struct uart_8250_port *port) 1497 { 1498 u8 qmcr; 1499 int rs422 = 0; 1500 1501 if (!pci_quatech_has_qmcr(port)) 1502 return 0; 1503 qmcr = pci_quatech_rqmcr(port); 1504 pci_quatech_wqmcr(port, 0xFF); 1505 if (pci_quatech_rqmcr(port)) 1506 rs422 = 1; 1507 pci_quatech_wqmcr(port, qmcr); 1508 return rs422; 1509 } 1510 1511 static int pci_quatech_init(struct pci_dev *dev) 1512 { 1513 const struct pci_device_id *match; 1514 bool amcc = false; 1515 1516 match = pci_match_id(quatech_cards, dev); 1517 if (match) 1518 amcc = match->driver_data; 1519 else 1520 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1521 1522 if (amcc) { 1523 unsigned long base = pci_resource_start(dev, 0); 1524 if (base) { 1525 u32 tmp; 1526 1527 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1528 tmp = inl(base + 0x3c); 1529 outl(tmp | 0x01000000, base + 0x3c); 1530 outl(tmp & ~0x01000000, base + 0x3c); 1531 } 1532 } 1533 return 0; 1534 } 1535 1536 static int pci_quatech_setup(struct serial_private *priv, 1537 const struct pciserial_board *board, 1538 struct uart_8250_port *port, int idx) 1539 { 1540 /* Needed by pci_quatech calls below */ 1541 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1542 /* Set up the clocking */ 1543 port->port.uartclk = pci_quatech_clock(port); 1544 /* For now just warn about RS422 */ 1545 if (pci_quatech_rs422(port)) 1546 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1547 return pci_default_setup(priv, board, port, idx); 1548 } 1549 1550 static int pci_default_setup(struct serial_private *priv, 1551 const struct pciserial_board *board, 1552 struct uart_8250_port *port, int idx) 1553 { 1554 unsigned int bar, offset = board->first_offset, maxnr; 1555 1556 bar = FL_GET_BASE(board->flags); 1557 if (board->flags & FL_BASE_BARS) 1558 bar += idx; 1559 else 1560 offset += idx * board->uart_offset; 1561 1562 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1563 (board->reg_shift + 3); 1564 1565 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1566 return 1; 1567 1568 return setup_port(priv, port, bar, offset, board->reg_shift); 1569 } 1570 1571 static int 1572 ce4100_serial_setup(struct serial_private *priv, 1573 const struct pciserial_board *board, 1574 struct uart_8250_port *port, int idx) 1575 { 1576 int ret; 1577 1578 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1579 port->port.iotype = UPIO_MEM32; 1580 port->port.type = PORT_XSCALE; 1581 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1582 port->port.regshift = 2; 1583 1584 return ret; 1585 } 1586 1587 static int 1588 pci_omegapci_setup(struct serial_private *priv, 1589 const struct pciserial_board *board, 1590 struct uart_8250_port *port, int idx) 1591 { 1592 return setup_port(priv, port, 2, idx * 8, 0); 1593 } 1594 1595 static int 1596 pci_brcm_trumanage_setup(struct serial_private *priv, 1597 const struct pciserial_board *board, 1598 struct uart_8250_port *port, int idx) 1599 { 1600 int ret = pci_default_setup(priv, board, port, idx); 1601 1602 port->port.type = PORT_BRCM_TRUMANAGE; 1603 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1604 return ret; 1605 } 1606 1607 /* RTS will control by MCR if this bit is 0 */ 1608 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1609 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1610 #define FINTEK_RTS_INVERT BIT(5) 1611 1612 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1613 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1614 struct serial_rs485 *rs485) 1615 { 1616 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1617 u8 setting; 1618 u8 *index = (u8 *) port->private_data; 1619 1620 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1621 1622 if (rs485->flags & SER_RS485_ENABLED) { 1623 /* Enable RTS H/W control mode */ 1624 setting |= FINTEK_RTS_CONTROL_BY_HW; 1625 1626 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1627 /* RTS driving high on TX */ 1628 setting &= ~FINTEK_RTS_INVERT; 1629 } else { 1630 /* RTS driving low on TX */ 1631 setting |= FINTEK_RTS_INVERT; 1632 } 1633 } else { 1634 /* Disable RTS H/W control mode */ 1635 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1636 } 1637 1638 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1639 1640 return 0; 1641 } 1642 1643 static const struct serial_rs485 pci_fintek_rs485_supported = { 1644 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 1645 /* F81504/508/512 does not support RTS delay before or after send */ 1646 }; 1647 1648 static int pci_fintek_setup(struct serial_private *priv, 1649 const struct pciserial_board *board, 1650 struct uart_8250_port *port, int idx) 1651 { 1652 struct pci_dev *pdev = priv->dev; 1653 u8 *data; 1654 u8 config_base; 1655 u16 iobase; 1656 1657 config_base = 0x40 + 0x08 * idx; 1658 1659 /* Get the io address from configuration space */ 1660 pci_read_config_word(pdev, config_base + 4, &iobase); 1661 1662 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1663 1664 port->port.iotype = UPIO_PORT; 1665 port->port.iobase = iobase; 1666 port->port.rs485_config = pci_fintek_rs485_config; 1667 port->port.rs485_supported = pci_fintek_rs485_supported; 1668 1669 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1670 if (!data) 1671 return -ENOMEM; 1672 1673 /* preserve index in PCI configuration space */ 1674 *data = idx; 1675 port->port.private_data = data; 1676 1677 return 0; 1678 } 1679 1680 static int pci_fintek_init(struct pci_dev *dev) 1681 { 1682 unsigned long iobase; 1683 u32 max_port, i; 1684 resource_size_t bar_data[3]; 1685 u8 config_base; 1686 struct serial_private *priv = pci_get_drvdata(dev); 1687 1688 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1689 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1690 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1691 return -ENODEV; 1692 1693 switch (dev->device) { 1694 case 0x1104: /* 4 ports */ 1695 case 0x1108: /* 8 ports */ 1696 max_port = dev->device & 0xff; 1697 break; 1698 case 0x1112: /* 12 ports */ 1699 max_port = 12; 1700 break; 1701 default: 1702 return -EINVAL; 1703 } 1704 1705 /* Get the io address dispatch from the BIOS */ 1706 bar_data[0] = pci_resource_start(dev, 5); 1707 bar_data[1] = pci_resource_start(dev, 4); 1708 bar_data[2] = pci_resource_start(dev, 3); 1709 1710 for (i = 0; i < max_port; ++i) { 1711 /* UART0 configuration offset start from 0x40 */ 1712 config_base = 0x40 + 0x08 * i; 1713 1714 /* Calculate Real IO Port */ 1715 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1716 1717 /* Enable UART I/O port */ 1718 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1719 1720 /* Select 128-byte FIFO and 8x FIFO threshold */ 1721 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1722 1723 /* LSB UART */ 1724 pci_write_config_byte(dev, config_base + 0x04, 1725 (u8)(iobase & 0xff)); 1726 1727 /* MSB UART */ 1728 pci_write_config_byte(dev, config_base + 0x05, 1729 (u8)((iobase & 0xff00) >> 8)); 1730 1731 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1732 1733 if (!priv) { 1734 /* First init without port data 1735 * force init to RS232 Mode 1736 */ 1737 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1738 } 1739 } 1740 1741 return max_port; 1742 } 1743 1744 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1745 { 1746 struct f815xxa_data *data = p->private_data; 1747 unsigned long flags; 1748 1749 spin_lock_irqsave(&data->lock, flags); 1750 writeb(value, p->membase + offset); 1751 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1752 spin_unlock_irqrestore(&data->lock, flags); 1753 } 1754 1755 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1756 const struct pciserial_board *board, 1757 struct uart_8250_port *port, int idx) 1758 { 1759 struct pci_dev *pdev = priv->dev; 1760 struct f815xxa_data *data; 1761 1762 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1763 if (!data) 1764 return -ENOMEM; 1765 1766 data->idx = idx; 1767 spin_lock_init(&data->lock); 1768 1769 port->port.private_data = data; 1770 port->port.iotype = UPIO_MEM; 1771 port->port.flags |= UPF_IOREMAP; 1772 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1773 port->port.serial_out = f815xxa_mem_serial_out; 1774 1775 return 0; 1776 } 1777 1778 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1779 { 1780 u32 max_port, i; 1781 int config_base; 1782 1783 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1784 return -ENODEV; 1785 1786 switch (dev->device) { 1787 case 0x1204: /* 4 ports */ 1788 case 0x1208: /* 8 ports */ 1789 max_port = dev->device & 0xff; 1790 break; 1791 case 0x1212: /* 12 ports */ 1792 max_port = 12; 1793 break; 1794 default: 1795 return -EINVAL; 1796 } 1797 1798 /* Set to mmio decode */ 1799 pci_write_config_byte(dev, 0x209, 0x40); 1800 1801 for (i = 0; i < max_port; ++i) { 1802 /* UART0 configuration offset start from 0x2A0 */ 1803 config_base = 0x2A0 + 0x08 * i; 1804 1805 /* Select 128-byte FIFO and 8x FIFO threshold */ 1806 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1807 1808 /* Enable UART I/O port */ 1809 pci_write_config_byte(dev, config_base + 0, 0x01); 1810 } 1811 1812 return max_port; 1813 } 1814 1815 static int skip_tx_en_setup(struct serial_private *priv, 1816 const struct pciserial_board *board, 1817 struct uart_8250_port *port, int idx) 1818 { 1819 port->port.quirks |= UPQ_NO_TXEN_TEST; 1820 pci_dbg(priv->dev, 1821 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1822 priv->dev->vendor, priv->dev->device, 1823 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1824 1825 return pci_default_setup(priv, board, port, idx); 1826 } 1827 1828 static void kt_handle_break(struct uart_port *p) 1829 { 1830 struct uart_8250_port *up = up_to_u8250p(p); 1831 /* 1832 * On receipt of a BI, serial device in Intel ME (Intel 1833 * management engine) needs to have its fifos cleared for sane 1834 * SOL (Serial Over Lan) output. 1835 */ 1836 serial8250_clear_and_reinit_fifos(up); 1837 } 1838 1839 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1840 { 1841 struct uart_8250_port *up = up_to_u8250p(p); 1842 unsigned int val; 1843 1844 /* 1845 * When the Intel ME (management engine) gets reset its serial 1846 * port registers could return 0 momentarily. Functions like 1847 * serial8250_console_write, read and save the IER, perform 1848 * some operation and then restore it. In order to avoid 1849 * setting IER register inadvertently to 0, if the value read 1850 * is 0, double check with ier value in uart_8250_port and use 1851 * that instead. up->ier should be the same value as what is 1852 * currently configured. 1853 */ 1854 val = inb(p->iobase + offset); 1855 if (offset == UART_IER) { 1856 if (val == 0) 1857 val = up->ier; 1858 } 1859 return val; 1860 } 1861 1862 static int kt_serial_setup(struct serial_private *priv, 1863 const struct pciserial_board *board, 1864 struct uart_8250_port *port, int idx) 1865 { 1866 port->port.flags |= UPF_BUG_THRE; 1867 port->port.serial_in = kt_serial_in; 1868 port->port.handle_break = kt_handle_break; 1869 return skip_tx_en_setup(priv, board, port, idx); 1870 } 1871 1872 static int pci_eg20t_init(struct pci_dev *dev) 1873 { 1874 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1875 return -ENODEV; 1876 #else 1877 return 0; 1878 #endif 1879 } 1880 1881 static int 1882 pci_wch_ch353_setup(struct serial_private *priv, 1883 const struct pciserial_board *board, 1884 struct uart_8250_port *port, int idx) 1885 { 1886 port->port.flags |= UPF_FIXED_TYPE; 1887 port->port.type = PORT_16550A; 1888 return pci_default_setup(priv, board, port, idx); 1889 } 1890 1891 static int 1892 pci_wch_ch355_setup(struct serial_private *priv, 1893 const struct pciserial_board *board, 1894 struct uart_8250_port *port, int idx) 1895 { 1896 port->port.flags |= UPF_FIXED_TYPE; 1897 port->port.type = PORT_16550A; 1898 return pci_default_setup(priv, board, port, idx); 1899 } 1900 1901 static int 1902 pci_wch_ch38x_setup(struct serial_private *priv, 1903 const struct pciserial_board *board, 1904 struct uart_8250_port *port, int idx) 1905 { 1906 port->port.flags |= UPF_FIXED_TYPE; 1907 port->port.type = PORT_16850; 1908 return pci_default_setup(priv, board, port, idx); 1909 } 1910 1911 1912 #define CH384_XINT_ENABLE_REG 0xEB 1913 #define CH384_XINT_ENABLE_BIT 0x02 1914 1915 static int pci_wch_ch38x_init(struct pci_dev *dev) 1916 { 1917 int max_port; 1918 unsigned long iobase; 1919 1920 1921 switch (dev->device) { 1922 case 0x3853: /* 8 ports */ 1923 max_port = 8; 1924 break; 1925 default: 1926 return -EINVAL; 1927 } 1928 1929 iobase = pci_resource_start(dev, 0); 1930 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1931 1932 return max_port; 1933 } 1934 1935 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1936 { 1937 unsigned long iobase; 1938 1939 iobase = pci_resource_start(dev, 0); 1940 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1941 } 1942 1943 1944 static int 1945 pci_sunix_setup(struct serial_private *priv, 1946 const struct pciserial_board *board, 1947 struct uart_8250_port *port, int idx) 1948 { 1949 int bar; 1950 int offset; 1951 1952 port->port.flags |= UPF_FIXED_TYPE; 1953 port->port.type = PORT_SUNIX; 1954 1955 if (idx < 4) { 1956 bar = 0; 1957 offset = idx * board->uart_offset; 1958 } else { 1959 bar = 1; 1960 idx -= 4; 1961 idx = div_s64_rem(idx, 4, &offset); 1962 offset = idx * 64 + offset * board->uart_offset; 1963 } 1964 1965 return setup_port(priv, port, bar, offset, 0); 1966 } 1967 1968 #define MOXA_PUART_GPIO_EN 0x09 1969 #define MOXA_PUART_GPIO_OUT 0x0A 1970 1971 #define MOXA_GPIO_PIN2 BIT(2) 1972 1973 static bool pci_moxa_is_mini_pcie(unsigned short device) 1974 { 1975 if (device == PCI_DEVICE_ID_MOXA_CP102N || 1976 device == PCI_DEVICE_ID_MOXA_CP104N || 1977 device == PCI_DEVICE_ID_MOXA_CP112N || 1978 device == PCI_DEVICE_ID_MOXA_CP114N || 1979 device == PCI_DEVICE_ID_MOXA_CP132N || 1980 device == PCI_DEVICE_ID_MOXA_CP134N) 1981 return true; 1982 1983 return false; 1984 } 1985 1986 static int pci_moxa_init(struct pci_dev *dev) 1987 { 1988 unsigned short device = dev->device; 1989 resource_size_t iobar_addr = pci_resource_start(dev, 2); 1990 unsigned int num_ports = (device & 0x00F0) >> 4; 1991 u8 val; 1992 1993 /* 1994 * Enable hardware buffer to prevent break signal output when system boots up. 1995 * This hardware buffer is only supported on Mini PCIe series. 1996 */ 1997 if (pci_moxa_is_mini_pcie(device)) { 1998 /* Set GPIO direction */ 1999 val = inb(iobar_addr + MOXA_PUART_GPIO_EN); 2000 val |= MOXA_GPIO_PIN2; 2001 outb(val, iobar_addr + MOXA_PUART_GPIO_EN); 2002 /* Enable low GPIO */ 2003 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT); 2004 val &= ~MOXA_GPIO_PIN2; 2005 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT); 2006 } 2007 2008 return num_ports; 2009 } 2010 2011 static int 2012 pci_moxa_setup(struct serial_private *priv, 2013 const struct pciserial_board *board, 2014 struct uart_8250_port *port, int idx) 2015 { 2016 unsigned int bar = FL_GET_BASE(board->flags); 2017 int offset; 2018 2019 if (board->num_ports == 4 && idx == 3) 2020 offset = 7 * board->uart_offset; 2021 else 2022 offset = idx * board->uart_offset; 2023 2024 return setup_port(priv, port, bar, offset, 0); 2025 } 2026 2027 /* 2028 * Master list of serial port init/setup/exit quirks. 2029 * This does not describe the general nature of the port. 2030 * (ie, baud base, number and location of ports, etc) 2031 * 2032 * This list is ordered alphabetically by vendor then device. 2033 * Specific entries must come before more generic entries. 2034 */ 2035 static struct pci_serial_quirk pci_serial_quirks[] = { 2036 /* 2037 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2038 */ 2039 { 2040 .vendor = PCI_VENDOR_ID_AMCC, 2041 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2042 .subvendor = PCI_ANY_ID, 2043 .subdevice = PCI_ANY_ID, 2044 .setup = addidata_apci7800_setup, 2045 }, 2046 /* 2047 * AFAVLAB cards - these may be called via parport_serial 2048 * It is not clear whether this applies to all products. 2049 */ 2050 { 2051 .vendor = PCI_VENDOR_ID_AFAVLAB, 2052 .device = PCI_ANY_ID, 2053 .subvendor = PCI_ANY_ID, 2054 .subdevice = PCI_ANY_ID, 2055 .setup = afavlab_setup, 2056 }, 2057 /* 2058 * HP Diva 2059 */ 2060 { 2061 .vendor = PCI_VENDOR_ID_HP, 2062 .device = PCI_DEVICE_ID_HP_DIVA, 2063 .subvendor = PCI_ANY_ID, 2064 .subdevice = PCI_ANY_ID, 2065 .init = pci_hp_diva_init, 2066 .setup = pci_hp_diva_setup, 2067 }, 2068 /* 2069 * HPE PCI serial device 2070 */ 2071 { 2072 .vendor = PCI_VENDOR_ID_HP_3PAR, 2073 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2074 .subvendor = PCI_ANY_ID, 2075 .subdevice = PCI_ANY_ID, 2076 .setup = pci_hp_diva_setup, 2077 }, 2078 /* 2079 * Intel 2080 */ 2081 { 2082 .vendor = PCI_VENDOR_ID_INTEL, 2083 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2084 .subvendor = 0xe4bf, 2085 .subdevice = PCI_ANY_ID, 2086 .init = pci_inteli960ni_init, 2087 .setup = pci_default_setup, 2088 }, 2089 { 2090 .vendor = PCI_VENDOR_ID_INTEL, 2091 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2092 .subvendor = PCI_ANY_ID, 2093 .subdevice = PCI_ANY_ID, 2094 .setup = skip_tx_en_setup, 2095 }, 2096 { 2097 .vendor = PCI_VENDOR_ID_INTEL, 2098 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2099 .subvendor = PCI_ANY_ID, 2100 .subdevice = PCI_ANY_ID, 2101 .setup = skip_tx_en_setup, 2102 }, 2103 { 2104 .vendor = PCI_VENDOR_ID_INTEL, 2105 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2106 .subvendor = PCI_ANY_ID, 2107 .subdevice = PCI_ANY_ID, 2108 .setup = skip_tx_en_setup, 2109 }, 2110 { 2111 .vendor = PCI_VENDOR_ID_INTEL, 2112 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2113 .subvendor = PCI_ANY_ID, 2114 .subdevice = PCI_ANY_ID, 2115 .setup = ce4100_serial_setup, 2116 }, 2117 { 2118 .vendor = PCI_VENDOR_ID_INTEL, 2119 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2120 .subvendor = PCI_ANY_ID, 2121 .subdevice = PCI_ANY_ID, 2122 .setup = kt_serial_setup, 2123 }, 2124 /* 2125 * ITE 2126 */ 2127 { 2128 .vendor = PCI_VENDOR_ID_ITE, 2129 .device = PCI_DEVICE_ID_ITE_8872, 2130 .subvendor = PCI_ANY_ID, 2131 .subdevice = PCI_ANY_ID, 2132 .init = pci_ite887x_init, 2133 .setup = pci_default_setup, 2134 .exit = pci_ite887x_exit, 2135 }, 2136 /* 2137 * National Instruments 2138 */ 2139 { 2140 .vendor = PCI_VENDOR_ID_NI, 2141 .device = PCI_DEVICE_ID_NI_PCI23216, 2142 .subvendor = PCI_ANY_ID, 2143 .subdevice = PCI_ANY_ID, 2144 .init = pci_ni8420_init, 2145 .setup = pci_default_setup, 2146 .exit = pci_ni8420_exit, 2147 }, 2148 { 2149 .vendor = PCI_VENDOR_ID_NI, 2150 .device = PCI_DEVICE_ID_NI_PCI2328, 2151 .subvendor = PCI_ANY_ID, 2152 .subdevice = PCI_ANY_ID, 2153 .init = pci_ni8420_init, 2154 .setup = pci_default_setup, 2155 .exit = pci_ni8420_exit, 2156 }, 2157 { 2158 .vendor = PCI_VENDOR_ID_NI, 2159 .device = PCI_DEVICE_ID_NI_PCI2324, 2160 .subvendor = PCI_ANY_ID, 2161 .subdevice = PCI_ANY_ID, 2162 .init = pci_ni8420_init, 2163 .setup = pci_default_setup, 2164 .exit = pci_ni8420_exit, 2165 }, 2166 { 2167 .vendor = PCI_VENDOR_ID_NI, 2168 .device = PCI_DEVICE_ID_NI_PCI2322, 2169 .subvendor = PCI_ANY_ID, 2170 .subdevice = PCI_ANY_ID, 2171 .init = pci_ni8420_init, 2172 .setup = pci_default_setup, 2173 .exit = pci_ni8420_exit, 2174 }, 2175 { 2176 .vendor = PCI_VENDOR_ID_NI, 2177 .device = PCI_DEVICE_ID_NI_PCI2324I, 2178 .subvendor = PCI_ANY_ID, 2179 .subdevice = PCI_ANY_ID, 2180 .init = pci_ni8420_init, 2181 .setup = pci_default_setup, 2182 .exit = pci_ni8420_exit, 2183 }, 2184 { 2185 .vendor = PCI_VENDOR_ID_NI, 2186 .device = PCI_DEVICE_ID_NI_PCI2322I, 2187 .subvendor = PCI_ANY_ID, 2188 .subdevice = PCI_ANY_ID, 2189 .init = pci_ni8420_init, 2190 .setup = pci_default_setup, 2191 .exit = pci_ni8420_exit, 2192 }, 2193 { 2194 .vendor = PCI_VENDOR_ID_NI, 2195 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2196 .subvendor = PCI_ANY_ID, 2197 .subdevice = PCI_ANY_ID, 2198 .init = pci_ni8420_init, 2199 .setup = pci_default_setup, 2200 .exit = pci_ni8420_exit, 2201 }, 2202 { 2203 .vendor = PCI_VENDOR_ID_NI, 2204 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2205 .subvendor = PCI_ANY_ID, 2206 .subdevice = PCI_ANY_ID, 2207 .init = pci_ni8420_init, 2208 .setup = pci_default_setup, 2209 .exit = pci_ni8420_exit, 2210 }, 2211 { 2212 .vendor = PCI_VENDOR_ID_NI, 2213 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2214 .subvendor = PCI_ANY_ID, 2215 .subdevice = PCI_ANY_ID, 2216 .init = pci_ni8420_init, 2217 .setup = pci_default_setup, 2218 .exit = pci_ni8420_exit, 2219 }, 2220 { 2221 .vendor = PCI_VENDOR_ID_NI, 2222 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2223 .subvendor = PCI_ANY_ID, 2224 .subdevice = PCI_ANY_ID, 2225 .init = pci_ni8420_init, 2226 .setup = pci_default_setup, 2227 .exit = pci_ni8420_exit, 2228 }, 2229 { 2230 .vendor = PCI_VENDOR_ID_NI, 2231 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2232 .subvendor = PCI_ANY_ID, 2233 .subdevice = PCI_ANY_ID, 2234 .init = pci_ni8420_init, 2235 .setup = pci_default_setup, 2236 .exit = pci_ni8420_exit, 2237 }, 2238 { 2239 .vendor = PCI_VENDOR_ID_NI, 2240 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2241 .subvendor = PCI_ANY_ID, 2242 .subdevice = PCI_ANY_ID, 2243 .init = pci_ni8420_init, 2244 .setup = pci_default_setup, 2245 .exit = pci_ni8420_exit, 2246 }, 2247 { 2248 .vendor = PCI_VENDOR_ID_NI, 2249 .device = PCI_ANY_ID, 2250 .subvendor = PCI_ANY_ID, 2251 .subdevice = PCI_ANY_ID, 2252 .init = pci_ni8430_init, 2253 .setup = pci_ni8430_setup, 2254 .exit = pci_ni8430_exit, 2255 }, 2256 /* Quatech */ 2257 { 2258 .vendor = PCI_VENDOR_ID_QUATECH, 2259 .device = PCI_ANY_ID, 2260 .subvendor = PCI_ANY_ID, 2261 .subdevice = PCI_ANY_ID, 2262 .init = pci_quatech_init, 2263 .setup = pci_quatech_setup, 2264 }, 2265 /* 2266 * Panacom 2267 */ 2268 { 2269 .vendor = PCI_VENDOR_ID_PANACOM, 2270 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2271 .subvendor = PCI_ANY_ID, 2272 .subdevice = PCI_ANY_ID, 2273 .init = pci_plx9050_init, 2274 .setup = pci_default_setup, 2275 .exit = pci_plx9050_exit, 2276 }, 2277 { 2278 .vendor = PCI_VENDOR_ID_PANACOM, 2279 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .init = pci_plx9050_init, 2283 .setup = pci_default_setup, 2284 .exit = pci_plx9050_exit, 2285 }, 2286 /* 2287 * PLX 2288 */ 2289 { 2290 .vendor = PCI_VENDOR_ID_PLX, 2291 .device = PCI_DEVICE_ID_PLX_9050, 2292 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2293 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2294 .init = pci_plx9050_init, 2295 .setup = pci_default_setup, 2296 .exit = pci_plx9050_exit, 2297 }, 2298 { 2299 .vendor = PCI_VENDOR_ID_PLX, 2300 .device = PCI_DEVICE_ID_PLX_9050, 2301 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2302 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2303 .init = pci_plx9050_init, 2304 .setup = pci_default_setup, 2305 .exit = pci_plx9050_exit, 2306 }, 2307 { 2308 .vendor = PCI_VENDOR_ID_PLX, 2309 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2310 .subvendor = PCI_VENDOR_ID_PLX, 2311 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2312 .init = pci_plx9050_init, 2313 .setup = pci_default_setup, 2314 .exit = pci_plx9050_exit, 2315 }, 2316 /* 2317 * SBS Technologies, Inc., PMC-OCTALPRO 232 2318 */ 2319 { 2320 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2321 .device = PCI_DEVICE_ID_OCTPRO, 2322 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2323 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2324 .init = sbs_init, 2325 .setup = sbs_setup, 2326 .exit = sbs_exit, 2327 }, 2328 /* 2329 * SBS Technologies, Inc., PMC-OCTALPRO 422 2330 */ 2331 { 2332 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2333 .device = PCI_DEVICE_ID_OCTPRO, 2334 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2335 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2336 .init = sbs_init, 2337 .setup = sbs_setup, 2338 .exit = sbs_exit, 2339 }, 2340 /* 2341 * SBS Technologies, Inc., P-Octal 232 2342 */ 2343 { 2344 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2345 .device = PCI_DEVICE_ID_OCTPRO, 2346 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2347 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2348 .init = sbs_init, 2349 .setup = sbs_setup, 2350 .exit = sbs_exit, 2351 }, 2352 /* 2353 * SBS Technologies, Inc., P-Octal 422 2354 */ 2355 { 2356 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2357 .device = PCI_DEVICE_ID_OCTPRO, 2358 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2359 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2360 .init = sbs_init, 2361 .setup = sbs_setup, 2362 .exit = sbs_exit, 2363 }, 2364 /* 2365 * SIIG cards - these may be called via parport_serial 2366 */ 2367 { 2368 .vendor = PCI_VENDOR_ID_SIIG, 2369 .device = PCI_ANY_ID, 2370 .subvendor = PCI_ANY_ID, 2371 .subdevice = PCI_ANY_ID, 2372 .init = pci_siig_init, 2373 .setup = pci_siig_setup, 2374 }, 2375 /* 2376 * Titan cards 2377 */ 2378 { 2379 .vendor = PCI_VENDOR_ID_TITAN, 2380 .device = PCI_DEVICE_ID_TITAN_400L, 2381 .subvendor = PCI_ANY_ID, 2382 .subdevice = PCI_ANY_ID, 2383 .setup = titan_400l_800l_setup, 2384 }, 2385 { 2386 .vendor = PCI_VENDOR_ID_TITAN, 2387 .device = PCI_DEVICE_ID_TITAN_800L, 2388 .subvendor = PCI_ANY_ID, 2389 .subdevice = PCI_ANY_ID, 2390 .setup = titan_400l_800l_setup, 2391 }, 2392 /* 2393 * Timedia cards 2394 */ 2395 { 2396 .vendor = PCI_VENDOR_ID_TIMEDIA, 2397 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2398 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2399 .subdevice = PCI_ANY_ID, 2400 .probe = pci_timedia_probe, 2401 .init = pci_timedia_init, 2402 .setup = pci_timedia_setup, 2403 }, 2404 { 2405 .vendor = PCI_VENDOR_ID_TIMEDIA, 2406 .device = PCI_ANY_ID, 2407 .subvendor = PCI_ANY_ID, 2408 .subdevice = PCI_ANY_ID, 2409 .setup = pci_timedia_setup, 2410 }, 2411 /* 2412 * Sunix PCI serial boards 2413 */ 2414 { 2415 .vendor = PCI_VENDOR_ID_SUNIX, 2416 .device = PCI_DEVICE_ID_SUNIX_1999, 2417 .subvendor = PCI_VENDOR_ID_SUNIX, 2418 .subdevice = PCI_ANY_ID, 2419 .setup = pci_sunix_setup, 2420 }, 2421 /* 2422 * Xircom cards 2423 */ 2424 { 2425 .vendor = PCI_VENDOR_ID_XIRCOM, 2426 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2427 .subvendor = PCI_ANY_ID, 2428 .subdevice = PCI_ANY_ID, 2429 .init = pci_xircom_init, 2430 .setup = pci_default_setup, 2431 }, 2432 /* 2433 * Netmos cards - these may be called via parport_serial 2434 */ 2435 { 2436 .vendor = PCI_VENDOR_ID_NETMOS, 2437 .device = PCI_ANY_ID, 2438 .subvendor = PCI_ANY_ID, 2439 .subdevice = PCI_ANY_ID, 2440 .init = pci_netmos_init, 2441 .setup = pci_netmos_9900_setup, 2442 }, 2443 /* 2444 * EndRun Technologies 2445 */ 2446 { 2447 .vendor = PCI_VENDOR_ID_ENDRUN, 2448 .device = PCI_ANY_ID, 2449 .subvendor = PCI_ANY_ID, 2450 .subdevice = PCI_ANY_ID, 2451 .init = pci_oxsemi_tornado_init, 2452 .setup = pci_default_setup, 2453 }, 2454 /* 2455 * For Oxford Semiconductor Tornado based devices 2456 */ 2457 { 2458 .vendor = PCI_VENDOR_ID_OXSEMI, 2459 .device = PCI_ANY_ID, 2460 .subvendor = PCI_ANY_ID, 2461 .subdevice = PCI_ANY_ID, 2462 .init = pci_oxsemi_tornado_init, 2463 .setup = pci_oxsemi_tornado_setup, 2464 }, 2465 { 2466 .vendor = PCI_VENDOR_ID_MAINPINE, 2467 .device = PCI_ANY_ID, 2468 .subvendor = PCI_ANY_ID, 2469 .subdevice = PCI_ANY_ID, 2470 .init = pci_oxsemi_tornado_init, 2471 .setup = pci_oxsemi_tornado_setup, 2472 }, 2473 { 2474 .vendor = PCI_VENDOR_ID_DIGI, 2475 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2476 .subvendor = PCI_SUBVENDOR_ID_IBM, 2477 .subdevice = PCI_ANY_ID, 2478 .init = pci_oxsemi_tornado_init, 2479 .setup = pci_oxsemi_tornado_setup, 2480 }, 2481 /* 2482 * Brainboxes devices - all Oxsemi based 2483 */ 2484 { 2485 .vendor = PCI_VENDOR_ID_INTASHIELD, 2486 .device = 0x4027, 2487 .subvendor = PCI_ANY_ID, 2488 .subdevice = PCI_ANY_ID, 2489 .init = pci_oxsemi_tornado_init, 2490 .setup = pci_oxsemi_tornado_setup, 2491 }, 2492 { 2493 .vendor = PCI_VENDOR_ID_INTASHIELD, 2494 .device = 0x4028, 2495 .subvendor = PCI_ANY_ID, 2496 .subdevice = PCI_ANY_ID, 2497 .init = pci_oxsemi_tornado_init, 2498 .setup = pci_oxsemi_tornado_setup, 2499 }, 2500 { 2501 .vendor = PCI_VENDOR_ID_INTASHIELD, 2502 .device = 0x4029, 2503 .subvendor = PCI_ANY_ID, 2504 .subdevice = PCI_ANY_ID, 2505 .init = pci_oxsemi_tornado_init, 2506 .setup = pci_oxsemi_tornado_setup, 2507 }, 2508 { 2509 .vendor = PCI_VENDOR_ID_INTASHIELD, 2510 .device = 0x4019, 2511 .subvendor = PCI_ANY_ID, 2512 .subdevice = PCI_ANY_ID, 2513 .init = pci_oxsemi_tornado_init, 2514 .setup = pci_oxsemi_tornado_setup, 2515 }, 2516 { 2517 .vendor = PCI_VENDOR_ID_INTASHIELD, 2518 .device = 0x4016, 2519 .subvendor = PCI_ANY_ID, 2520 .subdevice = PCI_ANY_ID, 2521 .init = pci_oxsemi_tornado_init, 2522 .setup = pci_oxsemi_tornado_setup, 2523 }, 2524 { 2525 .vendor = PCI_VENDOR_ID_INTASHIELD, 2526 .device = 0x4015, 2527 .subvendor = PCI_ANY_ID, 2528 .subdevice = PCI_ANY_ID, 2529 .init = pci_oxsemi_tornado_init, 2530 .setup = pci_oxsemi_tornado_setup, 2531 }, 2532 { 2533 .vendor = PCI_VENDOR_ID_INTASHIELD, 2534 .device = 0x400A, 2535 .subvendor = PCI_ANY_ID, 2536 .subdevice = PCI_ANY_ID, 2537 .init = pci_oxsemi_tornado_init, 2538 .setup = pci_oxsemi_tornado_setup, 2539 }, 2540 { 2541 .vendor = PCI_VENDOR_ID_INTASHIELD, 2542 .device = 0x400E, 2543 .subvendor = PCI_ANY_ID, 2544 .subdevice = PCI_ANY_ID, 2545 .init = pci_oxsemi_tornado_init, 2546 .setup = pci_oxsemi_tornado_setup, 2547 }, 2548 { 2549 .vendor = PCI_VENDOR_ID_INTASHIELD, 2550 .device = 0x400C, 2551 .subvendor = PCI_ANY_ID, 2552 .subdevice = PCI_ANY_ID, 2553 .init = pci_oxsemi_tornado_init, 2554 .setup = pci_oxsemi_tornado_setup, 2555 }, 2556 { 2557 .vendor = PCI_VENDOR_ID_INTASHIELD, 2558 .device = 0x400B, 2559 .subvendor = PCI_ANY_ID, 2560 .subdevice = PCI_ANY_ID, 2561 .init = pci_oxsemi_tornado_init, 2562 .setup = pci_oxsemi_tornado_setup, 2563 }, 2564 { 2565 .vendor = PCI_VENDOR_ID_INTASHIELD, 2566 .device = 0x400F, 2567 .subvendor = PCI_ANY_ID, 2568 .subdevice = PCI_ANY_ID, 2569 .init = pci_oxsemi_tornado_init, 2570 .setup = pci_oxsemi_tornado_setup, 2571 }, 2572 { 2573 .vendor = PCI_VENDOR_ID_INTASHIELD, 2574 .device = 0x4010, 2575 .subvendor = PCI_ANY_ID, 2576 .subdevice = PCI_ANY_ID, 2577 .init = pci_oxsemi_tornado_init, 2578 .setup = pci_oxsemi_tornado_setup, 2579 }, 2580 { 2581 .vendor = PCI_VENDOR_ID_INTASHIELD, 2582 .device = 0x4011, 2583 .subvendor = PCI_ANY_ID, 2584 .subdevice = PCI_ANY_ID, 2585 .init = pci_oxsemi_tornado_init, 2586 .setup = pci_oxsemi_tornado_setup, 2587 }, 2588 { 2589 .vendor = PCI_VENDOR_ID_INTASHIELD, 2590 .device = 0x401D, 2591 .subvendor = PCI_ANY_ID, 2592 .subdevice = PCI_ANY_ID, 2593 .init = pci_oxsemi_tornado_init, 2594 .setup = pci_oxsemi_tornado_setup, 2595 }, 2596 { 2597 .vendor = PCI_VENDOR_ID_INTASHIELD, 2598 .device = 0x401E, 2599 .subvendor = PCI_ANY_ID, 2600 .subdevice = PCI_ANY_ID, 2601 .init = pci_oxsemi_tornado_init, 2602 .setup = pci_oxsemi_tornado_setup, 2603 }, 2604 { 2605 .vendor = PCI_VENDOR_ID_INTASHIELD, 2606 .device = 0x4013, 2607 .subvendor = PCI_ANY_ID, 2608 .subdevice = PCI_ANY_ID, 2609 .init = pci_oxsemi_tornado_init, 2610 .setup = pci_oxsemi_tornado_setup, 2611 }, 2612 { 2613 .vendor = PCI_VENDOR_ID_INTASHIELD, 2614 .device = 0x4017, 2615 .subvendor = PCI_ANY_ID, 2616 .subdevice = PCI_ANY_ID, 2617 .init = pci_oxsemi_tornado_init, 2618 .setup = pci_oxsemi_tornado_setup, 2619 }, 2620 { 2621 .vendor = PCI_VENDOR_ID_INTASHIELD, 2622 .device = 0x4018, 2623 .subvendor = PCI_ANY_ID, 2624 .subdevice = PCI_ANY_ID, 2625 .init = pci_oxsemi_tornado_init, 2626 .setup = pci_oxsemi_tornado_setup, 2627 }, 2628 { 2629 .vendor = PCI_VENDOR_ID_INTEL, 2630 .device = 0x8811, 2631 .subvendor = PCI_ANY_ID, 2632 .subdevice = PCI_ANY_ID, 2633 .init = pci_eg20t_init, 2634 .setup = pci_default_setup, 2635 }, 2636 { 2637 .vendor = PCI_VENDOR_ID_INTEL, 2638 .device = 0x8812, 2639 .subvendor = PCI_ANY_ID, 2640 .subdevice = PCI_ANY_ID, 2641 .init = pci_eg20t_init, 2642 .setup = pci_default_setup, 2643 }, 2644 { 2645 .vendor = PCI_VENDOR_ID_INTEL, 2646 .device = 0x8813, 2647 .subvendor = PCI_ANY_ID, 2648 .subdevice = PCI_ANY_ID, 2649 .init = pci_eg20t_init, 2650 .setup = pci_default_setup, 2651 }, 2652 { 2653 .vendor = PCI_VENDOR_ID_INTEL, 2654 .device = 0x8814, 2655 .subvendor = PCI_ANY_ID, 2656 .subdevice = PCI_ANY_ID, 2657 .init = pci_eg20t_init, 2658 .setup = pci_default_setup, 2659 }, 2660 { 2661 .vendor = 0x10DB, 2662 .device = 0x8027, 2663 .subvendor = PCI_ANY_ID, 2664 .subdevice = PCI_ANY_ID, 2665 .init = pci_eg20t_init, 2666 .setup = pci_default_setup, 2667 }, 2668 { 2669 .vendor = 0x10DB, 2670 .device = 0x8028, 2671 .subvendor = PCI_ANY_ID, 2672 .subdevice = PCI_ANY_ID, 2673 .init = pci_eg20t_init, 2674 .setup = pci_default_setup, 2675 }, 2676 { 2677 .vendor = 0x10DB, 2678 .device = 0x8029, 2679 .subvendor = PCI_ANY_ID, 2680 .subdevice = PCI_ANY_ID, 2681 .init = pci_eg20t_init, 2682 .setup = pci_default_setup, 2683 }, 2684 { 2685 .vendor = 0x10DB, 2686 .device = 0x800C, 2687 .subvendor = PCI_ANY_ID, 2688 .subdevice = PCI_ANY_ID, 2689 .init = pci_eg20t_init, 2690 .setup = pci_default_setup, 2691 }, 2692 { 2693 .vendor = 0x10DB, 2694 .device = 0x800D, 2695 .subvendor = PCI_ANY_ID, 2696 .subdevice = PCI_ANY_ID, 2697 .init = pci_eg20t_init, 2698 .setup = pci_default_setup, 2699 }, 2700 /* 2701 * Cronyx Omega PCI (PLX-chip based) 2702 */ 2703 { 2704 .vendor = PCI_VENDOR_ID_PLX, 2705 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2706 .subvendor = PCI_ANY_ID, 2707 .subdevice = PCI_ANY_ID, 2708 .setup = pci_omegapci_setup, 2709 }, 2710 /* WCH CH353 1S1P card (16550 clone) */ 2711 { 2712 .vendor = PCI_VENDOR_ID_WCH, 2713 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2714 .subvendor = PCI_ANY_ID, 2715 .subdevice = PCI_ANY_ID, 2716 .setup = pci_wch_ch353_setup, 2717 }, 2718 /* WCH CH353 2S1P card (16550 clone) */ 2719 { 2720 .vendor = PCI_VENDOR_ID_WCH, 2721 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2722 .subvendor = PCI_ANY_ID, 2723 .subdevice = PCI_ANY_ID, 2724 .setup = pci_wch_ch353_setup, 2725 }, 2726 /* WCH CH353 4S card (16550 clone) */ 2727 { 2728 .vendor = PCI_VENDOR_ID_WCH, 2729 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2730 .subvendor = PCI_ANY_ID, 2731 .subdevice = PCI_ANY_ID, 2732 .setup = pci_wch_ch353_setup, 2733 }, 2734 /* WCH CH353 2S1PF card (16550 clone) */ 2735 { 2736 .vendor = PCI_VENDOR_ID_WCH, 2737 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2738 .subvendor = PCI_ANY_ID, 2739 .subdevice = PCI_ANY_ID, 2740 .setup = pci_wch_ch353_setup, 2741 }, 2742 /* WCH CH352 2S card (16550 clone) */ 2743 { 2744 .vendor = PCI_VENDOR_ID_WCH, 2745 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2746 .subvendor = PCI_ANY_ID, 2747 .subdevice = PCI_ANY_ID, 2748 .setup = pci_wch_ch353_setup, 2749 }, 2750 /* WCH CH355 4S card (16550 clone) */ 2751 { 2752 .vendor = PCI_VENDOR_ID_WCH, 2753 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2754 .subvendor = PCI_ANY_ID, 2755 .subdevice = PCI_ANY_ID, 2756 .setup = pci_wch_ch355_setup, 2757 }, 2758 /* WCH CH382 2S card (16850 clone) */ 2759 { 2760 .vendor = PCIE_VENDOR_ID_WCH, 2761 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2762 .subvendor = PCI_ANY_ID, 2763 .subdevice = PCI_ANY_ID, 2764 .setup = pci_wch_ch38x_setup, 2765 }, 2766 /* WCH CH382 2S1P card (16850 clone) */ 2767 { 2768 .vendor = PCIE_VENDOR_ID_WCH, 2769 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2770 .subvendor = PCI_ANY_ID, 2771 .subdevice = PCI_ANY_ID, 2772 .setup = pci_wch_ch38x_setup, 2773 }, 2774 /* WCH CH384 4S card (16850 clone) */ 2775 { 2776 .vendor = PCIE_VENDOR_ID_WCH, 2777 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2778 .subvendor = PCI_ANY_ID, 2779 .subdevice = PCI_ANY_ID, 2780 .setup = pci_wch_ch38x_setup, 2781 }, 2782 /* WCH CH384 8S card (16850 clone) */ 2783 { 2784 .vendor = PCIE_VENDOR_ID_WCH, 2785 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2786 .subvendor = PCI_ANY_ID, 2787 .subdevice = PCI_ANY_ID, 2788 .init = pci_wch_ch38x_init, 2789 .exit = pci_wch_ch38x_exit, 2790 .setup = pci_wch_ch38x_setup, 2791 }, 2792 /* 2793 * Broadcom TruManage (NetXtreme) 2794 */ 2795 { 2796 .vendor = PCI_VENDOR_ID_BROADCOM, 2797 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2798 .subvendor = PCI_ANY_ID, 2799 .subdevice = PCI_ANY_ID, 2800 .setup = pci_brcm_trumanage_setup, 2801 }, 2802 { 2803 .vendor = 0x1c29, 2804 .device = 0x1104, 2805 .subvendor = PCI_ANY_ID, 2806 .subdevice = PCI_ANY_ID, 2807 .setup = pci_fintek_setup, 2808 .init = pci_fintek_init, 2809 }, 2810 { 2811 .vendor = 0x1c29, 2812 .device = 0x1108, 2813 .subvendor = PCI_ANY_ID, 2814 .subdevice = PCI_ANY_ID, 2815 .setup = pci_fintek_setup, 2816 .init = pci_fintek_init, 2817 }, 2818 { 2819 .vendor = 0x1c29, 2820 .device = 0x1112, 2821 .subvendor = PCI_ANY_ID, 2822 .subdevice = PCI_ANY_ID, 2823 .setup = pci_fintek_setup, 2824 .init = pci_fintek_init, 2825 }, 2826 /* 2827 * MOXA 2828 */ 2829 { 2830 .vendor = PCI_VENDOR_ID_MOXA, 2831 .device = PCI_ANY_ID, 2832 .subvendor = PCI_ANY_ID, 2833 .subdevice = PCI_ANY_ID, 2834 .init = pci_moxa_init, 2835 .setup = pci_moxa_setup, 2836 }, 2837 { 2838 .vendor = 0x1c29, 2839 .device = 0x1204, 2840 .subvendor = PCI_ANY_ID, 2841 .subdevice = PCI_ANY_ID, 2842 .setup = pci_fintek_f815xxa_setup, 2843 .init = pci_fintek_f815xxa_init, 2844 }, 2845 { 2846 .vendor = 0x1c29, 2847 .device = 0x1208, 2848 .subvendor = PCI_ANY_ID, 2849 .subdevice = PCI_ANY_ID, 2850 .setup = pci_fintek_f815xxa_setup, 2851 .init = pci_fintek_f815xxa_init, 2852 }, 2853 { 2854 .vendor = 0x1c29, 2855 .device = 0x1212, 2856 .subvendor = PCI_ANY_ID, 2857 .subdevice = PCI_ANY_ID, 2858 .setup = pci_fintek_f815xxa_setup, 2859 .init = pci_fintek_f815xxa_init, 2860 }, 2861 2862 /* 2863 * Default "match everything" terminator entry 2864 */ 2865 { 2866 .vendor = PCI_ANY_ID, 2867 .device = PCI_ANY_ID, 2868 .subvendor = PCI_ANY_ID, 2869 .subdevice = PCI_ANY_ID, 2870 .setup = pci_default_setup, 2871 } 2872 }; 2873 2874 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2875 { 2876 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2877 } 2878 2879 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2880 { 2881 struct pci_serial_quirk *quirk; 2882 2883 for (quirk = pci_serial_quirks; ; quirk++) 2884 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2885 quirk_id_matches(quirk->device, dev->device) && 2886 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2887 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2888 break; 2889 return quirk; 2890 } 2891 2892 /* 2893 * This is the configuration table for all of the PCI serial boards 2894 * which we support. It is directly indexed by the pci_board_num_t enum 2895 * value, which is encoded in the pci_device_id PCI probe table's 2896 * driver_data member. 2897 * 2898 * The makeup of these names are: 2899 * pbn_bn{_bt}_n_baud{_offsetinhex} 2900 * 2901 * bn = PCI BAR number 2902 * bt = Index using PCI BARs 2903 * n = number of serial ports 2904 * baud = baud rate 2905 * offsetinhex = offset for each sequential port (in hex) 2906 * 2907 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2908 * 2909 * Please note: in theory if n = 1, _bt infix should make no difference. 2910 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2911 */ 2912 enum pci_board_num_t { 2913 pbn_default = 0, 2914 2915 pbn_b0_1_115200, 2916 pbn_b0_2_115200, 2917 pbn_b0_4_115200, 2918 pbn_b0_5_115200, 2919 pbn_b0_8_115200, 2920 2921 pbn_b0_1_921600, 2922 pbn_b0_2_921600, 2923 pbn_b0_4_921600, 2924 2925 pbn_b0_2_1130000, 2926 2927 pbn_b0_4_1152000, 2928 2929 pbn_b0_4_1250000, 2930 2931 pbn_b0_2_1843200, 2932 pbn_b0_4_1843200, 2933 2934 pbn_b0_1_15625000, 2935 2936 pbn_b0_bt_1_115200, 2937 pbn_b0_bt_2_115200, 2938 pbn_b0_bt_4_115200, 2939 pbn_b0_bt_8_115200, 2940 2941 pbn_b0_bt_1_460800, 2942 pbn_b0_bt_2_460800, 2943 pbn_b0_bt_4_460800, 2944 2945 pbn_b0_bt_1_921600, 2946 pbn_b0_bt_2_921600, 2947 pbn_b0_bt_4_921600, 2948 pbn_b0_bt_8_921600, 2949 2950 pbn_b1_1_115200, 2951 pbn_b1_2_115200, 2952 pbn_b1_4_115200, 2953 pbn_b1_8_115200, 2954 pbn_b1_16_115200, 2955 2956 pbn_b1_1_921600, 2957 pbn_b1_2_921600, 2958 pbn_b1_4_921600, 2959 pbn_b1_8_921600, 2960 2961 pbn_b1_2_1250000, 2962 2963 pbn_b1_bt_1_115200, 2964 pbn_b1_bt_2_115200, 2965 pbn_b1_bt_4_115200, 2966 2967 pbn_b1_bt_2_921600, 2968 2969 pbn_b1_1_1382400, 2970 pbn_b1_2_1382400, 2971 pbn_b1_4_1382400, 2972 pbn_b1_8_1382400, 2973 2974 pbn_b2_1_115200, 2975 pbn_b2_2_115200, 2976 pbn_b2_4_115200, 2977 pbn_b2_8_115200, 2978 2979 pbn_b2_1_460800, 2980 pbn_b2_4_460800, 2981 pbn_b2_8_460800, 2982 pbn_b2_16_460800, 2983 2984 pbn_b2_1_921600, 2985 pbn_b2_4_921600, 2986 pbn_b2_8_921600, 2987 2988 pbn_b2_8_1152000, 2989 2990 pbn_b2_bt_1_115200, 2991 pbn_b2_bt_2_115200, 2992 pbn_b2_bt_4_115200, 2993 2994 pbn_b2_bt_2_921600, 2995 pbn_b2_bt_4_921600, 2996 2997 pbn_b3_2_115200, 2998 pbn_b3_4_115200, 2999 pbn_b3_8_115200, 3000 3001 pbn_b4_bt_2_921600, 3002 pbn_b4_bt_4_921600, 3003 pbn_b4_bt_8_921600, 3004 3005 /* 3006 * Board-specific versions. 3007 */ 3008 pbn_panacom, 3009 pbn_panacom2, 3010 pbn_panacom4, 3011 pbn_plx_romulus, 3012 pbn_oxsemi, 3013 pbn_oxsemi_1_15625000, 3014 pbn_oxsemi_2_15625000, 3015 pbn_oxsemi_4_15625000, 3016 pbn_oxsemi_8_15625000, 3017 pbn_intel_i960, 3018 pbn_sgi_ioc3, 3019 pbn_computone_4, 3020 pbn_computone_6, 3021 pbn_computone_8, 3022 pbn_sbsxrsio, 3023 pbn_pasemi_1682M, 3024 pbn_ni8430_2, 3025 pbn_ni8430_4, 3026 pbn_ni8430_8, 3027 pbn_ni8430_16, 3028 pbn_ADDIDATA_PCIe_1_3906250, 3029 pbn_ADDIDATA_PCIe_2_3906250, 3030 pbn_ADDIDATA_PCIe_4_3906250, 3031 pbn_ADDIDATA_PCIe_8_3906250, 3032 pbn_ce4100_1_115200, 3033 pbn_omegapci, 3034 pbn_NETMOS9900_2s_115200, 3035 pbn_brcm_trumanage, 3036 pbn_fintek_4, 3037 pbn_fintek_8, 3038 pbn_fintek_12, 3039 pbn_fintek_F81504A, 3040 pbn_fintek_F81508A, 3041 pbn_fintek_F81512A, 3042 pbn_wch382_2, 3043 pbn_wch384_4, 3044 pbn_wch384_8, 3045 pbn_sunix_pci_1s, 3046 pbn_sunix_pci_2s, 3047 pbn_sunix_pci_4s, 3048 pbn_sunix_pci_8s, 3049 pbn_sunix_pci_16s, 3050 pbn_titan_1_4000000, 3051 pbn_titan_2_4000000, 3052 pbn_titan_4_4000000, 3053 pbn_titan_8_4000000, 3054 pbn_moxa_2, 3055 pbn_moxa_4, 3056 pbn_moxa_8, 3057 }; 3058 3059 /* 3060 * uart_offset - the space between channels 3061 * reg_shift - describes how the UART registers are mapped 3062 * to PCI memory by the card. 3063 * For example IER register on SBS, Inc. PMC-OctPro is located at 3064 * offset 0x10 from the UART base, while UART_IER is defined as 1 3065 * in include/linux/serial_reg.h, 3066 * see first lines of serial_in() and serial_out() in 8250.c 3067 */ 3068 3069 static struct pciserial_board pci_boards[] = { 3070 [pbn_default] = { 3071 .flags = FL_BASE0, 3072 .num_ports = 1, 3073 .base_baud = 115200, 3074 .uart_offset = 8, 3075 }, 3076 [pbn_b0_1_115200] = { 3077 .flags = FL_BASE0, 3078 .num_ports = 1, 3079 .base_baud = 115200, 3080 .uart_offset = 8, 3081 }, 3082 [pbn_b0_2_115200] = { 3083 .flags = FL_BASE0, 3084 .num_ports = 2, 3085 .base_baud = 115200, 3086 .uart_offset = 8, 3087 }, 3088 [pbn_b0_4_115200] = { 3089 .flags = FL_BASE0, 3090 .num_ports = 4, 3091 .base_baud = 115200, 3092 .uart_offset = 8, 3093 }, 3094 [pbn_b0_5_115200] = { 3095 .flags = FL_BASE0, 3096 .num_ports = 5, 3097 .base_baud = 115200, 3098 .uart_offset = 8, 3099 }, 3100 [pbn_b0_8_115200] = { 3101 .flags = FL_BASE0, 3102 .num_ports = 8, 3103 .base_baud = 115200, 3104 .uart_offset = 8, 3105 }, 3106 [pbn_b0_1_921600] = { 3107 .flags = FL_BASE0, 3108 .num_ports = 1, 3109 .base_baud = 921600, 3110 .uart_offset = 8, 3111 }, 3112 [pbn_b0_2_921600] = { 3113 .flags = FL_BASE0, 3114 .num_ports = 2, 3115 .base_baud = 921600, 3116 .uart_offset = 8, 3117 }, 3118 [pbn_b0_4_921600] = { 3119 .flags = FL_BASE0, 3120 .num_ports = 4, 3121 .base_baud = 921600, 3122 .uart_offset = 8, 3123 }, 3124 3125 [pbn_b0_2_1130000] = { 3126 .flags = FL_BASE0, 3127 .num_ports = 2, 3128 .base_baud = 1130000, 3129 .uart_offset = 8, 3130 }, 3131 3132 [pbn_b0_4_1152000] = { 3133 .flags = FL_BASE0, 3134 .num_ports = 4, 3135 .base_baud = 1152000, 3136 .uart_offset = 8, 3137 }, 3138 3139 [pbn_b0_4_1250000] = { 3140 .flags = FL_BASE0, 3141 .num_ports = 4, 3142 .base_baud = 1250000, 3143 .uart_offset = 8, 3144 }, 3145 3146 [pbn_b0_2_1843200] = { 3147 .flags = FL_BASE0, 3148 .num_ports = 2, 3149 .base_baud = 1843200, 3150 .uart_offset = 8, 3151 }, 3152 [pbn_b0_4_1843200] = { 3153 .flags = FL_BASE0, 3154 .num_ports = 4, 3155 .base_baud = 1843200, 3156 .uart_offset = 8, 3157 }, 3158 3159 [pbn_b0_1_15625000] = { 3160 .flags = FL_BASE0, 3161 .num_ports = 1, 3162 .base_baud = 15625000, 3163 .uart_offset = 8, 3164 }, 3165 3166 [pbn_b0_bt_1_115200] = { 3167 .flags = FL_BASE0|FL_BASE_BARS, 3168 .num_ports = 1, 3169 .base_baud = 115200, 3170 .uart_offset = 8, 3171 }, 3172 [pbn_b0_bt_2_115200] = { 3173 .flags = FL_BASE0|FL_BASE_BARS, 3174 .num_ports = 2, 3175 .base_baud = 115200, 3176 .uart_offset = 8, 3177 }, 3178 [pbn_b0_bt_4_115200] = { 3179 .flags = FL_BASE0|FL_BASE_BARS, 3180 .num_ports = 4, 3181 .base_baud = 115200, 3182 .uart_offset = 8, 3183 }, 3184 [pbn_b0_bt_8_115200] = { 3185 .flags = FL_BASE0|FL_BASE_BARS, 3186 .num_ports = 8, 3187 .base_baud = 115200, 3188 .uart_offset = 8, 3189 }, 3190 3191 [pbn_b0_bt_1_460800] = { 3192 .flags = FL_BASE0|FL_BASE_BARS, 3193 .num_ports = 1, 3194 .base_baud = 460800, 3195 .uart_offset = 8, 3196 }, 3197 [pbn_b0_bt_2_460800] = { 3198 .flags = FL_BASE0|FL_BASE_BARS, 3199 .num_ports = 2, 3200 .base_baud = 460800, 3201 .uart_offset = 8, 3202 }, 3203 [pbn_b0_bt_4_460800] = { 3204 .flags = FL_BASE0|FL_BASE_BARS, 3205 .num_ports = 4, 3206 .base_baud = 460800, 3207 .uart_offset = 8, 3208 }, 3209 3210 [pbn_b0_bt_1_921600] = { 3211 .flags = FL_BASE0|FL_BASE_BARS, 3212 .num_ports = 1, 3213 .base_baud = 921600, 3214 .uart_offset = 8, 3215 }, 3216 [pbn_b0_bt_2_921600] = { 3217 .flags = FL_BASE0|FL_BASE_BARS, 3218 .num_ports = 2, 3219 .base_baud = 921600, 3220 .uart_offset = 8, 3221 }, 3222 [pbn_b0_bt_4_921600] = { 3223 .flags = FL_BASE0|FL_BASE_BARS, 3224 .num_ports = 4, 3225 .base_baud = 921600, 3226 .uart_offset = 8, 3227 }, 3228 [pbn_b0_bt_8_921600] = { 3229 .flags = FL_BASE0|FL_BASE_BARS, 3230 .num_ports = 8, 3231 .base_baud = 921600, 3232 .uart_offset = 8, 3233 }, 3234 3235 [pbn_b1_1_115200] = { 3236 .flags = FL_BASE1, 3237 .num_ports = 1, 3238 .base_baud = 115200, 3239 .uart_offset = 8, 3240 }, 3241 [pbn_b1_2_115200] = { 3242 .flags = FL_BASE1, 3243 .num_ports = 2, 3244 .base_baud = 115200, 3245 .uart_offset = 8, 3246 }, 3247 [pbn_b1_4_115200] = { 3248 .flags = FL_BASE1, 3249 .num_ports = 4, 3250 .base_baud = 115200, 3251 .uart_offset = 8, 3252 }, 3253 [pbn_b1_8_115200] = { 3254 .flags = FL_BASE1, 3255 .num_ports = 8, 3256 .base_baud = 115200, 3257 .uart_offset = 8, 3258 }, 3259 [pbn_b1_16_115200] = { 3260 .flags = FL_BASE1, 3261 .num_ports = 16, 3262 .base_baud = 115200, 3263 .uart_offset = 8, 3264 }, 3265 3266 [pbn_b1_1_921600] = { 3267 .flags = FL_BASE1, 3268 .num_ports = 1, 3269 .base_baud = 921600, 3270 .uart_offset = 8, 3271 }, 3272 [pbn_b1_2_921600] = { 3273 .flags = FL_BASE1, 3274 .num_ports = 2, 3275 .base_baud = 921600, 3276 .uart_offset = 8, 3277 }, 3278 [pbn_b1_4_921600] = { 3279 .flags = FL_BASE1, 3280 .num_ports = 4, 3281 .base_baud = 921600, 3282 .uart_offset = 8, 3283 }, 3284 [pbn_b1_8_921600] = { 3285 .flags = FL_BASE1, 3286 .num_ports = 8, 3287 .base_baud = 921600, 3288 .uart_offset = 8, 3289 }, 3290 [pbn_b1_2_1250000] = { 3291 .flags = FL_BASE1, 3292 .num_ports = 2, 3293 .base_baud = 1250000, 3294 .uart_offset = 8, 3295 }, 3296 3297 [pbn_b1_bt_1_115200] = { 3298 .flags = FL_BASE1|FL_BASE_BARS, 3299 .num_ports = 1, 3300 .base_baud = 115200, 3301 .uart_offset = 8, 3302 }, 3303 [pbn_b1_bt_2_115200] = { 3304 .flags = FL_BASE1|FL_BASE_BARS, 3305 .num_ports = 2, 3306 .base_baud = 115200, 3307 .uart_offset = 8, 3308 }, 3309 [pbn_b1_bt_4_115200] = { 3310 .flags = FL_BASE1|FL_BASE_BARS, 3311 .num_ports = 4, 3312 .base_baud = 115200, 3313 .uart_offset = 8, 3314 }, 3315 3316 [pbn_b1_bt_2_921600] = { 3317 .flags = FL_BASE1|FL_BASE_BARS, 3318 .num_ports = 2, 3319 .base_baud = 921600, 3320 .uart_offset = 8, 3321 }, 3322 3323 [pbn_b1_1_1382400] = { 3324 .flags = FL_BASE1, 3325 .num_ports = 1, 3326 .base_baud = 1382400, 3327 .uart_offset = 8, 3328 }, 3329 [pbn_b1_2_1382400] = { 3330 .flags = FL_BASE1, 3331 .num_ports = 2, 3332 .base_baud = 1382400, 3333 .uart_offset = 8, 3334 }, 3335 [pbn_b1_4_1382400] = { 3336 .flags = FL_BASE1, 3337 .num_ports = 4, 3338 .base_baud = 1382400, 3339 .uart_offset = 8, 3340 }, 3341 [pbn_b1_8_1382400] = { 3342 .flags = FL_BASE1, 3343 .num_ports = 8, 3344 .base_baud = 1382400, 3345 .uart_offset = 8, 3346 }, 3347 3348 [pbn_b2_1_115200] = { 3349 .flags = FL_BASE2, 3350 .num_ports = 1, 3351 .base_baud = 115200, 3352 .uart_offset = 8, 3353 }, 3354 [pbn_b2_2_115200] = { 3355 .flags = FL_BASE2, 3356 .num_ports = 2, 3357 .base_baud = 115200, 3358 .uart_offset = 8, 3359 }, 3360 [pbn_b2_4_115200] = { 3361 .flags = FL_BASE2, 3362 .num_ports = 4, 3363 .base_baud = 115200, 3364 .uart_offset = 8, 3365 }, 3366 [pbn_b2_8_115200] = { 3367 .flags = FL_BASE2, 3368 .num_ports = 8, 3369 .base_baud = 115200, 3370 .uart_offset = 8, 3371 }, 3372 3373 [pbn_b2_1_460800] = { 3374 .flags = FL_BASE2, 3375 .num_ports = 1, 3376 .base_baud = 460800, 3377 .uart_offset = 8, 3378 }, 3379 [pbn_b2_4_460800] = { 3380 .flags = FL_BASE2, 3381 .num_ports = 4, 3382 .base_baud = 460800, 3383 .uart_offset = 8, 3384 }, 3385 [pbn_b2_8_460800] = { 3386 .flags = FL_BASE2, 3387 .num_ports = 8, 3388 .base_baud = 460800, 3389 .uart_offset = 8, 3390 }, 3391 [pbn_b2_16_460800] = { 3392 .flags = FL_BASE2, 3393 .num_ports = 16, 3394 .base_baud = 460800, 3395 .uart_offset = 8, 3396 }, 3397 3398 [pbn_b2_1_921600] = { 3399 .flags = FL_BASE2, 3400 .num_ports = 1, 3401 .base_baud = 921600, 3402 .uart_offset = 8, 3403 }, 3404 [pbn_b2_4_921600] = { 3405 .flags = FL_BASE2, 3406 .num_ports = 4, 3407 .base_baud = 921600, 3408 .uart_offset = 8, 3409 }, 3410 [pbn_b2_8_921600] = { 3411 .flags = FL_BASE2, 3412 .num_ports = 8, 3413 .base_baud = 921600, 3414 .uart_offset = 8, 3415 }, 3416 3417 [pbn_b2_8_1152000] = { 3418 .flags = FL_BASE2, 3419 .num_ports = 8, 3420 .base_baud = 1152000, 3421 .uart_offset = 8, 3422 }, 3423 3424 [pbn_b2_bt_1_115200] = { 3425 .flags = FL_BASE2|FL_BASE_BARS, 3426 .num_ports = 1, 3427 .base_baud = 115200, 3428 .uart_offset = 8, 3429 }, 3430 [pbn_b2_bt_2_115200] = { 3431 .flags = FL_BASE2|FL_BASE_BARS, 3432 .num_ports = 2, 3433 .base_baud = 115200, 3434 .uart_offset = 8, 3435 }, 3436 [pbn_b2_bt_4_115200] = { 3437 .flags = FL_BASE2|FL_BASE_BARS, 3438 .num_ports = 4, 3439 .base_baud = 115200, 3440 .uart_offset = 8, 3441 }, 3442 3443 [pbn_b2_bt_2_921600] = { 3444 .flags = FL_BASE2|FL_BASE_BARS, 3445 .num_ports = 2, 3446 .base_baud = 921600, 3447 .uart_offset = 8, 3448 }, 3449 [pbn_b2_bt_4_921600] = { 3450 .flags = FL_BASE2|FL_BASE_BARS, 3451 .num_ports = 4, 3452 .base_baud = 921600, 3453 .uart_offset = 8, 3454 }, 3455 3456 [pbn_b3_2_115200] = { 3457 .flags = FL_BASE3, 3458 .num_ports = 2, 3459 .base_baud = 115200, 3460 .uart_offset = 8, 3461 }, 3462 [pbn_b3_4_115200] = { 3463 .flags = FL_BASE3, 3464 .num_ports = 4, 3465 .base_baud = 115200, 3466 .uart_offset = 8, 3467 }, 3468 [pbn_b3_8_115200] = { 3469 .flags = FL_BASE3, 3470 .num_ports = 8, 3471 .base_baud = 115200, 3472 .uart_offset = 8, 3473 }, 3474 3475 [pbn_b4_bt_2_921600] = { 3476 .flags = FL_BASE4, 3477 .num_ports = 2, 3478 .base_baud = 921600, 3479 .uart_offset = 8, 3480 }, 3481 [pbn_b4_bt_4_921600] = { 3482 .flags = FL_BASE4, 3483 .num_ports = 4, 3484 .base_baud = 921600, 3485 .uart_offset = 8, 3486 }, 3487 [pbn_b4_bt_8_921600] = { 3488 .flags = FL_BASE4, 3489 .num_ports = 8, 3490 .base_baud = 921600, 3491 .uart_offset = 8, 3492 }, 3493 3494 /* 3495 * Entries following this are board-specific. 3496 */ 3497 3498 /* 3499 * Panacom - IOMEM 3500 */ 3501 [pbn_panacom] = { 3502 .flags = FL_BASE2, 3503 .num_ports = 2, 3504 .base_baud = 921600, 3505 .uart_offset = 0x400, 3506 .reg_shift = 7, 3507 }, 3508 [pbn_panacom2] = { 3509 .flags = FL_BASE2|FL_BASE_BARS, 3510 .num_ports = 2, 3511 .base_baud = 921600, 3512 .uart_offset = 0x400, 3513 .reg_shift = 7, 3514 }, 3515 [pbn_panacom4] = { 3516 .flags = FL_BASE2|FL_BASE_BARS, 3517 .num_ports = 4, 3518 .base_baud = 921600, 3519 .uart_offset = 0x400, 3520 .reg_shift = 7, 3521 }, 3522 3523 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3524 [pbn_plx_romulus] = { 3525 .flags = FL_BASE2, 3526 .num_ports = 4, 3527 .base_baud = 921600, 3528 .uart_offset = 8 << 2, 3529 .reg_shift = 2, 3530 .first_offset = 0x03, 3531 }, 3532 3533 /* 3534 * This board uses the size of PCI Base region 0 to 3535 * signal now many ports are available 3536 */ 3537 [pbn_oxsemi] = { 3538 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3539 .num_ports = 32, 3540 .base_baud = 115200, 3541 .uart_offset = 8, 3542 }, 3543 [pbn_oxsemi_1_15625000] = { 3544 .flags = FL_BASE0, 3545 .num_ports = 1, 3546 .base_baud = 15625000, 3547 .uart_offset = 0x200, 3548 .first_offset = 0x1000, 3549 }, 3550 [pbn_oxsemi_2_15625000] = { 3551 .flags = FL_BASE0, 3552 .num_ports = 2, 3553 .base_baud = 15625000, 3554 .uart_offset = 0x200, 3555 .first_offset = 0x1000, 3556 }, 3557 [pbn_oxsemi_4_15625000] = { 3558 .flags = FL_BASE0, 3559 .num_ports = 4, 3560 .base_baud = 15625000, 3561 .uart_offset = 0x200, 3562 .first_offset = 0x1000, 3563 }, 3564 [pbn_oxsemi_8_15625000] = { 3565 .flags = FL_BASE0, 3566 .num_ports = 8, 3567 .base_baud = 15625000, 3568 .uart_offset = 0x200, 3569 .first_offset = 0x1000, 3570 }, 3571 3572 3573 /* 3574 * EKF addition for i960 Boards form EKF with serial port. 3575 * Max 256 ports. 3576 */ 3577 [pbn_intel_i960] = { 3578 .flags = FL_BASE0, 3579 .num_ports = 32, 3580 .base_baud = 921600, 3581 .uart_offset = 8 << 2, 3582 .reg_shift = 2, 3583 .first_offset = 0x10000, 3584 }, 3585 [pbn_sgi_ioc3] = { 3586 .flags = FL_BASE0|FL_NOIRQ, 3587 .num_ports = 1, 3588 .base_baud = 458333, 3589 .uart_offset = 8, 3590 .reg_shift = 0, 3591 .first_offset = 0x20178, 3592 }, 3593 3594 /* 3595 * Computone - uses IOMEM. 3596 */ 3597 [pbn_computone_4] = { 3598 .flags = FL_BASE0, 3599 .num_ports = 4, 3600 .base_baud = 921600, 3601 .uart_offset = 0x40, 3602 .reg_shift = 2, 3603 .first_offset = 0x200, 3604 }, 3605 [pbn_computone_6] = { 3606 .flags = FL_BASE0, 3607 .num_ports = 6, 3608 .base_baud = 921600, 3609 .uart_offset = 0x40, 3610 .reg_shift = 2, 3611 .first_offset = 0x200, 3612 }, 3613 [pbn_computone_8] = { 3614 .flags = FL_BASE0, 3615 .num_ports = 8, 3616 .base_baud = 921600, 3617 .uart_offset = 0x40, 3618 .reg_shift = 2, 3619 .first_offset = 0x200, 3620 }, 3621 [pbn_sbsxrsio] = { 3622 .flags = FL_BASE0, 3623 .num_ports = 8, 3624 .base_baud = 460800, 3625 .uart_offset = 256, 3626 .reg_shift = 4, 3627 }, 3628 /* 3629 * PA Semi PWRficient PA6T-1682M on-chip UART 3630 */ 3631 [pbn_pasemi_1682M] = { 3632 .flags = FL_BASE0, 3633 .num_ports = 1, 3634 .base_baud = 8333333, 3635 }, 3636 /* 3637 * National Instruments 843x 3638 */ 3639 [pbn_ni8430_16] = { 3640 .flags = FL_BASE0, 3641 .num_ports = 16, 3642 .base_baud = 3686400, 3643 .uart_offset = 0x10, 3644 .first_offset = 0x800, 3645 }, 3646 [pbn_ni8430_8] = { 3647 .flags = FL_BASE0, 3648 .num_ports = 8, 3649 .base_baud = 3686400, 3650 .uart_offset = 0x10, 3651 .first_offset = 0x800, 3652 }, 3653 [pbn_ni8430_4] = { 3654 .flags = FL_BASE0, 3655 .num_ports = 4, 3656 .base_baud = 3686400, 3657 .uart_offset = 0x10, 3658 .first_offset = 0x800, 3659 }, 3660 [pbn_ni8430_2] = { 3661 .flags = FL_BASE0, 3662 .num_ports = 2, 3663 .base_baud = 3686400, 3664 .uart_offset = 0x10, 3665 .first_offset = 0x800, 3666 }, 3667 /* 3668 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3669 */ 3670 [pbn_ADDIDATA_PCIe_1_3906250] = { 3671 .flags = FL_BASE0, 3672 .num_ports = 1, 3673 .base_baud = 3906250, 3674 .uart_offset = 0x200, 3675 .first_offset = 0x1000, 3676 }, 3677 [pbn_ADDIDATA_PCIe_2_3906250] = { 3678 .flags = FL_BASE0, 3679 .num_ports = 2, 3680 .base_baud = 3906250, 3681 .uart_offset = 0x200, 3682 .first_offset = 0x1000, 3683 }, 3684 [pbn_ADDIDATA_PCIe_4_3906250] = { 3685 .flags = FL_BASE0, 3686 .num_ports = 4, 3687 .base_baud = 3906250, 3688 .uart_offset = 0x200, 3689 .first_offset = 0x1000, 3690 }, 3691 [pbn_ADDIDATA_PCIe_8_3906250] = { 3692 .flags = FL_BASE0, 3693 .num_ports = 8, 3694 .base_baud = 3906250, 3695 .uart_offset = 0x200, 3696 .first_offset = 0x1000, 3697 }, 3698 [pbn_ce4100_1_115200] = { 3699 .flags = FL_BASE_BARS, 3700 .num_ports = 2, 3701 .base_baud = 921600, 3702 .reg_shift = 2, 3703 }, 3704 [pbn_omegapci] = { 3705 .flags = FL_BASE0, 3706 .num_ports = 8, 3707 .base_baud = 115200, 3708 .uart_offset = 0x200, 3709 }, 3710 [pbn_NETMOS9900_2s_115200] = { 3711 .flags = FL_BASE0, 3712 .num_ports = 2, 3713 .base_baud = 115200, 3714 }, 3715 [pbn_brcm_trumanage] = { 3716 .flags = FL_BASE0, 3717 .num_ports = 1, 3718 .reg_shift = 2, 3719 .base_baud = 115200, 3720 }, 3721 [pbn_fintek_4] = { 3722 .num_ports = 4, 3723 .uart_offset = 8, 3724 .base_baud = 115200, 3725 .first_offset = 0x40, 3726 }, 3727 [pbn_fintek_8] = { 3728 .num_ports = 8, 3729 .uart_offset = 8, 3730 .base_baud = 115200, 3731 .first_offset = 0x40, 3732 }, 3733 [pbn_fintek_12] = { 3734 .num_ports = 12, 3735 .uart_offset = 8, 3736 .base_baud = 115200, 3737 .first_offset = 0x40, 3738 }, 3739 [pbn_fintek_F81504A] = { 3740 .num_ports = 4, 3741 .uart_offset = 8, 3742 .base_baud = 115200, 3743 }, 3744 [pbn_fintek_F81508A] = { 3745 .num_ports = 8, 3746 .uart_offset = 8, 3747 .base_baud = 115200, 3748 }, 3749 [pbn_fintek_F81512A] = { 3750 .num_ports = 12, 3751 .uart_offset = 8, 3752 .base_baud = 115200, 3753 }, 3754 [pbn_wch382_2] = { 3755 .flags = FL_BASE0, 3756 .num_ports = 2, 3757 .base_baud = 115200, 3758 .uart_offset = 8, 3759 .first_offset = 0xC0, 3760 }, 3761 [pbn_wch384_4] = { 3762 .flags = FL_BASE0, 3763 .num_ports = 4, 3764 .base_baud = 115200, 3765 .uart_offset = 8, 3766 .first_offset = 0xC0, 3767 }, 3768 [pbn_wch384_8] = { 3769 .flags = FL_BASE0, 3770 .num_ports = 8, 3771 .base_baud = 115200, 3772 .uart_offset = 8, 3773 .first_offset = 0x00, 3774 }, 3775 [pbn_sunix_pci_1s] = { 3776 .num_ports = 1, 3777 .base_baud = 921600, 3778 .uart_offset = 0x8, 3779 }, 3780 [pbn_sunix_pci_2s] = { 3781 .num_ports = 2, 3782 .base_baud = 921600, 3783 .uart_offset = 0x8, 3784 }, 3785 [pbn_sunix_pci_4s] = { 3786 .num_ports = 4, 3787 .base_baud = 921600, 3788 .uart_offset = 0x8, 3789 }, 3790 [pbn_sunix_pci_8s] = { 3791 .num_ports = 8, 3792 .base_baud = 921600, 3793 .uart_offset = 0x8, 3794 }, 3795 [pbn_sunix_pci_16s] = { 3796 .num_ports = 16, 3797 .base_baud = 921600, 3798 .uart_offset = 0x8, 3799 }, 3800 [pbn_titan_1_4000000] = { 3801 .flags = FL_BASE0, 3802 .num_ports = 1, 3803 .base_baud = 4000000, 3804 .uart_offset = 0x200, 3805 .first_offset = 0x1000, 3806 }, 3807 [pbn_titan_2_4000000] = { 3808 .flags = FL_BASE0, 3809 .num_ports = 2, 3810 .base_baud = 4000000, 3811 .uart_offset = 0x200, 3812 .first_offset = 0x1000, 3813 }, 3814 [pbn_titan_4_4000000] = { 3815 .flags = FL_BASE0, 3816 .num_ports = 4, 3817 .base_baud = 4000000, 3818 .uart_offset = 0x200, 3819 .first_offset = 0x1000, 3820 }, 3821 [pbn_titan_8_4000000] = { 3822 .flags = FL_BASE0, 3823 .num_ports = 8, 3824 .base_baud = 4000000, 3825 .uart_offset = 0x200, 3826 .first_offset = 0x1000, 3827 }, 3828 [pbn_moxa_2] = { 3829 .flags = FL_BASE1, 3830 .num_ports = 2, 3831 .base_baud = 921600, 3832 .uart_offset = 0x200, 3833 }, 3834 [pbn_moxa_4] = { 3835 .flags = FL_BASE1, 3836 .num_ports = 4, 3837 .base_baud = 921600, 3838 .uart_offset = 0x200, 3839 }, 3840 [pbn_moxa_8] = { 3841 .flags = FL_BASE1, 3842 .num_ports = 8, 3843 .base_baud = 921600, 3844 .uart_offset = 0x200, 3845 }, 3846 }; 3847 3848 #define REPORT_CONFIG(option) \ 3849 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3850 #define REPORT_8250_CONFIG(option) \ 3851 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3852 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3853 3854 static const struct pci_device_id blacklist[] = { 3855 /* softmodems */ 3856 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3857 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3858 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3859 3860 /* multi-io cards handled by parport_serial */ 3861 /* WCH CH353 2S1P */ 3862 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3863 /* WCH CH353 1S1P */ 3864 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3865 /* WCH CH382 2S1P */ 3866 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3867 3868 /* Intel platforms with MID UART */ 3869 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3870 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3871 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3872 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3873 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3874 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3875 3876 /* Intel platforms with DesignWare UART */ 3877 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3878 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3879 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3880 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3881 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3882 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3883 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3884 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3885 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3886 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3887 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3888 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3889 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3890 3891 /* Exar devices */ 3892 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3893 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3894 3895 /* Pericom devices */ 3896 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3897 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3898 3899 /* End of the black list */ 3900 { } 3901 }; 3902 3903 static int serial_pci_is_class_communication(struct pci_dev *dev) 3904 { 3905 /* 3906 * If it is not a communications device or the programming 3907 * interface is greater than 6, give up. 3908 */ 3909 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3910 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3911 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3912 (dev->class & 0xff) > 6) 3913 return -ENODEV; 3914 3915 return 0; 3916 } 3917 3918 /* 3919 * Given a complete unknown PCI device, try to use some heuristics to 3920 * guess what the configuration might be, based on the pitiful PCI 3921 * serial specs. Returns 0 on success, -ENODEV on failure. 3922 */ 3923 static int 3924 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3925 { 3926 int num_iomem, num_port, first_port = -1, i; 3927 int rc; 3928 3929 rc = serial_pci_is_class_communication(dev); 3930 if (rc) 3931 return rc; 3932 3933 /* 3934 * Should we try to make guesses for multiport serial devices later? 3935 */ 3936 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3937 return -ENODEV; 3938 3939 num_iomem = num_port = 0; 3940 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3941 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3942 num_port++; 3943 if (first_port == -1) 3944 first_port = i; 3945 } 3946 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3947 num_iomem++; 3948 } 3949 3950 /* 3951 * If there is 1 or 0 iomem regions, and exactly one port, 3952 * use it. We guess the number of ports based on the IO 3953 * region size. 3954 */ 3955 if (num_iomem <= 1 && num_port == 1) { 3956 board->flags = first_port; 3957 board->num_ports = pci_resource_len(dev, first_port) / 8; 3958 return 0; 3959 } 3960 3961 /* 3962 * Now guess if we've got a board which indexes by BARs. 3963 * Each IO BAR should be 8 bytes, and they should follow 3964 * consecutively. 3965 */ 3966 first_port = -1; 3967 num_port = 0; 3968 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3969 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3970 pci_resource_len(dev, i) == 8 && 3971 (first_port == -1 || (first_port + num_port) == i)) { 3972 num_port++; 3973 if (first_port == -1) 3974 first_port = i; 3975 } 3976 } 3977 3978 if (num_port > 1) { 3979 board->flags = first_port | FL_BASE_BARS; 3980 board->num_ports = num_port; 3981 return 0; 3982 } 3983 3984 return -ENODEV; 3985 } 3986 3987 static inline int 3988 serial_pci_matches(const struct pciserial_board *board, 3989 const struct pciserial_board *guessed) 3990 { 3991 return 3992 board->num_ports == guessed->num_ports && 3993 board->base_baud == guessed->base_baud && 3994 board->uart_offset == guessed->uart_offset && 3995 board->reg_shift == guessed->reg_shift && 3996 board->first_offset == guessed->first_offset; 3997 } 3998 3999 struct serial_private * 4000 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 4001 { 4002 struct uart_8250_port uart; 4003 struct serial_private *priv; 4004 struct pci_serial_quirk *quirk; 4005 int rc, nr_ports, i; 4006 4007 nr_ports = board->num_ports; 4008 4009 /* 4010 * Find an init and setup quirks. 4011 */ 4012 quirk = find_quirk(dev); 4013 4014 /* 4015 * Run the new-style initialization function. 4016 * The initialization function returns: 4017 * <0 - error 4018 * 0 - use board->num_ports 4019 * >0 - number of ports 4020 */ 4021 if (quirk->init) { 4022 rc = quirk->init(dev); 4023 if (rc < 0) { 4024 priv = ERR_PTR(rc); 4025 goto err_out; 4026 } 4027 if (rc) 4028 nr_ports = rc; 4029 } 4030 4031 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 4032 if (!priv) { 4033 priv = ERR_PTR(-ENOMEM); 4034 goto err_deinit; 4035 } 4036 4037 priv->dev = dev; 4038 priv->quirk = quirk; 4039 4040 memset(&uart, 0, sizeof(uart)); 4041 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 4042 uart.port.uartclk = board->base_baud * 16; 4043 4044 if (board->flags & FL_NOIRQ) { 4045 uart.port.irq = 0; 4046 } else { 4047 if (pci_match_id(pci_use_msi, dev)) { 4048 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 4049 pci_set_master(dev); 4050 uart.port.flags &= ~UPF_SHARE_IRQ; 4051 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 4052 } else { 4053 pci_dbg(dev, "Using legacy interrupts\n"); 4054 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 4055 } 4056 if (rc < 0) { 4057 kfree(priv); 4058 priv = ERR_PTR(rc); 4059 goto err_deinit; 4060 } 4061 4062 uart.port.irq = pci_irq_vector(dev, 0); 4063 } 4064 4065 uart.port.dev = &dev->dev; 4066 4067 for (i = 0; i < nr_ports; i++) { 4068 if (quirk->setup(priv, board, &uart, i)) 4069 break; 4070 4071 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 4072 uart.port.iobase, uart.port.irq, uart.port.iotype); 4073 4074 priv->line[i] = serial8250_register_8250_port(&uart); 4075 if (priv->line[i] < 0) { 4076 pci_err(dev, 4077 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4078 uart.port.iobase, uart.port.irq, 4079 uart.port.iotype, priv->line[i]); 4080 break; 4081 } 4082 } 4083 priv->nr = i; 4084 priv->board = board; 4085 return priv; 4086 4087 err_deinit: 4088 if (quirk->exit) 4089 quirk->exit(dev); 4090 err_out: 4091 return priv; 4092 } 4093 EXPORT_SYMBOL_GPL(pciserial_init_ports); 4094 4095 static void pciserial_detach_ports(struct serial_private *priv) 4096 { 4097 struct pci_serial_quirk *quirk; 4098 int i; 4099 4100 for (i = 0; i < priv->nr; i++) 4101 serial8250_unregister_port(priv->line[i]); 4102 4103 /* 4104 * Find the exit quirks. 4105 */ 4106 quirk = find_quirk(priv->dev); 4107 if (quirk->exit) 4108 quirk->exit(priv->dev); 4109 } 4110 4111 void pciserial_remove_ports(struct serial_private *priv) 4112 { 4113 pciserial_detach_ports(priv); 4114 kfree(priv); 4115 } 4116 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4117 4118 void pciserial_suspend_ports(struct serial_private *priv) 4119 { 4120 int i; 4121 4122 for (i = 0; i < priv->nr; i++) 4123 if (priv->line[i] >= 0) 4124 serial8250_suspend_port(priv->line[i]); 4125 4126 /* 4127 * Ensure that every init quirk is properly torn down 4128 */ 4129 if (priv->quirk->exit) 4130 priv->quirk->exit(priv->dev); 4131 } 4132 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4133 4134 void pciserial_resume_ports(struct serial_private *priv) 4135 { 4136 int i; 4137 4138 /* 4139 * Ensure that the board is correctly configured. 4140 */ 4141 if (priv->quirk->init) 4142 priv->quirk->init(priv->dev); 4143 4144 for (i = 0; i < priv->nr; i++) 4145 if (priv->line[i] >= 0) 4146 serial8250_resume_port(priv->line[i]); 4147 } 4148 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4149 4150 /* 4151 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4152 * to the arrangement of serial ports on a PCI card. 4153 */ 4154 static int 4155 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4156 { 4157 struct pci_serial_quirk *quirk; 4158 struct serial_private *priv; 4159 const struct pciserial_board *board; 4160 const struct pci_device_id *exclude; 4161 struct pciserial_board tmp; 4162 int rc; 4163 4164 quirk = find_quirk(dev); 4165 if (quirk->probe) { 4166 rc = quirk->probe(dev); 4167 if (rc) 4168 return rc; 4169 } 4170 4171 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4172 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4173 return -EINVAL; 4174 } 4175 4176 board = &pci_boards[ent->driver_data]; 4177 4178 exclude = pci_match_id(blacklist, dev); 4179 if (exclude) { 4180 if (exclude->driver_data) 4181 pci_warn(dev, "ignoring port, enable %s to handle\n", 4182 (const char *)exclude->driver_data); 4183 return -ENODEV; 4184 } 4185 4186 rc = pcim_enable_device(dev); 4187 pci_save_state(dev); 4188 if (rc) 4189 return rc; 4190 4191 if (ent->driver_data == pbn_default) { 4192 /* 4193 * Use a copy of the pci_board entry for this; 4194 * avoid changing entries in the table. 4195 */ 4196 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4197 board = &tmp; 4198 4199 /* 4200 * We matched one of our class entries. Try to 4201 * determine the parameters of this board. 4202 */ 4203 rc = serial_pci_guess_board(dev, &tmp); 4204 if (rc) 4205 return rc; 4206 } else { 4207 /* 4208 * We matched an explicit entry. If we are able to 4209 * detect this boards settings with our heuristic, 4210 * then we no longer need this entry. 4211 */ 4212 memcpy(&tmp, &pci_boards[pbn_default], 4213 sizeof(struct pciserial_board)); 4214 rc = serial_pci_guess_board(dev, &tmp); 4215 if (rc == 0 && serial_pci_matches(board, &tmp)) 4216 moan_device("Redundant entry in serial pci_table.", 4217 dev); 4218 } 4219 4220 priv = pciserial_init_ports(dev, board); 4221 if (IS_ERR(priv)) 4222 return PTR_ERR(priv); 4223 4224 pci_set_drvdata(dev, priv); 4225 return 0; 4226 } 4227 4228 static void pciserial_remove_one(struct pci_dev *dev) 4229 { 4230 struct serial_private *priv = pci_get_drvdata(dev); 4231 4232 pciserial_remove_ports(priv); 4233 } 4234 4235 #ifdef CONFIG_PM_SLEEP 4236 static int pciserial_suspend_one(struct device *dev) 4237 { 4238 struct serial_private *priv = dev_get_drvdata(dev); 4239 4240 if (priv) 4241 pciserial_suspend_ports(priv); 4242 4243 return 0; 4244 } 4245 4246 static int pciserial_resume_one(struct device *dev) 4247 { 4248 struct pci_dev *pdev = to_pci_dev(dev); 4249 struct serial_private *priv = pci_get_drvdata(pdev); 4250 int err; 4251 4252 if (priv) { 4253 /* 4254 * The device may have been disabled. Re-enable it. 4255 */ 4256 err = pci_enable_device(pdev); 4257 /* FIXME: We cannot simply error out here */ 4258 if (err) 4259 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4260 pciserial_resume_ports(priv); 4261 } 4262 return 0; 4263 } 4264 #endif 4265 4266 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4267 pciserial_resume_one); 4268 4269 static const struct pci_device_id serial_pci_tbl[] = { 4270 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4271 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, 4272 pbn_b0_4_921600 }, 4273 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4274 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4275 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4276 pbn_b2_8_921600 }, 4277 /* Advantech also use 0x3618 and 0xf618 */ 4278 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4279 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4280 pbn_b0_4_921600 }, 4281 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4282 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4283 pbn_b0_4_921600 }, 4284 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4285 PCI_SUBVENDOR_ID_CONNECT_TECH, 4286 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4287 pbn_b1_8_1382400 }, 4288 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4289 PCI_SUBVENDOR_ID_CONNECT_TECH, 4290 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4291 pbn_b1_4_1382400 }, 4292 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4293 PCI_SUBVENDOR_ID_CONNECT_TECH, 4294 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4295 pbn_b1_2_1382400 }, 4296 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4297 PCI_SUBVENDOR_ID_CONNECT_TECH, 4298 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4299 pbn_b1_8_1382400 }, 4300 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4301 PCI_SUBVENDOR_ID_CONNECT_TECH, 4302 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4303 pbn_b1_4_1382400 }, 4304 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4305 PCI_SUBVENDOR_ID_CONNECT_TECH, 4306 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4307 pbn_b1_2_1382400 }, 4308 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4309 PCI_SUBVENDOR_ID_CONNECT_TECH, 4310 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4311 pbn_b1_8_921600 }, 4312 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4313 PCI_SUBVENDOR_ID_CONNECT_TECH, 4314 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4315 pbn_b1_8_921600 }, 4316 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4317 PCI_SUBVENDOR_ID_CONNECT_TECH, 4318 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4319 pbn_b1_4_921600 }, 4320 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4321 PCI_SUBVENDOR_ID_CONNECT_TECH, 4322 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4323 pbn_b1_4_921600 }, 4324 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4325 PCI_SUBVENDOR_ID_CONNECT_TECH, 4326 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4327 pbn_b1_2_921600 }, 4328 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4329 PCI_SUBVENDOR_ID_CONNECT_TECH, 4330 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4331 pbn_b1_8_921600 }, 4332 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4333 PCI_SUBVENDOR_ID_CONNECT_TECH, 4334 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4335 pbn_b1_8_921600 }, 4336 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4337 PCI_SUBVENDOR_ID_CONNECT_TECH, 4338 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4339 pbn_b1_4_921600 }, 4340 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4341 PCI_SUBVENDOR_ID_CONNECT_TECH, 4342 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4343 pbn_b1_2_1250000 }, 4344 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4345 PCI_SUBVENDOR_ID_CONNECT_TECH, 4346 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4347 pbn_b0_2_1843200 }, 4348 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4349 PCI_SUBVENDOR_ID_CONNECT_TECH, 4350 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4351 pbn_b0_4_1843200 }, 4352 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4353 PCI_VENDOR_ID_AFAVLAB, 4354 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4355 pbn_b0_4_1152000 }, 4356 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4358 pbn_b2_bt_1_115200 }, 4359 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4361 pbn_b2_bt_2_115200 }, 4362 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4364 pbn_b2_bt_4_115200 }, 4365 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4367 pbn_b2_bt_2_115200 }, 4368 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4370 pbn_b2_bt_4_115200 }, 4371 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4373 pbn_b2_8_115200 }, 4374 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4376 pbn_b2_8_460800 }, 4377 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4379 pbn_b2_8_115200 }, 4380 4381 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4383 pbn_b2_bt_2_115200 }, 4384 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4386 pbn_b2_bt_2_921600 }, 4387 /* 4388 * VScom SPCOM800, from sl@s.pl 4389 */ 4390 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4392 pbn_b2_8_921600 }, 4393 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4395 pbn_b2_4_921600 }, 4396 /* Unknown card - subdevice 0x1584 */ 4397 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4398 PCI_VENDOR_ID_PLX, 4399 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4400 pbn_b2_4_115200 }, 4401 /* Unknown card - subdevice 0x1588 */ 4402 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4403 PCI_VENDOR_ID_PLX, 4404 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4405 pbn_b2_8_115200 }, 4406 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4407 PCI_SUBVENDOR_ID_KEYSPAN, 4408 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4409 pbn_panacom }, 4410 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4412 pbn_panacom4 }, 4413 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_panacom2 }, 4416 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4417 PCI_VENDOR_ID_ESDGMBH, 4418 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4419 pbn_b2_4_115200 }, 4420 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4421 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4422 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4423 pbn_b2_4_460800 }, 4424 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4425 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4426 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4427 pbn_b2_8_460800 }, 4428 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4429 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4430 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4431 pbn_b2_16_460800 }, 4432 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4433 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4434 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4435 pbn_b2_16_460800 }, 4436 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4437 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4438 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4439 pbn_b2_4_460800 }, 4440 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4441 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4442 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4443 pbn_b2_8_460800 }, 4444 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4445 PCI_SUBVENDOR_ID_EXSYS, 4446 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4447 pbn_b2_4_115200 }, 4448 /* 4449 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4450 * (Exoray@isys.ca) 4451 */ 4452 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4453 0x10b5, 0x106a, 0, 0, 4454 pbn_plx_romulus }, 4455 /* 4456 * Quatech cards. These actually have configurable clocks but for 4457 * now we just use the default. 4458 * 4459 * 100 series are RS232, 200 series RS422, 4460 */ 4461 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4463 pbn_b1_4_115200 }, 4464 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4466 pbn_b1_2_115200 }, 4467 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4469 pbn_b2_2_115200 }, 4470 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4472 pbn_b1_2_115200 }, 4473 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4475 pbn_b2_2_115200 }, 4476 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4478 pbn_b1_4_115200 }, 4479 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4481 pbn_b1_8_115200 }, 4482 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4484 pbn_b1_8_115200 }, 4485 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4487 pbn_b1_4_115200 }, 4488 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4490 pbn_b1_2_115200 }, 4491 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4493 pbn_b1_4_115200 }, 4494 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4496 pbn_b1_2_115200 }, 4497 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4499 pbn_b2_4_115200 }, 4500 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_b2_2_115200 }, 4503 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4505 pbn_b2_1_115200 }, 4506 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4508 pbn_b2_4_115200 }, 4509 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4511 pbn_b2_2_115200 }, 4512 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4514 pbn_b2_1_115200 }, 4515 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4517 pbn_b0_8_115200 }, 4518 4519 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4520 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4521 0, 0, 4522 pbn_b0_4_921600 }, 4523 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4524 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4525 0, 0, 4526 pbn_b0_4_1152000 }, 4527 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4529 pbn_b0_bt_2_921600 }, 4530 4531 /* 4532 * The below card is a little controversial since it is the 4533 * subject of a PCI vendor/device ID clash. (See 4534 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4535 * For now just used the hex ID 0x950a. 4536 */ 4537 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4538 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4539 0, 0, pbn_b0_2_115200 }, 4540 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4541 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4542 0, 0, pbn_b0_2_115200 }, 4543 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4545 pbn_b0_2_1130000 }, 4546 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4547 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4548 pbn_b0_1_921600 }, 4549 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4551 pbn_b0_4_115200 }, 4552 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4554 pbn_b0_bt_2_921600 }, 4555 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4557 pbn_b2_8_1152000 }, 4558 4559 /* 4560 * Oxford Semiconductor Inc. Tornado PCI express device range. 4561 */ 4562 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4564 pbn_b0_1_15625000 }, 4565 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4567 pbn_b0_1_15625000 }, 4568 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4570 pbn_oxsemi_1_15625000 }, 4571 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4573 pbn_oxsemi_1_15625000 }, 4574 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4576 pbn_b0_1_15625000 }, 4577 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4579 pbn_b0_1_15625000 }, 4580 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4582 pbn_oxsemi_1_15625000 }, 4583 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4585 pbn_oxsemi_1_15625000 }, 4586 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4588 pbn_b0_1_15625000 }, 4589 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4591 pbn_b0_1_15625000 }, 4592 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4594 pbn_b0_1_15625000 }, 4595 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4597 pbn_b0_1_15625000 }, 4598 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4600 pbn_oxsemi_2_15625000 }, 4601 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4603 pbn_oxsemi_2_15625000 }, 4604 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4606 pbn_oxsemi_4_15625000 }, 4607 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4609 pbn_oxsemi_4_15625000 }, 4610 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4612 pbn_oxsemi_8_15625000 }, 4613 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4615 pbn_oxsemi_8_15625000 }, 4616 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4618 pbn_oxsemi_1_15625000 }, 4619 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4621 pbn_oxsemi_1_15625000 }, 4622 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4624 pbn_oxsemi_1_15625000 }, 4625 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4627 pbn_oxsemi_1_15625000 }, 4628 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_oxsemi_1_15625000 }, 4631 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4633 pbn_oxsemi_1_15625000 }, 4634 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4636 pbn_oxsemi_1_15625000 }, 4637 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_oxsemi_1_15625000 }, 4640 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4642 pbn_oxsemi_1_15625000 }, 4643 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4645 pbn_oxsemi_1_15625000 }, 4646 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4648 pbn_oxsemi_1_15625000 }, 4649 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4651 pbn_oxsemi_1_15625000 }, 4652 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_oxsemi_1_15625000 }, 4655 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4657 pbn_oxsemi_1_15625000 }, 4658 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_oxsemi_1_15625000 }, 4661 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4663 pbn_oxsemi_1_15625000 }, 4664 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_oxsemi_1_15625000 }, 4667 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4669 pbn_oxsemi_1_15625000 }, 4670 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4672 pbn_oxsemi_1_15625000 }, 4673 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4675 pbn_oxsemi_1_15625000 }, 4676 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_oxsemi_1_15625000 }, 4679 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4681 pbn_oxsemi_1_15625000 }, 4682 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4684 pbn_oxsemi_1_15625000 }, 4685 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4687 pbn_oxsemi_1_15625000 }, 4688 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4690 pbn_oxsemi_1_15625000 }, 4691 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4693 pbn_oxsemi_1_15625000 }, 4694 /* 4695 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4696 */ 4697 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4698 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4699 pbn_oxsemi_1_15625000 }, 4700 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4701 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4702 pbn_oxsemi_2_15625000 }, 4703 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4704 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4705 pbn_oxsemi_4_15625000 }, 4706 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4707 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4708 pbn_oxsemi_8_15625000 }, 4709 4710 /* 4711 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4712 */ 4713 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4714 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4715 pbn_oxsemi_2_15625000 }, 4716 /* 4717 * EndRun Technologies. PCI express device range. 4718 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4719 */ 4720 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4722 pbn_oxsemi_2_15625000 }, 4723 4724 /* 4725 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4726 * from skokodyn@yahoo.com 4727 */ 4728 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4729 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4730 pbn_sbsxrsio }, 4731 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4732 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4733 pbn_sbsxrsio }, 4734 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4735 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4736 pbn_sbsxrsio }, 4737 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4738 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4739 pbn_sbsxrsio }, 4740 4741 /* 4742 * Digitan DS560-558, from jimd@esoft.com 4743 */ 4744 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4746 pbn_b1_1_115200 }, 4747 4748 /* 4749 * Titan Electronic cards 4750 * The 400L and 800L have a custom setup quirk. 4751 */ 4752 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4754 pbn_b0_1_921600 }, 4755 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4757 pbn_b0_2_921600 }, 4758 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4760 pbn_b0_4_921600 }, 4761 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4763 pbn_b0_4_921600 }, 4764 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4766 pbn_b1_1_921600 }, 4767 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4769 pbn_b1_bt_2_921600 }, 4770 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4772 pbn_b0_bt_4_921600 }, 4773 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4775 pbn_b0_bt_8_921600 }, 4776 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4778 pbn_b4_bt_2_921600 }, 4779 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4781 pbn_b4_bt_4_921600 }, 4782 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4784 pbn_b4_bt_8_921600 }, 4785 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4787 pbn_b0_4_921600 }, 4788 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4790 pbn_b0_4_921600 }, 4791 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4793 pbn_b0_4_921600 }, 4794 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4796 pbn_titan_1_4000000 }, 4797 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4799 pbn_titan_2_4000000 }, 4800 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4802 pbn_titan_4_4000000 }, 4803 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4805 pbn_titan_8_4000000 }, 4806 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4808 pbn_titan_2_4000000 }, 4809 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4811 pbn_titan_2_4000000 }, 4812 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4814 pbn_b0_bt_2_921600 }, 4815 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4817 pbn_b0_4_921600 }, 4818 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4820 pbn_b0_4_921600 }, 4821 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4823 pbn_b0_4_921600 }, 4824 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4826 pbn_b0_4_921600 }, 4827 4828 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4830 pbn_b2_1_460800 }, 4831 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4832 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4833 pbn_b2_1_460800 }, 4834 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4836 pbn_b2_1_460800 }, 4837 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4838 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4839 pbn_b2_bt_2_921600 }, 4840 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4842 pbn_b2_bt_2_921600 }, 4843 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4844 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4845 pbn_b2_bt_2_921600 }, 4846 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4848 pbn_b2_bt_4_921600 }, 4849 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4851 pbn_b2_bt_4_921600 }, 4852 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4854 pbn_b2_bt_4_921600 }, 4855 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4857 pbn_b0_1_921600 }, 4858 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4860 pbn_b0_1_921600 }, 4861 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4863 pbn_b0_1_921600 }, 4864 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4866 pbn_b0_bt_2_921600 }, 4867 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4869 pbn_b0_bt_2_921600 }, 4870 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4872 pbn_b0_bt_2_921600 }, 4873 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4875 pbn_b0_bt_4_921600 }, 4876 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4878 pbn_b0_bt_4_921600 }, 4879 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4881 pbn_b0_bt_4_921600 }, 4882 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4884 pbn_b0_bt_8_921600 }, 4885 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4887 pbn_b0_bt_8_921600 }, 4888 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4890 pbn_b0_bt_8_921600 }, 4891 4892 /* 4893 * Computone devices submitted by Doug McNash dmcnash@computone.com 4894 */ 4895 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4896 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4897 0, 0, pbn_computone_4 }, 4898 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4899 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4900 0, 0, pbn_computone_8 }, 4901 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4902 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4903 0, 0, pbn_computone_6 }, 4904 4905 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4907 pbn_oxsemi }, 4908 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4909 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4910 pbn_b0_bt_1_921600 }, 4911 4912 /* 4913 * Sunix PCI serial boards 4914 */ 4915 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4916 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4917 pbn_sunix_pci_1s }, 4918 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4919 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4920 pbn_sunix_pci_2s }, 4921 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4922 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4923 pbn_sunix_pci_4s }, 4924 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4925 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4926 pbn_sunix_pci_4s }, 4927 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4928 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4929 pbn_sunix_pci_8s }, 4930 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4931 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4932 pbn_sunix_pci_8s }, 4933 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4934 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4935 pbn_sunix_pci_16s }, 4936 4937 /* 4938 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4939 */ 4940 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4942 pbn_b0_bt_8_115200 }, 4943 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4945 pbn_b0_bt_8_115200 }, 4946 4947 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4949 pbn_b0_bt_2_115200 }, 4950 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4951 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4952 pbn_b0_bt_2_115200 }, 4953 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4955 pbn_b0_bt_2_115200 }, 4956 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4958 pbn_b0_bt_2_115200 }, 4959 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4961 pbn_b0_bt_2_115200 }, 4962 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4964 pbn_b0_bt_4_460800 }, 4965 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4967 pbn_b0_bt_4_460800 }, 4968 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4970 pbn_b0_bt_2_460800 }, 4971 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4973 pbn_b0_bt_2_460800 }, 4974 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4976 pbn_b0_bt_2_460800 }, 4977 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4979 pbn_b0_bt_1_115200 }, 4980 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4982 pbn_b0_bt_1_460800 }, 4983 4984 /* 4985 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4986 * Cards are identified by their subsystem vendor IDs, which 4987 * (in hex) match the model number. 4988 * 4989 * Note that JC140x are RS422/485 cards which require ox950 4990 * ACR = 0x10, and as such are not currently fully supported. 4991 */ 4992 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4993 0x1204, 0x0004, 0, 0, 4994 pbn_b0_4_921600 }, 4995 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4996 0x1208, 0x0004, 0, 0, 4997 pbn_b0_4_921600 }, 4998 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4999 0x1402, 0x0002, 0, 0, 5000 pbn_b0_2_921600 }, */ 5001 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5002 0x1404, 0x0004, 0, 0, 5003 pbn_b0_4_921600 }, */ 5004 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 5005 0x1208, 0x0004, 0, 0, 5006 pbn_b0_4_921600 }, 5007 5008 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5009 0x1204, 0x0004, 0, 0, 5010 pbn_b0_4_921600 }, 5011 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5012 0x1208, 0x0004, 0, 0, 5013 pbn_b0_4_921600 }, 5014 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 5015 0x1208, 0x0004, 0, 0, 5016 pbn_b0_4_921600 }, 5017 /* 5018 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 5019 */ 5020 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 5021 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5022 pbn_b1_1_1382400 }, 5023 5024 /* 5025 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 5026 */ 5027 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 5028 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5029 pbn_b1_1_1382400 }, 5030 5031 /* 5032 * RAStel 2 port modem, gerg@moreton.com.au 5033 */ 5034 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5036 pbn_b2_bt_2_115200 }, 5037 5038 /* 5039 * EKF addition for i960 Boards form EKF with serial port 5040 */ 5041 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 5042 0xE4BF, PCI_ANY_ID, 0, 0, 5043 pbn_intel_i960 }, 5044 5045 /* 5046 * Xircom Cardbus/Ethernet combos 5047 */ 5048 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5050 pbn_b0_1_115200 }, 5051 /* 5052 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 5053 */ 5054 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 5055 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5056 pbn_b0_1_115200 }, 5057 5058 /* 5059 * Untested PCI modems, sent in from various folks... 5060 */ 5061 5062 /* 5063 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 5064 */ 5065 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 5066 0x1048, 0x1500, 0, 0, 5067 pbn_b1_1_115200 }, 5068 5069 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 5070 0xFF00, 0, 0, 0, 5071 pbn_sgi_ioc3 }, 5072 5073 /* 5074 * HP Diva card 5075 */ 5076 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5077 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 5078 pbn_b1_1_115200 }, 5079 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5081 pbn_b0_5_115200 }, 5082 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5084 pbn_b2_1_115200 }, 5085 /* HPE PCI serial device */ 5086 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5088 pbn_b1_1_115200 }, 5089 5090 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5092 pbn_b3_2_115200 }, 5093 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5094 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5095 pbn_b3_4_115200 }, 5096 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5097 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5098 pbn_b3_8_115200 }, 5099 /* 5100 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5101 */ 5102 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5104 pbn_b0_1_115200 }, 5105 /* 5106 * ITE 5107 */ 5108 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5109 PCI_ANY_ID, PCI_ANY_ID, 5110 0, 0, 5111 pbn_b1_bt_1_115200 }, 5112 5113 /* 5114 * IntaShield IS-100 5115 */ 5116 { PCI_VENDOR_ID_INTASHIELD, 0x0D60, 5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5118 pbn_b2_1_115200 }, 5119 /* 5120 * IntaShield IS-200 5121 */ 5122 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */ 5124 pbn_b2_2_115200 }, 5125 /* 5126 * IntaShield IS-400 5127 */ 5128 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5130 pbn_b2_4_115200 }, 5131 /* 5132 * IntaShield IX-100 5133 */ 5134 { PCI_VENDOR_ID_INTASHIELD, 0x4027, 5135 PCI_ANY_ID, PCI_ANY_ID, 5136 0, 0, 5137 pbn_oxsemi_1_15625000 }, 5138 /* 5139 * IntaShield IX-200 5140 */ 5141 { PCI_VENDOR_ID_INTASHIELD, 0x4028, 5142 PCI_ANY_ID, PCI_ANY_ID, 5143 0, 0, 5144 pbn_oxsemi_2_15625000 }, 5145 /* 5146 * IntaShield IX-400 5147 */ 5148 { PCI_VENDOR_ID_INTASHIELD, 0x4029, 5149 PCI_ANY_ID, PCI_ANY_ID, 5150 0, 0, 5151 pbn_oxsemi_4_15625000 }, 5152 /* Brainboxes Devices */ 5153 /* 5154 * Brainboxes UC-101 5155 */ 5156 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 5157 PCI_ANY_ID, PCI_ANY_ID, 5158 0, 0, 5159 pbn_b2_2_115200 }, 5160 /* 5161 * Brainboxes UC-235/246 5162 */ 5163 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 5164 PCI_ANY_ID, PCI_ANY_ID, 5165 0, 0, 5166 pbn_b2_1_115200 }, 5167 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2, 5168 PCI_ANY_ID, PCI_ANY_ID, 5169 0, 0, 5170 pbn_b2_1_115200 }, 5171 /* 5172 * Brainboxes UC-253/UC-734 5173 */ 5174 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1, 5175 PCI_ANY_ID, PCI_ANY_ID, 5176 0, 0, 5177 pbn_b2_2_115200 }, 5178 /* 5179 * Brainboxes UC-260/271/701/756 5180 */ 5181 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5182 PCI_ANY_ID, PCI_ANY_ID, 5183 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5184 pbn_b2_4_115200 }, 5185 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5186 PCI_ANY_ID, PCI_ANY_ID, 5187 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5188 pbn_b2_4_115200 }, 5189 /* 5190 * Brainboxes UC-268 5191 */ 5192 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 5193 PCI_ANY_ID, PCI_ANY_ID, 5194 0, 0, 5195 pbn_b2_4_115200 }, 5196 /* 5197 * Brainboxes UC-275/279 5198 */ 5199 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 5200 PCI_ANY_ID, PCI_ANY_ID, 5201 0, 0, 5202 pbn_b2_8_115200 }, 5203 /* 5204 * Brainboxes UC-302 5205 */ 5206 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 5207 PCI_ANY_ID, PCI_ANY_ID, 5208 0, 0, 5209 pbn_b2_2_115200 }, 5210 { PCI_VENDOR_ID_INTASHIELD, 0x08E2, 5211 PCI_ANY_ID, PCI_ANY_ID, 5212 0, 0, 5213 pbn_b2_2_115200 }, 5214 { PCI_VENDOR_ID_INTASHIELD, 0x08E3, 5215 PCI_ANY_ID, PCI_ANY_ID, 5216 0, 0, 5217 pbn_b2_2_115200 }, 5218 /* 5219 * Brainboxes UC-310 5220 */ 5221 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5222 PCI_ANY_ID, PCI_ANY_ID, 5223 0, 0, 5224 pbn_b2_2_115200 }, 5225 /* 5226 * Brainboxes UC-313 5227 */ 5228 { PCI_VENDOR_ID_INTASHIELD, 0x08A1, 5229 PCI_ANY_ID, PCI_ANY_ID, 5230 0, 0, 5231 pbn_b2_2_115200 }, 5232 { PCI_VENDOR_ID_INTASHIELD, 0x08A2, 5233 PCI_ANY_ID, PCI_ANY_ID, 5234 0, 0, 5235 pbn_b2_2_115200 }, 5236 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5237 PCI_ANY_ID, PCI_ANY_ID, 5238 0, 0, 5239 pbn_b2_2_115200 }, 5240 /* 5241 * Brainboxes UC-320/324 5242 */ 5243 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5244 PCI_ANY_ID, PCI_ANY_ID, 5245 0, 0, 5246 pbn_b2_1_115200 }, 5247 /* 5248 * Brainboxes UC-346 5249 */ 5250 { PCI_VENDOR_ID_INTASHIELD, 0x0B01, 5251 PCI_ANY_ID, PCI_ANY_ID, 5252 0, 0, 5253 pbn_b2_4_115200 }, 5254 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5255 PCI_ANY_ID, PCI_ANY_ID, 5256 0, 0, 5257 pbn_b2_4_115200 }, 5258 /* 5259 * Brainboxes UC-357 5260 */ 5261 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5262 PCI_ANY_ID, PCI_ANY_ID, 5263 0, 0, 5264 pbn_b2_2_115200 }, 5265 { PCI_VENDOR_ID_INTASHIELD, 0x0A82, 5266 PCI_ANY_ID, PCI_ANY_ID, 5267 0, 0, 5268 pbn_b2_2_115200 }, 5269 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5270 PCI_ANY_ID, PCI_ANY_ID, 5271 0, 0, 5272 pbn_b2_2_115200 }, 5273 /* 5274 * Brainboxes UC-368 5275 */ 5276 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5277 PCI_ANY_ID, PCI_ANY_ID, 5278 0, 0, 5279 pbn_b2_4_115200 }, 5280 /* 5281 * Brainboxes UC-420 5282 */ 5283 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5284 PCI_ANY_ID, PCI_ANY_ID, 5285 0, 0, 5286 pbn_b2_4_115200 }, 5287 /* 5288 * Brainboxes UC-607 5289 */ 5290 { PCI_VENDOR_ID_INTASHIELD, 0x09A1, 5291 PCI_ANY_ID, PCI_ANY_ID, 5292 0, 0, 5293 pbn_b2_2_115200 }, 5294 { PCI_VENDOR_ID_INTASHIELD, 0x09A2, 5295 PCI_ANY_ID, PCI_ANY_ID, 5296 0, 0, 5297 pbn_b2_2_115200 }, 5298 { PCI_VENDOR_ID_INTASHIELD, 0x09A3, 5299 PCI_ANY_ID, PCI_ANY_ID, 5300 0, 0, 5301 pbn_b2_2_115200 }, 5302 /* 5303 * Brainboxes UC-836 5304 */ 5305 { PCI_VENDOR_ID_INTASHIELD, 0x0D41, 5306 PCI_ANY_ID, PCI_ANY_ID, 5307 0, 0, 5308 pbn_b2_4_115200 }, 5309 /* 5310 * Brainboxes UP-189 5311 */ 5312 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1, 5313 PCI_ANY_ID, PCI_ANY_ID, 5314 0, 0, 5315 pbn_b2_2_115200 }, 5316 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2, 5317 PCI_ANY_ID, PCI_ANY_ID, 5318 0, 0, 5319 pbn_b2_2_115200 }, 5320 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3, 5321 PCI_ANY_ID, PCI_ANY_ID, 5322 0, 0, 5323 pbn_b2_2_115200 }, 5324 /* 5325 * Brainboxes UP-200 5326 */ 5327 { PCI_VENDOR_ID_INTASHIELD, 0x0B21, 5328 PCI_ANY_ID, PCI_ANY_ID, 5329 0, 0, 5330 pbn_b2_2_115200 }, 5331 { PCI_VENDOR_ID_INTASHIELD, 0x0B22, 5332 PCI_ANY_ID, PCI_ANY_ID, 5333 0, 0, 5334 pbn_b2_2_115200 }, 5335 { PCI_VENDOR_ID_INTASHIELD, 0x0B23, 5336 PCI_ANY_ID, PCI_ANY_ID, 5337 0, 0, 5338 pbn_b2_2_115200 }, 5339 /* 5340 * Brainboxes UP-869 5341 */ 5342 { PCI_VENDOR_ID_INTASHIELD, 0x0C01, 5343 PCI_ANY_ID, PCI_ANY_ID, 5344 0, 0, 5345 pbn_b2_2_115200 }, 5346 { PCI_VENDOR_ID_INTASHIELD, 0x0C02, 5347 PCI_ANY_ID, PCI_ANY_ID, 5348 0, 0, 5349 pbn_b2_2_115200 }, 5350 { PCI_VENDOR_ID_INTASHIELD, 0x0C03, 5351 PCI_ANY_ID, PCI_ANY_ID, 5352 0, 0, 5353 pbn_b2_2_115200 }, 5354 /* 5355 * Brainboxes UP-880 5356 */ 5357 { PCI_VENDOR_ID_INTASHIELD, 0x0C21, 5358 PCI_ANY_ID, PCI_ANY_ID, 5359 0, 0, 5360 pbn_b2_2_115200 }, 5361 { PCI_VENDOR_ID_INTASHIELD, 0x0C22, 5362 PCI_ANY_ID, PCI_ANY_ID, 5363 0, 0, 5364 pbn_b2_2_115200 }, 5365 { PCI_VENDOR_ID_INTASHIELD, 0x0C23, 5366 PCI_ANY_ID, PCI_ANY_ID, 5367 0, 0, 5368 pbn_b2_2_115200 }, 5369 /* 5370 * Brainboxes PX-101 5371 */ 5372 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5373 PCI_ANY_ID, PCI_ANY_ID, 5374 0, 0, 5375 pbn_b0_2_115200 }, 5376 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5377 PCI_ANY_ID, PCI_ANY_ID, 5378 0, 0, 5379 pbn_oxsemi_2_15625000 }, 5380 /* 5381 * Brainboxes PX-235/246 5382 */ 5383 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5384 PCI_ANY_ID, PCI_ANY_ID, 5385 0, 0, 5386 pbn_b0_1_115200 }, 5387 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5388 PCI_ANY_ID, PCI_ANY_ID, 5389 0, 0, 5390 pbn_oxsemi_1_15625000 }, 5391 /* 5392 * Brainboxes PX-203/PX-257 5393 */ 5394 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5395 PCI_ANY_ID, PCI_ANY_ID, 5396 0, 0, 5397 pbn_b0_2_115200 }, 5398 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5399 PCI_ANY_ID, PCI_ANY_ID, 5400 0, 0, 5401 pbn_oxsemi_2_15625000 }, 5402 /* 5403 * Brainboxes PX-260/PX-701 5404 */ 5405 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5406 PCI_ANY_ID, PCI_ANY_ID, 5407 0, 0, 5408 pbn_oxsemi_4_15625000 }, 5409 /* 5410 * Brainboxes PX-275/279 5411 */ 5412 { PCI_VENDOR_ID_INTASHIELD, 0x0E41, 5413 PCI_ANY_ID, PCI_ANY_ID, 5414 0, 0, 5415 pbn_b2_8_115200 }, 5416 /* 5417 * Brainboxes PX-310 5418 */ 5419 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5420 PCI_ANY_ID, PCI_ANY_ID, 5421 0, 0, 5422 pbn_oxsemi_2_15625000 }, 5423 /* 5424 * Brainboxes PX-313 5425 */ 5426 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5427 PCI_ANY_ID, PCI_ANY_ID, 5428 0, 0, 5429 pbn_oxsemi_2_15625000 }, 5430 /* 5431 * Brainboxes PX-320/324/PX-376/PX-387 5432 */ 5433 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5434 PCI_ANY_ID, PCI_ANY_ID, 5435 0, 0, 5436 pbn_oxsemi_1_15625000 }, 5437 /* 5438 * Brainboxes PX-335/346 5439 */ 5440 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5441 PCI_ANY_ID, PCI_ANY_ID, 5442 0, 0, 5443 pbn_oxsemi_4_15625000 }, 5444 /* 5445 * Brainboxes PX-368 5446 */ 5447 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5448 PCI_ANY_ID, PCI_ANY_ID, 5449 0, 0, 5450 pbn_oxsemi_4_15625000 }, 5451 /* 5452 * Brainboxes PX-420 5453 */ 5454 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5455 PCI_ANY_ID, PCI_ANY_ID, 5456 0, 0, 5457 pbn_b0_4_115200 }, 5458 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5459 PCI_ANY_ID, PCI_ANY_ID, 5460 0, 0, 5461 pbn_oxsemi_4_15625000 }, 5462 /* 5463 * Brainboxes PX-475 5464 */ 5465 { PCI_VENDOR_ID_INTASHIELD, 0x401D, 5466 PCI_ANY_ID, PCI_ANY_ID, 5467 0, 0, 5468 pbn_oxsemi_1_15625000 }, 5469 /* 5470 * Brainboxes PX-803/PX-857 5471 */ 5472 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5473 PCI_ANY_ID, PCI_ANY_ID, 5474 0, 0, 5475 pbn_b0_2_115200 }, 5476 { PCI_VENDOR_ID_INTASHIELD, 0x4018, 5477 PCI_ANY_ID, PCI_ANY_ID, 5478 0, 0, 5479 pbn_oxsemi_2_15625000 }, 5480 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5481 PCI_ANY_ID, PCI_ANY_ID, 5482 0, 0, 5483 pbn_oxsemi_2_15625000 }, 5484 /* 5485 * Brainboxes PX-820 5486 */ 5487 { PCI_VENDOR_ID_INTASHIELD, 0x4002, 5488 PCI_ANY_ID, PCI_ANY_ID, 5489 0, 0, 5490 pbn_b0_4_115200 }, 5491 { PCI_VENDOR_ID_INTASHIELD, 0x4013, 5492 PCI_ANY_ID, PCI_ANY_ID, 5493 0, 0, 5494 pbn_oxsemi_4_15625000 }, 5495 /* 5496 * Brainboxes PX-835/PX-846 5497 */ 5498 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5499 PCI_ANY_ID, PCI_ANY_ID, 5500 0, 0, 5501 pbn_b0_1_115200 }, 5502 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5503 PCI_ANY_ID, PCI_ANY_ID, 5504 0, 0, 5505 pbn_oxsemi_1_15625000 }, 5506 5507 /* 5508 * Perle PCI-RAS cards 5509 */ 5510 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5511 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5512 0, 0, pbn_b2_4_921600 }, 5513 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5514 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5515 0, 0, pbn_b2_8_921600 }, 5516 5517 /* 5518 * Mainpine series cards: Fairly standard layout but fools 5519 * parts of the autodetect in some cases and uses otherwise 5520 * unmatched communications subclasses in the PCI Express case 5521 */ 5522 5523 { /* RockForceDUO */ 5524 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5525 PCI_VENDOR_ID_MAINPINE, 0x0200, 5526 0, 0, pbn_b0_2_115200 }, 5527 { /* RockForceQUATRO */ 5528 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5529 PCI_VENDOR_ID_MAINPINE, 0x0300, 5530 0, 0, pbn_b0_4_115200 }, 5531 { /* RockForceDUO+ */ 5532 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5533 PCI_VENDOR_ID_MAINPINE, 0x0400, 5534 0, 0, pbn_b0_2_115200 }, 5535 { /* RockForceQUATRO+ */ 5536 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5537 PCI_VENDOR_ID_MAINPINE, 0x0500, 5538 0, 0, pbn_b0_4_115200 }, 5539 { /* RockForce+ */ 5540 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5541 PCI_VENDOR_ID_MAINPINE, 0x0600, 5542 0, 0, pbn_b0_2_115200 }, 5543 { /* RockForce+ */ 5544 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5545 PCI_VENDOR_ID_MAINPINE, 0x0700, 5546 0, 0, pbn_b0_4_115200 }, 5547 { /* RockForceOCTO+ */ 5548 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5549 PCI_VENDOR_ID_MAINPINE, 0x0800, 5550 0, 0, pbn_b0_8_115200 }, 5551 { /* RockForceDUO+ */ 5552 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5553 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5554 0, 0, pbn_b0_2_115200 }, 5555 { /* RockForceQUARTRO+ */ 5556 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5557 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5558 0, 0, pbn_b0_4_115200 }, 5559 { /* RockForceOCTO+ */ 5560 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5561 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5562 0, 0, pbn_b0_8_115200 }, 5563 { /* RockForceD1 */ 5564 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5565 PCI_VENDOR_ID_MAINPINE, 0x2000, 5566 0, 0, pbn_b0_1_115200 }, 5567 { /* RockForceF1 */ 5568 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5569 PCI_VENDOR_ID_MAINPINE, 0x2100, 5570 0, 0, pbn_b0_1_115200 }, 5571 { /* RockForceD2 */ 5572 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5573 PCI_VENDOR_ID_MAINPINE, 0x2200, 5574 0, 0, pbn_b0_2_115200 }, 5575 { /* RockForceF2 */ 5576 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5577 PCI_VENDOR_ID_MAINPINE, 0x2300, 5578 0, 0, pbn_b0_2_115200 }, 5579 { /* RockForceD4 */ 5580 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5581 PCI_VENDOR_ID_MAINPINE, 0x2400, 5582 0, 0, pbn_b0_4_115200 }, 5583 { /* RockForceF4 */ 5584 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5585 PCI_VENDOR_ID_MAINPINE, 0x2500, 5586 0, 0, pbn_b0_4_115200 }, 5587 { /* RockForceD8 */ 5588 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5589 PCI_VENDOR_ID_MAINPINE, 0x2600, 5590 0, 0, pbn_b0_8_115200 }, 5591 { /* RockForceF8 */ 5592 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5593 PCI_VENDOR_ID_MAINPINE, 0x2700, 5594 0, 0, pbn_b0_8_115200 }, 5595 { /* IQ Express D1 */ 5596 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5597 PCI_VENDOR_ID_MAINPINE, 0x3000, 5598 0, 0, pbn_b0_1_115200 }, 5599 { /* IQ Express F1 */ 5600 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5601 PCI_VENDOR_ID_MAINPINE, 0x3100, 5602 0, 0, pbn_b0_1_115200 }, 5603 { /* IQ Express D2 */ 5604 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5605 PCI_VENDOR_ID_MAINPINE, 0x3200, 5606 0, 0, pbn_b0_2_115200 }, 5607 { /* IQ Express F2 */ 5608 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5609 PCI_VENDOR_ID_MAINPINE, 0x3300, 5610 0, 0, pbn_b0_2_115200 }, 5611 { /* IQ Express D4 */ 5612 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5613 PCI_VENDOR_ID_MAINPINE, 0x3400, 5614 0, 0, pbn_b0_4_115200 }, 5615 { /* IQ Express F4 */ 5616 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5617 PCI_VENDOR_ID_MAINPINE, 0x3500, 5618 0, 0, pbn_b0_4_115200 }, 5619 { /* IQ Express D8 */ 5620 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5621 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5622 0, 0, pbn_b0_8_115200 }, 5623 { /* IQ Express F8 */ 5624 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5625 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5626 0, 0, pbn_b0_8_115200 }, 5627 5628 5629 /* 5630 * PA Semi PA6T-1682M on-chip UART 5631 */ 5632 { PCI_VENDOR_ID_PASEMI, 0xa004, 5633 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5634 pbn_pasemi_1682M }, 5635 5636 /* 5637 * National Instruments 5638 */ 5639 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5640 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5641 pbn_b1_16_115200 }, 5642 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5643 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5644 pbn_b1_8_115200 }, 5645 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5646 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5647 pbn_b1_bt_4_115200 }, 5648 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5649 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5650 pbn_b1_bt_2_115200 }, 5651 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5652 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5653 pbn_b1_bt_4_115200 }, 5654 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5655 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5656 pbn_b1_bt_2_115200 }, 5657 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5658 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5659 pbn_b1_16_115200 }, 5660 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5661 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5662 pbn_b1_8_115200 }, 5663 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5664 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5665 pbn_b1_bt_4_115200 }, 5666 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5667 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5668 pbn_b1_bt_2_115200 }, 5669 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5671 pbn_b1_bt_4_115200 }, 5672 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5673 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5674 pbn_b1_bt_2_115200 }, 5675 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5677 pbn_ni8430_2 }, 5678 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5680 pbn_ni8430_2 }, 5681 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5682 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5683 pbn_ni8430_4 }, 5684 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5686 pbn_ni8430_4 }, 5687 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5689 pbn_ni8430_8 }, 5690 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5692 pbn_ni8430_8 }, 5693 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5695 pbn_ni8430_16 }, 5696 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5698 pbn_ni8430_16 }, 5699 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5701 pbn_ni8430_2 }, 5702 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5704 pbn_ni8430_2 }, 5705 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5707 pbn_ni8430_4 }, 5708 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5709 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5710 pbn_ni8430_4 }, 5711 5712 /* 5713 * MOXA 5714 */ 5715 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 }, 5716 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 }, 5717 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 }, 5718 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 }, 5719 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 }, 5720 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 }, 5721 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 }, 5722 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 }, 5723 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 }, 5724 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 }, 5725 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 }, 5726 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 }, 5727 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 }, 5728 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 }, 5729 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 }, 5730 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 }, 5731 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 }, 5732 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 }, 5733 5734 /* 5735 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5736 */ 5737 { PCI_VENDOR_ID_ADDIDATA, 5738 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5739 PCI_ANY_ID, 5740 PCI_ANY_ID, 5741 0, 5742 0, 5743 pbn_b0_4_115200 }, 5744 5745 { PCI_VENDOR_ID_ADDIDATA, 5746 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5747 PCI_ANY_ID, 5748 PCI_ANY_ID, 5749 0, 5750 0, 5751 pbn_b0_2_115200 }, 5752 5753 { PCI_VENDOR_ID_ADDIDATA, 5754 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5755 PCI_ANY_ID, 5756 PCI_ANY_ID, 5757 0, 5758 0, 5759 pbn_b0_1_115200 }, 5760 5761 { PCI_VENDOR_ID_AMCC, 5762 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5763 PCI_ANY_ID, 5764 PCI_ANY_ID, 5765 0, 5766 0, 5767 pbn_b1_8_115200 }, 5768 5769 { PCI_VENDOR_ID_ADDIDATA, 5770 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5771 PCI_ANY_ID, 5772 PCI_ANY_ID, 5773 0, 5774 0, 5775 pbn_b0_4_115200 }, 5776 5777 { PCI_VENDOR_ID_ADDIDATA, 5778 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5779 PCI_ANY_ID, 5780 PCI_ANY_ID, 5781 0, 5782 0, 5783 pbn_b0_2_115200 }, 5784 5785 { PCI_VENDOR_ID_ADDIDATA, 5786 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5787 PCI_ANY_ID, 5788 PCI_ANY_ID, 5789 0, 5790 0, 5791 pbn_b0_1_115200 }, 5792 5793 { PCI_VENDOR_ID_ADDIDATA, 5794 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5795 PCI_ANY_ID, 5796 PCI_ANY_ID, 5797 0, 5798 0, 5799 pbn_b0_4_115200 }, 5800 5801 { PCI_VENDOR_ID_ADDIDATA, 5802 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5803 PCI_ANY_ID, 5804 PCI_ANY_ID, 5805 0, 5806 0, 5807 pbn_b0_2_115200 }, 5808 5809 { PCI_VENDOR_ID_ADDIDATA, 5810 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5811 PCI_ANY_ID, 5812 PCI_ANY_ID, 5813 0, 5814 0, 5815 pbn_b0_1_115200 }, 5816 5817 { PCI_VENDOR_ID_ADDIDATA, 5818 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5819 PCI_ANY_ID, 5820 PCI_ANY_ID, 5821 0, 5822 0, 5823 pbn_b0_8_115200 }, 5824 5825 { PCI_VENDOR_ID_ADDIDATA, 5826 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5827 PCI_ANY_ID, 5828 PCI_ANY_ID, 5829 0, 5830 0, 5831 pbn_ADDIDATA_PCIe_4_3906250 }, 5832 5833 { PCI_VENDOR_ID_ADDIDATA, 5834 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5835 PCI_ANY_ID, 5836 PCI_ANY_ID, 5837 0, 5838 0, 5839 pbn_ADDIDATA_PCIe_2_3906250 }, 5840 5841 { PCI_VENDOR_ID_ADDIDATA, 5842 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5843 PCI_ANY_ID, 5844 PCI_ANY_ID, 5845 0, 5846 0, 5847 pbn_ADDIDATA_PCIe_1_3906250 }, 5848 5849 { PCI_VENDOR_ID_ADDIDATA, 5850 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5851 PCI_ANY_ID, 5852 PCI_ANY_ID, 5853 0, 5854 0, 5855 pbn_ADDIDATA_PCIe_8_3906250 }, 5856 5857 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5858 PCI_VENDOR_ID_IBM, 0x0299, 5859 0, 0, pbn_b0_bt_2_115200 }, 5860 5861 /* 5862 * other NetMos 9835 devices are most likely handled by the 5863 * parport_serial driver, check drivers/parport/parport_serial.c 5864 * before adding them here. 5865 */ 5866 5867 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5868 0xA000, 0x1000, 5869 0, 0, pbn_b0_1_115200 }, 5870 5871 /* the 9901 is a rebranded 9912 */ 5872 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5873 0xA000, 0x1000, 5874 0, 0, pbn_b0_1_115200 }, 5875 5876 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5877 0xA000, 0x1000, 5878 0, 0, pbn_b0_1_115200 }, 5879 5880 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5881 0xA000, 0x1000, 5882 0, 0, pbn_b0_1_115200 }, 5883 5884 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5885 0xA000, 0x1000, 5886 0, 0, pbn_b0_1_115200 }, 5887 5888 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5889 0xA000, 0x3002, 5890 0, 0, pbn_NETMOS9900_2s_115200 }, 5891 5892 /* 5893 * Best Connectivity and Rosewill PCI Multi I/O cards 5894 */ 5895 5896 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5897 0xA000, 0x1000, 5898 0, 0, pbn_b0_1_115200 }, 5899 5900 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5901 0xA000, 0x3002, 5902 0, 0, pbn_b0_bt_2_115200 }, 5903 5904 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5905 0xA000, 0x3004, 5906 0, 0, pbn_b0_bt_4_115200 }, 5907 5908 /* 5909 * ASIX AX99100 PCIe to Multi I/O Controller 5910 */ 5911 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 5912 0xA000, 0x1000, 5913 0, 0, pbn_b0_1_115200 }, 5914 5915 /* Intel CE4100 */ 5916 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5917 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5918 pbn_ce4100_1_115200 }, 5919 5920 /* 5921 * Cronyx Omega PCI 5922 */ 5923 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5925 pbn_omegapci }, 5926 5927 /* 5928 * Broadcom TruManage 5929 */ 5930 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5931 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5932 pbn_brcm_trumanage }, 5933 5934 /* 5935 * AgeStar as-prs2-009 5936 */ 5937 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5938 PCI_ANY_ID, PCI_ANY_ID, 5939 0, 0, pbn_b0_bt_2_115200 }, 5940 5941 /* 5942 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5943 * so not listed here. 5944 */ 5945 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5946 PCI_ANY_ID, PCI_ANY_ID, 5947 0, 0, pbn_b0_bt_4_115200 }, 5948 5949 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5950 PCI_ANY_ID, PCI_ANY_ID, 5951 0, 0, pbn_b0_bt_2_115200 }, 5952 5953 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5954 PCI_ANY_ID, PCI_ANY_ID, 5955 0, 0, pbn_b0_bt_4_115200 }, 5956 5957 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5958 PCI_ANY_ID, PCI_ANY_ID, 5959 0, 0, pbn_wch382_2 }, 5960 5961 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5962 PCI_ANY_ID, PCI_ANY_ID, 5963 0, 0, pbn_wch384_4 }, 5964 5965 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5966 PCI_ANY_ID, PCI_ANY_ID, 5967 0, 0, pbn_wch384_8 }, 5968 /* 5969 * Realtek RealManage 5970 */ 5971 { PCI_VENDOR_ID_REALTEK, 0x816a, 5972 PCI_ANY_ID, PCI_ANY_ID, 5973 0, 0, pbn_b0_1_115200 }, 5974 5975 { PCI_VENDOR_ID_REALTEK, 0x816b, 5976 PCI_ANY_ID, PCI_ANY_ID, 5977 0, 0, pbn_b0_1_115200 }, 5978 5979 /* Fintek PCI serial cards */ 5980 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5981 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5982 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5983 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5984 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5985 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5986 5987 /* MKS Tenta SCOM-080x serial cards */ 5988 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5989 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5990 5991 /* Amazon PCI serial device */ 5992 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5993 5994 /* 5995 * These entries match devices with class COMMUNICATION_SERIAL, 5996 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5997 */ 5998 { PCI_ANY_ID, PCI_ANY_ID, 5999 PCI_ANY_ID, PCI_ANY_ID, 6000 PCI_CLASS_COMMUNICATION_SERIAL << 8, 6001 0xffff00, pbn_default }, 6002 { PCI_ANY_ID, PCI_ANY_ID, 6003 PCI_ANY_ID, PCI_ANY_ID, 6004 PCI_CLASS_COMMUNICATION_MODEM << 8, 6005 0xffff00, pbn_default }, 6006 { PCI_ANY_ID, PCI_ANY_ID, 6007 PCI_ANY_ID, PCI_ANY_ID, 6008 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 6009 0xffff00, pbn_default }, 6010 { 0, } 6011 }; 6012 6013 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 6014 pci_channel_state_t state) 6015 { 6016 struct serial_private *priv = pci_get_drvdata(dev); 6017 6018 if (state == pci_channel_io_perm_failure) 6019 return PCI_ERS_RESULT_DISCONNECT; 6020 6021 if (priv) 6022 pciserial_detach_ports(priv); 6023 6024 pci_disable_device(dev); 6025 6026 return PCI_ERS_RESULT_NEED_RESET; 6027 } 6028 6029 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 6030 { 6031 int rc; 6032 6033 rc = pci_enable_device(dev); 6034 6035 if (rc) 6036 return PCI_ERS_RESULT_DISCONNECT; 6037 6038 pci_restore_state(dev); 6039 pci_save_state(dev); 6040 6041 return PCI_ERS_RESULT_RECOVERED; 6042 } 6043 6044 static void serial8250_io_resume(struct pci_dev *dev) 6045 { 6046 struct serial_private *priv = pci_get_drvdata(dev); 6047 struct serial_private *new; 6048 6049 if (!priv) 6050 return; 6051 6052 new = pciserial_init_ports(dev, priv->board); 6053 if (!IS_ERR(new)) { 6054 pci_set_drvdata(dev, new); 6055 kfree(priv); 6056 } 6057 } 6058 6059 static const struct pci_error_handlers serial8250_err_handler = { 6060 .error_detected = serial8250_io_error_detected, 6061 .slot_reset = serial8250_io_slot_reset, 6062 .resume = serial8250_io_resume, 6063 }; 6064 6065 static struct pci_driver serial_pci_driver = { 6066 .name = "serial", 6067 .probe = pciserial_init_one, 6068 .remove = pciserial_remove_one, 6069 .driver = { 6070 .pm = &pciserial_pm_ops, 6071 }, 6072 .id_table = serial_pci_tbl, 6073 .err_handler = &serial8250_err_handler, 6074 }; 6075 6076 module_pci_driver(serial_pci_driver); 6077 6078 MODULE_LICENSE("GPL"); 6079 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 6080 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 6081 MODULE_IMPORT_NS(SERIAL_8250_PCI); 6082