1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 31 #include "8250.h" 32 33 #define DEFAULT_CLK_SPEED 48000000 34 #define OMAP_UART_REGSHIFT 2 35 36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 38 #define OMAP_DMA_TX_KICK (1 << 2) 39 /* 40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 41 * The same errata is applicable to AM335x and DRA7x processors too. 42 */ 43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 44 #define UART_HAS_EFR2 BIT(4) 45 #define UART_HAS_RHR_IT_DIS BIT(5) 46 #define UART_RX_TIMEOUT_QUIRK BIT(6) 47 #define UART_HAS_NATIVE_RS485 BIT(7) 48 49 #define OMAP_UART_FCR_RX_TRIG 6 50 #define OMAP_UART_FCR_TX_TRIG 4 51 52 /* SCR register bitmasks */ 53 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 54 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 55 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 56 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 57 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 58 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 59 60 /* MVR register bitmasks */ 61 #define OMAP_UART_MVR_SCHEME_SHIFT 30 62 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 63 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 64 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 65 #define OMAP_UART_MVR_MAJ_MASK 0x700 66 #define OMAP_UART_MVR_MAJ_SHIFT 8 67 #define OMAP_UART_MVR_MIN_MASK 0x3f 68 69 /* SYSC register bitmasks */ 70 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 71 72 /* SYSS register bitmasks */ 73 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 74 75 #define UART_TI752_TLR_TX 0 76 #define UART_TI752_TLR_RX 4 77 78 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 79 #define TRIGGER_FCR_MASK(x) (x & 3) 80 81 /* Enable XON/XOFF flow control on output */ 82 #define OMAP_UART_SW_TX 0x08 83 /* Enable XON/XOFF flow control on input */ 84 #define OMAP_UART_SW_RX 0x02 85 86 #define OMAP_UART_WER_MOD_WKUP 0x7f 87 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 88 89 #define TX_TRIGGER 1 90 #define RX_TRIGGER 48 91 92 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 93 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 94 95 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 96 97 #define OMAP_UART_REV_46 0x0406 98 #define OMAP_UART_REV_52 0x0502 99 #define OMAP_UART_REV_63 0x0603 100 101 /* Interrupt Enable Register 2 */ 102 #define UART_OMAP_IER2 0x1B 103 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 104 105 /* Mode Definition Register 3 */ 106 #define UART_OMAP_MDR3 0x20 107 #define UART_OMAP_MDR3_DIR_POL BIT(3) 108 #define UART_OMAP_MDR3_DIR_EN BIT(4) 109 110 /* Enhanced features register 2 */ 111 #define UART_OMAP_EFR2 0x23 112 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 113 114 /* RX FIFO occupancy indicator */ 115 #define UART_OMAP_RX_LVL 0x19 116 117 /* Timeout low and High */ 118 #define UART_OMAP_TO_L 0x26 119 #define UART_OMAP_TO_H 0x27 120 121 struct omap8250_priv { 122 void __iomem *membase; 123 int line; 124 u8 habit; 125 u8 mdr1; 126 u8 mdr3; 127 u8 efr; 128 u8 scr; 129 u8 wer; 130 u8 xon; 131 u8 xoff; 132 u8 delayed_restore; 133 u16 quot; 134 135 u8 tx_trigger; 136 u8 rx_trigger; 137 atomic_t active; 138 bool is_suspending; 139 int wakeirq; 140 int wakeups_enabled; 141 u32 latency; 142 u32 calc_latency; 143 struct pm_qos_request pm_qos_request; 144 struct work_struct qos_work; 145 struct uart_8250_dma omap8250_dma; 146 spinlock_t rx_dma_lock; 147 bool rx_dma_broken; 148 bool throttled; 149 }; 150 151 struct omap8250_dma_params { 152 u32 rx_size; 153 u8 rx_trigger; 154 u8 tx_trigger; 155 }; 156 157 struct omap8250_platdata { 158 struct omap8250_dma_params *dma_params; 159 u8 habit; 160 }; 161 162 #ifdef CONFIG_SERIAL_8250_DMA 163 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 164 #else 165 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 166 #endif 167 168 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 169 { 170 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 171 } 172 173 /* 174 * Called on runtime PM resume path from omap8250_restore_regs(), and 175 * omap8250_set_mctrl(). 176 */ 177 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 178 { 179 struct uart_8250_port *up = up_to_u8250p(port); 180 struct omap8250_priv *priv = up->port.private_data; 181 u8 lcr; 182 183 serial8250_do_set_mctrl(port, mctrl); 184 185 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 186 /* 187 * Turn off autoRTS if RTS is lowered and restore autoRTS 188 * setting if RTS is raised 189 */ 190 lcr = serial_in(up, UART_LCR); 191 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 192 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 193 priv->efr |= UART_EFR_RTS; 194 else 195 priv->efr &= ~UART_EFR_RTS; 196 serial_out(up, UART_EFR, priv->efr); 197 serial_out(up, UART_LCR, lcr); 198 } 199 } 200 201 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 202 { 203 int err; 204 205 err = pm_runtime_resume_and_get(port->dev); 206 if (err) 207 return; 208 209 __omap8250_set_mctrl(port, mctrl); 210 211 pm_runtime_mark_last_busy(port->dev); 212 pm_runtime_put_autosuspend(port->dev); 213 } 214 215 /* 216 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 217 * The access to uart register after MDR1 Access 218 * causes UART to corrupt data. 219 * 220 * Need a delay = 221 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 222 * give 10 times as much 223 */ 224 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 225 struct omap8250_priv *priv) 226 { 227 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 228 udelay(2); 229 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 230 UART_FCR_CLEAR_RCVR); 231 } 232 233 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 234 struct omap8250_priv *priv) 235 { 236 unsigned int uartclk = port->uartclk; 237 unsigned int div_13, div_16; 238 unsigned int abs_d13, abs_d16; 239 240 /* 241 * Old custom speed handling. 242 */ 243 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 244 priv->quot = port->custom_divisor & UART_DIV_MAX; 245 /* 246 * I assume that nobody is using this. But hey, if somebody 247 * would like to specify the divisor _and_ the mode then the 248 * driver is ready and waiting for it. 249 */ 250 if (port->custom_divisor & (1 << 16)) 251 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 252 else 253 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 254 return; 255 } 256 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 257 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 258 259 if (!div_13) 260 div_13 = 1; 261 if (!div_16) 262 div_16 = 1; 263 264 abs_d13 = abs(baud - uartclk / 13 / div_13); 265 abs_d16 = abs(baud - uartclk / 16 / div_16); 266 267 if (abs_d13 >= abs_d16) { 268 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 269 priv->quot = div_16; 270 } else { 271 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 272 priv->quot = div_13; 273 } 274 } 275 276 static void omap8250_update_scr(struct uart_8250_port *up, 277 struct omap8250_priv *priv) 278 { 279 u8 old_scr; 280 281 old_scr = serial_in(up, UART_OMAP_SCR); 282 if (old_scr == priv->scr) 283 return; 284 285 /* 286 * The manual recommends not to enable the DMA mode selector in the SCR 287 * (instead of the FCR) register _and_ selecting the DMA mode as one 288 * register write because this may lead to malfunction. 289 */ 290 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 291 serial_out(up, UART_OMAP_SCR, 292 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 293 serial_out(up, UART_OMAP_SCR, priv->scr); 294 } 295 296 static void omap8250_update_mdr1(struct uart_8250_port *up, 297 struct omap8250_priv *priv) 298 { 299 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 300 omap_8250_mdr1_errataset(up, priv); 301 else 302 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 303 } 304 305 static void omap8250_restore_regs(struct uart_8250_port *up) 306 { 307 struct omap8250_priv *priv = up->port.private_data; 308 struct uart_8250_dma *dma = up->dma; 309 u8 mcr = serial8250_in_MCR(up); 310 311 /* Port locked to synchronize UART_IER access against the console. */ 312 lockdep_assert_held_once(&up->port.lock); 313 314 if (dma && dma->tx_running) { 315 /* 316 * TCSANOW requests the change to occur immediately however if 317 * we have a TX-DMA operation in progress then it has been 318 * observed that it might stall and never complete. Therefore we 319 * delay DMA completes to prevent this hang from happen. 320 */ 321 priv->delayed_restore = 1; 322 return; 323 } 324 325 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 326 serial_out(up, UART_EFR, UART_EFR_ECB); 327 328 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 329 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 330 serial_out(up, UART_FCR, up->fcr); 331 332 omap8250_update_scr(up, priv); 333 334 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 335 336 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 337 OMAP_UART_TCR_HALT(52)); 338 serial_out(up, UART_TI752_TLR, 339 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 340 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 341 342 serial_out(up, UART_LCR, 0); 343 344 /* drop TCR + TLR access, we setup XON/XOFF later */ 345 serial8250_out_MCR(up, mcr); 346 347 serial_out(up, UART_IER, up->ier); 348 349 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 350 serial_dl_write(up, priv->quot); 351 352 serial_out(up, UART_EFR, priv->efr); 353 354 /* Configure flow control */ 355 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 356 serial_out(up, UART_XON1, priv->xon); 357 serial_out(up, UART_XOFF1, priv->xoff); 358 359 serial_out(up, UART_LCR, up->lcr); 360 361 omap8250_update_mdr1(up, priv); 362 363 __omap8250_set_mctrl(&up->port, up->port.mctrl); 364 365 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 366 367 if (up->port.rs485.flags & SER_RS485_ENABLED && 368 up->port.rs485_config == serial8250_em485_config) 369 serial8250_em485_stop_tx(up); 370 } 371 372 /* 373 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 374 * some differences in how we want to handle flow control. 375 */ 376 static void omap_8250_set_termios(struct uart_port *port, 377 struct ktermios *termios, 378 const struct ktermios *old) 379 { 380 struct uart_8250_port *up = up_to_u8250p(port); 381 struct omap8250_priv *priv = up->port.private_data; 382 unsigned char cval = 0; 383 unsigned int baud; 384 385 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 386 387 if (termios->c_cflag & CSTOPB) 388 cval |= UART_LCR_STOP; 389 if (termios->c_cflag & PARENB) 390 cval |= UART_LCR_PARITY; 391 if (!(termios->c_cflag & PARODD)) 392 cval |= UART_LCR_EPAR; 393 if (termios->c_cflag & CMSPAR) 394 cval |= UART_LCR_SPAR; 395 396 /* 397 * Ask the core to calculate the divisor for us. 398 */ 399 baud = uart_get_baud_rate(port, termios, old, 400 port->uartclk / 16 / UART_DIV_MAX, 401 port->uartclk / 13); 402 omap_8250_get_divisor(port, baud, priv); 403 404 /* 405 * Ok, we're now changing the port state. Do it with 406 * interrupts disabled. 407 */ 408 pm_runtime_get_sync(port->dev); 409 uart_port_lock_irq(port); 410 411 /* 412 * Update the per-port timeout. 413 */ 414 uart_update_timeout(port, termios->c_cflag, baud); 415 416 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 417 if (termios->c_iflag & INPCK) 418 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 419 if (termios->c_iflag & (IGNBRK | PARMRK)) 420 up->port.read_status_mask |= UART_LSR_BI; 421 422 /* 423 * Characters to ignore 424 */ 425 up->port.ignore_status_mask = 0; 426 if (termios->c_iflag & IGNPAR) 427 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 428 if (termios->c_iflag & IGNBRK) { 429 up->port.ignore_status_mask |= UART_LSR_BI; 430 /* 431 * If we're ignoring parity and break indicators, 432 * ignore overruns too (for real raw support). 433 */ 434 if (termios->c_iflag & IGNPAR) 435 up->port.ignore_status_mask |= UART_LSR_OE; 436 } 437 438 /* 439 * ignore all characters if CREAD is not set 440 */ 441 if ((termios->c_cflag & CREAD) == 0) 442 up->port.ignore_status_mask |= UART_LSR_DR; 443 444 /* 445 * Modem status interrupts 446 */ 447 up->ier &= ~UART_IER_MSI; 448 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 449 up->ier |= UART_IER_MSI; 450 451 up->lcr = cval; 452 /* Up to here it was mostly serial8250_do_set_termios() */ 453 454 /* 455 * We enable TRIG_GRANU for RX and TX and additionally we set 456 * SCR_TX_EMPTY bit. The result is the following: 457 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 458 * - less than RX_TRIGGER number of bytes will also cause an interrupt 459 * once the UART decides that there no new bytes arriving. 460 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 461 * empty - the trigger level is ignored here. 462 * 463 * Once DMA is enabled: 464 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 465 * bytes in the TX FIFO. On each assert the DMA engine will move 466 * TX_TRIGGER bytes into the FIFO. 467 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 468 * the FIFO and move RX_TRIGGER bytes. 469 * This is because threshold and trigger values are the same. 470 */ 471 up->fcr = UART_FCR_ENABLE_FIFO; 472 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 473 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 474 475 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 476 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 477 478 if (up->dma) 479 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 480 OMAP_UART_SCR_DMAMODE_CTL; 481 482 priv->xon = termios->c_cc[VSTART]; 483 priv->xoff = termios->c_cc[VSTOP]; 484 485 priv->efr = 0; 486 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 487 488 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 489 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 490 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 491 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 492 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 493 priv->efr |= UART_EFR_CTS; 494 } else if (up->port.flags & UPF_SOFT_FLOW) { 495 /* 496 * OMAP rx s/w flow control is borked; the transmitter remains 497 * stuck off even if rx flow control is subsequently disabled 498 */ 499 500 /* 501 * IXOFF Flag: 502 * Enable XON/XOFF flow control on output. 503 * Transmit XON1, XOFF1 504 */ 505 if (termios->c_iflag & IXOFF) { 506 up->port.status |= UPSTAT_AUTOXOFF; 507 priv->efr |= OMAP_UART_SW_TX; 508 } 509 } 510 omap8250_restore_regs(up); 511 512 uart_port_unlock_irq(&up->port); 513 pm_runtime_mark_last_busy(port->dev); 514 pm_runtime_put_autosuspend(port->dev); 515 516 /* calculate wakeup latency constraint */ 517 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 518 priv->latency = priv->calc_latency; 519 520 schedule_work(&priv->qos_work); 521 522 /* Don't rewrite B0 */ 523 if (tty_termios_baud_rate(termios)) 524 tty_termios_encode_baud_rate(termios, baud, baud); 525 } 526 527 /* same as 8250 except that we may have extra flow bits set in EFR */ 528 static void omap_8250_pm(struct uart_port *port, unsigned int state, 529 unsigned int oldstate) 530 { 531 struct uart_8250_port *up = up_to_u8250p(port); 532 u8 efr; 533 534 pm_runtime_get_sync(port->dev); 535 536 /* Synchronize UART_IER access against the console. */ 537 uart_port_lock_irq(port); 538 539 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 540 efr = serial_in(up, UART_EFR); 541 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 542 serial_out(up, UART_LCR, 0); 543 544 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 545 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 546 serial_out(up, UART_EFR, efr); 547 serial_out(up, UART_LCR, 0); 548 549 uart_port_unlock_irq(port); 550 551 pm_runtime_mark_last_busy(port->dev); 552 pm_runtime_put_autosuspend(port->dev); 553 } 554 555 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 556 struct omap8250_priv *priv) 557 { 558 static const struct soc_device_attribute k3_soc_devices[] = { 559 { .family = "AM65X", }, 560 { .family = "J721E", .revision = "SR1.0" }, 561 { /* sentinel */ } 562 }; 563 u32 mvr, scheme; 564 u16 revision, major, minor; 565 566 mvr = uart_read(priv, UART_OMAP_MVER); 567 568 /* Check revision register scheme */ 569 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 570 571 switch (scheme) { 572 case 0: /* Legacy Scheme: OMAP2/3 */ 573 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 574 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 575 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 576 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 577 break; 578 case 1: 579 /* New Scheme: OMAP4+ */ 580 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 581 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 582 OMAP_UART_MVR_MAJ_SHIFT; 583 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 584 break; 585 default: 586 dev_warn(up->port.dev, 587 "Unknown revision, defaulting to highest\n"); 588 /* highest possible revision */ 589 major = 0xff; 590 minor = 0xff; 591 } 592 /* normalize revision for the driver */ 593 revision = UART_BUILD_REVISION(major, minor); 594 595 switch (revision) { 596 case OMAP_UART_REV_46: 597 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 598 break; 599 case OMAP_UART_REV_52: 600 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 601 OMAP_UART_WER_HAS_TX_WAKEUP; 602 break; 603 case OMAP_UART_REV_63: 604 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 605 OMAP_UART_WER_HAS_TX_WAKEUP; 606 break; 607 default: 608 break; 609 } 610 611 /* 612 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 613 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 614 * to enable errata workaround. 615 */ 616 if (soc_device_match(k3_soc_devices)) 617 priv->habit &= ~UART_HAS_RHR_IT_DIS; 618 } 619 620 static void omap8250_uart_qos_work(struct work_struct *work) 621 { 622 struct omap8250_priv *priv; 623 624 priv = container_of(work, struct omap8250_priv, qos_work); 625 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 626 } 627 628 #ifdef CONFIG_SERIAL_8250_DMA 629 static int omap_8250_dma_handle_irq(struct uart_port *port); 630 #endif 631 632 static irqreturn_t omap8250_irq(int irq, void *dev_id) 633 { 634 struct omap8250_priv *priv = dev_id; 635 struct uart_8250_port *up = serial8250_get_port(priv->line); 636 struct uart_port *port = &up->port; 637 unsigned int iir, lsr; 638 int ret; 639 640 pm_runtime_get_noresume(port->dev); 641 642 /* Shallow idle state wake-up to an IO interrupt? */ 643 if (atomic_add_unless(&priv->active, 1, 1)) { 644 priv->latency = priv->calc_latency; 645 schedule_work(&priv->qos_work); 646 } 647 648 #ifdef CONFIG_SERIAL_8250_DMA 649 if (up->dma) { 650 ret = omap_8250_dma_handle_irq(port); 651 pm_runtime_mark_last_busy(port->dev); 652 pm_runtime_put(port->dev); 653 return IRQ_RETVAL(ret); 654 } 655 #endif 656 657 lsr = serial_port_in(port, UART_LSR); 658 iir = serial_port_in(port, UART_IIR); 659 ret = serial8250_handle_irq(port, iir); 660 661 /* 662 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 663 * FIFO has been drained or erroneously. 664 * So apply solution of Errata i2310 as mentioned in 665 * https://www.ti.com/lit/pdf/sprz536 666 */ 667 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 668 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 669 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 670 unsigned char efr2, timeout_h, timeout_l; 671 672 efr2 = serial_in(up, UART_OMAP_EFR2); 673 timeout_h = serial_in(up, UART_OMAP_TO_H); 674 timeout_l = serial_in(up, UART_OMAP_TO_L); 675 serial_out(up, UART_OMAP_TO_H, 0xFF); 676 serial_out(up, UART_OMAP_TO_L, 0xFF); 677 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 678 serial_in(up, UART_IIR); 679 serial_out(up, UART_OMAP_EFR2, efr2); 680 serial_out(up, UART_OMAP_TO_H, timeout_h); 681 serial_out(up, UART_OMAP_TO_L, timeout_l); 682 } 683 684 /* Stop processing interrupts on input overrun */ 685 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 686 unsigned long delay; 687 688 /* Synchronize UART_IER access against the console. */ 689 uart_port_lock(port); 690 up->ier = port->serial_in(port, UART_IER); 691 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 692 port->ops->stop_rx(port); 693 } else { 694 /* Keep restarting the timer until 695 * the input overrun subsides. 696 */ 697 cancel_delayed_work(&up->overrun_backoff); 698 } 699 uart_port_unlock(port); 700 701 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 702 schedule_delayed_work(&up->overrun_backoff, delay); 703 } 704 705 pm_runtime_mark_last_busy(port->dev); 706 pm_runtime_put(port->dev); 707 708 return IRQ_RETVAL(ret); 709 } 710 711 static int omap_8250_startup(struct uart_port *port) 712 { 713 struct uart_8250_port *up = up_to_u8250p(port); 714 struct omap8250_priv *priv = port->private_data; 715 struct uart_8250_dma *dma = &priv->omap8250_dma; 716 int ret; 717 718 if (priv->wakeirq) { 719 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 720 if (ret) 721 return ret; 722 } 723 724 pm_runtime_get_sync(port->dev); 725 726 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 727 728 serial_out(up, UART_LCR, UART_LCR_WLEN8); 729 730 up->lsr_saved_flags = 0; 731 up->msr_saved_flags = 0; 732 733 /* Disable DMA for console UART */ 734 if (dma->fn && !uart_console(port)) { 735 up->dma = &priv->omap8250_dma; 736 ret = serial8250_request_dma(up); 737 if (ret) { 738 dev_warn_ratelimited(port->dev, 739 "failed to request DMA\n"); 740 up->dma = NULL; 741 } 742 } else { 743 up->dma = NULL; 744 } 745 746 /* Synchronize UART_IER access against the console. */ 747 uart_port_lock_irq(port); 748 up->ier = UART_IER_RLSI | UART_IER_RDI; 749 serial_out(up, UART_IER, up->ier); 750 uart_port_unlock_irq(port); 751 752 #ifdef CONFIG_PM 753 up->capabilities |= UART_CAP_RPM; 754 #endif 755 756 /* Enable module level wake up */ 757 priv->wer = OMAP_UART_WER_MOD_WKUP; 758 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 759 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 760 serial_out(up, UART_OMAP_WER, priv->wer); 761 762 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 763 uart_port_lock_irq(port); 764 up->dma->rx_dma(up); 765 uart_port_unlock_irq(port); 766 } 767 768 enable_irq(up->port.irq); 769 770 pm_runtime_mark_last_busy(port->dev); 771 pm_runtime_put_autosuspend(port->dev); 772 return 0; 773 } 774 775 static void omap_8250_shutdown(struct uart_port *port) 776 { 777 struct uart_8250_port *up = up_to_u8250p(port); 778 struct omap8250_priv *priv = port->private_data; 779 780 flush_work(&priv->qos_work); 781 if (up->dma) 782 omap_8250_rx_dma_flush(up); 783 784 pm_runtime_get_sync(port->dev); 785 786 serial_out(up, UART_OMAP_WER, 0); 787 if (priv->habit & UART_HAS_EFR2) 788 serial_out(up, UART_OMAP_EFR2, 0x0); 789 790 /* Synchronize UART_IER access against the console. */ 791 uart_port_lock_irq(port); 792 up->ier = 0; 793 serial_out(up, UART_IER, 0); 794 uart_port_unlock_irq(port); 795 disable_irq_nosync(up->port.irq); 796 dev_pm_clear_wake_irq(port->dev); 797 798 serial8250_release_dma(up); 799 up->dma = NULL; 800 801 /* 802 * Disable break condition and FIFOs 803 */ 804 if (up->lcr & UART_LCR_SBC) 805 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 806 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 807 808 pm_runtime_mark_last_busy(port->dev); 809 pm_runtime_put_autosuspend(port->dev); 810 } 811 812 static void omap_8250_throttle(struct uart_port *port) 813 { 814 struct omap8250_priv *priv = port->private_data; 815 unsigned long flags; 816 817 pm_runtime_get_sync(port->dev); 818 819 uart_port_lock_irqsave(port, &flags); 820 port->ops->stop_rx(port); 821 priv->throttled = true; 822 uart_port_unlock_irqrestore(port, flags); 823 824 pm_runtime_mark_last_busy(port->dev); 825 pm_runtime_put_autosuspend(port->dev); 826 } 827 828 static void omap_8250_unthrottle(struct uart_port *port) 829 { 830 struct omap8250_priv *priv = port->private_data; 831 struct uart_8250_port *up = up_to_u8250p(port); 832 unsigned long flags; 833 834 pm_runtime_get_sync(port->dev); 835 836 /* Synchronize UART_IER access against the console. */ 837 uart_port_lock_irqsave(port, &flags); 838 priv->throttled = false; 839 if (up->dma) 840 up->dma->rx_dma(up); 841 up->ier |= UART_IER_RLSI | UART_IER_RDI; 842 port->read_status_mask |= UART_LSR_DR; 843 serial_out(up, UART_IER, up->ier); 844 uart_port_unlock_irqrestore(port, flags); 845 846 pm_runtime_mark_last_busy(port->dev); 847 pm_runtime_put_autosuspend(port->dev); 848 } 849 850 static int omap8250_rs485_config(struct uart_port *port, 851 struct ktermios *termios, 852 struct serial_rs485 *rs485) 853 { 854 struct omap8250_priv *priv = port->private_data; 855 struct uart_8250_port *up = up_to_u8250p(port); 856 u32 fixed_delay_rts_before_send = 0; 857 u32 fixed_delay_rts_after_send = 0; 858 unsigned int baud; 859 860 /* 861 * There is a fixed delay of 3 bit clock cycles after the TX shift 862 * register is going empty to allow time for the stop bit to transition 863 * through the transceiver before direction is changed to receive. 864 * 865 * Additionally there appears to be a 1 bit clock delay between writing 866 * to the THR register and transmission of the start bit, per page 8783 867 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 868 */ 869 if (priv->quot) { 870 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 871 baud = port->uartclk / (16 * priv->quot); 872 else 873 baud = port->uartclk / (13 * priv->quot); 874 875 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 876 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 877 } 878 879 /* 880 * Fall back to RS485 software emulation if the UART is missing 881 * hardware support, if the device tree specifies an mctrl_gpio 882 * (indicates that RTS is unavailable due to a pinmux conflict) 883 * or if the requested delays exceed the fixed hardware delays. 884 */ 885 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 886 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 887 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 888 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 889 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 890 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 891 892 port->rs485_config = serial8250_em485_config; 893 return serial8250_em485_config(port, termios, rs485); 894 } 895 896 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 897 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 898 899 if (rs485->flags & SER_RS485_ENABLED) 900 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 901 else 902 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 903 904 /* 905 * Retain same polarity semantics as RS485 software emulation, 906 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 907 */ 908 if (rs485->flags & SER_RS485_RTS_ON_SEND) 909 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 910 else 911 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 912 913 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 914 915 return 0; 916 } 917 918 #ifdef CONFIG_SERIAL_8250_DMA 919 static int omap_8250_rx_dma(struct uart_8250_port *p); 920 921 /* Must be called while priv->rx_dma_lock is held */ 922 static void __dma_rx_do_complete(struct uart_8250_port *p) 923 { 924 struct uart_8250_dma *dma = p->dma; 925 struct tty_port *tty_port = &p->port.state->port; 926 struct omap8250_priv *priv = p->port.private_data; 927 struct dma_chan *rxchan = dma->rxchan; 928 dma_cookie_t cookie; 929 struct dma_tx_state state; 930 int count; 931 int ret; 932 u32 reg; 933 934 if (!dma->rx_running) 935 goto out; 936 937 cookie = dma->rx_cookie; 938 dma->rx_running = 0; 939 940 /* Re-enable RX FIFO interrupt now that transfer is complete */ 941 if (priv->habit & UART_HAS_RHR_IT_DIS) { 942 reg = serial_in(p, UART_OMAP_IER2); 943 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 944 serial_out(p, UART_OMAP_IER2, reg); 945 } 946 947 dmaengine_tx_status(rxchan, cookie, &state); 948 949 count = dma->rx_size - state.residue + state.in_flight_bytes; 950 if (count < dma->rx_size) { 951 dmaengine_terminate_async(rxchan); 952 953 /* 954 * Poll for teardown to complete which guarantees in 955 * flight data is drained. 956 */ 957 if (state.in_flight_bytes) { 958 int poll_count = 25; 959 960 while (dmaengine_tx_status(rxchan, cookie, NULL) && 961 poll_count--) 962 cpu_relax(); 963 964 if (poll_count == -1) 965 dev_err(p->port.dev, "teardown incomplete\n"); 966 } 967 } 968 if (!count) 969 goto out; 970 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 971 972 p->port.icount.rx += ret; 973 p->port.icount.buf_overrun += count - ret; 974 out: 975 976 tty_flip_buffer_push(tty_port); 977 } 978 979 static void __dma_rx_complete(void *param) 980 { 981 struct uart_8250_port *p = param; 982 struct omap8250_priv *priv = p->port.private_data; 983 struct uart_8250_dma *dma = p->dma; 984 struct dma_tx_state state; 985 unsigned long flags; 986 987 /* Synchronize UART_IER access against the console. */ 988 uart_port_lock_irqsave(&p->port, &flags); 989 990 /* 991 * If the tx status is not DMA_COMPLETE, then this is a delayed 992 * completion callback. A previous RX timeout flush would have 993 * already pushed the data, so exit. 994 */ 995 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 996 DMA_COMPLETE) { 997 uart_port_unlock_irqrestore(&p->port, flags); 998 return; 999 } 1000 __dma_rx_do_complete(p); 1001 if (!priv->throttled) { 1002 p->ier |= UART_IER_RLSI | UART_IER_RDI; 1003 serial_out(p, UART_IER, p->ier); 1004 if (!(priv->habit & UART_HAS_EFR2)) 1005 omap_8250_rx_dma(p); 1006 } 1007 1008 uart_port_unlock_irqrestore(&p->port, flags); 1009 } 1010 1011 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 1012 { 1013 struct omap8250_priv *priv = p->port.private_data; 1014 struct uart_8250_dma *dma = p->dma; 1015 struct dma_tx_state state; 1016 unsigned long flags; 1017 int ret; 1018 1019 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1020 1021 if (!dma->rx_running) { 1022 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1023 return; 1024 } 1025 1026 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1027 if (ret == DMA_IN_PROGRESS) { 1028 ret = dmaengine_pause(dma->rxchan); 1029 if (WARN_ON_ONCE(ret)) 1030 priv->rx_dma_broken = true; 1031 } 1032 __dma_rx_do_complete(p); 1033 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1034 } 1035 1036 static int omap_8250_rx_dma(struct uart_8250_port *p) 1037 { 1038 struct omap8250_priv *priv = p->port.private_data; 1039 struct uart_8250_dma *dma = p->dma; 1040 int err = 0; 1041 struct dma_async_tx_descriptor *desc; 1042 unsigned long flags; 1043 u32 reg; 1044 1045 /* Port locked to synchronize UART_IER access against the console. */ 1046 lockdep_assert_held_once(&p->port.lock); 1047 1048 if (priv->rx_dma_broken) 1049 return -EINVAL; 1050 1051 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1052 1053 if (dma->rx_running) { 1054 enum dma_status state; 1055 1056 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1057 if (state == DMA_COMPLETE) { 1058 /* 1059 * Disable RX interrupts to allow RX DMA completion 1060 * callback to run. 1061 */ 1062 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1063 serial_out(p, UART_IER, p->ier); 1064 } 1065 goto out; 1066 } 1067 1068 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1069 dma->rx_size, DMA_DEV_TO_MEM, 1070 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1071 if (!desc) { 1072 err = -EBUSY; 1073 goto out; 1074 } 1075 1076 dma->rx_running = 1; 1077 desc->callback = __dma_rx_complete; 1078 desc->callback_param = p; 1079 1080 dma->rx_cookie = dmaengine_submit(desc); 1081 1082 /* 1083 * Disable RX FIFO interrupt while RX DMA is enabled, else 1084 * spurious interrupt may be raised when data is in the RX FIFO 1085 * but is yet to be drained by DMA. 1086 */ 1087 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1088 reg = serial_in(p, UART_OMAP_IER2); 1089 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1090 serial_out(p, UART_OMAP_IER2, reg); 1091 } 1092 1093 dma_async_issue_pending(dma->rxchan); 1094 out: 1095 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1096 return err; 1097 } 1098 1099 static int omap_8250_tx_dma(struct uart_8250_port *p); 1100 1101 static void omap_8250_dma_tx_complete(void *param) 1102 { 1103 struct uart_8250_port *p = param; 1104 struct uart_8250_dma *dma = p->dma; 1105 struct tty_port *tport = &p->port.state->port; 1106 unsigned long flags; 1107 bool en_thri = false; 1108 struct omap8250_priv *priv = p->port.private_data; 1109 1110 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1111 UART_XMIT_SIZE, DMA_TO_DEVICE); 1112 1113 uart_port_lock_irqsave(&p->port, &flags); 1114 1115 dma->tx_running = 0; 1116 1117 uart_xmit_advance(&p->port, dma->tx_size); 1118 1119 if (priv->delayed_restore) { 1120 priv->delayed_restore = 0; 1121 omap8250_restore_regs(p); 1122 } 1123 1124 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1125 uart_write_wakeup(&p->port); 1126 1127 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1128 int ret; 1129 1130 ret = omap_8250_tx_dma(p); 1131 if (ret) 1132 en_thri = true; 1133 } else if (p->capabilities & UART_CAP_RPM) { 1134 en_thri = true; 1135 } 1136 1137 if (en_thri) { 1138 dma->tx_err = 1; 1139 serial8250_set_THRI(p); 1140 } 1141 1142 uart_port_unlock_irqrestore(&p->port, flags); 1143 } 1144 1145 static int omap_8250_tx_dma(struct uart_8250_port *p) 1146 { 1147 struct uart_8250_dma *dma = p->dma; 1148 struct omap8250_priv *priv = p->port.private_data; 1149 struct tty_port *tport = &p->port.state->port; 1150 struct dma_async_tx_descriptor *desc; 1151 struct scatterlist sg; 1152 int skip_byte = -1; 1153 int ret; 1154 1155 if (dma->tx_running) 1156 return 0; 1157 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1158 1159 /* 1160 * Even if no data, we need to return an error for the two cases 1161 * below so serial8250_tx_chars() is invoked and properly clears 1162 * THRI and/or runtime suspend. 1163 */ 1164 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1165 ret = -EBUSY; 1166 goto err; 1167 } 1168 serial8250_clear_THRI(p); 1169 return 0; 1170 } 1171 1172 sg_init_table(&sg, 1); 1173 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1174 UART_XMIT_SIZE, dma->tx_addr); 1175 if (ret != 1) { 1176 serial8250_clear_THRI(p); 1177 return 0; 1178 } 1179 1180 dma->tx_size = sg_dma_len(&sg); 1181 1182 if (priv->habit & OMAP_DMA_TX_KICK) { 1183 unsigned char c; 1184 u8 tx_lvl; 1185 1186 /* 1187 * We need to put the first byte into the FIFO in order to start 1188 * the DMA transfer. For transfers smaller than four bytes we 1189 * don't bother doing DMA at all. It seem not matter if there 1190 * are still bytes in the FIFO from the last transfer (in case 1191 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1192 * leaving the FIFO seem not to trigger the DMA transfer. It is 1193 * really the byte that we put into the FIFO. 1194 * If the FIFO is already full then we most likely got here from 1195 * omap_8250_dma_tx_complete(). And this means the DMA engine 1196 * just completed its work. We don't have to wait the complete 1197 * 86us at 115200,8n1 but around 60us (not to mention lower 1198 * baudrates). So in that case we take the interrupt and try 1199 * again with an empty FIFO. 1200 */ 1201 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1202 if (tx_lvl == p->tx_loadsz) { 1203 ret = -EBUSY; 1204 goto err; 1205 } 1206 if (dma->tx_size < 4) { 1207 ret = -EINVAL; 1208 goto err; 1209 } 1210 if (!kfifo_get(&tport->xmit_fifo, &c)) { 1211 ret = -EINVAL; 1212 goto err; 1213 } 1214 skip_byte = c; 1215 /* now we need to recompute due to kfifo_get */ 1216 kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1217 UART_XMIT_SIZE, dma->tx_addr); 1218 } 1219 1220 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1221 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1222 if (!desc) { 1223 ret = -EBUSY; 1224 goto err; 1225 } 1226 1227 dma->tx_running = 1; 1228 1229 desc->callback = omap_8250_dma_tx_complete; 1230 desc->callback_param = p; 1231 1232 dma->tx_cookie = dmaengine_submit(desc); 1233 1234 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1235 UART_XMIT_SIZE, DMA_TO_DEVICE); 1236 1237 dma_async_issue_pending(dma->txchan); 1238 if (dma->tx_err) 1239 dma->tx_err = 0; 1240 1241 serial8250_clear_THRI(p); 1242 ret = 0; 1243 goto out_skip; 1244 err: 1245 dma->tx_err = 1; 1246 out_skip: 1247 if (skip_byte >= 0) 1248 serial_out(p, UART_TX, skip_byte); 1249 return ret; 1250 } 1251 1252 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1253 { 1254 switch (iir & 0x3f) { 1255 case UART_IIR_RLSI: 1256 case UART_IIR_RX_TIMEOUT: 1257 case UART_IIR_RDI: 1258 omap_8250_rx_dma_flush(up); 1259 return true; 1260 } 1261 return omap_8250_rx_dma(up); 1262 } 1263 1264 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1265 { 1266 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1267 (iir & UART_IIR_RDI)) { 1268 if (handle_rx_dma(up, iir)) { 1269 status = serial8250_rx_chars(up, status); 1270 omap_8250_rx_dma(up); 1271 } 1272 } 1273 1274 return status; 1275 } 1276 1277 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1278 u16 status) 1279 { 1280 /* Port locked to synchronize UART_IER access against the console. */ 1281 lockdep_assert_held_once(&up->port.lock); 1282 1283 /* 1284 * Queue a new transfer if FIFO has data. 1285 */ 1286 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1287 (up->ier & UART_IER_RDI)) { 1288 omap_8250_rx_dma(up); 1289 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1290 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1291 /* 1292 * Disable RX timeout, read IIR to clear 1293 * current timeout condition, clear EFR2 to 1294 * periodic timeouts, re-enable interrupts. 1295 */ 1296 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1297 serial_out(up, UART_IER, up->ier); 1298 omap_8250_rx_dma_flush(up); 1299 serial_in(up, UART_IIR); 1300 serial_out(up, UART_OMAP_EFR2, 0x0); 1301 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1302 serial_out(up, UART_IER, up->ier); 1303 } 1304 } 1305 1306 /* 1307 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1308 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1309 * use the default routine in the non-DMA case and this one for with DMA. 1310 */ 1311 static int omap_8250_dma_handle_irq(struct uart_port *port) 1312 { 1313 struct uart_8250_port *up = up_to_u8250p(port); 1314 struct omap8250_priv *priv = up->port.private_data; 1315 u16 status; 1316 u8 iir; 1317 1318 iir = serial_port_in(port, UART_IIR); 1319 if (iir & UART_IIR_NO_INT) { 1320 return IRQ_HANDLED; 1321 } 1322 1323 uart_port_lock(port); 1324 1325 status = serial_port_in(port, UART_LSR); 1326 1327 if ((iir & 0x3f) != UART_IIR_THRI) { 1328 if (priv->habit & UART_HAS_EFR2) 1329 am654_8250_handle_rx_dma(up, iir, status); 1330 else 1331 status = omap_8250_handle_rx_dma(up, iir, status); 1332 } 1333 1334 serial8250_modem_status(up); 1335 if (status & UART_LSR_THRE && up->dma->tx_err) { 1336 if (uart_tx_stopped(&up->port) || 1337 kfifo_is_empty(&up->port.state->port.xmit_fifo)) { 1338 up->dma->tx_err = 0; 1339 serial8250_tx_chars(up); 1340 } else { 1341 /* 1342 * try again due to an earlier failer which 1343 * might have been resolved by now. 1344 */ 1345 if (omap_8250_tx_dma(up)) 1346 serial8250_tx_chars(up); 1347 } 1348 } 1349 1350 uart_unlock_and_check_sysrq(port); 1351 1352 return 1; 1353 } 1354 1355 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1356 { 1357 return false; 1358 } 1359 1360 #else 1361 1362 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1363 { 1364 return -EINVAL; 1365 } 1366 #endif 1367 1368 static int omap8250_no_handle_irq(struct uart_port *port) 1369 { 1370 /* IRQ has not been requested but handling irq? */ 1371 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1372 return 0; 1373 } 1374 1375 static struct omap8250_dma_params am654_dma = { 1376 .rx_size = SZ_2K, 1377 .rx_trigger = 1, 1378 .tx_trigger = TX_TRIGGER, 1379 }; 1380 1381 static struct omap8250_dma_params am33xx_dma = { 1382 .rx_size = RX_TRIGGER, 1383 .rx_trigger = RX_TRIGGER, 1384 .tx_trigger = TX_TRIGGER, 1385 }; 1386 1387 static struct omap8250_platdata am654_platdata = { 1388 .dma_params = &am654_dma, 1389 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1390 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1391 }; 1392 1393 static struct omap8250_platdata am33xx_platdata = { 1394 .dma_params = &am33xx_dma, 1395 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1396 }; 1397 1398 static struct omap8250_platdata omap4_platdata = { 1399 .dma_params = &am33xx_dma, 1400 .habit = UART_ERRATA_CLOCK_DISABLE, 1401 }; 1402 1403 static const struct of_device_id omap8250_dt_ids[] = { 1404 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1405 { .compatible = "ti,omap2-uart" }, 1406 { .compatible = "ti,omap3-uart" }, 1407 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1408 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1409 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1410 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1411 {}, 1412 }; 1413 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1414 1415 static int omap8250_probe(struct platform_device *pdev) 1416 { 1417 struct device_node *np = pdev->dev.of_node; 1418 struct omap8250_priv *priv; 1419 const struct omap8250_platdata *pdata; 1420 struct uart_8250_port up; 1421 struct resource *regs; 1422 void __iomem *membase; 1423 int ret; 1424 1425 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1426 if (!regs) { 1427 dev_err(&pdev->dev, "missing registers\n"); 1428 return -EINVAL; 1429 } 1430 1431 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1432 if (!priv) 1433 return -ENOMEM; 1434 1435 membase = devm_ioremap(&pdev->dev, regs->start, 1436 resource_size(regs)); 1437 if (!membase) 1438 return -ENODEV; 1439 1440 memset(&up, 0, sizeof(up)); 1441 up.port.dev = &pdev->dev; 1442 up.port.mapbase = regs->start; 1443 up.port.membase = membase; 1444 /* 1445 * It claims to be 16C750 compatible however it is a little different. 1446 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1447 * have) is enabled via EFR instead of MCR. The type is set here 8250 1448 * just to get things going. UNKNOWN does not work for a few reasons and 1449 * we don't need our own type since we don't use 8250's set_termios() 1450 * or pm callback. 1451 */ 1452 up.port.type = PORT_8250; 1453 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1454 up.port.private_data = priv; 1455 1456 up.tx_loadsz = 64; 1457 up.capabilities = UART_CAP_FIFO; 1458 #ifdef CONFIG_PM 1459 /* 1460 * Runtime PM is mostly transparent. However to do it right we need to a 1461 * TX empty interrupt before we can put the device to auto idle. So if 1462 * PM is not enabled we don't add that flag and can spare that one extra 1463 * interrupt in the TX path. 1464 */ 1465 up.capabilities |= UART_CAP_RPM; 1466 #endif 1467 up.port.set_termios = omap_8250_set_termios; 1468 up.port.set_mctrl = omap8250_set_mctrl; 1469 up.port.pm = omap_8250_pm; 1470 up.port.startup = omap_8250_startup; 1471 up.port.shutdown = omap_8250_shutdown; 1472 up.port.throttle = omap_8250_throttle; 1473 up.port.unthrottle = omap_8250_unthrottle; 1474 up.port.rs485_config = omap8250_rs485_config; 1475 /* same rs485_supported for software emulation and native RS485 */ 1476 up.port.rs485_supported = serial8250_em485_supported; 1477 up.rs485_start_tx = serial8250_em485_start_tx; 1478 up.rs485_stop_tx = serial8250_em485_stop_tx; 1479 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1480 1481 ret = uart_read_port_properties(&up.port); 1482 if (ret) 1483 return ret; 1484 1485 up.port.regshift = OMAP_UART_REGSHIFT; 1486 up.port.fifosize = 64; 1487 1488 if (!up.port.uartclk) { 1489 struct clk *clk; 1490 1491 clk = devm_clk_get(&pdev->dev, NULL); 1492 if (IS_ERR(clk)) { 1493 if (PTR_ERR(clk) == -EPROBE_DEFER) 1494 return -EPROBE_DEFER; 1495 } else { 1496 up.port.uartclk = clk_get_rate(clk); 1497 } 1498 } 1499 1500 if (of_property_read_u32(np, "overrun-throttle-ms", 1501 &up.overrun_backoff_time_ms) != 0) 1502 up.overrun_backoff_time_ms = 0; 1503 1504 pdata = of_device_get_match_data(&pdev->dev); 1505 if (pdata) 1506 priv->habit |= pdata->habit; 1507 1508 if (!up.port.uartclk) { 1509 up.port.uartclk = DEFAULT_CLK_SPEED; 1510 dev_warn(&pdev->dev, 1511 "No clock speed specified: using default: %d\n", 1512 DEFAULT_CLK_SPEED); 1513 } 1514 1515 priv->membase = membase; 1516 priv->line = -ENODEV; 1517 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1518 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1519 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1520 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1521 1522 spin_lock_init(&priv->rx_dma_lock); 1523 1524 platform_set_drvdata(pdev, priv); 1525 1526 device_init_wakeup(&pdev->dev, true); 1527 pm_runtime_enable(&pdev->dev); 1528 pm_runtime_use_autosuspend(&pdev->dev); 1529 1530 /* 1531 * Disable runtime PM until autosuspend delay unless specifically 1532 * enabled by the user via sysfs. This is the historic way to 1533 * prevent an unsafe default policy with lossy characters on wake-up. 1534 * For serdev devices this is not needed, the policy can be managed by 1535 * the serdev driver. 1536 */ 1537 if (!of_get_available_child_count(pdev->dev.of_node)) 1538 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1539 1540 pm_runtime_get_sync(&pdev->dev); 1541 1542 omap_serial_fill_features_erratas(&up, priv); 1543 up.port.handle_irq = omap8250_no_handle_irq; 1544 priv->rx_trigger = RX_TRIGGER; 1545 priv->tx_trigger = TX_TRIGGER; 1546 #ifdef CONFIG_SERIAL_8250_DMA 1547 /* 1548 * Oh DMA support. If there are no DMA properties in the DT then 1549 * we will fall back to a generic DMA channel which does not 1550 * really work here. To ensure that we do not get a generic DMA 1551 * channel assigned, we have the the_no_dma_filter_fn() here. 1552 * To avoid "failed to request DMA" messages we check for DMA 1553 * properties in DT. 1554 */ 1555 ret = of_property_count_strings(np, "dma-names"); 1556 if (ret == 2) { 1557 struct omap8250_dma_params *dma_params = NULL; 1558 struct uart_8250_dma *dma = &priv->omap8250_dma; 1559 1560 dma->fn = the_no_dma_filter_fn; 1561 dma->tx_dma = omap_8250_tx_dma; 1562 dma->rx_dma = omap_8250_rx_dma; 1563 if (pdata) 1564 dma_params = pdata->dma_params; 1565 1566 if (dma_params) { 1567 dma->rx_size = dma_params->rx_size; 1568 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1569 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1570 priv->rx_trigger = dma_params->rx_trigger; 1571 priv->tx_trigger = dma_params->tx_trigger; 1572 } else { 1573 dma->rx_size = RX_TRIGGER; 1574 dma->rxconf.src_maxburst = RX_TRIGGER; 1575 dma->txconf.dst_maxburst = TX_TRIGGER; 1576 } 1577 } 1578 #endif 1579 1580 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1581 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1582 dev_name(&pdev->dev), priv); 1583 if (ret < 0) 1584 return ret; 1585 1586 priv->wakeirq = irq_of_parse_and_map(np, 1); 1587 1588 ret = serial8250_register_8250_port(&up); 1589 if (ret < 0) { 1590 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1591 goto err; 1592 } 1593 priv->line = ret; 1594 pm_runtime_mark_last_busy(&pdev->dev); 1595 pm_runtime_put_autosuspend(&pdev->dev); 1596 return 0; 1597 err: 1598 pm_runtime_dont_use_autosuspend(&pdev->dev); 1599 pm_runtime_put_sync(&pdev->dev); 1600 flush_work(&priv->qos_work); 1601 pm_runtime_disable(&pdev->dev); 1602 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1603 return ret; 1604 } 1605 1606 static void omap8250_remove(struct platform_device *pdev) 1607 { 1608 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1609 struct uart_8250_port *up; 1610 int err; 1611 1612 err = pm_runtime_resume_and_get(&pdev->dev); 1613 if (err) 1614 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1615 1616 up = serial8250_get_port(priv->line); 1617 omap_8250_shutdown(&up->port); 1618 serial8250_unregister_port(priv->line); 1619 priv->line = -ENODEV; 1620 pm_runtime_dont_use_autosuspend(&pdev->dev); 1621 pm_runtime_put_sync(&pdev->dev); 1622 flush_work(&priv->qos_work); 1623 pm_runtime_disable(&pdev->dev); 1624 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1625 device_init_wakeup(&pdev->dev, false); 1626 } 1627 1628 static int omap8250_prepare(struct device *dev) 1629 { 1630 struct omap8250_priv *priv = dev_get_drvdata(dev); 1631 1632 if (!priv) 1633 return 0; 1634 priv->is_suspending = true; 1635 return 0; 1636 } 1637 1638 static void omap8250_complete(struct device *dev) 1639 { 1640 struct omap8250_priv *priv = dev_get_drvdata(dev); 1641 1642 if (!priv) 1643 return; 1644 priv->is_suspending = false; 1645 } 1646 1647 static int omap8250_suspend(struct device *dev) 1648 { 1649 struct omap8250_priv *priv = dev_get_drvdata(dev); 1650 struct uart_8250_port *up = serial8250_get_port(priv->line); 1651 int err = 0; 1652 1653 serial8250_suspend_port(priv->line); 1654 1655 err = pm_runtime_resume_and_get(dev); 1656 if (err) 1657 return err; 1658 if (!device_may_wakeup(dev)) 1659 priv->wer = 0; 1660 serial_out(up, UART_OMAP_WER, priv->wer); 1661 if (uart_console(&up->port) && console_suspend_enabled) 1662 err = pm_runtime_force_suspend(dev); 1663 flush_work(&priv->qos_work); 1664 1665 return err; 1666 } 1667 1668 static int omap8250_resume(struct device *dev) 1669 { 1670 struct omap8250_priv *priv = dev_get_drvdata(dev); 1671 struct uart_8250_port *up = serial8250_get_port(priv->line); 1672 int err; 1673 1674 if (uart_console(&up->port) && console_suspend_enabled) { 1675 err = pm_runtime_force_resume(dev); 1676 if (err) 1677 return err; 1678 } 1679 1680 serial8250_resume_port(priv->line); 1681 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1682 pm_runtime_mark_last_busy(dev); 1683 pm_runtime_put_autosuspend(dev); 1684 1685 return 0; 1686 } 1687 1688 static int omap8250_lost_context(struct uart_8250_port *up) 1689 { 1690 u32 val; 1691 1692 val = serial_in(up, UART_OMAP_SCR); 1693 /* 1694 * If we lose context, then SCR is set to its reset value of zero. 1695 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1696 * among other bits, to never set the register back to zero again. 1697 */ 1698 if (!val) 1699 return 1; 1700 return 0; 1701 } 1702 1703 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1704 { 1705 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1706 } 1707 1708 /* TODO: in future, this should happen via API in drivers/reset/ */ 1709 static int omap8250_soft_reset(struct device *dev) 1710 { 1711 struct omap8250_priv *priv = dev_get_drvdata(dev); 1712 int timeout = 100; 1713 int sysc; 1714 int syss; 1715 1716 /* 1717 * At least on omap4, unused uarts may not idle after reset without 1718 * a basic scr dma configuration even with no dma in use. The 1719 * module clkctrl status bits will be 1 instead of 3 blocking idle 1720 * for the whole clockdomain. The softreset below will clear scr, 1721 * and we restore it on resume so this is safe to do on all SoCs 1722 * needing omap8250_soft_reset() quirk. Do it in two writes as 1723 * recommended in the comment for omap8250_update_scr(). 1724 */ 1725 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1726 uart_write(priv, UART_OMAP_SCR, 1727 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1728 1729 sysc = uart_read(priv, UART_OMAP_SYSC); 1730 1731 /* softreset the UART */ 1732 sysc |= OMAP_UART_SYSC_SOFTRESET; 1733 uart_write(priv, UART_OMAP_SYSC, sysc); 1734 1735 /* By experiments, 1us enough for reset complete on AM335x */ 1736 do { 1737 udelay(1); 1738 syss = uart_read(priv, UART_OMAP_SYSS); 1739 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1740 1741 if (!timeout) { 1742 dev_err(dev, "timed out waiting for reset done\n"); 1743 return -ETIMEDOUT; 1744 } 1745 1746 return 0; 1747 } 1748 1749 static int omap8250_runtime_suspend(struct device *dev) 1750 { 1751 struct omap8250_priv *priv = dev_get_drvdata(dev); 1752 struct uart_8250_port *up = NULL; 1753 1754 if (priv->line >= 0) 1755 up = serial8250_get_port(priv->line); 1756 1757 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1758 int ret; 1759 1760 ret = omap8250_soft_reset(dev); 1761 if (ret) 1762 return ret; 1763 1764 if (up) { 1765 /* Restore to UART mode after reset (for wakeup) */ 1766 omap8250_update_mdr1(up, priv); 1767 /* Restore wakeup enable register */ 1768 serial_out(up, UART_OMAP_WER, priv->wer); 1769 } 1770 } 1771 1772 if (up && up->dma && up->dma->rxchan) 1773 omap_8250_rx_dma_flush(up); 1774 1775 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1776 schedule_work(&priv->qos_work); 1777 atomic_set(&priv->active, 0); 1778 1779 return 0; 1780 } 1781 1782 static int omap8250_runtime_resume(struct device *dev) 1783 { 1784 struct omap8250_priv *priv = dev_get_drvdata(dev); 1785 struct uart_8250_port *up = NULL; 1786 1787 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1788 if (atomic_read(&priv->active)) 1789 return 0; 1790 1791 if (priv->line >= 0) 1792 up = serial8250_get_port(priv->line); 1793 1794 if (up && omap8250_lost_context(up)) { 1795 uart_port_lock_irq(&up->port); 1796 omap8250_restore_regs(up); 1797 uart_port_unlock_irq(&up->port); 1798 } 1799 1800 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1801 uart_port_lock_irq(&up->port); 1802 omap_8250_rx_dma(up); 1803 uart_port_unlock_irq(&up->port); 1804 } 1805 1806 atomic_set(&priv->active, 1); 1807 priv->latency = priv->calc_latency; 1808 schedule_work(&priv->qos_work); 1809 1810 return 0; 1811 } 1812 1813 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1814 static int __init omap8250_console_fixup(void) 1815 { 1816 char *omap_str; 1817 char *options; 1818 u8 idx; 1819 1820 if (strstr(boot_command_line, "console=ttyS")) 1821 /* user set a ttyS based name for the console */ 1822 return 0; 1823 1824 omap_str = strstr(boot_command_line, "console=ttyO"); 1825 if (!omap_str) 1826 /* user did not set ttyO based console, so we don't care */ 1827 return 0; 1828 1829 omap_str += 12; 1830 if ('0' <= *omap_str && *omap_str <= '9') 1831 idx = *omap_str - '0'; 1832 else 1833 return 0; 1834 1835 omap_str++; 1836 if (omap_str[0] == ',') { 1837 omap_str++; 1838 options = omap_str; 1839 } else { 1840 options = NULL; 1841 } 1842 1843 add_preferred_console("ttyS", idx, options); 1844 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1845 idx, idx); 1846 pr_err("This ensures that you still see kernel messages. Please\n"); 1847 pr_err("update your kernel commandline.\n"); 1848 return 0; 1849 } 1850 console_initcall(omap8250_console_fixup); 1851 #endif 1852 1853 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1854 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1855 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1856 omap8250_runtime_resume, NULL) 1857 .prepare = pm_sleep_ptr(omap8250_prepare), 1858 .complete = pm_sleep_ptr(omap8250_complete), 1859 }; 1860 1861 static struct platform_driver omap8250_platform_driver = { 1862 .driver = { 1863 .name = "omap8250", 1864 .pm = pm_ptr(&omap8250_dev_pm_ops), 1865 .of_match_table = omap8250_dt_ids, 1866 }, 1867 .probe = omap8250_probe, 1868 .remove_new = omap8250_remove, 1869 }; 1870 module_platform_driver(omap8250_platform_driver); 1871 1872 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1873 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1874 MODULE_LICENSE("GPL v2"); 1875