1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 31 #include "8250.h" 32 33 #define DEFAULT_CLK_SPEED 48000000 34 #define OMAP_UART_REGSHIFT 2 35 36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 38 #define OMAP_DMA_TX_KICK (1 << 2) 39 /* 40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 41 * The same errata is applicable to AM335x and DRA7x processors too. 42 */ 43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 44 #define UART_HAS_EFR2 BIT(4) 45 #define UART_HAS_RHR_IT_DIS BIT(5) 46 #define UART_RX_TIMEOUT_QUIRK BIT(6) 47 #define UART_HAS_NATIVE_RS485 BIT(7) 48 49 #define OMAP_UART_FCR_RX_TRIG 6 50 #define OMAP_UART_FCR_TX_TRIG 4 51 52 /* SCR register bitmasks */ 53 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 54 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 55 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 56 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 57 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 58 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 59 60 /* MVR register bitmasks */ 61 #define OMAP_UART_MVR_SCHEME_SHIFT 30 62 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 63 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 64 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 65 #define OMAP_UART_MVR_MAJ_MASK 0x700 66 #define OMAP_UART_MVR_MAJ_SHIFT 8 67 #define OMAP_UART_MVR_MIN_MASK 0x3f 68 69 /* SYSC register bitmasks */ 70 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 71 72 /* SYSS register bitmasks */ 73 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 74 75 #define UART_TI752_TLR_TX 0 76 #define UART_TI752_TLR_RX 4 77 78 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 79 #define TRIGGER_FCR_MASK(x) (x & 3) 80 81 /* Enable XON/XOFF flow control on output */ 82 #define OMAP_UART_SW_TX 0x08 83 /* Enable XON/XOFF flow control on input */ 84 #define OMAP_UART_SW_RX 0x02 85 86 #define OMAP_UART_WER_MOD_WKUP 0x7f 87 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 88 89 #define TX_TRIGGER 1 90 #define RX_TRIGGER 48 91 92 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 93 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 94 95 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 96 97 #define OMAP_UART_REV_46 0x0406 98 #define OMAP_UART_REV_52 0x0502 99 #define OMAP_UART_REV_63 0x0603 100 101 /* Interrupt Enable Register 2 */ 102 #define UART_OMAP_IER2 0x1B 103 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 104 105 /* Mode Definition Register 3 */ 106 #define UART_OMAP_MDR3 0x20 107 #define UART_OMAP_MDR3_DIR_POL BIT(3) 108 #define UART_OMAP_MDR3_DIR_EN BIT(4) 109 110 /* Enhanced features register 2 */ 111 #define UART_OMAP_EFR2 0x23 112 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 113 114 /* RX FIFO occupancy indicator */ 115 #define UART_OMAP_RX_LVL 0x19 116 117 /* Timeout low and High */ 118 #define UART_OMAP_TO_L 0x26 119 #define UART_OMAP_TO_H 0x27 120 121 struct omap8250_priv { 122 void __iomem *membase; 123 int line; 124 u8 habit; 125 u8 mdr1; 126 u8 mdr3; 127 u8 efr; 128 u8 scr; 129 u8 wer; 130 u8 xon; 131 u8 xoff; 132 u8 delayed_restore; 133 u16 quot; 134 135 u8 tx_trigger; 136 u8 rx_trigger; 137 atomic_t active; 138 bool is_suspending; 139 int wakeirq; 140 u32 latency; 141 u32 calc_latency; 142 struct pm_qos_request pm_qos_request; 143 struct work_struct qos_work; 144 struct uart_8250_dma omap8250_dma; 145 spinlock_t rx_dma_lock; 146 bool rx_dma_broken; 147 bool throttled; 148 }; 149 150 struct omap8250_dma_params { 151 u32 rx_size; 152 u8 rx_trigger; 153 u8 tx_trigger; 154 }; 155 156 struct omap8250_platdata { 157 struct omap8250_dma_params *dma_params; 158 u8 habit; 159 }; 160 161 #ifdef CONFIG_SERIAL_8250_DMA 162 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 163 #else 164 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 165 #endif 166 167 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 168 { 169 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 170 } 171 172 /* 173 * Called on runtime PM resume path from omap8250_restore_regs(), and 174 * omap8250_set_mctrl(). 175 */ 176 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 177 { 178 struct uart_8250_port *up = up_to_u8250p(port); 179 struct omap8250_priv *priv = up->port.private_data; 180 u8 lcr; 181 182 serial8250_do_set_mctrl(port, mctrl); 183 184 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 185 /* 186 * Turn off autoRTS if RTS is lowered and restore autoRTS 187 * setting if RTS is raised 188 */ 189 lcr = serial_in(up, UART_LCR); 190 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 191 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 192 priv->efr |= UART_EFR_RTS; 193 else 194 priv->efr &= ~UART_EFR_RTS; 195 serial_out(up, UART_EFR, priv->efr); 196 serial_out(up, UART_LCR, lcr); 197 } 198 } 199 200 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 201 { 202 int err; 203 204 err = pm_runtime_resume_and_get(port->dev); 205 if (err) 206 return; 207 208 __omap8250_set_mctrl(port, mctrl); 209 210 pm_runtime_mark_last_busy(port->dev); 211 pm_runtime_put_autosuspend(port->dev); 212 } 213 214 /* 215 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 216 * The access to uart register after MDR1 Access 217 * causes UART to corrupt data. 218 * 219 * Need a delay = 220 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 221 * give 10 times as much 222 */ 223 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 224 struct omap8250_priv *priv) 225 { 226 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 227 udelay(2); 228 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 229 UART_FCR_CLEAR_RCVR); 230 } 231 232 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 233 struct omap8250_priv *priv) 234 { 235 unsigned int uartclk = port->uartclk; 236 unsigned int div_13, div_16; 237 unsigned int abs_d13, abs_d16; 238 239 /* 240 * Old custom speed handling. 241 */ 242 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 243 priv->quot = port->custom_divisor & UART_DIV_MAX; 244 /* 245 * I assume that nobody is using this. But hey, if somebody 246 * would like to specify the divisor _and_ the mode then the 247 * driver is ready and waiting for it. 248 */ 249 if (port->custom_divisor & (1 << 16)) 250 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 251 else 252 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 253 return; 254 } 255 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 256 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 257 258 if (!div_13) 259 div_13 = 1; 260 if (!div_16) 261 div_16 = 1; 262 263 abs_d13 = abs(baud - uartclk / 13 / div_13); 264 abs_d16 = abs(baud - uartclk / 16 / div_16); 265 266 if (abs_d13 >= abs_d16) { 267 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 268 priv->quot = div_16; 269 } else { 270 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 271 priv->quot = div_13; 272 } 273 } 274 275 static void omap8250_update_scr(struct uart_8250_port *up, 276 struct omap8250_priv *priv) 277 { 278 u8 old_scr; 279 280 old_scr = serial_in(up, UART_OMAP_SCR); 281 if (old_scr == priv->scr) 282 return; 283 284 /* 285 * The manual recommends not to enable the DMA mode selector in the SCR 286 * (instead of the FCR) register _and_ selecting the DMA mode as one 287 * register write because this may lead to malfunction. 288 */ 289 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 290 serial_out(up, UART_OMAP_SCR, 291 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 292 serial_out(up, UART_OMAP_SCR, priv->scr); 293 } 294 295 static void omap8250_update_mdr1(struct uart_8250_port *up, 296 struct omap8250_priv *priv) 297 { 298 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 299 omap_8250_mdr1_errataset(up, priv); 300 else 301 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 302 } 303 304 static void omap8250_restore_regs(struct uart_8250_port *up) 305 { 306 struct omap8250_priv *priv = up->port.private_data; 307 struct uart_8250_dma *dma = up->dma; 308 u8 mcr = serial8250_in_MCR(up); 309 310 /* Port locked to synchronize UART_IER access against the console. */ 311 lockdep_assert_held_once(&up->port.lock); 312 313 if (dma && dma->tx_running) { 314 /* 315 * TCSANOW requests the change to occur immediately however if 316 * we have a TX-DMA operation in progress then it has been 317 * observed that it might stall and never complete. Therefore we 318 * delay DMA completes to prevent this hang from happen. 319 */ 320 priv->delayed_restore = 1; 321 return; 322 } 323 324 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 325 serial_out(up, UART_EFR, UART_EFR_ECB); 326 327 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 328 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 329 serial_out(up, UART_FCR, up->fcr); 330 331 omap8250_update_scr(up, priv); 332 333 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 334 335 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 336 OMAP_UART_TCR_HALT(52)); 337 serial_out(up, UART_TI752_TLR, 338 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 339 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 340 341 serial_out(up, UART_LCR, 0); 342 343 /* drop TCR + TLR access, we setup XON/XOFF later */ 344 serial8250_out_MCR(up, mcr); 345 346 serial_out(up, UART_IER, up->ier); 347 348 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 349 serial_dl_write(up, priv->quot); 350 351 serial_out(up, UART_EFR, priv->efr); 352 353 /* Configure flow control */ 354 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 355 serial_out(up, UART_XON1, priv->xon); 356 serial_out(up, UART_XOFF1, priv->xoff); 357 358 serial_out(up, UART_LCR, up->lcr); 359 360 omap8250_update_mdr1(up, priv); 361 362 __omap8250_set_mctrl(&up->port, up->port.mctrl); 363 364 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 365 366 if (up->port.rs485.flags & SER_RS485_ENABLED && 367 up->port.rs485_config == serial8250_em485_config) 368 serial8250_em485_stop_tx(up, true); 369 } 370 371 /* 372 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 373 * some differences in how we want to handle flow control. 374 */ 375 static void omap_8250_set_termios(struct uart_port *port, 376 struct ktermios *termios, 377 const struct ktermios *old) 378 { 379 struct uart_8250_port *up = up_to_u8250p(port); 380 struct omap8250_priv *priv = up->port.private_data; 381 unsigned char cval = 0; 382 unsigned int baud; 383 384 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 385 386 if (termios->c_cflag & CSTOPB) 387 cval |= UART_LCR_STOP; 388 if (termios->c_cflag & PARENB) 389 cval |= UART_LCR_PARITY; 390 if (!(termios->c_cflag & PARODD)) 391 cval |= UART_LCR_EPAR; 392 if (termios->c_cflag & CMSPAR) 393 cval |= UART_LCR_SPAR; 394 395 /* 396 * Ask the core to calculate the divisor for us. 397 */ 398 baud = uart_get_baud_rate(port, termios, old, 399 port->uartclk / 16 / UART_DIV_MAX, 400 port->uartclk / 13); 401 omap_8250_get_divisor(port, baud, priv); 402 403 /* 404 * Ok, we're now changing the port state. Do it with 405 * interrupts disabled. 406 */ 407 pm_runtime_get_sync(port->dev); 408 uart_port_lock_irq(port); 409 410 /* 411 * Update the per-port timeout. 412 */ 413 uart_update_timeout(port, termios->c_cflag, baud); 414 415 /* 416 * Specify which conditions may be considered for error 417 * handling and the ignoring of characters. The actual 418 * ignoring of characters only occurs if the bit is set 419 * in @ignore_status_mask as well. 420 */ 421 up->port.read_status_mask = UART_LSR_OE | UART_LSR_DR; 422 if (termios->c_iflag & INPCK) 423 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 424 if (termios->c_iflag & (IGNBRK | PARMRK)) 425 up->port.read_status_mask |= UART_LSR_BI; 426 427 /* 428 * Characters to ignore 429 */ 430 up->port.ignore_status_mask = 0; 431 if (termios->c_iflag & IGNPAR) 432 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 433 if (termios->c_iflag & IGNBRK) { 434 up->port.ignore_status_mask |= UART_LSR_BI; 435 /* 436 * If we're ignoring parity and break indicators, 437 * ignore overruns too (for real raw support). 438 */ 439 if (termios->c_iflag & IGNPAR) 440 up->port.ignore_status_mask |= UART_LSR_OE; 441 } 442 443 /* 444 * ignore all characters if CREAD is not set 445 */ 446 if ((termios->c_cflag & CREAD) == 0) 447 up->port.ignore_status_mask |= UART_LSR_DR; 448 449 /* 450 * Modem status interrupts 451 */ 452 up->ier &= ~UART_IER_MSI; 453 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 454 up->ier |= UART_IER_MSI; 455 456 up->lcr = cval; 457 /* Up to here it was mostly serial8250_do_set_termios() */ 458 459 /* 460 * We enable TRIG_GRANU for RX and TX and additionally we set 461 * SCR_TX_EMPTY bit. The result is the following: 462 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 463 * - less than RX_TRIGGER number of bytes will also cause an interrupt 464 * once the UART decides that there no new bytes arriving. 465 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 466 * empty - the trigger level is ignored here. 467 * 468 * Once DMA is enabled: 469 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 470 * bytes in the TX FIFO. On each assert the DMA engine will move 471 * TX_TRIGGER bytes into the FIFO. 472 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 473 * the FIFO and move RX_TRIGGER bytes. 474 * This is because threshold and trigger values are the same. 475 */ 476 up->fcr = UART_FCR_ENABLE_FIFO; 477 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 478 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 479 480 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 481 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 482 483 if (up->dma) 484 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 485 OMAP_UART_SCR_DMAMODE_CTL; 486 487 priv->xon = termios->c_cc[VSTART]; 488 priv->xoff = termios->c_cc[VSTOP]; 489 490 priv->efr = 0; 491 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 492 493 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 494 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 495 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 496 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 497 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 498 priv->efr |= UART_EFR_CTS; 499 } else if (up->port.flags & UPF_SOFT_FLOW) { 500 /* 501 * OMAP rx s/w flow control is borked; the transmitter remains 502 * stuck off even if rx flow control is subsequently disabled 503 */ 504 505 /* 506 * IXOFF Flag: 507 * Enable XON/XOFF flow control on output. 508 * Transmit XON1, XOFF1 509 */ 510 if (termios->c_iflag & IXOFF) { 511 up->port.status |= UPSTAT_AUTOXOFF; 512 priv->efr |= OMAP_UART_SW_TX; 513 } 514 } 515 omap8250_restore_regs(up); 516 517 uart_port_unlock_irq(&up->port); 518 pm_runtime_mark_last_busy(port->dev); 519 pm_runtime_put_autosuspend(port->dev); 520 521 /* calculate wakeup latency constraint */ 522 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 523 priv->latency = priv->calc_latency; 524 525 schedule_work(&priv->qos_work); 526 527 /* Don't rewrite B0 */ 528 if (tty_termios_baud_rate(termios)) 529 tty_termios_encode_baud_rate(termios, baud, baud); 530 } 531 532 /* same as 8250 except that we may have extra flow bits set in EFR */ 533 static void omap_8250_pm(struct uart_port *port, unsigned int state, 534 unsigned int oldstate) 535 { 536 struct uart_8250_port *up = up_to_u8250p(port); 537 u8 efr; 538 539 pm_runtime_get_sync(port->dev); 540 541 /* Synchronize UART_IER access against the console. */ 542 uart_port_lock_irq(port); 543 544 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 545 efr = serial_in(up, UART_EFR); 546 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 547 serial_out(up, UART_LCR, 0); 548 549 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 550 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 551 serial_out(up, UART_EFR, efr); 552 serial_out(up, UART_LCR, 0); 553 554 uart_port_unlock_irq(port); 555 556 pm_runtime_mark_last_busy(port->dev); 557 pm_runtime_put_autosuspend(port->dev); 558 } 559 560 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 561 struct omap8250_priv *priv) 562 { 563 static const struct soc_device_attribute k3_soc_devices[] = { 564 { .family = "AM65X", }, 565 { .family = "J721E", .revision = "SR1.0" }, 566 { /* sentinel */ } 567 }; 568 u32 mvr, scheme; 569 u16 revision, major, minor; 570 571 mvr = uart_read(priv, UART_OMAP_MVER); 572 573 /* Check revision register scheme */ 574 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 575 576 switch (scheme) { 577 case 0: /* Legacy Scheme: OMAP2/3 */ 578 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 579 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 580 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 581 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 582 break; 583 case 1: 584 /* New Scheme: OMAP4+ */ 585 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 586 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 587 OMAP_UART_MVR_MAJ_SHIFT; 588 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 589 break; 590 default: 591 dev_warn(up->port.dev, 592 "Unknown revision, defaulting to highest\n"); 593 /* highest possible revision */ 594 major = 0xff; 595 minor = 0xff; 596 } 597 /* normalize revision for the driver */ 598 revision = UART_BUILD_REVISION(major, minor); 599 600 switch (revision) { 601 case OMAP_UART_REV_46: 602 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 603 break; 604 case OMAP_UART_REV_52: 605 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 606 OMAP_UART_WER_HAS_TX_WAKEUP; 607 break; 608 case OMAP_UART_REV_63: 609 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 610 OMAP_UART_WER_HAS_TX_WAKEUP; 611 break; 612 default: 613 break; 614 } 615 616 /* 617 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 618 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 619 * to enable errata workaround. 620 */ 621 if (soc_device_match(k3_soc_devices)) 622 priv->habit &= ~UART_HAS_RHR_IT_DIS; 623 } 624 625 static void omap8250_uart_qos_work(struct work_struct *work) 626 { 627 struct omap8250_priv *priv; 628 629 priv = container_of(work, struct omap8250_priv, qos_work); 630 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 631 } 632 633 #ifdef CONFIG_SERIAL_8250_DMA 634 static int omap_8250_dma_handle_irq(struct uart_port *port); 635 #endif 636 637 static irqreturn_t omap8250_irq(int irq, void *dev_id) 638 { 639 struct omap8250_priv *priv = dev_id; 640 struct uart_8250_port *up = serial8250_get_port(priv->line); 641 struct uart_port *port = &up->port; 642 unsigned int iir, lsr; 643 int ret; 644 645 pm_runtime_get_noresume(port->dev); 646 647 /* Shallow idle state wake-up to an IO interrupt? */ 648 if (atomic_add_unless(&priv->active, 1, 1)) { 649 priv->latency = priv->calc_latency; 650 schedule_work(&priv->qos_work); 651 } 652 653 #ifdef CONFIG_SERIAL_8250_DMA 654 if (up->dma) { 655 ret = omap_8250_dma_handle_irq(port); 656 pm_runtime_mark_last_busy(port->dev); 657 pm_runtime_put(port->dev); 658 return IRQ_RETVAL(ret); 659 } 660 #endif 661 662 lsr = serial_port_in(port, UART_LSR); 663 iir = serial_port_in(port, UART_IIR); 664 ret = serial8250_handle_irq(port, iir); 665 666 /* 667 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 668 * FIFO has been drained or erroneously. 669 * So apply solution of Errata i2310 as mentioned in 670 * https://www.ti.com/lit/pdf/sprz536 671 */ 672 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 673 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 674 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 675 unsigned char efr2, timeout_h, timeout_l; 676 677 efr2 = serial_in(up, UART_OMAP_EFR2); 678 timeout_h = serial_in(up, UART_OMAP_TO_H); 679 timeout_l = serial_in(up, UART_OMAP_TO_L); 680 serial_out(up, UART_OMAP_TO_H, 0xFF); 681 serial_out(up, UART_OMAP_TO_L, 0xFF); 682 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 683 serial_in(up, UART_IIR); 684 serial_out(up, UART_OMAP_EFR2, efr2); 685 serial_out(up, UART_OMAP_TO_H, timeout_h); 686 serial_out(up, UART_OMAP_TO_L, timeout_l); 687 } 688 689 /* Stop processing interrupts on input overrun */ 690 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 691 unsigned long delay; 692 693 /* Synchronize UART_IER access against the console. */ 694 uart_port_lock(port); 695 up->ier = serial_port_in(port, UART_IER); 696 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 697 port->ops->stop_rx(port); 698 } else { 699 /* Keep restarting the timer until 700 * the input overrun subsides. 701 */ 702 cancel_delayed_work(&up->overrun_backoff); 703 } 704 uart_port_unlock(port); 705 706 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 707 schedule_delayed_work(&up->overrun_backoff, delay); 708 } 709 710 pm_runtime_mark_last_busy(port->dev); 711 pm_runtime_put(port->dev); 712 713 return IRQ_RETVAL(ret); 714 } 715 716 static int omap_8250_startup(struct uart_port *port) 717 { 718 struct uart_8250_port *up = up_to_u8250p(port); 719 struct omap8250_priv *priv = port->private_data; 720 struct uart_8250_dma *dma = &priv->omap8250_dma; 721 int ret; 722 723 if (priv->wakeirq) { 724 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 725 if (ret) 726 return ret; 727 } 728 729 pm_runtime_get_sync(port->dev); 730 731 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 732 733 serial_out(up, UART_LCR, UART_LCR_WLEN8); 734 735 up->lsr_saved_flags = 0; 736 up->msr_saved_flags = 0; 737 738 /* Disable DMA for console UART */ 739 if (dma->fn && !uart_console(port)) { 740 up->dma = &priv->omap8250_dma; 741 ret = serial8250_request_dma(up); 742 if (ret) { 743 dev_warn_ratelimited(port->dev, 744 "failed to request DMA\n"); 745 up->dma = NULL; 746 } 747 } else { 748 up->dma = NULL; 749 } 750 751 /* Synchronize UART_IER access against the console. */ 752 uart_port_lock_irq(port); 753 up->ier = UART_IER_RLSI | UART_IER_RDI; 754 serial_out(up, UART_IER, up->ier); 755 uart_port_unlock_irq(port); 756 757 #ifdef CONFIG_PM 758 up->capabilities |= UART_CAP_RPM; 759 #endif 760 761 /* Enable module level wake up */ 762 priv->wer = OMAP_UART_WER_MOD_WKUP; 763 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 764 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 765 serial_out(up, UART_OMAP_WER, priv->wer); 766 767 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 768 uart_port_lock_irq(port); 769 up->dma->rx_dma(up); 770 uart_port_unlock_irq(port); 771 } 772 773 enable_irq(up->port.irq); 774 775 pm_runtime_mark_last_busy(port->dev); 776 pm_runtime_put_autosuspend(port->dev); 777 return 0; 778 } 779 780 static void omap_8250_shutdown(struct uart_port *port) 781 { 782 struct uart_8250_port *up = up_to_u8250p(port); 783 struct omap8250_priv *priv = port->private_data; 784 785 pm_runtime_get_sync(port->dev); 786 787 flush_work(&priv->qos_work); 788 if (up->dma) 789 omap_8250_rx_dma_flush(up); 790 791 serial_out(up, UART_OMAP_WER, 0); 792 if (priv->habit & UART_HAS_EFR2) 793 serial_out(up, UART_OMAP_EFR2, 0x0); 794 795 /* Synchronize UART_IER access against the console. */ 796 uart_port_lock_irq(port); 797 up->ier = 0; 798 serial_out(up, UART_IER, 0); 799 uart_port_unlock_irq(port); 800 disable_irq_nosync(up->port.irq); 801 dev_pm_clear_wake_irq(port->dev); 802 803 serial8250_release_dma(up); 804 up->dma = NULL; 805 806 /* 807 * Disable break condition and FIFOs 808 */ 809 if (up->lcr & UART_LCR_SBC) 810 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 811 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 812 813 pm_runtime_mark_last_busy(port->dev); 814 pm_runtime_put_autosuspend(port->dev); 815 } 816 817 static void omap_8250_throttle(struct uart_port *port) 818 { 819 struct omap8250_priv *priv = port->private_data; 820 unsigned long flags; 821 822 pm_runtime_get_sync(port->dev); 823 824 uart_port_lock_irqsave(port, &flags); 825 port->ops->stop_rx(port); 826 priv->throttled = true; 827 uart_port_unlock_irqrestore(port, flags); 828 829 pm_runtime_mark_last_busy(port->dev); 830 pm_runtime_put_autosuspend(port->dev); 831 } 832 833 static void omap_8250_unthrottle(struct uart_port *port) 834 { 835 struct omap8250_priv *priv = port->private_data; 836 struct uart_8250_port *up = up_to_u8250p(port); 837 unsigned long flags; 838 839 pm_runtime_get_sync(port->dev); 840 841 /* Synchronize UART_IER access against the console. */ 842 uart_port_lock_irqsave(port, &flags); 843 priv->throttled = false; 844 if (up->dma) 845 up->dma->rx_dma(up); 846 up->ier |= UART_IER_RLSI | UART_IER_RDI; 847 serial_out(up, UART_IER, up->ier); 848 uart_port_unlock_irqrestore(port, flags); 849 850 pm_runtime_mark_last_busy(port->dev); 851 pm_runtime_put_autosuspend(port->dev); 852 } 853 854 static int omap8250_rs485_config(struct uart_port *port, 855 struct ktermios *termios, 856 struct serial_rs485 *rs485) 857 { 858 struct omap8250_priv *priv = port->private_data; 859 struct uart_8250_port *up = up_to_u8250p(port); 860 u32 fixed_delay_rts_before_send = 0; 861 u32 fixed_delay_rts_after_send = 0; 862 unsigned int baud; 863 864 /* 865 * There is a fixed delay of 3 bit clock cycles after the TX shift 866 * register is going empty to allow time for the stop bit to transition 867 * through the transceiver before direction is changed to receive. 868 * 869 * Additionally there appears to be a 1 bit clock delay between writing 870 * to the THR register and transmission of the start bit, per page 8783 871 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 872 */ 873 if (priv->quot) { 874 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 875 baud = port->uartclk / (16 * priv->quot); 876 else 877 baud = port->uartclk / (13 * priv->quot); 878 879 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 880 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 881 } 882 883 /* 884 * Fall back to RS485 software emulation if the UART is missing 885 * hardware support, if the device tree specifies an mctrl_gpio 886 * (indicates that RTS is unavailable due to a pinmux conflict) 887 * or if the requested delays exceed the fixed hardware delays. 888 */ 889 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 890 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 891 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 892 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 893 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 894 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 895 896 port->rs485_config = serial8250_em485_config; 897 return serial8250_em485_config(port, termios, rs485); 898 } 899 900 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 901 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 902 903 if (rs485->flags & SER_RS485_ENABLED) 904 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 905 else 906 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 907 908 /* 909 * Retain same polarity semantics as RS485 software emulation, 910 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 911 */ 912 if (rs485->flags & SER_RS485_RTS_ON_SEND) 913 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 914 else 915 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 916 917 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 918 919 return 0; 920 } 921 922 #ifdef CONFIG_SERIAL_8250_DMA 923 static int omap_8250_rx_dma(struct uart_8250_port *p); 924 925 /* Must be called while priv->rx_dma_lock is held */ 926 static void __dma_rx_do_complete(struct uart_8250_port *p) 927 { 928 struct uart_8250_dma *dma = p->dma; 929 struct tty_port *tty_port = &p->port.state->port; 930 struct omap8250_priv *priv = p->port.private_data; 931 struct dma_chan *rxchan = dma->rxchan; 932 dma_cookie_t cookie; 933 struct dma_tx_state state; 934 int count; 935 int ret; 936 u32 reg; 937 938 if (!dma->rx_running) 939 goto out; 940 941 cookie = dma->rx_cookie; 942 dma->rx_running = 0; 943 944 /* Re-enable RX FIFO interrupt now that transfer is complete */ 945 if (priv->habit & UART_HAS_RHR_IT_DIS) { 946 reg = serial_in(p, UART_OMAP_IER2); 947 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 948 serial_out(p, UART_OMAP_IER2, reg); 949 } 950 951 dmaengine_tx_status(rxchan, cookie, &state); 952 953 count = dma->rx_size - state.residue + state.in_flight_bytes; 954 if (count < dma->rx_size) { 955 dmaengine_terminate_async(rxchan); 956 957 /* 958 * Poll for teardown to complete which guarantees in 959 * flight data is drained. 960 */ 961 if (state.in_flight_bytes) { 962 int poll_count = 25; 963 964 while (dmaengine_tx_status(rxchan, cookie, NULL) && 965 poll_count--) 966 cpu_relax(); 967 968 if (poll_count == -1) 969 dev_err(p->port.dev, "teardown incomplete\n"); 970 } 971 } 972 if (!count) 973 goto out; 974 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 975 976 p->port.icount.rx += ret; 977 p->port.icount.buf_overrun += count - ret; 978 out: 979 980 tty_flip_buffer_push(tty_port); 981 } 982 983 static void __dma_rx_complete(void *param) 984 { 985 struct uart_8250_port *p = param; 986 struct omap8250_priv *priv = p->port.private_data; 987 struct uart_8250_dma *dma = p->dma; 988 struct dma_tx_state state; 989 unsigned long flags; 990 991 /* Synchronize UART_IER access against the console. */ 992 uart_port_lock_irqsave(&p->port, &flags); 993 994 /* 995 * If the tx status is not DMA_COMPLETE, then this is a delayed 996 * completion callback. A previous RX timeout flush would have 997 * already pushed the data, so exit. 998 */ 999 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 1000 DMA_COMPLETE) { 1001 uart_port_unlock_irqrestore(&p->port, flags); 1002 return; 1003 } 1004 __dma_rx_do_complete(p); 1005 if (!priv->throttled) { 1006 p->ier |= UART_IER_RLSI | UART_IER_RDI; 1007 serial_out(p, UART_IER, p->ier); 1008 if (!(priv->habit & UART_HAS_EFR2)) 1009 omap_8250_rx_dma(p); 1010 } 1011 1012 uart_port_unlock_irqrestore(&p->port, flags); 1013 } 1014 1015 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 1016 { 1017 struct omap8250_priv *priv = p->port.private_data; 1018 struct uart_8250_dma *dma = p->dma; 1019 struct dma_tx_state state; 1020 unsigned long flags; 1021 int ret; 1022 1023 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1024 1025 if (!dma->rx_running) { 1026 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1027 return; 1028 } 1029 1030 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1031 if (ret == DMA_IN_PROGRESS) { 1032 ret = dmaengine_pause(dma->rxchan); 1033 if (WARN_ON_ONCE(ret)) 1034 priv->rx_dma_broken = true; 1035 } 1036 __dma_rx_do_complete(p); 1037 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1038 } 1039 1040 static int omap_8250_rx_dma(struct uart_8250_port *p) 1041 { 1042 struct omap8250_priv *priv = p->port.private_data; 1043 struct uart_8250_dma *dma = p->dma; 1044 int err = 0; 1045 struct dma_async_tx_descriptor *desc; 1046 unsigned long flags; 1047 u32 reg; 1048 1049 /* Port locked to synchronize UART_IER access against the console. */ 1050 lockdep_assert_held_once(&p->port.lock); 1051 1052 if (priv->rx_dma_broken) 1053 return -EINVAL; 1054 1055 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1056 1057 if (dma->rx_running) { 1058 enum dma_status state; 1059 1060 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1061 if (state == DMA_COMPLETE) { 1062 /* 1063 * Disable RX interrupts to allow RX DMA completion 1064 * callback to run. 1065 */ 1066 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1067 serial_out(p, UART_IER, p->ier); 1068 } 1069 goto out; 1070 } 1071 1072 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1073 dma->rx_size, DMA_DEV_TO_MEM, 1074 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1075 if (!desc) { 1076 err = -EBUSY; 1077 goto out; 1078 } 1079 1080 dma->rx_running = 1; 1081 desc->callback = __dma_rx_complete; 1082 desc->callback_param = p; 1083 1084 dma->rx_cookie = dmaengine_submit(desc); 1085 1086 /* 1087 * Disable RX FIFO interrupt while RX DMA is enabled, else 1088 * spurious interrupt may be raised when data is in the RX FIFO 1089 * but is yet to be drained by DMA. 1090 */ 1091 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1092 reg = serial_in(p, UART_OMAP_IER2); 1093 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1094 serial_out(p, UART_OMAP_IER2, reg); 1095 } 1096 1097 dma_async_issue_pending(dma->rxchan); 1098 out: 1099 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1100 return err; 1101 } 1102 1103 static int omap_8250_tx_dma(struct uart_8250_port *p); 1104 1105 static void omap_8250_dma_tx_complete(void *param) 1106 { 1107 struct uart_8250_port *p = param; 1108 struct uart_8250_dma *dma = p->dma; 1109 struct tty_port *tport = &p->port.state->port; 1110 unsigned long flags; 1111 bool en_thri = false; 1112 struct omap8250_priv *priv = p->port.private_data; 1113 1114 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1115 UART_XMIT_SIZE, DMA_TO_DEVICE); 1116 1117 uart_port_lock_irqsave(&p->port, &flags); 1118 1119 dma->tx_running = 0; 1120 1121 uart_xmit_advance(&p->port, dma->tx_size); 1122 1123 if (priv->delayed_restore) { 1124 priv->delayed_restore = 0; 1125 omap8250_restore_regs(p); 1126 } 1127 1128 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1129 uart_write_wakeup(&p->port); 1130 1131 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1132 int ret; 1133 1134 ret = omap_8250_tx_dma(p); 1135 if (ret) 1136 en_thri = true; 1137 } else if (p->capabilities & UART_CAP_RPM) { 1138 en_thri = true; 1139 } 1140 1141 if (en_thri) { 1142 dma->tx_err = 1; 1143 serial8250_set_THRI(p); 1144 } 1145 1146 uart_port_unlock_irqrestore(&p->port, flags); 1147 } 1148 1149 static int omap_8250_tx_dma(struct uart_8250_port *p) 1150 { 1151 struct uart_8250_dma *dma = p->dma; 1152 struct omap8250_priv *priv = p->port.private_data; 1153 struct tty_port *tport = &p->port.state->port; 1154 struct dma_async_tx_descriptor *desc; 1155 struct scatterlist sg; 1156 int skip_byte = -1; 1157 int ret; 1158 1159 if (dma->tx_running) 1160 return 0; 1161 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1162 1163 /* 1164 * Even if no data, we need to return an error for the two cases 1165 * below so serial8250_tx_chars() is invoked and properly clears 1166 * THRI and/or runtime suspend. 1167 */ 1168 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1169 ret = -EBUSY; 1170 goto err; 1171 } 1172 serial8250_clear_THRI(p); 1173 return 0; 1174 } 1175 1176 sg_init_table(&sg, 1); 1177 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1178 UART_XMIT_SIZE, dma->tx_addr); 1179 if (ret != 1) { 1180 serial8250_clear_THRI(p); 1181 return 0; 1182 } 1183 1184 dma->tx_size = sg_dma_len(&sg); 1185 1186 if (priv->habit & OMAP_DMA_TX_KICK) { 1187 unsigned char c; 1188 u8 tx_lvl; 1189 1190 /* 1191 * We need to put the first byte into the FIFO in order to start 1192 * the DMA transfer. For transfers smaller than four bytes we 1193 * don't bother doing DMA at all. It seem not matter if there 1194 * are still bytes in the FIFO from the last transfer (in case 1195 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1196 * leaving the FIFO seem not to trigger the DMA transfer. It is 1197 * really the byte that we put into the FIFO. 1198 * If the FIFO is already full then we most likely got here from 1199 * omap_8250_dma_tx_complete(). And this means the DMA engine 1200 * just completed its work. We don't have to wait the complete 1201 * 86us at 115200,8n1 but around 60us (not to mention lower 1202 * baudrates). So in that case we take the interrupt and try 1203 * again with an empty FIFO. 1204 */ 1205 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1206 if (tx_lvl == p->tx_loadsz) { 1207 ret = -EBUSY; 1208 goto err; 1209 } 1210 if (dma->tx_size < 4) { 1211 ret = -EINVAL; 1212 goto err; 1213 } 1214 if (!kfifo_get(&tport->xmit_fifo, &c)) { 1215 ret = -EINVAL; 1216 goto err; 1217 } 1218 skip_byte = c; 1219 /* now we need to recompute due to kfifo_get */ 1220 kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1221 UART_XMIT_SIZE, dma->tx_addr); 1222 } 1223 1224 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1225 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1226 if (!desc) { 1227 ret = -EBUSY; 1228 goto err; 1229 } 1230 1231 dma->tx_running = 1; 1232 1233 desc->callback = omap_8250_dma_tx_complete; 1234 desc->callback_param = p; 1235 1236 dma->tx_cookie = dmaengine_submit(desc); 1237 1238 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1239 UART_XMIT_SIZE, DMA_TO_DEVICE); 1240 1241 dma_async_issue_pending(dma->txchan); 1242 if (dma->tx_err) 1243 dma->tx_err = 0; 1244 1245 serial8250_clear_THRI(p); 1246 ret = 0; 1247 goto out_skip; 1248 err: 1249 dma->tx_err = 1; 1250 out_skip: 1251 if (skip_byte >= 0) 1252 serial_out(p, UART_TX, skip_byte); 1253 return ret; 1254 } 1255 1256 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1257 { 1258 switch (iir & 0x3f) { 1259 case UART_IIR_RLSI: 1260 case UART_IIR_RX_TIMEOUT: 1261 case UART_IIR_RDI: 1262 omap_8250_rx_dma_flush(up); 1263 return true; 1264 } 1265 return omap_8250_rx_dma(up); 1266 } 1267 1268 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1269 { 1270 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1271 (iir & UART_IIR_RDI)) { 1272 if (handle_rx_dma(up, iir)) { 1273 status = serial8250_rx_chars(up, status); 1274 omap_8250_rx_dma(up); 1275 } 1276 } 1277 1278 return status; 1279 } 1280 1281 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1282 u16 status) 1283 { 1284 /* Port locked to synchronize UART_IER access against the console. */ 1285 lockdep_assert_held_once(&up->port.lock); 1286 1287 /* 1288 * Queue a new transfer if FIFO has data. 1289 */ 1290 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1291 (up->ier & UART_IER_RDI)) { 1292 omap_8250_rx_dma(up); 1293 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1294 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1295 /* 1296 * Disable RX timeout, read IIR to clear 1297 * current timeout condition, clear EFR2 to 1298 * periodic timeouts, re-enable interrupts. 1299 */ 1300 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1301 serial_out(up, UART_IER, up->ier); 1302 omap_8250_rx_dma_flush(up); 1303 serial_in(up, UART_IIR); 1304 serial_out(up, UART_OMAP_EFR2, 0x0); 1305 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1306 serial_out(up, UART_IER, up->ier); 1307 } 1308 } 1309 1310 /* 1311 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1312 * hook for RX/TX and need different logic for them in the ISR. Therefore we 1313 * use the default routine in the non-DMA case and this one for with DMA. 1314 */ 1315 static int omap_8250_dma_handle_irq(struct uart_port *port) 1316 { 1317 struct uart_8250_port *up = up_to_u8250p(port); 1318 struct omap8250_priv *priv = up->port.private_data; 1319 u16 status; 1320 u8 iir; 1321 1322 iir = serial_port_in(port, UART_IIR); 1323 if (iir & UART_IIR_NO_INT) { 1324 return IRQ_HANDLED; 1325 } 1326 1327 uart_port_lock(port); 1328 1329 status = serial_port_in(port, UART_LSR); 1330 1331 if ((iir & 0x3f) != UART_IIR_THRI) { 1332 if (priv->habit & UART_HAS_EFR2) 1333 am654_8250_handle_rx_dma(up, iir, status); 1334 else 1335 status = omap_8250_handle_rx_dma(up, iir, status); 1336 } 1337 1338 serial8250_modem_status(up); 1339 if (status & UART_LSR_THRE && up->dma->tx_err) { 1340 if (uart_tx_stopped(&up->port) || 1341 kfifo_is_empty(&up->port.state->port.xmit_fifo)) { 1342 up->dma->tx_err = 0; 1343 serial8250_tx_chars(up); 1344 } else { 1345 /* 1346 * try again due to an earlier failure which 1347 * might have been resolved by now. 1348 */ 1349 if (omap_8250_tx_dma(up)) 1350 serial8250_tx_chars(up); 1351 } 1352 } 1353 1354 uart_unlock_and_check_sysrq(port); 1355 1356 return 1; 1357 } 1358 1359 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1360 { 1361 return false; 1362 } 1363 1364 #else 1365 1366 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1367 { 1368 return -EINVAL; 1369 } 1370 #endif 1371 1372 static int omap8250_no_handle_irq(struct uart_port *port) 1373 { 1374 /* IRQ has not been requested but handling irq? */ 1375 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1376 return 0; 1377 } 1378 1379 static struct omap8250_dma_params am654_dma = { 1380 .rx_size = SZ_2K, 1381 .rx_trigger = 1, 1382 .tx_trigger = TX_TRIGGER, 1383 }; 1384 1385 static struct omap8250_dma_params am33xx_dma = { 1386 .rx_size = RX_TRIGGER, 1387 .rx_trigger = RX_TRIGGER, 1388 .tx_trigger = TX_TRIGGER, 1389 }; 1390 1391 static struct omap8250_platdata am654_platdata = { 1392 .dma_params = &am654_dma, 1393 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1394 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1395 }; 1396 1397 static struct omap8250_platdata am33xx_platdata = { 1398 .dma_params = &am33xx_dma, 1399 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1400 }; 1401 1402 static struct omap8250_platdata omap4_platdata = { 1403 .dma_params = &am33xx_dma, 1404 .habit = UART_ERRATA_CLOCK_DISABLE, 1405 }; 1406 1407 static const struct of_device_id omap8250_dt_ids[] = { 1408 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1409 { .compatible = "ti,omap2-uart" }, 1410 { .compatible = "ti,omap3-uart" }, 1411 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1412 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1413 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1414 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1415 {}, 1416 }; 1417 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1418 1419 static int omap8250_probe(struct platform_device *pdev) 1420 { 1421 struct device_node *np = pdev->dev.of_node; 1422 struct omap8250_priv *priv; 1423 const struct omap8250_platdata *pdata; 1424 struct uart_8250_port up; 1425 struct resource *regs; 1426 void __iomem *membase; 1427 int ret; 1428 1429 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1430 if (!regs) { 1431 dev_err(&pdev->dev, "missing registers\n"); 1432 return -EINVAL; 1433 } 1434 1435 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1436 if (!priv) 1437 return -ENOMEM; 1438 1439 membase = devm_ioremap(&pdev->dev, regs->start, 1440 resource_size(regs)); 1441 if (!membase) 1442 return -ENODEV; 1443 1444 memset(&up, 0, sizeof(up)); 1445 up.port.dev = &pdev->dev; 1446 up.port.mapbase = regs->start; 1447 up.port.membase = membase; 1448 /* 1449 * It claims to be 16C750 compatible however it is a little different. 1450 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1451 * have) is enabled via EFR instead of MCR. The type is set here 8250 1452 * just to get things going. UNKNOWN does not work for a few reasons and 1453 * we don't need our own type since we don't use 8250's set_termios() 1454 * or pm callback. 1455 */ 1456 up.port.type = PORT_8250; 1457 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1458 up.port.private_data = priv; 1459 1460 up.tx_loadsz = 64; 1461 up.capabilities = UART_CAP_FIFO; 1462 #ifdef CONFIG_PM 1463 /* 1464 * Runtime PM is mostly transparent. However to do it right we need to a 1465 * TX empty interrupt before we can put the device to auto idle. So if 1466 * PM is not enabled we don't add that flag and can spare that one extra 1467 * interrupt in the TX path. 1468 */ 1469 up.capabilities |= UART_CAP_RPM; 1470 #endif 1471 up.port.set_termios = omap_8250_set_termios; 1472 up.port.set_mctrl = omap8250_set_mctrl; 1473 up.port.pm = omap_8250_pm; 1474 up.port.startup = omap_8250_startup; 1475 up.port.shutdown = omap_8250_shutdown; 1476 up.port.throttle = omap_8250_throttle; 1477 up.port.unthrottle = omap_8250_unthrottle; 1478 up.port.rs485_config = omap8250_rs485_config; 1479 /* same rs485_supported for software emulation and native RS485 */ 1480 up.port.rs485_supported = serial8250_em485_supported; 1481 up.rs485_start_tx = serial8250_em485_start_tx; 1482 up.rs485_stop_tx = serial8250_em485_stop_tx; 1483 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1484 1485 ret = uart_read_port_properties(&up.port); 1486 if (ret) 1487 return ret; 1488 1489 up.port.regshift = OMAP_UART_REGSHIFT; 1490 up.port.fifosize = 64; 1491 1492 if (!up.port.uartclk) { 1493 struct clk *clk; 1494 1495 clk = devm_clk_get(&pdev->dev, NULL); 1496 if (IS_ERR(clk)) { 1497 if (PTR_ERR(clk) == -EPROBE_DEFER) 1498 return -EPROBE_DEFER; 1499 } else { 1500 up.port.uartclk = clk_get_rate(clk); 1501 } 1502 } 1503 1504 if (of_property_read_u32(np, "overrun-throttle-ms", 1505 &up.overrun_backoff_time_ms) != 0) 1506 up.overrun_backoff_time_ms = 0; 1507 1508 pdata = of_device_get_match_data(&pdev->dev); 1509 if (pdata) 1510 priv->habit |= pdata->habit; 1511 1512 if (!up.port.uartclk) { 1513 up.port.uartclk = DEFAULT_CLK_SPEED; 1514 dev_warn(&pdev->dev, 1515 "No clock speed specified: using default: %d\n", 1516 DEFAULT_CLK_SPEED); 1517 } 1518 1519 priv->membase = membase; 1520 priv->line = -ENODEV; 1521 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1522 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1523 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1524 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1525 1526 spin_lock_init(&priv->rx_dma_lock); 1527 1528 platform_set_drvdata(pdev, priv); 1529 1530 device_set_wakeup_capable(&pdev->dev, true); 1531 if (of_property_read_bool(np, "wakeup-source")) 1532 device_set_wakeup_enable(&pdev->dev, true); 1533 1534 pm_runtime_enable(&pdev->dev); 1535 pm_runtime_use_autosuspend(&pdev->dev); 1536 1537 /* 1538 * Disable runtime PM until autosuspend delay unless specifically 1539 * enabled by the user via sysfs. This is the historic way to 1540 * prevent an unsafe default policy with lossy characters on wake-up. 1541 * For serdev devices this is not needed, the policy can be managed by 1542 * the serdev driver. 1543 */ 1544 if (!of_get_available_child_count(pdev->dev.of_node)) 1545 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1546 1547 pm_runtime_get_sync(&pdev->dev); 1548 1549 omap_serial_fill_features_erratas(&up, priv); 1550 up.port.handle_irq = omap8250_no_handle_irq; 1551 priv->rx_trigger = RX_TRIGGER; 1552 priv->tx_trigger = TX_TRIGGER; 1553 #ifdef CONFIG_SERIAL_8250_DMA 1554 /* 1555 * Oh DMA support. If there are no DMA properties in the DT then 1556 * we will fall back to a generic DMA channel which does not 1557 * really work here. To ensure that we do not get a generic DMA 1558 * channel assigned, we have the the_no_dma_filter_fn() here. 1559 * To avoid "failed to request DMA" messages we check for DMA 1560 * properties in DT. 1561 */ 1562 ret = of_property_count_strings(np, "dma-names"); 1563 if (ret == 2) { 1564 struct omap8250_dma_params *dma_params = NULL; 1565 struct uart_8250_dma *dma = &priv->omap8250_dma; 1566 1567 dma->fn = the_no_dma_filter_fn; 1568 dma->tx_dma = omap_8250_tx_dma; 1569 dma->rx_dma = omap_8250_rx_dma; 1570 if (pdata) 1571 dma_params = pdata->dma_params; 1572 1573 if (dma_params) { 1574 dma->rx_size = dma_params->rx_size; 1575 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1576 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1577 priv->rx_trigger = dma_params->rx_trigger; 1578 priv->tx_trigger = dma_params->tx_trigger; 1579 } else { 1580 dma->rx_size = RX_TRIGGER; 1581 dma->rxconf.src_maxburst = RX_TRIGGER; 1582 dma->txconf.dst_maxburst = TX_TRIGGER; 1583 } 1584 } 1585 #endif 1586 1587 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1588 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1589 dev_name(&pdev->dev), priv); 1590 if (ret < 0) 1591 goto err; 1592 1593 priv->wakeirq = irq_of_parse_and_map(np, 1); 1594 1595 ret = serial8250_register_8250_port(&up); 1596 if (ret < 0) { 1597 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1598 goto err; 1599 } 1600 priv->line = ret; 1601 pm_runtime_mark_last_busy(&pdev->dev); 1602 pm_runtime_put_autosuspend(&pdev->dev); 1603 return 0; 1604 err: 1605 pm_runtime_dont_use_autosuspend(&pdev->dev); 1606 pm_runtime_put_sync(&pdev->dev); 1607 flush_work(&priv->qos_work); 1608 pm_runtime_disable(&pdev->dev); 1609 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1610 return ret; 1611 } 1612 1613 static void omap8250_remove(struct platform_device *pdev) 1614 { 1615 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1616 struct uart_8250_port *up; 1617 int err; 1618 1619 err = pm_runtime_resume_and_get(&pdev->dev); 1620 if (err) 1621 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1622 1623 up = serial8250_get_port(priv->line); 1624 omap_8250_shutdown(&up->port); 1625 serial8250_unregister_port(priv->line); 1626 priv->line = -ENODEV; 1627 pm_runtime_dont_use_autosuspend(&pdev->dev); 1628 pm_runtime_put_sync(&pdev->dev); 1629 flush_work(&priv->qos_work); 1630 pm_runtime_disable(&pdev->dev); 1631 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1632 device_set_wakeup_capable(&pdev->dev, false); 1633 } 1634 1635 static int omap8250_prepare(struct device *dev) 1636 { 1637 struct omap8250_priv *priv = dev_get_drvdata(dev); 1638 1639 if (!priv) 1640 return 0; 1641 priv->is_suspending = true; 1642 return 0; 1643 } 1644 1645 static void omap8250_complete(struct device *dev) 1646 { 1647 struct omap8250_priv *priv = dev_get_drvdata(dev); 1648 1649 if (!priv) 1650 return; 1651 priv->is_suspending = false; 1652 } 1653 1654 static int omap8250_suspend(struct device *dev) 1655 { 1656 struct omap8250_priv *priv = dev_get_drvdata(dev); 1657 struct uart_8250_port *up = serial8250_get_port(priv->line); 1658 int err = 0; 1659 1660 serial8250_suspend_port(priv->line); 1661 1662 err = pm_runtime_resume_and_get(dev); 1663 if (err) 1664 return err; 1665 if (!device_may_wakeup(dev)) 1666 priv->wer = 0; 1667 serial_out(up, UART_OMAP_WER, priv->wer); 1668 if (uart_console(&up->port) && console_suspend_enabled) 1669 err = pm_runtime_force_suspend(dev); 1670 flush_work(&priv->qos_work); 1671 1672 return err; 1673 } 1674 1675 static int omap8250_resume(struct device *dev) 1676 { 1677 struct omap8250_priv *priv = dev_get_drvdata(dev); 1678 struct uart_8250_port *up = serial8250_get_port(priv->line); 1679 int err; 1680 1681 if (uart_console(&up->port) && console_suspend_enabled) { 1682 err = pm_runtime_force_resume(dev); 1683 if (err) 1684 return err; 1685 } 1686 1687 serial8250_resume_port(priv->line); 1688 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1689 pm_runtime_mark_last_busy(dev); 1690 pm_runtime_put_autosuspend(dev); 1691 1692 return 0; 1693 } 1694 1695 static int omap8250_lost_context(struct uart_8250_port *up) 1696 { 1697 u32 val; 1698 1699 val = serial_in(up, UART_OMAP_SCR); 1700 /* 1701 * If we lose context, then SCR is set to its reset value of zero. 1702 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1703 * among other bits, to never set the register back to zero again. 1704 */ 1705 if (!val) 1706 return 1; 1707 return 0; 1708 } 1709 1710 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1711 { 1712 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1713 } 1714 1715 /* TODO: in future, this should happen via API in drivers/reset/ */ 1716 static int omap8250_soft_reset(struct device *dev) 1717 { 1718 struct omap8250_priv *priv = dev_get_drvdata(dev); 1719 int timeout = 100; 1720 int sysc; 1721 int syss; 1722 1723 /* 1724 * At least on omap4, unused uarts may not idle after reset without 1725 * a basic scr dma configuration even with no dma in use. The 1726 * module clkctrl status bits will be 1 instead of 3 blocking idle 1727 * for the whole clockdomain. The softreset below will clear scr, 1728 * and we restore it on resume so this is safe to do on all SoCs 1729 * needing omap8250_soft_reset() quirk. Do it in two writes as 1730 * recommended in the comment for omap8250_update_scr(). 1731 */ 1732 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1733 uart_write(priv, UART_OMAP_SCR, 1734 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1735 1736 sysc = uart_read(priv, UART_OMAP_SYSC); 1737 1738 /* softreset the UART */ 1739 sysc |= OMAP_UART_SYSC_SOFTRESET; 1740 uart_write(priv, UART_OMAP_SYSC, sysc); 1741 1742 /* By experiments, 1us enough for reset complete on AM335x */ 1743 do { 1744 udelay(1); 1745 syss = uart_read(priv, UART_OMAP_SYSS); 1746 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1747 1748 if (!timeout) { 1749 dev_err(dev, "timed out waiting for reset done\n"); 1750 return -ETIMEDOUT; 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int omap8250_runtime_suspend(struct device *dev) 1757 { 1758 struct omap8250_priv *priv = dev_get_drvdata(dev); 1759 struct uart_8250_port *up = NULL; 1760 1761 if (priv->line >= 0) 1762 up = serial8250_get_port(priv->line); 1763 1764 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1765 int ret; 1766 1767 ret = omap8250_soft_reset(dev); 1768 if (ret) 1769 return ret; 1770 1771 if (up) { 1772 /* Restore to UART mode after reset (for wakeup) */ 1773 omap8250_update_mdr1(up, priv); 1774 /* Restore wakeup enable register */ 1775 serial_out(up, UART_OMAP_WER, priv->wer); 1776 } 1777 } 1778 1779 if (up && up->dma && up->dma->rxchan) 1780 omap_8250_rx_dma_flush(up); 1781 1782 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1783 schedule_work(&priv->qos_work); 1784 atomic_set(&priv->active, 0); 1785 1786 return 0; 1787 } 1788 1789 static int omap8250_runtime_resume(struct device *dev) 1790 { 1791 struct omap8250_priv *priv = dev_get_drvdata(dev); 1792 struct uart_8250_port *up = NULL; 1793 1794 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1795 if (atomic_read(&priv->active)) 1796 return 0; 1797 1798 if (priv->line >= 0) 1799 up = serial8250_get_port(priv->line); 1800 1801 if (up && omap8250_lost_context(up)) { 1802 uart_port_lock_irq(&up->port); 1803 omap8250_restore_regs(up); 1804 uart_port_unlock_irq(&up->port); 1805 } 1806 1807 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1808 uart_port_lock_irq(&up->port); 1809 omap_8250_rx_dma(up); 1810 uart_port_unlock_irq(&up->port); 1811 } 1812 1813 atomic_set(&priv->active, 1); 1814 priv->latency = priv->calc_latency; 1815 schedule_work(&priv->qos_work); 1816 1817 return 0; 1818 } 1819 1820 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1821 static int __init omap8250_console_fixup(void) 1822 { 1823 char *omap_str; 1824 char *options; 1825 u8 idx; 1826 1827 if (strstr(boot_command_line, "console=ttyS")) 1828 /* user set a ttyS based name for the console */ 1829 return 0; 1830 1831 omap_str = strstr(boot_command_line, "console=ttyO"); 1832 if (!omap_str) 1833 /* user did not set ttyO based console, so we don't care */ 1834 return 0; 1835 1836 omap_str += 12; 1837 if ('0' <= *omap_str && *omap_str <= '9') 1838 idx = *omap_str - '0'; 1839 else 1840 return 0; 1841 1842 omap_str++; 1843 if (omap_str[0] == ',') { 1844 omap_str++; 1845 options = omap_str; 1846 } else { 1847 options = NULL; 1848 } 1849 1850 add_preferred_console("ttyS", idx, options); 1851 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1852 idx, idx); 1853 pr_err("This ensures that you still see kernel messages. Please\n"); 1854 pr_err("update your kernel commandline.\n"); 1855 return 0; 1856 } 1857 console_initcall(omap8250_console_fixup); 1858 #endif 1859 1860 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1861 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1862 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1863 omap8250_runtime_resume, NULL) 1864 .prepare = pm_sleep_ptr(omap8250_prepare), 1865 .complete = pm_sleep_ptr(omap8250_complete), 1866 }; 1867 1868 static struct platform_driver omap8250_platform_driver = { 1869 .driver = { 1870 .name = "omap8250", 1871 .pm = pm_ptr(&omap8250_dev_pm_ops), 1872 .of_match_table = omap8250_dt_ids, 1873 }, 1874 .probe = omap8250_probe, 1875 .remove = omap8250_remove, 1876 }; 1877 module_platform_driver(omap8250_platform_driver); 1878 1879 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1880 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1881 MODULE_LICENSE("GPL v2"); 1882