1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 #include <linux/pm_domain.h> 31 32 #include "8250.h" 33 34 #define DEFAULT_CLK_SPEED 48000000 35 #define OMAP_UART_REGSHIFT 2 36 37 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 38 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 39 #define OMAP_DMA_TX_KICK (1 << 2) 40 /* 41 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 42 * The same errata is applicable to AM335x and DRA7x processors too. 43 */ 44 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 45 #define UART_HAS_EFR2 BIT(4) 46 #define UART_HAS_RHR_IT_DIS BIT(5) 47 #define UART_RX_TIMEOUT_QUIRK BIT(6) 48 #define UART_HAS_NATIVE_RS485 BIT(7) 49 50 #define OMAP_UART_FCR_RX_TRIG 6 51 #define OMAP_UART_FCR_TX_TRIG 4 52 53 /* SCR register bitmasks */ 54 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 55 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 56 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 57 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 58 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 59 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 60 61 /* MVR register bitmasks */ 62 #define OMAP_UART_MVR_SCHEME_SHIFT 30 63 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 64 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 65 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 66 #define OMAP_UART_MVR_MAJ_MASK 0x700 67 #define OMAP_UART_MVR_MAJ_SHIFT 8 68 #define OMAP_UART_MVR_MIN_MASK 0x3f 69 70 /* SYSC register bitmasks */ 71 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 72 73 /* SYSS register bitmasks */ 74 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 75 76 #define UART_TI752_TLR_TX 0 77 #define UART_TI752_TLR_RX 4 78 79 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 80 #define TRIGGER_FCR_MASK(x) (x & 3) 81 82 /* Enable XON/XOFF flow control on output */ 83 #define OMAP_UART_SW_TX 0x08 84 /* Enable XON/XOFF flow control on input */ 85 #define OMAP_UART_SW_RX 0x02 86 87 #define OMAP_UART_WER_MOD_WKUP 0x7f 88 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 89 90 #define TX_TRIGGER 1 91 #define RX_TRIGGER 48 92 93 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 94 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 95 96 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 97 98 #define OMAP_UART_REV_46 0x0406 99 #define OMAP_UART_REV_52 0x0502 100 #define OMAP_UART_REV_63 0x0603 101 102 /* Interrupt Enable Register 2 */ 103 #define UART_OMAP_IER2 0x1B 104 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 105 106 /* Mode Definition Register 3 */ 107 #define UART_OMAP_MDR3 0x20 108 #define UART_OMAP_MDR3_DIR_POL BIT(3) 109 #define UART_OMAP_MDR3_DIR_EN BIT(4) 110 111 /* Enhanced features register 2 */ 112 #define UART_OMAP_EFR2 0x23 113 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 114 115 /* RX FIFO occupancy indicator */ 116 #define UART_OMAP_RX_LVL 0x19 117 118 /* Timeout low and High */ 119 #define UART_OMAP_TO_L 0x26 120 #define UART_OMAP_TO_H 0x27 121 122 /* 123 * Copy of the genpd flags for the console. 124 * Only used if console suspend is disabled 125 */ 126 static unsigned int genpd_flags_console; 127 128 struct omap8250_priv { 129 void __iomem *membase; 130 int line; 131 u8 habit; 132 u8 mdr1; 133 u8 mdr3; 134 u8 efr; 135 u8 scr; 136 u8 wer; 137 u8 xon; 138 u8 xoff; 139 u8 delayed_restore; 140 u16 quot; 141 142 u8 tx_trigger; 143 u8 rx_trigger; 144 atomic_t active; 145 bool is_suspending; 146 int wakeirq; 147 int wakeups_enabled; 148 u32 latency; 149 u32 calc_latency; 150 struct pm_qos_request pm_qos_request; 151 struct work_struct qos_work; 152 struct uart_8250_dma omap8250_dma; 153 spinlock_t rx_dma_lock; 154 bool rx_dma_broken; 155 bool throttled; 156 }; 157 158 struct omap8250_dma_params { 159 u32 rx_size; 160 u8 rx_trigger; 161 u8 tx_trigger; 162 }; 163 164 struct omap8250_platdata { 165 struct omap8250_dma_params *dma_params; 166 u8 habit; 167 }; 168 169 #ifdef CONFIG_SERIAL_8250_DMA 170 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 171 #else 172 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 173 #endif 174 175 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 176 { 177 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 178 } 179 180 /* 181 * Called on runtime PM resume path from omap8250_restore_regs(), and 182 * omap8250_set_mctrl(). 183 */ 184 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 185 { 186 struct uart_8250_port *up = up_to_u8250p(port); 187 struct omap8250_priv *priv = up->port.private_data; 188 u8 lcr; 189 190 serial8250_do_set_mctrl(port, mctrl); 191 192 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 193 /* 194 * Turn off autoRTS if RTS is lowered and restore autoRTS 195 * setting if RTS is raised 196 */ 197 lcr = serial_in(up, UART_LCR); 198 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 199 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 200 priv->efr |= UART_EFR_RTS; 201 else 202 priv->efr &= ~UART_EFR_RTS; 203 serial_out(up, UART_EFR, priv->efr); 204 serial_out(up, UART_LCR, lcr); 205 } 206 } 207 208 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 209 { 210 int err; 211 212 err = pm_runtime_resume_and_get(port->dev); 213 if (err) 214 return; 215 216 __omap8250_set_mctrl(port, mctrl); 217 218 pm_runtime_mark_last_busy(port->dev); 219 pm_runtime_put_autosuspend(port->dev); 220 } 221 222 /* 223 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 224 * The access to uart register after MDR1 Access 225 * causes UART to corrupt data. 226 * 227 * Need a delay = 228 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 229 * give 10 times as much 230 */ 231 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 232 struct omap8250_priv *priv) 233 { 234 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 235 udelay(2); 236 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 237 UART_FCR_CLEAR_RCVR); 238 } 239 240 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 241 struct omap8250_priv *priv) 242 { 243 unsigned int uartclk = port->uartclk; 244 unsigned int div_13, div_16; 245 unsigned int abs_d13, abs_d16; 246 247 /* 248 * Old custom speed handling. 249 */ 250 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 251 priv->quot = port->custom_divisor & UART_DIV_MAX; 252 /* 253 * I assume that nobody is using this. But hey, if somebody 254 * would like to specify the divisor _and_ the mode then the 255 * driver is ready and waiting for it. 256 */ 257 if (port->custom_divisor & (1 << 16)) 258 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 259 else 260 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 261 return; 262 } 263 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 264 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 265 266 if (!div_13) 267 div_13 = 1; 268 if (!div_16) 269 div_16 = 1; 270 271 abs_d13 = abs(baud - uartclk / 13 / div_13); 272 abs_d16 = abs(baud - uartclk / 16 / div_16); 273 274 if (abs_d13 >= abs_d16) { 275 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 276 priv->quot = div_16; 277 } else { 278 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 279 priv->quot = div_13; 280 } 281 } 282 283 static void omap8250_update_scr(struct uart_8250_port *up, 284 struct omap8250_priv *priv) 285 { 286 u8 old_scr; 287 288 old_scr = serial_in(up, UART_OMAP_SCR); 289 if (old_scr == priv->scr) 290 return; 291 292 /* 293 * The manual recommends not to enable the DMA mode selector in the SCR 294 * (instead of the FCR) register _and_ selecting the DMA mode as one 295 * register write because this may lead to malfunction. 296 */ 297 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 298 serial_out(up, UART_OMAP_SCR, 299 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 300 serial_out(up, UART_OMAP_SCR, priv->scr); 301 } 302 303 static void omap8250_update_mdr1(struct uart_8250_port *up, 304 struct omap8250_priv *priv) 305 { 306 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 307 omap_8250_mdr1_errataset(up, priv); 308 else 309 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 310 } 311 312 static void omap8250_restore_regs(struct uart_8250_port *up) 313 { 314 struct omap8250_priv *priv = up->port.private_data; 315 struct uart_8250_dma *dma = up->dma; 316 u8 mcr = serial8250_in_MCR(up); 317 318 /* Port locked to synchronize UART_IER access against the console. */ 319 lockdep_assert_held_once(&up->port.lock); 320 321 if (dma && dma->tx_running) { 322 /* 323 * TCSANOW requests the change to occur immediately however if 324 * we have a TX-DMA operation in progress then it has been 325 * observed that it might stall and never complete. Therefore we 326 * delay DMA completes to prevent this hang from happen. 327 */ 328 priv->delayed_restore = 1; 329 return; 330 } 331 332 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 333 serial_out(up, UART_EFR, UART_EFR_ECB); 334 335 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 336 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 337 serial_out(up, UART_FCR, up->fcr); 338 339 omap8250_update_scr(up, priv); 340 341 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 342 343 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 344 OMAP_UART_TCR_HALT(52)); 345 serial_out(up, UART_TI752_TLR, 346 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 347 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 348 349 serial_out(up, UART_LCR, 0); 350 351 /* drop TCR + TLR access, we setup XON/XOFF later */ 352 serial8250_out_MCR(up, mcr); 353 354 serial_out(up, UART_IER, up->ier); 355 356 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 357 serial_dl_write(up, priv->quot); 358 359 serial_out(up, UART_EFR, priv->efr); 360 361 /* Configure flow control */ 362 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 363 serial_out(up, UART_XON1, priv->xon); 364 serial_out(up, UART_XOFF1, priv->xoff); 365 366 serial_out(up, UART_LCR, up->lcr); 367 368 omap8250_update_mdr1(up, priv); 369 370 __omap8250_set_mctrl(&up->port, up->port.mctrl); 371 372 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 373 374 if (up->port.rs485.flags & SER_RS485_ENABLED && 375 up->port.rs485_config == serial8250_em485_config) 376 serial8250_em485_stop_tx(up); 377 } 378 379 /* 380 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 381 * some differences in how we want to handle flow control. 382 */ 383 static void omap_8250_set_termios(struct uart_port *port, 384 struct ktermios *termios, 385 const struct ktermios *old) 386 { 387 struct uart_8250_port *up = up_to_u8250p(port); 388 struct omap8250_priv *priv = up->port.private_data; 389 unsigned char cval = 0; 390 unsigned int baud; 391 392 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 393 394 if (termios->c_cflag & CSTOPB) 395 cval |= UART_LCR_STOP; 396 if (termios->c_cflag & PARENB) 397 cval |= UART_LCR_PARITY; 398 if (!(termios->c_cflag & PARODD)) 399 cval |= UART_LCR_EPAR; 400 if (termios->c_cflag & CMSPAR) 401 cval |= UART_LCR_SPAR; 402 403 /* 404 * Ask the core to calculate the divisor for us. 405 */ 406 baud = uart_get_baud_rate(port, termios, old, 407 port->uartclk / 16 / UART_DIV_MAX, 408 port->uartclk / 13); 409 omap_8250_get_divisor(port, baud, priv); 410 411 /* 412 * Ok, we're now changing the port state. Do it with 413 * interrupts disabled. 414 */ 415 pm_runtime_get_sync(port->dev); 416 uart_port_lock_irq(port); 417 418 /* 419 * Update the per-port timeout. 420 */ 421 uart_update_timeout(port, termios->c_cflag, baud); 422 423 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 424 if (termios->c_iflag & INPCK) 425 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 426 if (termios->c_iflag & (IGNBRK | PARMRK)) 427 up->port.read_status_mask |= UART_LSR_BI; 428 429 /* 430 * Characters to ignore 431 */ 432 up->port.ignore_status_mask = 0; 433 if (termios->c_iflag & IGNPAR) 434 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 435 if (termios->c_iflag & IGNBRK) { 436 up->port.ignore_status_mask |= UART_LSR_BI; 437 /* 438 * If we're ignoring parity and break indicators, 439 * ignore overruns too (for real raw support). 440 */ 441 if (termios->c_iflag & IGNPAR) 442 up->port.ignore_status_mask |= UART_LSR_OE; 443 } 444 445 /* 446 * ignore all characters if CREAD is not set 447 */ 448 if ((termios->c_cflag & CREAD) == 0) 449 up->port.ignore_status_mask |= UART_LSR_DR; 450 451 /* 452 * Modem status interrupts 453 */ 454 up->ier &= ~UART_IER_MSI; 455 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 456 up->ier |= UART_IER_MSI; 457 458 up->lcr = cval; 459 /* Up to here it was mostly serial8250_do_set_termios() */ 460 461 /* 462 * We enable TRIG_GRANU for RX and TX and additionally we set 463 * SCR_TX_EMPTY bit. The result is the following: 464 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 465 * - less than RX_TRIGGER number of bytes will also cause an interrupt 466 * once the UART decides that there no new bytes arriving. 467 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 468 * empty - the trigger level is ignored here. 469 * 470 * Once DMA is enabled: 471 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 472 * bytes in the TX FIFO. On each assert the DMA engine will move 473 * TX_TRIGGER bytes into the FIFO. 474 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 475 * the FIFO and move RX_TRIGGER bytes. 476 * This is because threshold and trigger values are the same. 477 */ 478 up->fcr = UART_FCR_ENABLE_FIFO; 479 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 480 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 481 482 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 483 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 484 485 if (up->dma) 486 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 487 OMAP_UART_SCR_DMAMODE_CTL; 488 489 priv->xon = termios->c_cc[VSTART]; 490 priv->xoff = termios->c_cc[VSTOP]; 491 492 priv->efr = 0; 493 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 494 495 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 496 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 497 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 498 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 499 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 500 priv->efr |= UART_EFR_CTS; 501 } else if (up->port.flags & UPF_SOFT_FLOW) { 502 /* 503 * OMAP rx s/w flow control is borked; the transmitter remains 504 * stuck off even if rx flow control is subsequently disabled 505 */ 506 507 /* 508 * IXOFF Flag: 509 * Enable XON/XOFF flow control on output. 510 * Transmit XON1, XOFF1 511 */ 512 if (termios->c_iflag & IXOFF) { 513 up->port.status |= UPSTAT_AUTOXOFF; 514 priv->efr |= OMAP_UART_SW_TX; 515 } 516 } 517 omap8250_restore_regs(up); 518 519 uart_port_unlock_irq(&up->port); 520 pm_runtime_mark_last_busy(port->dev); 521 pm_runtime_put_autosuspend(port->dev); 522 523 /* calculate wakeup latency constraint */ 524 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 525 priv->latency = priv->calc_latency; 526 527 schedule_work(&priv->qos_work); 528 529 /* Don't rewrite B0 */ 530 if (tty_termios_baud_rate(termios)) 531 tty_termios_encode_baud_rate(termios, baud, baud); 532 } 533 534 /* same as 8250 except that we may have extra flow bits set in EFR */ 535 static void omap_8250_pm(struct uart_port *port, unsigned int state, 536 unsigned int oldstate) 537 { 538 struct uart_8250_port *up = up_to_u8250p(port); 539 u8 efr; 540 541 pm_runtime_get_sync(port->dev); 542 543 /* Synchronize UART_IER access against the console. */ 544 uart_port_lock_irq(port); 545 546 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 547 efr = serial_in(up, UART_EFR); 548 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 549 serial_out(up, UART_LCR, 0); 550 551 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 552 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 553 serial_out(up, UART_EFR, efr); 554 serial_out(up, UART_LCR, 0); 555 556 uart_port_unlock_irq(port); 557 558 pm_runtime_mark_last_busy(port->dev); 559 pm_runtime_put_autosuspend(port->dev); 560 } 561 562 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 563 struct omap8250_priv *priv) 564 { 565 static const struct soc_device_attribute k3_soc_devices[] = { 566 { .family = "AM65X", }, 567 { .family = "J721E", .revision = "SR1.0" }, 568 { /* sentinel */ } 569 }; 570 u32 mvr, scheme; 571 u16 revision, major, minor; 572 573 mvr = uart_read(priv, UART_OMAP_MVER); 574 575 /* Check revision register scheme */ 576 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 577 578 switch (scheme) { 579 case 0: /* Legacy Scheme: OMAP2/3 */ 580 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 581 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 582 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 583 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 584 break; 585 case 1: 586 /* New Scheme: OMAP4+ */ 587 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 588 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 589 OMAP_UART_MVR_MAJ_SHIFT; 590 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 591 break; 592 default: 593 dev_warn(up->port.dev, 594 "Unknown revision, defaulting to highest\n"); 595 /* highest possible revision */ 596 major = 0xff; 597 minor = 0xff; 598 } 599 /* normalize revision for the driver */ 600 revision = UART_BUILD_REVISION(major, minor); 601 602 switch (revision) { 603 case OMAP_UART_REV_46: 604 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 605 break; 606 case OMAP_UART_REV_52: 607 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 608 OMAP_UART_WER_HAS_TX_WAKEUP; 609 break; 610 case OMAP_UART_REV_63: 611 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 612 OMAP_UART_WER_HAS_TX_WAKEUP; 613 break; 614 default: 615 break; 616 } 617 618 /* 619 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 620 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 621 * to enable errata workaround. 622 */ 623 if (soc_device_match(k3_soc_devices)) 624 priv->habit &= ~UART_HAS_RHR_IT_DIS; 625 } 626 627 static void omap8250_uart_qos_work(struct work_struct *work) 628 { 629 struct omap8250_priv *priv; 630 631 priv = container_of(work, struct omap8250_priv, qos_work); 632 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 633 } 634 635 #ifdef CONFIG_SERIAL_8250_DMA 636 static int omap_8250_dma_handle_irq(struct uart_port *port); 637 #endif 638 639 static irqreturn_t omap8250_irq(int irq, void *dev_id) 640 { 641 struct omap8250_priv *priv = dev_id; 642 struct uart_8250_port *up = serial8250_get_port(priv->line); 643 struct uart_port *port = &up->port; 644 unsigned int iir, lsr; 645 int ret; 646 647 pm_runtime_get_noresume(port->dev); 648 649 /* Shallow idle state wake-up to an IO interrupt? */ 650 if (atomic_add_unless(&priv->active, 1, 1)) { 651 priv->latency = priv->calc_latency; 652 schedule_work(&priv->qos_work); 653 } 654 655 #ifdef CONFIG_SERIAL_8250_DMA 656 if (up->dma) { 657 ret = omap_8250_dma_handle_irq(port); 658 pm_runtime_mark_last_busy(port->dev); 659 pm_runtime_put(port->dev); 660 return IRQ_RETVAL(ret); 661 } 662 #endif 663 664 lsr = serial_port_in(port, UART_LSR); 665 iir = serial_port_in(port, UART_IIR); 666 ret = serial8250_handle_irq(port, iir); 667 668 /* 669 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 670 * FIFO has been drained or erroneously. 671 * So apply solution of Errata i2310 as mentioned in 672 * https://www.ti.com/lit/pdf/sprz536 673 */ 674 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 675 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 676 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 677 unsigned char efr2, timeout_h, timeout_l; 678 679 efr2 = serial_in(up, UART_OMAP_EFR2); 680 timeout_h = serial_in(up, UART_OMAP_TO_H); 681 timeout_l = serial_in(up, UART_OMAP_TO_L); 682 serial_out(up, UART_OMAP_TO_H, 0xFF); 683 serial_out(up, UART_OMAP_TO_L, 0xFF); 684 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 685 serial_in(up, UART_IIR); 686 serial_out(up, UART_OMAP_EFR2, efr2); 687 serial_out(up, UART_OMAP_TO_H, timeout_h); 688 serial_out(up, UART_OMAP_TO_L, timeout_l); 689 } 690 691 /* Stop processing interrupts on input overrun */ 692 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 693 unsigned long delay; 694 695 /* Synchronize UART_IER access against the console. */ 696 uart_port_lock(port); 697 up->ier = port->serial_in(port, UART_IER); 698 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 699 port->ops->stop_rx(port); 700 } else { 701 /* Keep restarting the timer until 702 * the input overrun subsides. 703 */ 704 cancel_delayed_work(&up->overrun_backoff); 705 } 706 uart_port_unlock(port); 707 708 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 709 schedule_delayed_work(&up->overrun_backoff, delay); 710 } 711 712 pm_runtime_mark_last_busy(port->dev); 713 pm_runtime_put(port->dev); 714 715 return IRQ_RETVAL(ret); 716 } 717 718 static int omap_8250_startup(struct uart_port *port) 719 { 720 struct uart_8250_port *up = up_to_u8250p(port); 721 struct omap8250_priv *priv = port->private_data; 722 struct uart_8250_dma *dma = &priv->omap8250_dma; 723 int ret; 724 725 if (priv->wakeirq) { 726 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 727 if (ret) 728 return ret; 729 } 730 731 pm_runtime_get_sync(port->dev); 732 733 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 734 735 serial_out(up, UART_LCR, UART_LCR_WLEN8); 736 737 up->lsr_saved_flags = 0; 738 up->msr_saved_flags = 0; 739 740 /* Disable DMA for console UART */ 741 if (dma->fn && !uart_console(port)) { 742 up->dma = &priv->omap8250_dma; 743 ret = serial8250_request_dma(up); 744 if (ret) { 745 dev_warn_ratelimited(port->dev, 746 "failed to request DMA\n"); 747 up->dma = NULL; 748 } 749 } else { 750 up->dma = NULL; 751 } 752 753 /* Synchronize UART_IER access against the console. */ 754 uart_port_lock_irq(port); 755 up->ier = UART_IER_RLSI | UART_IER_RDI; 756 serial_out(up, UART_IER, up->ier); 757 uart_port_unlock_irq(port); 758 759 #ifdef CONFIG_PM 760 up->capabilities |= UART_CAP_RPM; 761 #endif 762 763 /* Enable module level wake up */ 764 priv->wer = OMAP_UART_WER_MOD_WKUP; 765 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 766 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 767 serial_out(up, UART_OMAP_WER, priv->wer); 768 769 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 770 uart_port_lock_irq(port); 771 up->dma->rx_dma(up); 772 uart_port_unlock_irq(port); 773 } 774 775 enable_irq(up->port.irq); 776 777 pm_runtime_mark_last_busy(port->dev); 778 pm_runtime_put_autosuspend(port->dev); 779 return 0; 780 } 781 782 static void omap_8250_shutdown(struct uart_port *port) 783 { 784 struct uart_8250_port *up = up_to_u8250p(port); 785 struct omap8250_priv *priv = port->private_data; 786 787 flush_work(&priv->qos_work); 788 if (up->dma) 789 omap_8250_rx_dma_flush(up); 790 791 pm_runtime_get_sync(port->dev); 792 793 serial_out(up, UART_OMAP_WER, 0); 794 if (priv->habit & UART_HAS_EFR2) 795 serial_out(up, UART_OMAP_EFR2, 0x0); 796 797 /* Synchronize UART_IER access against the console. */ 798 uart_port_lock_irq(port); 799 up->ier = 0; 800 serial_out(up, UART_IER, 0); 801 uart_port_unlock_irq(port); 802 disable_irq_nosync(up->port.irq); 803 dev_pm_clear_wake_irq(port->dev); 804 805 serial8250_release_dma(up); 806 up->dma = NULL; 807 808 /* 809 * Disable break condition and FIFOs 810 */ 811 if (up->lcr & UART_LCR_SBC) 812 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 813 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 814 815 pm_runtime_mark_last_busy(port->dev); 816 pm_runtime_put_autosuspend(port->dev); 817 } 818 819 static void omap_8250_throttle(struct uart_port *port) 820 { 821 struct omap8250_priv *priv = port->private_data; 822 unsigned long flags; 823 824 pm_runtime_get_sync(port->dev); 825 826 uart_port_lock_irqsave(port, &flags); 827 port->ops->stop_rx(port); 828 priv->throttled = true; 829 uart_port_unlock_irqrestore(port, flags); 830 831 pm_runtime_mark_last_busy(port->dev); 832 pm_runtime_put_autosuspend(port->dev); 833 } 834 835 static void omap_8250_unthrottle(struct uart_port *port) 836 { 837 struct omap8250_priv *priv = port->private_data; 838 struct uart_8250_port *up = up_to_u8250p(port); 839 unsigned long flags; 840 841 pm_runtime_get_sync(port->dev); 842 843 /* Synchronize UART_IER access against the console. */ 844 uart_port_lock_irqsave(port, &flags); 845 priv->throttled = false; 846 if (up->dma) 847 up->dma->rx_dma(up); 848 up->ier |= UART_IER_RLSI | UART_IER_RDI; 849 port->read_status_mask |= UART_LSR_DR; 850 serial_out(up, UART_IER, up->ier); 851 uart_port_unlock_irqrestore(port, flags); 852 853 pm_runtime_mark_last_busy(port->dev); 854 pm_runtime_put_autosuspend(port->dev); 855 } 856 857 static int omap8250_rs485_config(struct uart_port *port, 858 struct ktermios *termios, 859 struct serial_rs485 *rs485) 860 { 861 struct omap8250_priv *priv = port->private_data; 862 struct uart_8250_port *up = up_to_u8250p(port); 863 u32 fixed_delay_rts_before_send = 0; 864 u32 fixed_delay_rts_after_send = 0; 865 unsigned int baud; 866 867 /* 868 * There is a fixed delay of 3 bit clock cycles after the TX shift 869 * register is going empty to allow time for the stop bit to transition 870 * through the transceiver before direction is changed to receive. 871 * 872 * Additionally there appears to be a 1 bit clock delay between writing 873 * to the THR register and transmission of the start bit, per page 8783 874 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 875 */ 876 if (priv->quot) { 877 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 878 baud = port->uartclk / (16 * priv->quot); 879 else 880 baud = port->uartclk / (13 * priv->quot); 881 882 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 883 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 884 } 885 886 /* 887 * Fall back to RS485 software emulation if the UART is missing 888 * hardware support, if the device tree specifies an mctrl_gpio 889 * (indicates that RTS is unavailable due to a pinmux conflict) 890 * or if the requested delays exceed the fixed hardware delays. 891 */ 892 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 893 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 894 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 895 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 896 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 897 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 898 899 port->rs485_config = serial8250_em485_config; 900 return serial8250_em485_config(port, termios, rs485); 901 } 902 903 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 904 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 905 906 if (rs485->flags & SER_RS485_ENABLED) 907 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 908 else 909 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 910 911 /* 912 * Retain same polarity semantics as RS485 software emulation, 913 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 914 */ 915 if (rs485->flags & SER_RS485_RTS_ON_SEND) 916 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 917 else 918 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 919 920 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 921 922 return 0; 923 } 924 925 #ifdef CONFIG_SERIAL_8250_DMA 926 static int omap_8250_rx_dma(struct uart_8250_port *p); 927 928 /* Must be called while priv->rx_dma_lock is held */ 929 static void __dma_rx_do_complete(struct uart_8250_port *p) 930 { 931 struct uart_8250_dma *dma = p->dma; 932 struct tty_port *tty_port = &p->port.state->port; 933 struct omap8250_priv *priv = p->port.private_data; 934 struct dma_chan *rxchan = dma->rxchan; 935 dma_cookie_t cookie; 936 struct dma_tx_state state; 937 int count; 938 int ret; 939 u32 reg; 940 941 if (!dma->rx_running) 942 goto out; 943 944 cookie = dma->rx_cookie; 945 dma->rx_running = 0; 946 947 /* Re-enable RX FIFO interrupt now that transfer is complete */ 948 if (priv->habit & UART_HAS_RHR_IT_DIS) { 949 reg = serial_in(p, UART_OMAP_IER2); 950 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 951 serial_out(p, UART_OMAP_IER2, reg); 952 } 953 954 dmaengine_tx_status(rxchan, cookie, &state); 955 956 count = dma->rx_size - state.residue + state.in_flight_bytes; 957 if (count < dma->rx_size) { 958 dmaengine_terminate_async(rxchan); 959 960 /* 961 * Poll for teardown to complete which guarantees in 962 * flight data is drained. 963 */ 964 if (state.in_flight_bytes) { 965 int poll_count = 25; 966 967 while (dmaengine_tx_status(rxchan, cookie, NULL) && 968 poll_count--) 969 cpu_relax(); 970 971 if (poll_count == -1) 972 dev_err(p->port.dev, "teardown incomplete\n"); 973 } 974 } 975 if (!count) 976 goto out; 977 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 978 979 p->port.icount.rx += ret; 980 p->port.icount.buf_overrun += count - ret; 981 out: 982 983 tty_flip_buffer_push(tty_port); 984 } 985 986 static void __dma_rx_complete(void *param) 987 { 988 struct uart_8250_port *p = param; 989 struct omap8250_priv *priv = p->port.private_data; 990 struct uart_8250_dma *dma = p->dma; 991 struct dma_tx_state state; 992 unsigned long flags; 993 994 /* Synchronize UART_IER access against the console. */ 995 uart_port_lock_irqsave(&p->port, &flags); 996 997 /* 998 * If the tx status is not DMA_COMPLETE, then this is a delayed 999 * completion callback. A previous RX timeout flush would have 1000 * already pushed the data, so exit. 1001 */ 1002 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 1003 DMA_COMPLETE) { 1004 uart_port_unlock_irqrestore(&p->port, flags); 1005 return; 1006 } 1007 __dma_rx_do_complete(p); 1008 if (!priv->throttled) { 1009 p->ier |= UART_IER_RLSI | UART_IER_RDI; 1010 serial_out(p, UART_IER, p->ier); 1011 if (!(priv->habit & UART_HAS_EFR2)) 1012 omap_8250_rx_dma(p); 1013 } 1014 1015 uart_port_unlock_irqrestore(&p->port, flags); 1016 } 1017 1018 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 1019 { 1020 struct omap8250_priv *priv = p->port.private_data; 1021 struct uart_8250_dma *dma = p->dma; 1022 struct dma_tx_state state; 1023 unsigned long flags; 1024 int ret; 1025 1026 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1027 1028 if (!dma->rx_running) { 1029 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1030 return; 1031 } 1032 1033 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1034 if (ret == DMA_IN_PROGRESS) { 1035 ret = dmaengine_pause(dma->rxchan); 1036 if (WARN_ON_ONCE(ret)) 1037 priv->rx_dma_broken = true; 1038 } 1039 __dma_rx_do_complete(p); 1040 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1041 } 1042 1043 static int omap_8250_rx_dma(struct uart_8250_port *p) 1044 { 1045 struct omap8250_priv *priv = p->port.private_data; 1046 struct uart_8250_dma *dma = p->dma; 1047 int err = 0; 1048 struct dma_async_tx_descriptor *desc; 1049 unsigned long flags; 1050 u32 reg; 1051 1052 /* Port locked to synchronize UART_IER access against the console. */ 1053 lockdep_assert_held_once(&p->port.lock); 1054 1055 if (priv->rx_dma_broken) 1056 return -EINVAL; 1057 1058 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1059 1060 if (dma->rx_running) { 1061 enum dma_status state; 1062 1063 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1064 if (state == DMA_COMPLETE) { 1065 /* 1066 * Disable RX interrupts to allow RX DMA completion 1067 * callback to run. 1068 */ 1069 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1070 serial_out(p, UART_IER, p->ier); 1071 } 1072 goto out; 1073 } 1074 1075 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1076 dma->rx_size, DMA_DEV_TO_MEM, 1077 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1078 if (!desc) { 1079 err = -EBUSY; 1080 goto out; 1081 } 1082 1083 dma->rx_running = 1; 1084 desc->callback = __dma_rx_complete; 1085 desc->callback_param = p; 1086 1087 dma->rx_cookie = dmaengine_submit(desc); 1088 1089 /* 1090 * Disable RX FIFO interrupt while RX DMA is enabled, else 1091 * spurious interrupt may be raised when data is in the RX FIFO 1092 * but is yet to be drained by DMA. 1093 */ 1094 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1095 reg = serial_in(p, UART_OMAP_IER2); 1096 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1097 serial_out(p, UART_OMAP_IER2, reg); 1098 } 1099 1100 dma_async_issue_pending(dma->rxchan); 1101 out: 1102 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1103 return err; 1104 } 1105 1106 static int omap_8250_tx_dma(struct uart_8250_port *p); 1107 1108 static void omap_8250_dma_tx_complete(void *param) 1109 { 1110 struct uart_8250_port *p = param; 1111 struct uart_8250_dma *dma = p->dma; 1112 struct tty_port *tport = &p->port.state->port; 1113 unsigned long flags; 1114 bool en_thri = false; 1115 struct omap8250_priv *priv = p->port.private_data; 1116 1117 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1118 UART_XMIT_SIZE, DMA_TO_DEVICE); 1119 1120 uart_port_lock_irqsave(&p->port, &flags); 1121 1122 dma->tx_running = 0; 1123 1124 uart_xmit_advance(&p->port, dma->tx_size); 1125 1126 if (priv->delayed_restore) { 1127 priv->delayed_restore = 0; 1128 omap8250_restore_regs(p); 1129 } 1130 1131 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1132 uart_write_wakeup(&p->port); 1133 1134 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1135 int ret; 1136 1137 ret = omap_8250_tx_dma(p); 1138 if (ret) 1139 en_thri = true; 1140 } else if (p->capabilities & UART_CAP_RPM) { 1141 en_thri = true; 1142 } 1143 1144 if (en_thri) { 1145 dma->tx_err = 1; 1146 serial8250_set_THRI(p); 1147 } 1148 1149 uart_port_unlock_irqrestore(&p->port, flags); 1150 } 1151 1152 static int omap_8250_tx_dma(struct uart_8250_port *p) 1153 { 1154 struct uart_8250_dma *dma = p->dma; 1155 struct omap8250_priv *priv = p->port.private_data; 1156 struct tty_port *tport = &p->port.state->port; 1157 struct dma_async_tx_descriptor *desc; 1158 struct scatterlist sg; 1159 int skip_byte = -1; 1160 int ret; 1161 1162 if (dma->tx_running) 1163 return 0; 1164 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1165 1166 /* 1167 * Even if no data, we need to return an error for the two cases 1168 * below so serial8250_tx_chars() is invoked and properly clears 1169 * THRI and/or runtime suspend. 1170 */ 1171 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1172 ret = -EBUSY; 1173 goto err; 1174 } 1175 serial8250_clear_THRI(p); 1176 return 0; 1177 } 1178 1179 sg_init_table(&sg, 1); 1180 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1181 UART_XMIT_SIZE, dma->tx_addr); 1182 if (ret != 1) { 1183 serial8250_clear_THRI(p); 1184 return 0; 1185 } 1186 1187 dma->tx_size = sg_dma_len(&sg); 1188 1189 if (priv->habit & OMAP_DMA_TX_KICK) { 1190 unsigned char c; 1191 u8 tx_lvl; 1192 1193 /* 1194 * We need to put the first byte into the FIFO in order to start 1195 * the DMA transfer. For transfers smaller than four bytes we 1196 * don't bother doing DMA at all. It seem not matter if there 1197 * are still bytes in the FIFO from the last transfer (in case 1198 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1199 * leaving the FIFO seem not to trigger the DMA transfer. It is 1200 * really the byte that we put into the FIFO. 1201 * If the FIFO is already full then we most likely got here from 1202 * omap_8250_dma_tx_complete(). And this means the DMA engine 1203 * just completed its work. We don't have to wait the complete 1204 * 86us at 115200,8n1 but around 60us (not to mention lower 1205 * baudrates). So in that case we take the interrupt and try 1206 * again with an empty FIFO. 1207 */ 1208 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1209 if (tx_lvl == p->tx_loadsz) { 1210 ret = -EBUSY; 1211 goto err; 1212 } 1213 if (dma->tx_size < 4) { 1214 ret = -EINVAL; 1215 goto err; 1216 } 1217 if (!kfifo_get(&tport->xmit_fifo, &c)) { 1218 ret = -EINVAL; 1219 goto err; 1220 } 1221 skip_byte = c; 1222 /* now we need to recompute due to kfifo_get */ 1223 kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1224 UART_XMIT_SIZE, dma->tx_addr); 1225 } 1226 1227 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1228 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1229 if (!desc) { 1230 ret = -EBUSY; 1231 goto err; 1232 } 1233 1234 dma->tx_running = 1; 1235 1236 desc->callback = omap_8250_dma_tx_complete; 1237 desc->callback_param = p; 1238 1239 dma->tx_cookie = dmaengine_submit(desc); 1240 1241 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1242 UART_XMIT_SIZE, DMA_TO_DEVICE); 1243 1244 dma_async_issue_pending(dma->txchan); 1245 if (dma->tx_err) 1246 dma->tx_err = 0; 1247 1248 serial8250_clear_THRI(p); 1249 ret = 0; 1250 goto out_skip; 1251 err: 1252 dma->tx_err = 1; 1253 out_skip: 1254 if (skip_byte >= 0) 1255 serial_out(p, UART_TX, skip_byte); 1256 return ret; 1257 } 1258 1259 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1260 { 1261 switch (iir & 0x3f) { 1262 case UART_IIR_RLSI: 1263 case UART_IIR_RX_TIMEOUT: 1264 case UART_IIR_RDI: 1265 omap_8250_rx_dma_flush(up); 1266 return true; 1267 } 1268 return omap_8250_rx_dma(up); 1269 } 1270 1271 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1272 { 1273 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1274 (iir & UART_IIR_RDI)) { 1275 if (handle_rx_dma(up, iir)) { 1276 status = serial8250_rx_chars(up, status); 1277 omap_8250_rx_dma(up); 1278 } 1279 } 1280 1281 return status; 1282 } 1283 1284 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1285 u16 status) 1286 { 1287 /* Port locked to synchronize UART_IER access against the console. */ 1288 lockdep_assert_held_once(&up->port.lock); 1289 1290 /* 1291 * Queue a new transfer if FIFO has data. 1292 */ 1293 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1294 (up->ier & UART_IER_RDI)) { 1295 omap_8250_rx_dma(up); 1296 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1297 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1298 /* 1299 * Disable RX timeout, read IIR to clear 1300 * current timeout condition, clear EFR2 to 1301 * periodic timeouts, re-enable interrupts. 1302 */ 1303 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1304 serial_out(up, UART_IER, up->ier); 1305 omap_8250_rx_dma_flush(up); 1306 serial_in(up, UART_IIR); 1307 serial_out(up, UART_OMAP_EFR2, 0x0); 1308 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1309 serial_out(up, UART_IER, up->ier); 1310 } 1311 } 1312 1313 /* 1314 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1315 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1316 * use the default routine in the non-DMA case and this one for with DMA. 1317 */ 1318 static int omap_8250_dma_handle_irq(struct uart_port *port) 1319 { 1320 struct uart_8250_port *up = up_to_u8250p(port); 1321 struct omap8250_priv *priv = up->port.private_data; 1322 u16 status; 1323 u8 iir; 1324 1325 iir = serial_port_in(port, UART_IIR); 1326 if (iir & UART_IIR_NO_INT) { 1327 return IRQ_HANDLED; 1328 } 1329 1330 uart_port_lock(port); 1331 1332 status = serial_port_in(port, UART_LSR); 1333 1334 if ((iir & 0x3f) != UART_IIR_THRI) { 1335 if (priv->habit & UART_HAS_EFR2) 1336 am654_8250_handle_rx_dma(up, iir, status); 1337 else 1338 status = omap_8250_handle_rx_dma(up, iir, status); 1339 } 1340 1341 serial8250_modem_status(up); 1342 if (status & UART_LSR_THRE && up->dma->tx_err) { 1343 if (uart_tx_stopped(&up->port) || 1344 kfifo_is_empty(&up->port.state->port.xmit_fifo)) { 1345 up->dma->tx_err = 0; 1346 serial8250_tx_chars(up); 1347 } else { 1348 /* 1349 * try again due to an earlier failer which 1350 * might have been resolved by now. 1351 */ 1352 if (omap_8250_tx_dma(up)) 1353 serial8250_tx_chars(up); 1354 } 1355 } 1356 1357 uart_unlock_and_check_sysrq(port); 1358 1359 return 1; 1360 } 1361 1362 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1363 { 1364 return false; 1365 } 1366 1367 #else 1368 1369 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1370 { 1371 return -EINVAL; 1372 } 1373 #endif 1374 1375 static int omap8250_no_handle_irq(struct uart_port *port) 1376 { 1377 /* IRQ has not been requested but handling irq? */ 1378 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1379 return 0; 1380 } 1381 1382 static struct omap8250_dma_params am654_dma = { 1383 .rx_size = SZ_2K, 1384 .rx_trigger = 1, 1385 .tx_trigger = TX_TRIGGER, 1386 }; 1387 1388 static struct omap8250_dma_params am33xx_dma = { 1389 .rx_size = RX_TRIGGER, 1390 .rx_trigger = RX_TRIGGER, 1391 .tx_trigger = TX_TRIGGER, 1392 }; 1393 1394 static struct omap8250_platdata am654_platdata = { 1395 .dma_params = &am654_dma, 1396 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1397 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1398 }; 1399 1400 static struct omap8250_platdata am33xx_platdata = { 1401 .dma_params = &am33xx_dma, 1402 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1403 }; 1404 1405 static struct omap8250_platdata omap4_platdata = { 1406 .dma_params = &am33xx_dma, 1407 .habit = UART_ERRATA_CLOCK_DISABLE, 1408 }; 1409 1410 static const struct of_device_id omap8250_dt_ids[] = { 1411 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1412 { .compatible = "ti,omap2-uart" }, 1413 { .compatible = "ti,omap3-uart" }, 1414 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1415 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1416 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1417 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1418 {}, 1419 }; 1420 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1421 1422 static int omap8250_probe(struct platform_device *pdev) 1423 { 1424 struct device_node *np = pdev->dev.of_node; 1425 struct omap8250_priv *priv; 1426 const struct omap8250_platdata *pdata; 1427 struct uart_8250_port up; 1428 struct resource *regs; 1429 void __iomem *membase; 1430 int ret; 1431 1432 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1433 if (!regs) { 1434 dev_err(&pdev->dev, "missing registers\n"); 1435 return -EINVAL; 1436 } 1437 1438 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1439 if (!priv) 1440 return -ENOMEM; 1441 1442 membase = devm_ioremap(&pdev->dev, regs->start, 1443 resource_size(regs)); 1444 if (!membase) 1445 return -ENODEV; 1446 1447 memset(&up, 0, sizeof(up)); 1448 up.port.dev = &pdev->dev; 1449 up.port.mapbase = regs->start; 1450 up.port.membase = membase; 1451 /* 1452 * It claims to be 16C750 compatible however it is a little different. 1453 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1454 * have) is enabled via EFR instead of MCR. The type is set here 8250 1455 * just to get things going. UNKNOWN does not work for a few reasons and 1456 * we don't need our own type since we don't use 8250's set_termios() 1457 * or pm callback. 1458 */ 1459 up.port.type = PORT_8250; 1460 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1461 up.port.private_data = priv; 1462 1463 up.tx_loadsz = 64; 1464 up.capabilities = UART_CAP_FIFO; 1465 #ifdef CONFIG_PM 1466 /* 1467 * Runtime PM is mostly transparent. However to do it right we need to a 1468 * TX empty interrupt before we can put the device to auto idle. So if 1469 * PM is not enabled we don't add that flag and can spare that one extra 1470 * interrupt in the TX path. 1471 */ 1472 up.capabilities |= UART_CAP_RPM; 1473 #endif 1474 up.port.set_termios = omap_8250_set_termios; 1475 up.port.set_mctrl = omap8250_set_mctrl; 1476 up.port.pm = omap_8250_pm; 1477 up.port.startup = omap_8250_startup; 1478 up.port.shutdown = omap_8250_shutdown; 1479 up.port.throttle = omap_8250_throttle; 1480 up.port.unthrottle = omap_8250_unthrottle; 1481 up.port.rs485_config = omap8250_rs485_config; 1482 /* same rs485_supported for software emulation and native RS485 */ 1483 up.port.rs485_supported = serial8250_em485_supported; 1484 up.rs485_start_tx = serial8250_em485_start_tx; 1485 up.rs485_stop_tx = serial8250_em485_stop_tx; 1486 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1487 1488 ret = uart_read_port_properties(&up.port); 1489 if (ret) 1490 return ret; 1491 1492 up.port.regshift = OMAP_UART_REGSHIFT; 1493 up.port.fifosize = 64; 1494 1495 if (!up.port.uartclk) { 1496 struct clk *clk; 1497 1498 clk = devm_clk_get(&pdev->dev, NULL); 1499 if (IS_ERR(clk)) { 1500 if (PTR_ERR(clk) == -EPROBE_DEFER) 1501 return -EPROBE_DEFER; 1502 } else { 1503 up.port.uartclk = clk_get_rate(clk); 1504 } 1505 } 1506 1507 if (of_property_read_u32(np, "overrun-throttle-ms", 1508 &up.overrun_backoff_time_ms) != 0) 1509 up.overrun_backoff_time_ms = 0; 1510 1511 pdata = of_device_get_match_data(&pdev->dev); 1512 if (pdata) 1513 priv->habit |= pdata->habit; 1514 1515 if (!up.port.uartclk) { 1516 up.port.uartclk = DEFAULT_CLK_SPEED; 1517 dev_warn(&pdev->dev, 1518 "No clock speed specified: using default: %d\n", 1519 DEFAULT_CLK_SPEED); 1520 } 1521 1522 priv->membase = membase; 1523 priv->line = -ENODEV; 1524 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1525 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1526 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1527 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1528 1529 spin_lock_init(&priv->rx_dma_lock); 1530 1531 platform_set_drvdata(pdev, priv); 1532 1533 device_init_wakeup(&pdev->dev, true); 1534 pm_runtime_enable(&pdev->dev); 1535 pm_runtime_use_autosuspend(&pdev->dev); 1536 1537 /* 1538 * Disable runtime PM until autosuspend delay unless specifically 1539 * enabled by the user via sysfs. This is the historic way to 1540 * prevent an unsafe default policy with lossy characters on wake-up. 1541 * For serdev devices this is not needed, the policy can be managed by 1542 * the serdev driver. 1543 */ 1544 if (!of_get_available_child_count(pdev->dev.of_node)) 1545 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1546 1547 pm_runtime_get_sync(&pdev->dev); 1548 1549 omap_serial_fill_features_erratas(&up, priv); 1550 up.port.handle_irq = omap8250_no_handle_irq; 1551 priv->rx_trigger = RX_TRIGGER; 1552 priv->tx_trigger = TX_TRIGGER; 1553 #ifdef CONFIG_SERIAL_8250_DMA 1554 /* 1555 * Oh DMA support. If there are no DMA properties in the DT then 1556 * we will fall back to a generic DMA channel which does not 1557 * really work here. To ensure that we do not get a generic DMA 1558 * channel assigned, we have the the_no_dma_filter_fn() here. 1559 * To avoid "failed to request DMA" messages we check for DMA 1560 * properties in DT. 1561 */ 1562 ret = of_property_count_strings(np, "dma-names"); 1563 if (ret == 2) { 1564 struct omap8250_dma_params *dma_params = NULL; 1565 struct uart_8250_dma *dma = &priv->omap8250_dma; 1566 1567 dma->fn = the_no_dma_filter_fn; 1568 dma->tx_dma = omap_8250_tx_dma; 1569 dma->rx_dma = omap_8250_rx_dma; 1570 if (pdata) 1571 dma_params = pdata->dma_params; 1572 1573 if (dma_params) { 1574 dma->rx_size = dma_params->rx_size; 1575 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1576 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1577 priv->rx_trigger = dma_params->rx_trigger; 1578 priv->tx_trigger = dma_params->tx_trigger; 1579 } else { 1580 dma->rx_size = RX_TRIGGER; 1581 dma->rxconf.src_maxburst = RX_TRIGGER; 1582 dma->txconf.dst_maxburst = TX_TRIGGER; 1583 } 1584 } 1585 #endif 1586 1587 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1588 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1589 dev_name(&pdev->dev), priv); 1590 if (ret < 0) 1591 return ret; 1592 1593 priv->wakeirq = irq_of_parse_and_map(np, 1); 1594 1595 ret = serial8250_register_8250_port(&up); 1596 if (ret < 0) { 1597 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1598 goto err; 1599 } 1600 priv->line = ret; 1601 pm_runtime_mark_last_busy(&pdev->dev); 1602 pm_runtime_put_autosuspend(&pdev->dev); 1603 return 0; 1604 err: 1605 pm_runtime_dont_use_autosuspend(&pdev->dev); 1606 pm_runtime_put_sync(&pdev->dev); 1607 flush_work(&priv->qos_work); 1608 pm_runtime_disable(&pdev->dev); 1609 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1610 return ret; 1611 } 1612 1613 static void omap8250_remove(struct platform_device *pdev) 1614 { 1615 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1616 struct uart_8250_port *up; 1617 int err; 1618 1619 err = pm_runtime_resume_and_get(&pdev->dev); 1620 if (err) 1621 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1622 1623 up = serial8250_get_port(priv->line); 1624 omap_8250_shutdown(&up->port); 1625 serial8250_unregister_port(priv->line); 1626 priv->line = -ENODEV; 1627 pm_runtime_dont_use_autosuspend(&pdev->dev); 1628 pm_runtime_put_sync(&pdev->dev); 1629 flush_work(&priv->qos_work); 1630 pm_runtime_disable(&pdev->dev); 1631 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1632 device_init_wakeup(&pdev->dev, false); 1633 } 1634 1635 static int omap8250_prepare(struct device *dev) 1636 { 1637 struct omap8250_priv *priv = dev_get_drvdata(dev); 1638 1639 if (!priv) 1640 return 0; 1641 priv->is_suspending = true; 1642 return 0; 1643 } 1644 1645 static void omap8250_complete(struct device *dev) 1646 { 1647 struct omap8250_priv *priv = dev_get_drvdata(dev); 1648 1649 if (!priv) 1650 return; 1651 priv->is_suspending = false; 1652 } 1653 1654 static int omap8250_suspend(struct device *dev) 1655 { 1656 struct omap8250_priv *priv = dev_get_drvdata(dev); 1657 struct uart_8250_port *up = serial8250_get_port(priv->line); 1658 struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); 1659 int err = 0; 1660 1661 serial8250_suspend_port(priv->line); 1662 1663 err = pm_runtime_resume_and_get(dev); 1664 if (err) 1665 return err; 1666 if (!device_may_wakeup(dev)) 1667 priv->wer = 0; 1668 serial_out(up, UART_OMAP_WER, priv->wer); 1669 if (uart_console(&up->port)) { 1670 if (console_suspend_enabled) 1671 err = pm_runtime_force_suspend(dev); 1672 else { 1673 /* 1674 * The pd shall not be powered-off (no console suspend). 1675 * Make copy of genpd flags before to set it always on. 1676 * The original value is restored during the resume. 1677 */ 1678 genpd_flags_console = genpd->flags; 1679 genpd->flags |= GENPD_FLAG_ALWAYS_ON; 1680 } 1681 } 1682 flush_work(&priv->qos_work); 1683 1684 return err; 1685 } 1686 1687 static int omap8250_resume(struct device *dev) 1688 { 1689 struct omap8250_priv *priv = dev_get_drvdata(dev); 1690 struct uart_8250_port *up = serial8250_get_port(priv->line); 1691 struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); 1692 int err; 1693 1694 if (uart_console(&up->port) && console_suspend_enabled) { 1695 if (console_suspend_enabled) { 1696 err = pm_runtime_force_resume(dev); 1697 if (err) 1698 return err; 1699 } else 1700 genpd->flags = genpd_flags_console; 1701 } 1702 1703 serial8250_resume_port(priv->line); 1704 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1705 pm_runtime_mark_last_busy(dev); 1706 pm_runtime_put_autosuspend(dev); 1707 1708 return 0; 1709 } 1710 1711 static int omap8250_lost_context(struct uart_8250_port *up) 1712 { 1713 u32 val; 1714 1715 val = serial_in(up, UART_OMAP_SCR); 1716 /* 1717 * If we lose context, then SCR is set to its reset value of zero. 1718 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1719 * among other bits, to never set the register back to zero again. 1720 */ 1721 if (!val) 1722 return 1; 1723 return 0; 1724 } 1725 1726 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1727 { 1728 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1729 } 1730 1731 /* TODO: in future, this should happen via API in drivers/reset/ */ 1732 static int omap8250_soft_reset(struct device *dev) 1733 { 1734 struct omap8250_priv *priv = dev_get_drvdata(dev); 1735 int timeout = 100; 1736 int sysc; 1737 int syss; 1738 1739 /* 1740 * At least on omap4, unused uarts may not idle after reset without 1741 * a basic scr dma configuration even with no dma in use. The 1742 * module clkctrl status bits will be 1 instead of 3 blocking idle 1743 * for the whole clockdomain. The softreset below will clear scr, 1744 * and we restore it on resume so this is safe to do on all SoCs 1745 * needing omap8250_soft_reset() quirk. Do it in two writes as 1746 * recommended in the comment for omap8250_update_scr(). 1747 */ 1748 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1749 uart_write(priv, UART_OMAP_SCR, 1750 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1751 1752 sysc = uart_read(priv, UART_OMAP_SYSC); 1753 1754 /* softreset the UART */ 1755 sysc |= OMAP_UART_SYSC_SOFTRESET; 1756 uart_write(priv, UART_OMAP_SYSC, sysc); 1757 1758 /* By experiments, 1us enough for reset complete on AM335x */ 1759 do { 1760 udelay(1); 1761 syss = uart_read(priv, UART_OMAP_SYSS); 1762 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1763 1764 if (!timeout) { 1765 dev_err(dev, "timed out waiting for reset done\n"); 1766 return -ETIMEDOUT; 1767 } 1768 1769 return 0; 1770 } 1771 1772 static int omap8250_runtime_suspend(struct device *dev) 1773 { 1774 struct omap8250_priv *priv = dev_get_drvdata(dev); 1775 struct uart_8250_port *up = NULL; 1776 1777 if (priv->line >= 0) 1778 up = serial8250_get_port(priv->line); 1779 1780 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1781 int ret; 1782 1783 ret = omap8250_soft_reset(dev); 1784 if (ret) 1785 return ret; 1786 1787 if (up) { 1788 /* Restore to UART mode after reset (for wakeup) */ 1789 omap8250_update_mdr1(up, priv); 1790 /* Restore wakeup enable register */ 1791 serial_out(up, UART_OMAP_WER, priv->wer); 1792 } 1793 } 1794 1795 if (up && up->dma && up->dma->rxchan) 1796 omap_8250_rx_dma_flush(up); 1797 1798 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1799 schedule_work(&priv->qos_work); 1800 atomic_set(&priv->active, 0); 1801 1802 return 0; 1803 } 1804 1805 static int omap8250_runtime_resume(struct device *dev) 1806 { 1807 struct omap8250_priv *priv = dev_get_drvdata(dev); 1808 struct uart_8250_port *up = NULL; 1809 1810 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1811 if (atomic_read(&priv->active)) 1812 return 0; 1813 1814 if (priv->line >= 0) 1815 up = serial8250_get_port(priv->line); 1816 1817 if (up && omap8250_lost_context(up)) { 1818 uart_port_lock_irq(&up->port); 1819 omap8250_restore_regs(up); 1820 uart_port_unlock_irq(&up->port); 1821 } 1822 1823 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1824 uart_port_lock_irq(&up->port); 1825 omap_8250_rx_dma(up); 1826 uart_port_unlock_irq(&up->port); 1827 } 1828 1829 atomic_set(&priv->active, 1); 1830 priv->latency = priv->calc_latency; 1831 schedule_work(&priv->qos_work); 1832 1833 return 0; 1834 } 1835 1836 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1837 static int __init omap8250_console_fixup(void) 1838 { 1839 char *omap_str; 1840 char *options; 1841 u8 idx; 1842 1843 if (strstr(boot_command_line, "console=ttyS")) 1844 /* user set a ttyS based name for the console */ 1845 return 0; 1846 1847 omap_str = strstr(boot_command_line, "console=ttyO"); 1848 if (!omap_str) 1849 /* user did not set ttyO based console, so we don't care */ 1850 return 0; 1851 1852 omap_str += 12; 1853 if ('0' <= *omap_str && *omap_str <= '9') 1854 idx = *omap_str - '0'; 1855 else 1856 return 0; 1857 1858 omap_str++; 1859 if (omap_str[0] == ',') { 1860 omap_str++; 1861 options = omap_str; 1862 } else { 1863 options = NULL; 1864 } 1865 1866 add_preferred_console("ttyS", idx, options); 1867 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1868 idx, idx); 1869 pr_err("This ensures that you still see kernel messages. Please\n"); 1870 pr_err("update your kernel commandline.\n"); 1871 return 0; 1872 } 1873 console_initcall(omap8250_console_fixup); 1874 #endif 1875 1876 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1877 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1878 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1879 omap8250_runtime_resume, NULL) 1880 .prepare = pm_sleep_ptr(omap8250_prepare), 1881 .complete = pm_sleep_ptr(omap8250_complete), 1882 }; 1883 1884 static struct platform_driver omap8250_platform_driver = { 1885 .driver = { 1886 .name = "omap8250", 1887 .pm = pm_ptr(&omap8250_dev_pm_ops), 1888 .of_match_table = omap8250_dt_ids, 1889 }, 1890 .probe = omap8250_probe, 1891 .remove_new = omap8250_remove, 1892 }; 1893 module_platform_driver(omap8250_platform_driver); 1894 1895 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1896 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1897 MODULE_LICENSE("GPL v2"); 1898