1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 #include <linux/reboot.h> 31 #include <linux/pinctrl/consumer.h> 32 33 #include "8250.h" 34 35 #define DEFAULT_CLK_SPEED 48000000 36 #define OMAP_UART_REGSHIFT 2 37 38 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 39 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 40 #define OMAP_DMA_TX_KICK (1 << 2) 41 /* 42 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 43 * The same errata is applicable to AM335x and DRA7x processors too. 44 */ 45 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 46 #define UART_HAS_EFR2 BIT(4) 47 #define UART_HAS_RHR_IT_DIS BIT(5) 48 #define UART_RX_TIMEOUT_QUIRK BIT(6) 49 #define UART_HAS_NATIVE_RS485 BIT(7) 50 51 #define OMAP_UART_FCR_RX_TRIG 6 52 #define OMAP_UART_FCR_TX_TRIG 4 53 54 /* SCR register bitmasks */ 55 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 56 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 57 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 58 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 59 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 60 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 61 62 /* MVR register bitmasks */ 63 #define OMAP_UART_MVR_SCHEME_SHIFT 30 64 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 65 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 66 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 67 #define OMAP_UART_MVR_MAJ_MASK 0x700 68 #define OMAP_UART_MVR_MAJ_SHIFT 8 69 #define OMAP_UART_MVR_MIN_MASK 0x3f 70 71 /* SYSC register bitmasks */ 72 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 73 74 /* SYSS register bitmasks */ 75 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 76 77 #define UART_TI752_TLR_TX 0 78 #define UART_TI752_TLR_RX 4 79 80 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 81 #define TRIGGER_FCR_MASK(x) (x & 3) 82 83 /* Enable XON/XOFF flow control on output */ 84 #define OMAP_UART_SW_TX 0x08 85 /* Enable XON/XOFF flow control on input */ 86 #define OMAP_UART_SW_RX 0x02 87 88 #define OMAP_UART_WER_MOD_WKUP 0x7f 89 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 90 91 #define TX_TRIGGER 1 92 #define RX_TRIGGER 48 93 94 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 95 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 96 97 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 98 99 #define OMAP_UART_REV_46 0x0406 100 #define OMAP_UART_REV_52 0x0502 101 #define OMAP_UART_REV_63 0x0603 102 103 /* Interrupt Enable Register 2 */ 104 #define UART_OMAP_IER2 0x1B 105 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 106 107 /* Mode Definition Register 3 */ 108 #define UART_OMAP_MDR3 0x20 109 #define UART_OMAP_MDR3_DIR_POL BIT(3) 110 #define UART_OMAP_MDR3_DIR_EN BIT(4) 111 112 /* Enhanced features register 2 */ 113 #define UART_OMAP_EFR2 0x23 114 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 115 116 /* RX FIFO occupancy indicator */ 117 #define UART_OMAP_RX_LVL 0x19 118 119 /* Timeout low and High */ 120 #define UART_OMAP_TO_L 0x26 121 #define UART_OMAP_TO_H 0x27 122 123 struct omap8250_priv { 124 void __iomem *membase; 125 int line; 126 u8 habit; 127 u8 mdr1; 128 u8 mdr3; 129 u8 efr; 130 u8 scr; 131 u8 wer; 132 u8 xon; 133 u8 xoff; 134 u8 delayed_restore; 135 u16 quot; 136 137 u8 tx_trigger; 138 u8 rx_trigger; 139 atomic_t active; 140 bool is_suspending; 141 int wakeirq; 142 u32 latency; 143 u32 calc_latency; 144 struct pm_qos_request pm_qos_request; 145 struct work_struct qos_work; 146 struct uart_8250_dma omap8250_dma; 147 spinlock_t rx_dma_lock; 148 bool rx_dma_broken; 149 bool throttled; 150 151 struct pinctrl *pinctrl; 152 struct pinctrl_state *pinctrl_wakeup; 153 }; 154 155 struct omap8250_dma_params { 156 u32 rx_size; 157 u8 rx_trigger; 158 u8 tx_trigger; 159 }; 160 161 struct omap8250_platdata { 162 struct omap8250_dma_params *dma_params; 163 u8 habit; 164 }; 165 166 #ifdef CONFIG_SERIAL_8250_DMA 167 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 168 #else 169 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 170 #endif 171 172 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 173 { 174 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 175 } 176 177 /* 178 * Called on runtime PM resume path from omap8250_restore_regs(), and 179 * omap8250_set_mctrl(). 180 */ 181 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 182 { 183 struct uart_8250_port *up = up_to_u8250p(port); 184 struct omap8250_priv *priv = port->private_data; 185 u8 lcr; 186 187 serial8250_do_set_mctrl(port, mctrl); 188 189 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 190 /* 191 * Turn off autoRTS if RTS is lowered and restore autoRTS 192 * setting if RTS is raised 193 */ 194 lcr = serial_in(up, UART_LCR); 195 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 196 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 197 priv->efr |= UART_EFR_RTS; 198 else 199 priv->efr &= ~UART_EFR_RTS; 200 serial_out(up, UART_EFR, priv->efr); 201 serial_out(up, UART_LCR, lcr); 202 } 203 } 204 205 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 206 { 207 int err; 208 209 err = pm_runtime_resume_and_get(port->dev); 210 if (err) 211 return; 212 213 __omap8250_set_mctrl(port, mctrl); 214 215 pm_runtime_mark_last_busy(port->dev); 216 pm_runtime_put_autosuspend(port->dev); 217 } 218 219 /* 220 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 221 * The access to uart register after MDR1 Access 222 * causes UART to corrupt data. 223 * 224 * Need a delay = 225 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 226 * give 10 times as much 227 */ 228 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 229 struct omap8250_priv *priv) 230 { 231 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 232 udelay(2); 233 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 234 UART_FCR_CLEAR_RCVR); 235 } 236 237 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 238 struct omap8250_priv *priv) 239 { 240 unsigned int uartclk = port->uartclk; 241 unsigned int div_13, div_16; 242 unsigned int abs_d13, abs_d16; 243 244 /* 245 * Old custom speed handling. 246 */ 247 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 248 priv->quot = port->custom_divisor & UART_DIV_MAX; 249 /* 250 * I assume that nobody is using this. But hey, if somebody 251 * would like to specify the divisor _and_ the mode then the 252 * driver is ready and waiting for it. 253 */ 254 if (port->custom_divisor & (1 << 16)) 255 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 256 else 257 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 258 return; 259 } 260 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 261 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 262 263 if (!div_13) 264 div_13 = 1; 265 if (!div_16) 266 div_16 = 1; 267 268 abs_d13 = abs(baud - uartclk / 13 / div_13); 269 abs_d16 = abs(baud - uartclk / 16 / div_16); 270 271 if (abs_d13 >= abs_d16) { 272 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 273 priv->quot = div_16; 274 } else { 275 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 276 priv->quot = div_13; 277 } 278 } 279 280 static void omap8250_update_scr(struct uart_8250_port *up, 281 struct omap8250_priv *priv) 282 { 283 u8 old_scr; 284 285 old_scr = serial_in(up, UART_OMAP_SCR); 286 if (old_scr == priv->scr) 287 return; 288 289 /* 290 * The manual recommends not to enable the DMA mode selector in the SCR 291 * (instead of the FCR) register _and_ selecting the DMA mode as one 292 * register write because this may lead to malfunction. 293 */ 294 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 295 serial_out(up, UART_OMAP_SCR, 296 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 297 serial_out(up, UART_OMAP_SCR, priv->scr); 298 } 299 300 static void omap8250_update_mdr1(struct uart_8250_port *up, 301 struct omap8250_priv *priv) 302 { 303 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 304 omap_8250_mdr1_errataset(up, priv); 305 else 306 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 307 } 308 309 static void omap8250_restore_regs(struct uart_8250_port *up) 310 { 311 struct uart_port *port = &up->port; 312 struct omap8250_priv *priv = port->private_data; 313 struct uart_8250_dma *dma = up->dma; 314 u8 mcr = serial8250_in_MCR(up); 315 316 /* Port locked to synchronize UART_IER access against the console. */ 317 lockdep_assert_held_once(&port->lock); 318 319 if (dma && dma->tx_running) { 320 /* 321 * TCSANOW requests the change to occur immediately however if 322 * we have a TX-DMA operation in progress then it has been 323 * observed that it might stall and never complete. Therefore we 324 * delay DMA completes to prevent this hang from happen. 325 */ 326 priv->delayed_restore = 1; 327 return; 328 } 329 330 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 331 serial_out(up, UART_EFR, UART_EFR_ECB); 332 333 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 334 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 335 serial_out(up, UART_FCR, up->fcr); 336 337 omap8250_update_scr(up, priv); 338 339 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 340 341 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 342 OMAP_UART_TCR_HALT(52)); 343 serial_out(up, UART_TI752_TLR, 344 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 345 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 346 347 serial_out(up, UART_LCR, 0); 348 349 /* drop TCR + TLR access, we setup XON/XOFF later */ 350 serial8250_out_MCR(up, mcr); 351 352 serial_out(up, UART_IER, up->ier); 353 354 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 355 serial_dl_write(up, priv->quot); 356 357 serial_out(up, UART_EFR, priv->efr); 358 359 /* Configure flow control */ 360 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 361 serial_out(up, UART_XON1, priv->xon); 362 serial_out(up, UART_XOFF1, priv->xoff); 363 364 serial_out(up, UART_LCR, up->lcr); 365 366 omap8250_update_mdr1(up, priv); 367 368 __omap8250_set_mctrl(port, port->mctrl); 369 370 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 371 372 if (port->rs485.flags & SER_RS485_ENABLED && 373 port->rs485_config == serial8250_em485_config) 374 serial8250_em485_stop_tx(up, true); 375 } 376 377 static void omap_8250_set_termios_atomic(struct uart_port *port, struct ktermios *termios, 378 const struct ktermios *old, unsigned int baud) 379 { 380 struct uart_8250_port *up = up_to_u8250p(port); 381 struct omap8250_priv *priv = port->private_data; 382 u8 cval; 383 384 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 385 386 if (termios->c_cflag & CSTOPB) 387 cval |= UART_LCR_STOP; 388 if (termios->c_cflag & PARENB) 389 cval |= UART_LCR_PARITY; 390 if (!(termios->c_cflag & PARODD)) 391 cval |= UART_LCR_EPAR; 392 if (termios->c_cflag & CMSPAR) 393 cval |= UART_LCR_SPAR; 394 395 omap_8250_get_divisor(port, baud, priv); 396 397 /* 398 * Ok, we're now changing the port state. Do it with 399 * interrupts disabled. 400 */ 401 guard(serial8250_rpm)(up); 402 guard(uart_port_lock_irq)(port); 403 404 /* 405 * Update the per-port timeout. 406 */ 407 uart_update_timeout(port, termios->c_cflag, baud); 408 409 /* 410 * Specify which conditions may be considered for error 411 * handling and the ignoring of characters. The actual 412 * ignoring of characters only occurs if the bit is set 413 * in @ignore_status_mask as well. 414 */ 415 port->read_status_mask = UART_LSR_OE | UART_LSR_DR; 416 if (termios->c_iflag & INPCK) 417 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 418 if (termios->c_iflag & (IGNBRK | PARMRK)) 419 port->read_status_mask |= UART_LSR_BI; 420 421 /* 422 * Characters to ignore 423 */ 424 port->ignore_status_mask = 0; 425 if (termios->c_iflag & IGNPAR) 426 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 427 if (termios->c_iflag & IGNBRK) { 428 port->ignore_status_mask |= UART_LSR_BI; 429 /* 430 * If we're ignoring parity and break indicators, 431 * ignore overruns too (for real raw support). 432 */ 433 if (termios->c_iflag & IGNPAR) 434 port->ignore_status_mask |= UART_LSR_OE; 435 } 436 437 /* 438 * ignore all characters if CREAD is not set 439 */ 440 if ((termios->c_cflag & CREAD) == 0) 441 port->ignore_status_mask |= UART_LSR_DR; 442 443 /* 444 * Modem status interrupts 445 */ 446 up->ier &= ~UART_IER_MSI; 447 if (UART_ENABLE_MS(port, termios->c_cflag)) 448 up->ier |= UART_IER_MSI; 449 450 up->lcr = cval; 451 /* Up to here it was mostly serial8250_do_set_termios() */ 452 453 /* 454 * We enable TRIG_GRANU for RX and TX and additionally we set 455 * SCR_TX_EMPTY bit. The result is the following: 456 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 457 * - less than RX_TRIGGER number of bytes will also cause an interrupt 458 * once the UART decides that there no new bytes arriving. 459 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 460 * empty - the trigger level is ignored here. 461 * 462 * Once DMA is enabled: 463 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 464 * bytes in the TX FIFO. On each assert the DMA engine will move 465 * TX_TRIGGER bytes into the FIFO. 466 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 467 * the FIFO and move RX_TRIGGER bytes. 468 * This is because threshold and trigger values are the same. 469 */ 470 up->fcr = UART_FCR_ENABLE_FIFO; 471 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 472 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 473 474 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 475 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 476 477 if (up->dma) 478 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 479 OMAP_UART_SCR_DMAMODE_CTL; 480 481 priv->xon = termios->c_cc[VSTART]; 482 priv->xoff = termios->c_cc[VSTOP]; 483 484 priv->efr = 0; 485 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 486 487 if (termios->c_cflag & CRTSCTS && port->flags & UPF_HARD_FLOW && 488 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 489 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 490 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 491 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 492 priv->efr |= UART_EFR_CTS; 493 } else if (port->flags & UPF_SOFT_FLOW) { 494 /* 495 * OMAP rx s/w flow control is borked; the transmitter remains 496 * stuck off even if rx flow control is subsequently disabled 497 */ 498 499 /* 500 * IXOFF Flag: 501 * Enable XON/XOFF flow control on output. 502 * Transmit XON1, XOFF1 503 */ 504 if (termios->c_iflag & IXOFF) { 505 port->status |= UPSTAT_AUTOXOFF; 506 priv->efr |= OMAP_UART_SW_TX; 507 } 508 } 509 omap8250_restore_regs(up); 510 } 511 512 /* 513 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 514 * some differences in how we want to handle flow control. 515 */ 516 static void omap_8250_set_termios(struct uart_port *port, 517 struct ktermios *termios, 518 const struct ktermios *old) 519 { 520 struct omap8250_priv *priv = port->private_data; 521 unsigned int baud; 522 523 /* 524 * Ask the core to calculate the divisor for us. 525 */ 526 baud = uart_get_baud_rate(port, termios, old, 527 port->uartclk / 16 / UART_DIV_MAX, 528 port->uartclk / 13); 529 530 omap_8250_set_termios_atomic(port, termios, old, baud); 531 532 /* calculate wakeup latency constraint */ 533 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 534 priv->latency = priv->calc_latency; 535 536 schedule_work(&priv->qos_work); 537 538 /* Don't rewrite B0 */ 539 if (tty_termios_baud_rate(termios)) 540 tty_termios_encode_baud_rate(termios, baud, baud); 541 } 542 543 /* same as 8250 except that we may have extra flow bits set in EFR */ 544 static void omap_8250_pm(struct uart_port *port, unsigned int state, 545 unsigned int oldstate) 546 { 547 struct uart_8250_port *up = up_to_u8250p(port); 548 u8 efr; 549 550 guard(serial8250_rpm)(up); 551 /* Synchronize UART_IER access against the console. */ 552 guard(uart_port_lock_irq)(port); 553 554 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 555 efr = serial_in(up, UART_EFR); 556 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 557 serial_out(up, UART_LCR, 0); 558 559 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 560 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 561 serial_out(up, UART_EFR, efr); 562 serial_out(up, UART_LCR, 0); 563 } 564 565 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 566 struct omap8250_priv *priv) 567 { 568 static const struct soc_device_attribute k3_soc_devices[] = { 569 { .family = "AM65X", }, 570 { .family = "J721E", .revision = "SR1.0" }, 571 { /* sentinel */ } 572 }; 573 u32 mvr, scheme; 574 u16 revision, major, minor; 575 576 mvr = uart_read(priv, UART_OMAP_MVER); 577 578 /* Check revision register scheme */ 579 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 580 581 switch (scheme) { 582 case 0: /* Legacy Scheme: OMAP2/3 */ 583 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 584 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 585 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 586 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 587 break; 588 case 1: 589 /* New Scheme: OMAP4+ */ 590 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 591 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 592 OMAP_UART_MVR_MAJ_SHIFT; 593 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 594 break; 595 default: 596 dev_warn(up->port.dev, 597 "Unknown revision, defaulting to highest\n"); 598 /* highest possible revision */ 599 major = 0xff; 600 minor = 0xff; 601 } 602 /* normalize revision for the driver */ 603 revision = UART_BUILD_REVISION(major, minor); 604 605 switch (revision) { 606 case OMAP_UART_REV_46: 607 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 608 break; 609 case OMAP_UART_REV_52: 610 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 611 OMAP_UART_WER_HAS_TX_WAKEUP; 612 break; 613 case OMAP_UART_REV_63: 614 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 615 OMAP_UART_WER_HAS_TX_WAKEUP; 616 break; 617 default: 618 break; 619 } 620 621 /* 622 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 623 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 624 * to enable errata workaround. 625 */ 626 if (soc_device_match(k3_soc_devices)) 627 priv->habit &= ~UART_HAS_RHR_IT_DIS; 628 } 629 630 static void omap8250_uart_qos_work(struct work_struct *work) 631 { 632 struct omap8250_priv *priv; 633 634 priv = container_of(work, struct omap8250_priv, qos_work); 635 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 636 } 637 638 #ifdef CONFIG_SERIAL_8250_DMA 639 static int omap_8250_dma_handle_irq(struct uart_port *port); 640 #endif 641 642 static irqreturn_t omap8250_irq(int irq, void *dev_id) 643 { 644 struct omap8250_priv *priv = dev_id; 645 struct uart_8250_port *up = serial8250_get_port(priv->line); 646 struct uart_port *port = &up->port; 647 unsigned int iir, lsr; 648 int ret; 649 650 pm_runtime_get_noresume(port->dev); 651 652 /* Shallow idle state wake-up to an IO interrupt? */ 653 if (atomic_add_unless(&priv->active, 1, 1)) { 654 priv->latency = priv->calc_latency; 655 schedule_work(&priv->qos_work); 656 } 657 658 #ifdef CONFIG_SERIAL_8250_DMA 659 if (up->dma) { 660 ret = omap_8250_dma_handle_irq(port); 661 pm_runtime_mark_last_busy(port->dev); 662 pm_runtime_put(port->dev); 663 return IRQ_RETVAL(ret); 664 } 665 #endif 666 667 lsr = serial_port_in(port, UART_LSR); 668 iir = serial_port_in(port, UART_IIR); 669 ret = serial8250_handle_irq(port, iir); 670 671 /* 672 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 673 * FIFO has been drained or erroneously. 674 * So apply solution of Errata i2310 as mentioned in 675 * https://www.ti.com/lit/pdf/sprz536 676 */ 677 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 678 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 679 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 680 unsigned char efr2, timeout_h, timeout_l; 681 682 efr2 = serial_in(up, UART_OMAP_EFR2); 683 timeout_h = serial_in(up, UART_OMAP_TO_H); 684 timeout_l = serial_in(up, UART_OMAP_TO_L); 685 serial_out(up, UART_OMAP_TO_H, 0xFF); 686 serial_out(up, UART_OMAP_TO_L, 0xFF); 687 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 688 serial_in(up, UART_IIR); 689 serial_out(up, UART_OMAP_EFR2, efr2); 690 serial_out(up, UART_OMAP_TO_H, timeout_h); 691 serial_out(up, UART_OMAP_TO_L, timeout_l); 692 } 693 694 /* Stop processing interrupts on input overrun */ 695 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 696 unsigned long delay; 697 698 /* Synchronize UART_IER access against the console. */ 699 uart_port_lock(port); 700 up->ier = serial_port_in(port, UART_IER); 701 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 702 port->ops->stop_rx(port); 703 } else { 704 /* Keep restarting the timer until 705 * the input overrun subsides. 706 */ 707 cancel_delayed_work(&up->overrun_backoff); 708 } 709 uart_port_unlock(port); 710 711 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 712 schedule_delayed_work(&up->overrun_backoff, delay); 713 } 714 715 pm_runtime_mark_last_busy(port->dev); 716 pm_runtime_put(port->dev); 717 718 return IRQ_RETVAL(ret); 719 } 720 721 static int omap_8250_startup(struct uart_port *port) 722 { 723 struct uart_8250_port *up = up_to_u8250p(port); 724 struct omap8250_priv *priv = port->private_data; 725 struct uart_8250_dma *dma = &priv->omap8250_dma; 726 int ret; 727 728 if (priv->wakeirq) { 729 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 730 if (ret) 731 return ret; 732 } 733 734 #ifdef CONFIG_PM 735 up->capabilities |= UART_CAP_RPM; 736 #endif 737 738 guard(serial8250_rpm)(up); 739 740 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 741 742 serial_out(up, UART_LCR, UART_LCR_WLEN8); 743 744 up->lsr_saved_flags = 0; 745 up->msr_saved_flags = 0; 746 747 /* Disable DMA for console UART */ 748 if (dma->fn && !uart_console(port)) { 749 up->dma = &priv->omap8250_dma; 750 ret = serial8250_request_dma(up); 751 if (ret) { 752 dev_warn_ratelimited(port->dev, 753 "failed to request DMA\n"); 754 up->dma = NULL; 755 } 756 } else { 757 up->dma = NULL; 758 } 759 760 /* Synchronize UART_IER access against the console. */ 761 scoped_guard(uart_port_lock_irq, port) { 762 up->ier = UART_IER_RLSI | UART_IER_RDI; 763 serial_out(up, UART_IER, up->ier); 764 } 765 766 /* Enable module level wake up */ 767 priv->wer = OMAP_UART_WER_MOD_WKUP; 768 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 769 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 770 serial_out(up, UART_OMAP_WER, priv->wer); 771 772 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 773 guard(uart_port_lock_irq)(port); 774 up->dma->rx_dma(up); 775 } 776 777 enable_irq(port->irq); 778 779 return 0; 780 } 781 782 static void omap_8250_shutdown(struct uart_port *port) 783 { 784 struct uart_8250_port *up = up_to_u8250p(port); 785 struct omap8250_priv *priv = port->private_data; 786 787 guard(serial8250_rpm)(up); 788 789 flush_work(&priv->qos_work); 790 if (up->dma) 791 omap_8250_rx_dma_flush(up); 792 793 serial_out(up, UART_OMAP_WER, 0); 794 if (priv->habit & UART_HAS_EFR2) 795 serial_out(up, UART_OMAP_EFR2, 0x0); 796 797 /* Synchronize UART_IER access against the console. */ 798 scoped_guard(uart_port_lock_irq, port) { 799 up->ier = 0; 800 serial_out(up, UART_IER, 0); 801 } 802 803 disable_irq_nosync(port->irq); 804 dev_pm_clear_wake_irq(port->dev); 805 806 serial8250_release_dma(up); 807 up->dma = NULL; 808 809 /* 810 * Disable break condition and FIFOs 811 */ 812 if (up->lcr & UART_LCR_SBC) 813 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 814 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 815 } 816 817 static void omap_8250_throttle(struct uart_port *port) 818 { 819 struct omap8250_priv *priv = port->private_data; 820 821 guard(serial8250_rpm)(up_to_u8250p(port)); 822 guard(uart_port_lock_irqsave)(port); 823 824 port->ops->stop_rx(port); 825 priv->throttled = true; 826 } 827 828 static void omap_8250_unthrottle(struct uart_port *port) 829 { 830 struct omap8250_priv *priv = port->private_data; 831 struct uart_8250_port *up = up_to_u8250p(port); 832 833 guard(serial8250_rpm)(up); 834 /* Synchronize UART_IER access against the console. */ 835 guard(uart_port_lock_irqsave)(port); 836 837 priv->throttled = false; 838 if (up->dma) 839 up->dma->rx_dma(up); 840 up->ier |= UART_IER_RLSI | UART_IER_RDI; 841 serial_out(up, UART_IER, up->ier); 842 } 843 844 static int omap8250_rs485_config(struct uart_port *port, 845 struct ktermios *termios, 846 struct serial_rs485 *rs485) 847 { 848 struct omap8250_priv *priv = port->private_data; 849 struct uart_8250_port *up = up_to_u8250p(port); 850 u32 fixed_delay_rts_before_send = 0; 851 u32 fixed_delay_rts_after_send = 0; 852 unsigned int baud; 853 854 /* 855 * There is a fixed delay of 3 bit clock cycles after the TX shift 856 * register is going empty to allow time for the stop bit to transition 857 * through the transceiver before direction is changed to receive. 858 * 859 * Additionally there appears to be a 1 bit clock delay between writing 860 * to the THR register and transmission of the start bit, per page 8783 861 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 862 */ 863 if (priv->quot) { 864 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 865 baud = port->uartclk / (16 * priv->quot); 866 else 867 baud = port->uartclk / (13 * priv->quot); 868 869 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 870 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 871 } 872 873 /* 874 * Fall back to RS485 software emulation if the UART is missing 875 * hardware support, if the device tree specifies an mctrl_gpio 876 * (indicates that RTS is unavailable due to a pinmux conflict) 877 * or if the requested delays exceed the fixed hardware delays. 878 */ 879 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 880 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 881 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 882 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 883 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 884 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 885 886 port->rs485_config = serial8250_em485_config; 887 return serial8250_em485_config(port, termios, rs485); 888 } 889 890 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 891 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 892 893 if (rs485->flags & SER_RS485_ENABLED) 894 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 895 else 896 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 897 898 /* 899 * Retain same polarity semantics as RS485 software emulation, 900 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 901 */ 902 if (rs485->flags & SER_RS485_RTS_ON_SEND) 903 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 904 else 905 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 906 907 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 908 909 return 0; 910 } 911 912 #ifdef CONFIG_SERIAL_8250_DMA 913 static int omap_8250_rx_dma(struct uart_8250_port *p); 914 915 /* Must be called while priv->rx_dma_lock is held */ 916 static void __dma_rx_do_complete(struct uart_8250_port *p) 917 { 918 struct uart_8250_dma *dma = p->dma; 919 struct tty_port *tty_port = &p->port.state->port; 920 struct omap8250_priv *priv = p->port.private_data; 921 struct dma_chan *rxchan = dma->rxchan; 922 dma_cookie_t cookie; 923 struct dma_tx_state state; 924 int count; 925 int ret; 926 u32 reg; 927 928 if (!dma->rx_running) 929 goto out; 930 931 cookie = dma->rx_cookie; 932 dma->rx_running = 0; 933 934 /* Re-enable RX FIFO interrupt now that transfer is complete */ 935 if (priv->habit & UART_HAS_RHR_IT_DIS) { 936 reg = serial_in(p, UART_OMAP_IER2); 937 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 938 serial_out(p, UART_OMAP_IER2, reg); 939 } 940 941 dmaengine_tx_status(rxchan, cookie, &state); 942 943 count = dma->rx_size - state.residue + state.in_flight_bytes; 944 if (count < dma->rx_size) { 945 dmaengine_terminate_async(rxchan); 946 947 /* 948 * Poll for teardown to complete which guarantees in 949 * flight data is drained. 950 */ 951 if (state.in_flight_bytes) { 952 int poll_count = 25; 953 954 while (dmaengine_tx_status(rxchan, cookie, NULL) && 955 poll_count--) 956 cpu_relax(); 957 958 if (poll_count == -1) 959 dev_err(p->port.dev, "teardown incomplete\n"); 960 } 961 } 962 if (!count) 963 goto out; 964 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 965 966 p->port.icount.rx += ret; 967 p->port.icount.buf_overrun += count - ret; 968 out: 969 970 tty_flip_buffer_push(tty_port); 971 } 972 973 static void __dma_rx_complete(void *param) 974 { 975 struct uart_8250_port *p = param; 976 struct omap8250_priv *priv = p->port.private_data; 977 struct uart_8250_dma *dma = p->dma; 978 struct dma_tx_state state; 979 980 /* Synchronize UART_IER access against the console. */ 981 guard(uart_port_lock_irqsave)(&p->port); 982 983 /* 984 * If the tx status is not DMA_COMPLETE, then this is a delayed 985 * completion callback. A previous RX timeout flush would have 986 * already pushed the data, so exit. 987 */ 988 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != DMA_COMPLETE) 989 return; 990 991 __dma_rx_do_complete(p); 992 if (priv->throttled) 993 return; 994 995 p->ier |= UART_IER_RLSI | UART_IER_RDI; 996 serial_out(p, UART_IER, p->ier); 997 if (!(priv->habit & UART_HAS_EFR2)) 998 omap_8250_rx_dma(p); 999 } 1000 1001 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 1002 { 1003 struct omap8250_priv *priv = p->port.private_data; 1004 struct uart_8250_dma *dma = p->dma; 1005 struct dma_tx_state state; 1006 unsigned long flags; 1007 int ret; 1008 1009 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1010 1011 if (!dma->rx_running) { 1012 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1013 return; 1014 } 1015 1016 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1017 if (ret == DMA_IN_PROGRESS) { 1018 ret = dmaengine_pause(dma->rxchan); 1019 if (WARN_ON_ONCE(ret)) 1020 priv->rx_dma_broken = true; 1021 } 1022 __dma_rx_do_complete(p); 1023 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1024 } 1025 1026 static int omap_8250_rx_dma(struct uart_8250_port *p) 1027 { 1028 struct omap8250_priv *priv = p->port.private_data; 1029 struct uart_8250_dma *dma = p->dma; 1030 int err = 0; 1031 struct dma_async_tx_descriptor *desc; 1032 unsigned long flags; 1033 u32 reg; 1034 1035 /* Port locked to synchronize UART_IER access against the console. */ 1036 lockdep_assert_held_once(&p->port.lock); 1037 1038 if (priv->rx_dma_broken) 1039 return -EINVAL; 1040 1041 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1042 1043 if (dma->rx_running) { 1044 enum dma_status state; 1045 1046 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1047 if (state == DMA_COMPLETE) { 1048 /* 1049 * Disable RX interrupts to allow RX DMA completion 1050 * callback to run. 1051 */ 1052 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1053 serial_out(p, UART_IER, p->ier); 1054 } 1055 goto out; 1056 } 1057 1058 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1059 dma->rx_size, DMA_DEV_TO_MEM, 1060 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1061 if (!desc) { 1062 err = -EBUSY; 1063 goto out; 1064 } 1065 1066 dma->rx_running = 1; 1067 desc->callback = __dma_rx_complete; 1068 desc->callback_param = p; 1069 1070 dma->rx_cookie = dmaengine_submit(desc); 1071 1072 /* 1073 * Disable RX FIFO interrupt while RX DMA is enabled, else 1074 * spurious interrupt may be raised when data is in the RX FIFO 1075 * but is yet to be drained by DMA. 1076 */ 1077 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1078 reg = serial_in(p, UART_OMAP_IER2); 1079 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1080 serial_out(p, UART_OMAP_IER2, reg); 1081 } 1082 1083 dma_async_issue_pending(dma->rxchan); 1084 out: 1085 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1086 return err; 1087 } 1088 1089 static int omap_8250_tx_dma(struct uart_8250_port *p); 1090 1091 static void omap_8250_dma_tx_complete(void *param) 1092 { 1093 struct uart_8250_port *p = param; 1094 struct uart_8250_dma *dma = p->dma; 1095 struct tty_port *tport = &p->port.state->port; 1096 bool en_thri = false; 1097 struct omap8250_priv *priv = p->port.private_data; 1098 1099 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1100 UART_XMIT_SIZE, DMA_TO_DEVICE); 1101 1102 guard(uart_port_lock_irqsave)(&p->port); 1103 1104 dma->tx_running = 0; 1105 1106 uart_xmit_advance(&p->port, dma->tx_size); 1107 1108 if (priv->delayed_restore) { 1109 priv->delayed_restore = 0; 1110 omap8250_restore_regs(p); 1111 } 1112 1113 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1114 uart_write_wakeup(&p->port); 1115 1116 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1117 int ret; 1118 1119 ret = omap_8250_tx_dma(p); 1120 if (ret) 1121 en_thri = true; 1122 } else if (p->capabilities & UART_CAP_RPM) { 1123 en_thri = true; 1124 } 1125 1126 if (en_thri) { 1127 dma->tx_err = 1; 1128 serial8250_set_THRI(p); 1129 } 1130 } 1131 1132 static int omap_8250_tx_dma(struct uart_8250_port *p) 1133 { 1134 struct uart_8250_dma *dma = p->dma; 1135 struct omap8250_priv *priv = p->port.private_data; 1136 struct tty_port *tport = &p->port.state->port; 1137 struct dma_async_tx_descriptor *desc; 1138 struct scatterlist sg; 1139 int skip_byte = -1; 1140 int ret; 1141 1142 if (dma->tx_running) 1143 return 0; 1144 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1145 1146 /* 1147 * Even if no data, we need to return an error for the two cases 1148 * below so serial8250_tx_chars() is invoked and properly clears 1149 * THRI and/or runtime suspend. 1150 */ 1151 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1152 ret = -EBUSY; 1153 goto err; 1154 } 1155 serial8250_clear_THRI(p); 1156 return 0; 1157 } 1158 1159 if (priv->habit & OMAP_DMA_TX_KICK) { 1160 unsigned char c; 1161 u8 tx_lvl; 1162 1163 /* 1164 * We need to put the first byte into the FIFO in order to start 1165 * the DMA transfer. For transfers smaller than four bytes we 1166 * don't bother doing DMA at all. It seem not matter if there 1167 * are still bytes in the FIFO from the last transfer (in case 1168 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1169 * leaving the FIFO seem not to trigger the DMA transfer. It is 1170 * really the byte that we put into the FIFO. 1171 * If the FIFO is already full then we most likely got here from 1172 * omap_8250_dma_tx_complete(). And this means the DMA engine 1173 * just completed its work. We don't have to wait the complete 1174 * 86us at 115200,8n1 but around 60us (not to mention lower 1175 * baudrates). So in that case we take the interrupt and try 1176 * again with an empty FIFO. 1177 */ 1178 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1179 if (tx_lvl == p->tx_loadsz) { 1180 ret = -EBUSY; 1181 goto err; 1182 } 1183 if (kfifo_len(&tport->xmit_fifo) < 4) { 1184 ret = -EINVAL; 1185 goto err; 1186 } 1187 if (!uart_fifo_out(&p->port, &c, 1)) { 1188 ret = -EINVAL; 1189 goto err; 1190 } 1191 skip_byte = c; 1192 } 1193 1194 sg_init_table(&sg, 1); 1195 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, UART_XMIT_SIZE, dma->tx_addr); 1196 if (ret != 1) { 1197 ret = -EINVAL; 1198 goto err; 1199 } 1200 1201 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1202 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1203 if (!desc) { 1204 ret = -EBUSY; 1205 goto err; 1206 } 1207 1208 dma->tx_size = sg_dma_len(&sg); 1209 dma->tx_running = 1; 1210 1211 desc->callback = omap_8250_dma_tx_complete; 1212 desc->callback_param = p; 1213 1214 dma->tx_cookie = dmaengine_submit(desc); 1215 1216 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1217 UART_XMIT_SIZE, DMA_TO_DEVICE); 1218 1219 dma_async_issue_pending(dma->txchan); 1220 if (dma->tx_err) 1221 dma->tx_err = 0; 1222 1223 serial8250_clear_THRI(p); 1224 ret = 0; 1225 goto out_skip; 1226 err: 1227 dma->tx_err = 1; 1228 out_skip: 1229 if (skip_byte >= 0) 1230 serial_out(p, UART_TX, skip_byte); 1231 return ret; 1232 } 1233 1234 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1235 { 1236 switch (iir & 0x3f) { 1237 case UART_IIR_RLSI: 1238 case UART_IIR_RX_TIMEOUT: 1239 case UART_IIR_RDI: 1240 omap_8250_rx_dma_flush(up); 1241 return true; 1242 } 1243 return omap_8250_rx_dma(up); 1244 } 1245 1246 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1247 { 1248 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1249 (iir & UART_IIR_RDI)) { 1250 if (handle_rx_dma(up, iir)) { 1251 status = serial8250_rx_chars(up, status); 1252 omap_8250_rx_dma(up); 1253 } 1254 } 1255 1256 return status; 1257 } 1258 1259 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1260 u16 status) 1261 { 1262 /* Port locked to synchronize UART_IER access against the console. */ 1263 lockdep_assert_held_once(&up->port.lock); 1264 1265 /* 1266 * Queue a new transfer if FIFO has data. 1267 */ 1268 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1269 (up->ier & UART_IER_RDI)) { 1270 omap_8250_rx_dma(up); 1271 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1272 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1273 /* 1274 * Disable RX timeout, read IIR to clear 1275 * current timeout condition, clear EFR2 to 1276 * periodic timeouts, re-enable interrupts. 1277 */ 1278 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1279 serial_out(up, UART_IER, up->ier); 1280 omap_8250_rx_dma_flush(up); 1281 serial_in(up, UART_IIR); 1282 serial_out(up, UART_OMAP_EFR2, 0x0); 1283 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1284 serial_out(up, UART_IER, up->ier); 1285 } 1286 } 1287 1288 /* 1289 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1290 * hook for RX/TX and need different logic for them in the ISR. Therefore we 1291 * use the default routine in the non-DMA case and this one for with DMA. 1292 */ 1293 static int omap_8250_dma_handle_irq(struct uart_port *port) 1294 { 1295 struct uart_8250_port *up = up_to_u8250p(port); 1296 struct omap8250_priv *priv = port->private_data; 1297 u16 status; 1298 u8 iir; 1299 1300 iir = serial_port_in(port, UART_IIR); 1301 if (iir & UART_IIR_NO_INT) { 1302 return IRQ_HANDLED; 1303 } 1304 1305 uart_port_lock(port); 1306 1307 status = serial_port_in(port, UART_LSR); 1308 1309 if ((iir & 0x3f) != UART_IIR_THRI) { 1310 if (priv->habit & UART_HAS_EFR2) 1311 am654_8250_handle_rx_dma(up, iir, status); 1312 else 1313 status = omap_8250_handle_rx_dma(up, iir, status); 1314 } 1315 1316 serial8250_modem_status(up); 1317 if (status & UART_LSR_THRE && up->dma->tx_err) { 1318 if (uart_tx_stopped(port) || 1319 kfifo_is_empty(&port->state->port.xmit_fifo)) { 1320 up->dma->tx_err = 0; 1321 serial8250_tx_chars(up); 1322 } else { 1323 /* 1324 * try again due to an earlier failure which 1325 * might have been resolved by now. 1326 */ 1327 if (omap_8250_tx_dma(up)) 1328 serial8250_tx_chars(up); 1329 } 1330 } 1331 1332 uart_unlock_and_check_sysrq(port); 1333 1334 return 1; 1335 } 1336 1337 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1338 { 1339 return false; 1340 } 1341 1342 #else 1343 1344 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1345 { 1346 return -EINVAL; 1347 } 1348 #endif 1349 1350 static int omap8250_no_handle_irq(struct uart_port *port) 1351 { 1352 /* IRQ has not been requested but handling irq? */ 1353 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1354 return 0; 1355 } 1356 1357 static int omap8250_select_wakeup_pinctrl(struct device *dev, 1358 struct omap8250_priv *priv) 1359 { 1360 if (IS_ERR_OR_NULL(priv->pinctrl_wakeup)) 1361 return 0; 1362 1363 if (!device_may_wakeup(dev)) 1364 return 0; 1365 1366 return pinctrl_select_state(priv->pinctrl, priv->pinctrl_wakeup); 1367 } 1368 1369 static struct omap8250_dma_params am654_dma = { 1370 .rx_size = SZ_2K, 1371 .rx_trigger = 1, 1372 .tx_trigger = TX_TRIGGER, 1373 }; 1374 1375 static struct omap8250_dma_params am33xx_dma = { 1376 .rx_size = RX_TRIGGER, 1377 .rx_trigger = RX_TRIGGER, 1378 .tx_trigger = TX_TRIGGER, 1379 }; 1380 1381 static struct omap8250_platdata am654_platdata = { 1382 .dma_params = &am654_dma, 1383 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1384 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1385 }; 1386 1387 static struct omap8250_platdata am33xx_platdata = { 1388 .dma_params = &am33xx_dma, 1389 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1390 }; 1391 1392 static struct omap8250_platdata omap4_platdata = { 1393 .dma_params = &am33xx_dma, 1394 .habit = UART_ERRATA_CLOCK_DISABLE, 1395 }; 1396 1397 static const struct of_device_id omap8250_dt_ids[] = { 1398 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1399 { .compatible = "ti,omap2-uart" }, 1400 { .compatible = "ti,omap3-uart" }, 1401 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1402 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1403 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1404 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1405 {}, 1406 }; 1407 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1408 1409 static int omap8250_probe(struct platform_device *pdev) 1410 { 1411 struct device_node *np = pdev->dev.of_node; 1412 struct omap8250_priv *priv; 1413 const struct omap8250_platdata *pdata; 1414 struct uart_8250_port up; 1415 struct resource *regs; 1416 void __iomem *membase; 1417 int ret; 1418 1419 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1420 if (!regs) { 1421 dev_err(&pdev->dev, "missing registers\n"); 1422 return -EINVAL; 1423 } 1424 1425 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1426 if (!priv) 1427 return -ENOMEM; 1428 1429 membase = devm_ioremap(&pdev->dev, regs->start, 1430 resource_size(regs)); 1431 if (!membase) 1432 return -ENODEV; 1433 1434 memset(&up, 0, sizeof(up)); 1435 up.port.dev = &pdev->dev; 1436 up.port.mapbase = regs->start; 1437 up.port.membase = membase; 1438 /* 1439 * It claims to be 16C750 compatible however it is a little different. 1440 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1441 * have) is enabled via EFR instead of MCR. The type is set here 8250 1442 * just to get things going. UNKNOWN does not work for a few reasons and 1443 * we don't need our own type since we don't use 8250's set_termios() 1444 * or pm callback. 1445 */ 1446 up.port.type = PORT_8250; 1447 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1448 up.port.private_data = priv; 1449 1450 up.tx_loadsz = 64; 1451 up.capabilities = UART_CAP_FIFO; 1452 #ifdef CONFIG_PM 1453 /* 1454 * Runtime PM is mostly transparent. However to do it right we need to a 1455 * TX empty interrupt before we can put the device to auto idle. So if 1456 * PM is not enabled we don't add that flag and can spare that one extra 1457 * interrupt in the TX path. 1458 */ 1459 up.capabilities |= UART_CAP_RPM; 1460 #endif 1461 up.port.set_termios = omap_8250_set_termios; 1462 up.port.set_mctrl = omap8250_set_mctrl; 1463 up.port.pm = omap_8250_pm; 1464 up.port.startup = omap_8250_startup; 1465 up.port.shutdown = omap_8250_shutdown; 1466 up.port.throttle = omap_8250_throttle; 1467 up.port.unthrottle = omap_8250_unthrottle; 1468 up.port.rs485_config = omap8250_rs485_config; 1469 /* same rs485_supported for software emulation and native RS485 */ 1470 up.port.rs485_supported = serial8250_em485_supported; 1471 up.rs485_start_tx = serial8250_em485_start_tx; 1472 up.rs485_stop_tx = serial8250_em485_stop_tx; 1473 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1474 1475 ret = uart_read_port_properties(&up.port); 1476 if (ret) 1477 return ret; 1478 1479 up.port.regshift = OMAP_UART_REGSHIFT; 1480 up.port.fifosize = 64; 1481 1482 if (!up.port.uartclk) { 1483 struct clk *clk; 1484 1485 clk = devm_clk_get(&pdev->dev, NULL); 1486 if (IS_ERR(clk)) { 1487 if (PTR_ERR(clk) == -EPROBE_DEFER) 1488 return -EPROBE_DEFER; 1489 } else { 1490 up.port.uartclk = clk_get_rate(clk); 1491 } 1492 } 1493 1494 if (of_property_read_u32(np, "overrun-throttle-ms", 1495 &up.overrun_backoff_time_ms) != 0) 1496 up.overrun_backoff_time_ms = 0; 1497 1498 pdata = of_device_get_match_data(&pdev->dev); 1499 if (pdata) 1500 priv->habit |= pdata->habit; 1501 1502 if (!up.port.uartclk) { 1503 up.port.uartclk = DEFAULT_CLK_SPEED; 1504 dev_warn(&pdev->dev, 1505 "No clock speed specified: using default: %d\n", 1506 DEFAULT_CLK_SPEED); 1507 } 1508 1509 priv->membase = membase; 1510 priv->line = -ENODEV; 1511 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1512 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1513 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1514 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1515 1516 spin_lock_init(&priv->rx_dma_lock); 1517 1518 platform_set_drvdata(pdev, priv); 1519 1520 device_set_wakeup_capable(&pdev->dev, true); 1521 if (of_property_read_bool(np, "wakeup-source")) 1522 device_set_wakeup_enable(&pdev->dev, true); 1523 1524 pm_runtime_enable(&pdev->dev); 1525 pm_runtime_use_autosuspend(&pdev->dev); 1526 1527 /* 1528 * Disable runtime PM until autosuspend delay unless specifically 1529 * enabled by the user via sysfs. This is the historic way to 1530 * prevent an unsafe default policy with lossy characters on wake-up. 1531 * For serdev devices this is not needed, the policy can be managed by 1532 * the serdev driver. 1533 */ 1534 if (!of_get_available_child_count(pdev->dev.of_node)) 1535 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1536 1537 pm_runtime_get_sync(&pdev->dev); 1538 1539 omap_serial_fill_features_erratas(&up, priv); 1540 up.port.handle_irq = omap8250_no_handle_irq; 1541 priv->rx_trigger = RX_TRIGGER; 1542 priv->tx_trigger = TX_TRIGGER; 1543 #ifdef CONFIG_SERIAL_8250_DMA 1544 /* 1545 * Oh DMA support. If there are no DMA properties in the DT then 1546 * we will fall back to a generic DMA channel which does not 1547 * really work here. To ensure that we do not get a generic DMA 1548 * channel assigned, we have the the_no_dma_filter_fn() here. 1549 * To avoid "failed to request DMA" messages we check for DMA 1550 * properties in DT. 1551 */ 1552 ret = of_property_count_strings(np, "dma-names"); 1553 if (ret == 2) { 1554 struct omap8250_dma_params *dma_params = NULL; 1555 struct uart_8250_dma *dma = &priv->omap8250_dma; 1556 1557 dma->fn = the_no_dma_filter_fn; 1558 dma->tx_dma = omap_8250_tx_dma; 1559 dma->rx_dma = omap_8250_rx_dma; 1560 if (pdata) 1561 dma_params = pdata->dma_params; 1562 1563 if (dma_params) { 1564 dma->rx_size = dma_params->rx_size; 1565 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1566 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1567 priv->rx_trigger = dma_params->rx_trigger; 1568 priv->tx_trigger = dma_params->tx_trigger; 1569 } else { 1570 dma->rx_size = RX_TRIGGER; 1571 dma->rxconf.src_maxburst = RX_TRIGGER; 1572 dma->txconf.dst_maxburst = TX_TRIGGER; 1573 } 1574 } 1575 #endif 1576 1577 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1578 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1579 dev_name(&pdev->dev), priv); 1580 if (ret < 0) 1581 goto err; 1582 1583 priv->wakeirq = irq_of_parse_and_map(np, 1); 1584 1585 ret = serial8250_register_8250_port(&up); 1586 if (ret < 0) { 1587 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1588 goto err; 1589 } 1590 priv->line = ret; 1591 pm_runtime_mark_last_busy(&pdev->dev); 1592 pm_runtime_put_autosuspend(&pdev->dev); 1593 1594 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1595 if (!IS_ERR_OR_NULL(priv->pinctrl)) 1596 priv->pinctrl_wakeup = pinctrl_lookup_state(priv->pinctrl, "wakeup"); 1597 1598 return 0; 1599 err: 1600 pm_runtime_dont_use_autosuspend(&pdev->dev); 1601 pm_runtime_put_sync(&pdev->dev); 1602 flush_work(&priv->qos_work); 1603 pm_runtime_disable(&pdev->dev); 1604 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1605 return ret; 1606 } 1607 1608 static void omap8250_remove(struct platform_device *pdev) 1609 { 1610 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1611 struct uart_8250_port *up; 1612 int err; 1613 1614 err = pm_runtime_resume_and_get(&pdev->dev); 1615 if (err) 1616 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1617 1618 up = serial8250_get_port(priv->line); 1619 omap_8250_shutdown(&up->port); 1620 serial8250_unregister_port(priv->line); 1621 priv->line = -ENODEV; 1622 pm_runtime_dont_use_autosuspend(&pdev->dev); 1623 pm_runtime_put_sync(&pdev->dev); 1624 flush_work(&priv->qos_work); 1625 pm_runtime_disable(&pdev->dev); 1626 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1627 device_set_wakeup_capable(&pdev->dev, false); 1628 } 1629 1630 static int omap8250_prepare(struct device *dev) 1631 { 1632 struct omap8250_priv *priv = dev_get_drvdata(dev); 1633 1634 if (!priv) 1635 return 0; 1636 priv->is_suspending = true; 1637 return 0; 1638 } 1639 1640 static void omap8250_complete(struct device *dev) 1641 { 1642 struct omap8250_priv *priv = dev_get_drvdata(dev); 1643 1644 if (!priv) 1645 return; 1646 priv->is_suspending = false; 1647 } 1648 1649 static int omap8250_suspend(struct device *dev) 1650 { 1651 struct omap8250_priv *priv = dev_get_drvdata(dev); 1652 struct uart_8250_port *up = serial8250_get_port(priv->line); 1653 int err = 0; 1654 1655 err = omap8250_select_wakeup_pinctrl(dev, priv); 1656 if (err) { 1657 dev_err(dev, "Failed to select wakeup pinctrl, aborting suspend %pe\n", 1658 ERR_PTR(err)); 1659 return err; 1660 } 1661 1662 serial8250_suspend_port(priv->line); 1663 1664 err = pm_runtime_resume_and_get(dev); 1665 if (err) 1666 return err; 1667 if (!device_may_wakeup(dev)) 1668 priv->wer = 0; 1669 serial_out(up, UART_OMAP_WER, priv->wer); 1670 if (uart_console(&up->port) && console_suspend_enabled) 1671 err = pm_runtime_force_suspend(dev); 1672 flush_work(&priv->qos_work); 1673 1674 return err; 1675 } 1676 1677 static int omap8250_resume(struct device *dev) 1678 { 1679 struct omap8250_priv *priv = dev_get_drvdata(dev); 1680 struct uart_8250_port *up = serial8250_get_port(priv->line); 1681 int err; 1682 1683 err = pinctrl_select_default_state(dev); 1684 if (err) { 1685 dev_err(dev, "Failed to select default pinctrl state on resume: %pe\n", 1686 ERR_PTR(err)); 1687 return err; 1688 } 1689 1690 if (uart_console(&up->port) && console_suspend_enabled) { 1691 err = pm_runtime_force_resume(dev); 1692 if (err) 1693 return err; 1694 } 1695 1696 serial8250_resume_port(priv->line); 1697 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1698 pm_runtime_mark_last_busy(dev); 1699 pm_runtime_put_autosuspend(dev); 1700 1701 return 0; 1702 } 1703 1704 static int omap8250_lost_context(struct uart_8250_port *up) 1705 { 1706 u32 val; 1707 1708 val = serial_in(up, UART_OMAP_SCR); 1709 /* 1710 * If we lose context, then SCR is set to its reset value of zero. 1711 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1712 * among other bits, to never set the register back to zero again. 1713 */ 1714 if (!val) 1715 return 1; 1716 return 0; 1717 } 1718 1719 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1720 { 1721 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1722 } 1723 1724 /* TODO: in future, this should happen via API in drivers/reset/ */ 1725 static int omap8250_soft_reset(struct device *dev) 1726 { 1727 struct omap8250_priv *priv = dev_get_drvdata(dev); 1728 int timeout = 100; 1729 int sysc; 1730 int syss; 1731 1732 /* 1733 * At least on omap4, unused uarts may not idle after reset without 1734 * a basic scr dma configuration even with no dma in use. The 1735 * module clkctrl status bits will be 1 instead of 3 blocking idle 1736 * for the whole clockdomain. The softreset below will clear scr, 1737 * and we restore it on resume so this is safe to do on all SoCs 1738 * needing omap8250_soft_reset() quirk. Do it in two writes as 1739 * recommended in the comment for omap8250_update_scr(). 1740 */ 1741 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1742 uart_write(priv, UART_OMAP_SCR, 1743 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1744 1745 sysc = uart_read(priv, UART_OMAP_SYSC); 1746 1747 /* softreset the UART */ 1748 sysc |= OMAP_UART_SYSC_SOFTRESET; 1749 uart_write(priv, UART_OMAP_SYSC, sysc); 1750 1751 /* By experiments, 1us enough for reset complete on AM335x */ 1752 do { 1753 udelay(1); 1754 syss = uart_read(priv, UART_OMAP_SYSS); 1755 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1756 1757 if (!timeout) { 1758 dev_err(dev, "timed out waiting for reset done\n"); 1759 return -ETIMEDOUT; 1760 } 1761 1762 return 0; 1763 } 1764 1765 static int omap8250_runtime_suspend(struct device *dev) 1766 { 1767 struct omap8250_priv *priv = dev_get_drvdata(dev); 1768 struct uart_8250_port *up = NULL; 1769 1770 if (priv->line >= 0) 1771 up = serial8250_get_port(priv->line); 1772 1773 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1774 int ret; 1775 1776 ret = omap8250_soft_reset(dev); 1777 if (ret) 1778 return ret; 1779 1780 if (up) { 1781 /* Restore to UART mode after reset (for wakeup) */ 1782 omap8250_update_mdr1(up, priv); 1783 /* Restore wakeup enable register */ 1784 serial_out(up, UART_OMAP_WER, priv->wer); 1785 } 1786 } 1787 1788 if (up && up->dma && up->dma->rxchan) 1789 omap_8250_rx_dma_flush(up); 1790 1791 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1792 schedule_work(&priv->qos_work); 1793 atomic_set(&priv->active, 0); 1794 1795 return 0; 1796 } 1797 1798 static int omap8250_runtime_resume(struct device *dev) 1799 { 1800 struct omap8250_priv *priv = dev_get_drvdata(dev); 1801 struct uart_8250_port *up = NULL; 1802 1803 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1804 if (atomic_read(&priv->active)) 1805 return 0; 1806 1807 if (priv->line >= 0) 1808 up = serial8250_get_port(priv->line); 1809 1810 if (up && omap8250_lost_context(up)) { 1811 guard(uart_port_lock_irq)(&up->port); 1812 omap8250_restore_regs(up); 1813 } 1814 1815 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1816 guard(uart_port_lock_irq)(&up->port); 1817 omap_8250_rx_dma(up); 1818 } 1819 1820 atomic_set(&priv->active, 1); 1821 priv->latency = priv->calc_latency; 1822 schedule_work(&priv->qos_work); 1823 1824 return 0; 1825 } 1826 1827 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1828 static int __init omap8250_console_fixup(void) 1829 { 1830 char *omap_str; 1831 char *options; 1832 u8 idx; 1833 1834 if (strstr(boot_command_line, "console=ttyS")) 1835 /* user set a ttyS based name for the console */ 1836 return 0; 1837 1838 omap_str = strstr(boot_command_line, "console=ttyO"); 1839 if (!omap_str) 1840 /* user did not set ttyO based console, so we don't care */ 1841 return 0; 1842 1843 omap_str += 12; 1844 if ('0' <= *omap_str && *omap_str <= '9') 1845 idx = *omap_str - '0'; 1846 else 1847 return 0; 1848 1849 omap_str++; 1850 if (omap_str[0] == ',') { 1851 omap_str++; 1852 options = omap_str; 1853 } else { 1854 options = NULL; 1855 } 1856 1857 add_preferred_console("ttyS", idx, options); 1858 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1859 idx, idx); 1860 pr_err("This ensures that you still see kernel messages. Please\n"); 1861 pr_err("update your kernel commandline.\n"); 1862 return 0; 1863 } 1864 console_initcall(omap8250_console_fixup); 1865 #endif 1866 1867 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1868 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1869 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1870 omap8250_runtime_resume, NULL) 1871 .prepare = pm_sleep_ptr(omap8250_prepare), 1872 .complete = pm_sleep_ptr(omap8250_complete), 1873 }; 1874 1875 static struct platform_driver omap8250_platform_driver = { 1876 .driver = { 1877 .name = "omap8250", 1878 .pm = pm_ptr(&omap8250_dev_pm_ops), 1879 .of_match_table = omap8250_dt_ids, 1880 }, 1881 .probe = omap8250_probe, 1882 .remove = omap8250_remove, 1883 }; 1884 module_platform_driver(omap8250_platform_driver); 1885 1886 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1887 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1888 MODULE_LICENSE("GPL v2"); 1889