1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 #include <linux/pm_domain.h> 31 32 #include "8250.h" 33 34 #define DEFAULT_CLK_SPEED 48000000 35 #define OMAP_UART_REGSHIFT 2 36 37 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 38 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 39 #define OMAP_DMA_TX_KICK (1 << 2) 40 /* 41 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 42 * The same errata is applicable to AM335x and DRA7x processors too. 43 */ 44 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 45 #define UART_HAS_EFR2 BIT(4) 46 #define UART_HAS_RHR_IT_DIS BIT(5) 47 #define UART_RX_TIMEOUT_QUIRK BIT(6) 48 #define UART_HAS_NATIVE_RS485 BIT(7) 49 50 #define OMAP_UART_FCR_RX_TRIG 6 51 #define OMAP_UART_FCR_TX_TRIG 4 52 53 /* SCR register bitmasks */ 54 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 55 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 56 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 57 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 58 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 59 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 60 61 /* MVR register bitmasks */ 62 #define OMAP_UART_MVR_SCHEME_SHIFT 30 63 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 64 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 65 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 66 #define OMAP_UART_MVR_MAJ_MASK 0x700 67 #define OMAP_UART_MVR_MAJ_SHIFT 8 68 #define OMAP_UART_MVR_MIN_MASK 0x3f 69 70 /* SYSC register bitmasks */ 71 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 72 73 /* SYSS register bitmasks */ 74 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 75 76 #define UART_TI752_TLR_TX 0 77 #define UART_TI752_TLR_RX 4 78 79 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 80 #define TRIGGER_FCR_MASK(x) (x & 3) 81 82 /* Enable XON/XOFF flow control on output */ 83 #define OMAP_UART_SW_TX 0x08 84 /* Enable XON/XOFF flow control on input */ 85 #define OMAP_UART_SW_RX 0x02 86 87 #define OMAP_UART_WER_MOD_WKUP 0x7f 88 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 89 90 #define TX_TRIGGER 1 91 #define RX_TRIGGER 48 92 93 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 94 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 95 96 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 97 98 #define OMAP_UART_REV_46 0x0406 99 #define OMAP_UART_REV_52 0x0502 100 #define OMAP_UART_REV_63 0x0603 101 102 /* Interrupt Enable Register 2 */ 103 #define UART_OMAP_IER2 0x1B 104 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 105 106 /* Mode Definition Register 3 */ 107 #define UART_OMAP_MDR3 0x20 108 #define UART_OMAP_MDR3_DIR_POL BIT(3) 109 #define UART_OMAP_MDR3_DIR_EN BIT(4) 110 111 /* Enhanced features register 2 */ 112 #define UART_OMAP_EFR2 0x23 113 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 114 115 /* RX FIFO occupancy indicator */ 116 #define UART_OMAP_RX_LVL 0x19 117 118 /* Timeout low and High */ 119 #define UART_OMAP_TO_L 0x26 120 #define UART_OMAP_TO_H 0x27 121 122 /* 123 * Copy of the genpd flags for the console. 124 * Only used if console suspend is disabled 125 */ 126 static unsigned int genpd_flags_console; 127 128 struct omap8250_priv { 129 void __iomem *membase; 130 int line; 131 u8 habit; 132 u8 mdr1; 133 u8 mdr3; 134 u8 efr; 135 u8 scr; 136 u8 wer; 137 u8 xon; 138 u8 xoff; 139 u8 delayed_restore; 140 u16 quot; 141 142 u8 tx_trigger; 143 u8 rx_trigger; 144 atomic_t active; 145 bool is_suspending; 146 int wakeirq; 147 int wakeups_enabled; 148 u32 latency; 149 u32 calc_latency; 150 struct pm_qos_request pm_qos_request; 151 struct work_struct qos_work; 152 struct uart_8250_dma omap8250_dma; 153 spinlock_t rx_dma_lock; 154 bool rx_dma_broken; 155 bool throttled; 156 }; 157 158 struct omap8250_dma_params { 159 u32 rx_size; 160 u8 rx_trigger; 161 u8 tx_trigger; 162 }; 163 164 struct omap8250_platdata { 165 struct omap8250_dma_params *dma_params; 166 u8 habit; 167 }; 168 169 #ifdef CONFIG_SERIAL_8250_DMA 170 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 171 #else 172 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 173 #endif 174 175 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 176 { 177 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 178 } 179 180 /* 181 * Called on runtime PM resume path from omap8250_restore_regs(), and 182 * omap8250_set_mctrl(). 183 */ 184 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 185 { 186 struct uart_8250_port *up = up_to_u8250p(port); 187 struct omap8250_priv *priv = up->port.private_data; 188 u8 lcr; 189 190 serial8250_do_set_mctrl(port, mctrl); 191 192 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 193 /* 194 * Turn off autoRTS if RTS is lowered and restore autoRTS 195 * setting if RTS is raised 196 */ 197 lcr = serial_in(up, UART_LCR); 198 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 199 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 200 priv->efr |= UART_EFR_RTS; 201 else 202 priv->efr &= ~UART_EFR_RTS; 203 serial_out(up, UART_EFR, priv->efr); 204 serial_out(up, UART_LCR, lcr); 205 } 206 } 207 208 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 209 { 210 int err; 211 212 err = pm_runtime_resume_and_get(port->dev); 213 if (err) 214 return; 215 216 __omap8250_set_mctrl(port, mctrl); 217 218 pm_runtime_mark_last_busy(port->dev); 219 pm_runtime_put_autosuspend(port->dev); 220 } 221 222 /* 223 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 224 * The access to uart register after MDR1 Access 225 * causes UART to corrupt data. 226 * 227 * Need a delay = 228 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 229 * give 10 times as much 230 */ 231 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 232 struct omap8250_priv *priv) 233 { 234 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 235 udelay(2); 236 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 237 UART_FCR_CLEAR_RCVR); 238 } 239 240 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 241 struct omap8250_priv *priv) 242 { 243 unsigned int uartclk = port->uartclk; 244 unsigned int div_13, div_16; 245 unsigned int abs_d13, abs_d16; 246 247 /* 248 * Old custom speed handling. 249 */ 250 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 251 priv->quot = port->custom_divisor & UART_DIV_MAX; 252 /* 253 * I assume that nobody is using this. But hey, if somebody 254 * would like to specify the divisor _and_ the mode then the 255 * driver is ready and waiting for it. 256 */ 257 if (port->custom_divisor & (1 << 16)) 258 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 259 else 260 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 261 return; 262 } 263 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 264 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 265 266 if (!div_13) 267 div_13 = 1; 268 if (!div_16) 269 div_16 = 1; 270 271 abs_d13 = abs(baud - uartclk / 13 / div_13); 272 abs_d16 = abs(baud - uartclk / 16 / div_16); 273 274 if (abs_d13 >= abs_d16) { 275 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 276 priv->quot = div_16; 277 } else { 278 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 279 priv->quot = div_13; 280 } 281 } 282 283 static void omap8250_update_scr(struct uart_8250_port *up, 284 struct omap8250_priv *priv) 285 { 286 u8 old_scr; 287 288 old_scr = serial_in(up, UART_OMAP_SCR); 289 if (old_scr == priv->scr) 290 return; 291 292 /* 293 * The manual recommends not to enable the DMA mode selector in the SCR 294 * (instead of the FCR) register _and_ selecting the DMA mode as one 295 * register write because this may lead to malfunction. 296 */ 297 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 298 serial_out(up, UART_OMAP_SCR, 299 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 300 serial_out(up, UART_OMAP_SCR, priv->scr); 301 } 302 303 static void omap8250_update_mdr1(struct uart_8250_port *up, 304 struct omap8250_priv *priv) 305 { 306 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 307 omap_8250_mdr1_errataset(up, priv); 308 else 309 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 310 } 311 312 static void omap8250_restore_regs(struct uart_8250_port *up) 313 { 314 struct omap8250_priv *priv = up->port.private_data; 315 struct uart_8250_dma *dma = up->dma; 316 u8 mcr = serial8250_in_MCR(up); 317 318 /* Port locked to synchronize UART_IER access against the console. */ 319 lockdep_assert_held_once(&up->port.lock); 320 321 if (dma && dma->tx_running) { 322 /* 323 * TCSANOW requests the change to occur immediately however if 324 * we have a TX-DMA operation in progress then it has been 325 * observed that it might stall and never complete. Therefore we 326 * delay DMA completes to prevent this hang from happen. 327 */ 328 priv->delayed_restore = 1; 329 return; 330 } 331 332 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 333 serial_out(up, UART_EFR, UART_EFR_ECB); 334 335 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 336 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 337 serial_out(up, UART_FCR, up->fcr); 338 339 omap8250_update_scr(up, priv); 340 341 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 342 343 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 344 OMAP_UART_TCR_HALT(52)); 345 serial_out(up, UART_TI752_TLR, 346 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 347 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 348 349 serial_out(up, UART_LCR, 0); 350 351 /* drop TCR + TLR access, we setup XON/XOFF later */ 352 serial8250_out_MCR(up, mcr); 353 354 serial_out(up, UART_IER, up->ier); 355 356 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 357 serial_dl_write(up, priv->quot); 358 359 serial_out(up, UART_EFR, priv->efr); 360 361 /* Configure flow control */ 362 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 363 serial_out(up, UART_XON1, priv->xon); 364 serial_out(up, UART_XOFF1, priv->xoff); 365 366 serial_out(up, UART_LCR, up->lcr); 367 368 omap8250_update_mdr1(up, priv); 369 370 __omap8250_set_mctrl(&up->port, up->port.mctrl); 371 372 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 373 374 if (up->port.rs485.flags & SER_RS485_ENABLED && 375 up->port.rs485_config == serial8250_em485_config) 376 serial8250_em485_stop_tx(up); 377 } 378 379 /* 380 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 381 * some differences in how we want to handle flow control. 382 */ 383 static void omap_8250_set_termios(struct uart_port *port, 384 struct ktermios *termios, 385 const struct ktermios *old) 386 { 387 struct uart_8250_port *up = up_to_u8250p(port); 388 struct omap8250_priv *priv = up->port.private_data; 389 unsigned char cval = 0; 390 unsigned int baud; 391 392 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 393 394 if (termios->c_cflag & CSTOPB) 395 cval |= UART_LCR_STOP; 396 if (termios->c_cflag & PARENB) 397 cval |= UART_LCR_PARITY; 398 if (!(termios->c_cflag & PARODD)) 399 cval |= UART_LCR_EPAR; 400 if (termios->c_cflag & CMSPAR) 401 cval |= UART_LCR_SPAR; 402 403 /* 404 * Ask the core to calculate the divisor for us. 405 */ 406 baud = uart_get_baud_rate(port, termios, old, 407 port->uartclk / 16 / UART_DIV_MAX, 408 port->uartclk / 13); 409 omap_8250_get_divisor(port, baud, priv); 410 411 /* 412 * Ok, we're now changing the port state. Do it with 413 * interrupts disabled. 414 */ 415 pm_runtime_get_sync(port->dev); 416 uart_port_lock_irq(port); 417 418 /* 419 * Update the per-port timeout. 420 */ 421 uart_update_timeout(port, termios->c_cflag, baud); 422 423 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 424 if (termios->c_iflag & INPCK) 425 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 426 if (termios->c_iflag & (IGNBRK | PARMRK)) 427 up->port.read_status_mask |= UART_LSR_BI; 428 429 /* 430 * Characters to ignore 431 */ 432 up->port.ignore_status_mask = 0; 433 if (termios->c_iflag & IGNPAR) 434 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 435 if (termios->c_iflag & IGNBRK) { 436 up->port.ignore_status_mask |= UART_LSR_BI; 437 /* 438 * If we're ignoring parity and break indicators, 439 * ignore overruns too (for real raw support). 440 */ 441 if (termios->c_iflag & IGNPAR) 442 up->port.ignore_status_mask |= UART_LSR_OE; 443 } 444 445 /* 446 * ignore all characters if CREAD is not set 447 */ 448 if ((termios->c_cflag & CREAD) == 0) 449 up->port.ignore_status_mask |= UART_LSR_DR; 450 451 /* 452 * Modem status interrupts 453 */ 454 up->ier &= ~UART_IER_MSI; 455 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 456 up->ier |= UART_IER_MSI; 457 458 up->lcr = cval; 459 /* Up to here it was mostly serial8250_do_set_termios() */ 460 461 /* 462 * We enable TRIG_GRANU for RX and TX and additionally we set 463 * SCR_TX_EMPTY bit. The result is the following: 464 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 465 * - less than RX_TRIGGER number of bytes will also cause an interrupt 466 * once the UART decides that there no new bytes arriving. 467 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 468 * empty - the trigger level is ignored here. 469 * 470 * Once DMA is enabled: 471 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 472 * bytes in the TX FIFO. On each assert the DMA engine will move 473 * TX_TRIGGER bytes into the FIFO. 474 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 475 * the FIFO and move RX_TRIGGER bytes. 476 * This is because threshold and trigger values are the same. 477 */ 478 up->fcr = UART_FCR_ENABLE_FIFO; 479 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 480 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 481 482 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 483 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 484 485 if (up->dma) 486 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 487 OMAP_UART_SCR_DMAMODE_CTL; 488 489 priv->xon = termios->c_cc[VSTART]; 490 priv->xoff = termios->c_cc[VSTOP]; 491 492 priv->efr = 0; 493 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 494 495 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 496 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 497 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 498 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 499 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 500 priv->efr |= UART_EFR_CTS; 501 } else if (up->port.flags & UPF_SOFT_FLOW) { 502 /* 503 * OMAP rx s/w flow control is borked; the transmitter remains 504 * stuck off even if rx flow control is subsequently disabled 505 */ 506 507 /* 508 * IXOFF Flag: 509 * Enable XON/XOFF flow control on output. 510 * Transmit XON1, XOFF1 511 */ 512 if (termios->c_iflag & IXOFF) { 513 up->port.status |= UPSTAT_AUTOXOFF; 514 priv->efr |= OMAP_UART_SW_TX; 515 } 516 } 517 omap8250_restore_regs(up); 518 519 uart_port_unlock_irq(&up->port); 520 pm_runtime_mark_last_busy(port->dev); 521 pm_runtime_put_autosuspend(port->dev); 522 523 /* calculate wakeup latency constraint */ 524 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 525 priv->latency = priv->calc_latency; 526 527 schedule_work(&priv->qos_work); 528 529 /* Don't rewrite B0 */ 530 if (tty_termios_baud_rate(termios)) 531 tty_termios_encode_baud_rate(termios, baud, baud); 532 } 533 534 /* same as 8250 except that we may have extra flow bits set in EFR */ 535 static void omap_8250_pm(struct uart_port *port, unsigned int state, 536 unsigned int oldstate) 537 { 538 struct uart_8250_port *up = up_to_u8250p(port); 539 u8 efr; 540 541 pm_runtime_get_sync(port->dev); 542 543 /* Synchronize UART_IER access against the console. */ 544 uart_port_lock_irq(port); 545 546 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 547 efr = serial_in(up, UART_EFR); 548 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 549 serial_out(up, UART_LCR, 0); 550 551 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 552 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 553 serial_out(up, UART_EFR, efr); 554 serial_out(up, UART_LCR, 0); 555 556 uart_port_unlock_irq(port); 557 558 pm_runtime_mark_last_busy(port->dev); 559 pm_runtime_put_autosuspend(port->dev); 560 } 561 562 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 563 struct omap8250_priv *priv) 564 { 565 static const struct soc_device_attribute k3_soc_devices[] = { 566 { .family = "AM65X", }, 567 { .family = "J721E", .revision = "SR1.0" }, 568 { /* sentinel */ } 569 }; 570 u32 mvr, scheme; 571 u16 revision, major, minor; 572 573 mvr = uart_read(priv, UART_OMAP_MVER); 574 575 /* Check revision register scheme */ 576 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 577 578 switch (scheme) { 579 case 0: /* Legacy Scheme: OMAP2/3 */ 580 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 581 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 582 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 583 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 584 break; 585 case 1: 586 /* New Scheme: OMAP4+ */ 587 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 588 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 589 OMAP_UART_MVR_MAJ_SHIFT; 590 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 591 break; 592 default: 593 dev_warn(up->port.dev, 594 "Unknown revision, defaulting to highest\n"); 595 /* highest possible revision */ 596 major = 0xff; 597 minor = 0xff; 598 } 599 /* normalize revision for the driver */ 600 revision = UART_BUILD_REVISION(major, minor); 601 602 switch (revision) { 603 case OMAP_UART_REV_46: 604 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 605 break; 606 case OMAP_UART_REV_52: 607 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 608 OMAP_UART_WER_HAS_TX_WAKEUP; 609 break; 610 case OMAP_UART_REV_63: 611 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 612 OMAP_UART_WER_HAS_TX_WAKEUP; 613 break; 614 default: 615 break; 616 } 617 618 /* 619 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 620 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 621 * to enable errata workaround. 622 */ 623 if (soc_device_match(k3_soc_devices)) 624 priv->habit &= ~UART_HAS_RHR_IT_DIS; 625 } 626 627 static void omap8250_uart_qos_work(struct work_struct *work) 628 { 629 struct omap8250_priv *priv; 630 631 priv = container_of(work, struct omap8250_priv, qos_work); 632 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 633 } 634 635 #ifdef CONFIG_SERIAL_8250_DMA 636 static int omap_8250_dma_handle_irq(struct uart_port *port); 637 #endif 638 639 static irqreturn_t omap8250_irq(int irq, void *dev_id) 640 { 641 struct omap8250_priv *priv = dev_id; 642 struct uart_8250_port *up = serial8250_get_port(priv->line); 643 struct uart_port *port = &up->port; 644 unsigned int iir, lsr; 645 int ret; 646 647 pm_runtime_get_noresume(port->dev); 648 649 /* Shallow idle state wake-up to an IO interrupt? */ 650 if (atomic_add_unless(&priv->active, 1, 1)) { 651 priv->latency = priv->calc_latency; 652 schedule_work(&priv->qos_work); 653 } 654 655 #ifdef CONFIG_SERIAL_8250_DMA 656 if (up->dma) { 657 ret = omap_8250_dma_handle_irq(port); 658 pm_runtime_mark_last_busy(port->dev); 659 pm_runtime_put(port->dev); 660 return IRQ_RETVAL(ret); 661 } 662 #endif 663 664 lsr = serial_port_in(port, UART_LSR); 665 iir = serial_port_in(port, UART_IIR); 666 ret = serial8250_handle_irq(port, iir); 667 668 /* 669 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 670 * FIFO has been drained or erroneously. 671 * So apply solution of Errata i2310 as mentioned in 672 * https://www.ti.com/lit/pdf/sprz536 673 */ 674 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 675 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT) { 676 unsigned char efr2, timeout_h, timeout_l; 677 678 efr2 = serial_in(up, UART_OMAP_EFR2); 679 timeout_h = serial_in(up, UART_OMAP_TO_H); 680 timeout_l = serial_in(up, UART_OMAP_TO_L); 681 serial_out(up, UART_OMAP_TO_H, 0xFF); 682 serial_out(up, UART_OMAP_TO_L, 0xFF); 683 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 684 serial_in(up, UART_IIR); 685 serial_out(up, UART_OMAP_EFR2, efr2); 686 serial_out(up, UART_OMAP_TO_H, timeout_h); 687 serial_out(up, UART_OMAP_TO_L, timeout_l); 688 } 689 690 /* Stop processing interrupts on input overrun */ 691 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 692 unsigned long delay; 693 694 /* Synchronize UART_IER access against the console. */ 695 uart_port_lock(port); 696 up->ier = port->serial_in(port, UART_IER); 697 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 698 port->ops->stop_rx(port); 699 } else { 700 /* Keep restarting the timer until 701 * the input overrun subsides. 702 */ 703 cancel_delayed_work(&up->overrun_backoff); 704 } 705 uart_port_unlock(port); 706 707 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 708 schedule_delayed_work(&up->overrun_backoff, delay); 709 } 710 711 pm_runtime_mark_last_busy(port->dev); 712 pm_runtime_put(port->dev); 713 714 return IRQ_RETVAL(ret); 715 } 716 717 static int omap_8250_startup(struct uart_port *port) 718 { 719 struct uart_8250_port *up = up_to_u8250p(port); 720 struct omap8250_priv *priv = port->private_data; 721 struct uart_8250_dma *dma = &priv->omap8250_dma; 722 int ret; 723 724 if (priv->wakeirq) { 725 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 726 if (ret) 727 return ret; 728 } 729 730 pm_runtime_get_sync(port->dev); 731 732 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 733 734 serial_out(up, UART_LCR, UART_LCR_WLEN8); 735 736 up->lsr_saved_flags = 0; 737 up->msr_saved_flags = 0; 738 739 /* Disable DMA for console UART */ 740 if (dma->fn && !uart_console(port)) { 741 up->dma = &priv->omap8250_dma; 742 ret = serial8250_request_dma(up); 743 if (ret) { 744 dev_warn_ratelimited(port->dev, 745 "failed to request DMA\n"); 746 up->dma = NULL; 747 } 748 } else { 749 up->dma = NULL; 750 } 751 752 /* Synchronize UART_IER access against the console. */ 753 uart_port_lock_irq(port); 754 up->ier = UART_IER_RLSI | UART_IER_RDI; 755 serial_out(up, UART_IER, up->ier); 756 uart_port_unlock_irq(port); 757 758 #ifdef CONFIG_PM 759 up->capabilities |= UART_CAP_RPM; 760 #endif 761 762 /* Enable module level wake up */ 763 priv->wer = OMAP_UART_WER_MOD_WKUP; 764 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 765 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 766 serial_out(up, UART_OMAP_WER, priv->wer); 767 768 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 769 uart_port_lock_irq(port); 770 up->dma->rx_dma(up); 771 uart_port_unlock_irq(port); 772 } 773 774 enable_irq(up->port.irq); 775 776 pm_runtime_mark_last_busy(port->dev); 777 pm_runtime_put_autosuspend(port->dev); 778 return 0; 779 } 780 781 static void omap_8250_shutdown(struct uart_port *port) 782 { 783 struct uart_8250_port *up = up_to_u8250p(port); 784 struct omap8250_priv *priv = port->private_data; 785 786 flush_work(&priv->qos_work); 787 if (up->dma) 788 omap_8250_rx_dma_flush(up); 789 790 pm_runtime_get_sync(port->dev); 791 792 serial_out(up, UART_OMAP_WER, 0); 793 if (priv->habit & UART_HAS_EFR2) 794 serial_out(up, UART_OMAP_EFR2, 0x0); 795 796 /* Synchronize UART_IER access against the console. */ 797 uart_port_lock_irq(port); 798 up->ier = 0; 799 serial_out(up, UART_IER, 0); 800 uart_port_unlock_irq(port); 801 disable_irq_nosync(up->port.irq); 802 dev_pm_clear_wake_irq(port->dev); 803 804 serial8250_release_dma(up); 805 up->dma = NULL; 806 807 /* 808 * Disable break condition and FIFOs 809 */ 810 if (up->lcr & UART_LCR_SBC) 811 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 812 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 813 814 pm_runtime_mark_last_busy(port->dev); 815 pm_runtime_put_autosuspend(port->dev); 816 } 817 818 static void omap_8250_throttle(struct uart_port *port) 819 { 820 struct omap8250_priv *priv = port->private_data; 821 unsigned long flags; 822 823 pm_runtime_get_sync(port->dev); 824 825 uart_port_lock_irqsave(port, &flags); 826 port->ops->stop_rx(port); 827 priv->throttled = true; 828 uart_port_unlock_irqrestore(port, flags); 829 830 pm_runtime_mark_last_busy(port->dev); 831 pm_runtime_put_autosuspend(port->dev); 832 } 833 834 static void omap_8250_unthrottle(struct uart_port *port) 835 { 836 struct omap8250_priv *priv = port->private_data; 837 struct uart_8250_port *up = up_to_u8250p(port); 838 unsigned long flags; 839 840 pm_runtime_get_sync(port->dev); 841 842 /* Synchronize UART_IER access against the console. */ 843 uart_port_lock_irqsave(port, &flags); 844 priv->throttled = false; 845 if (up->dma) 846 up->dma->rx_dma(up); 847 up->ier |= UART_IER_RLSI | UART_IER_RDI; 848 port->read_status_mask |= UART_LSR_DR; 849 serial_out(up, UART_IER, up->ier); 850 uart_port_unlock_irqrestore(port, flags); 851 852 pm_runtime_mark_last_busy(port->dev); 853 pm_runtime_put_autosuspend(port->dev); 854 } 855 856 static int omap8250_rs485_config(struct uart_port *port, 857 struct ktermios *termios, 858 struct serial_rs485 *rs485) 859 { 860 struct omap8250_priv *priv = port->private_data; 861 struct uart_8250_port *up = up_to_u8250p(port); 862 u32 fixed_delay_rts_before_send = 0; 863 u32 fixed_delay_rts_after_send = 0; 864 unsigned int baud; 865 866 /* 867 * There is a fixed delay of 3 bit clock cycles after the TX shift 868 * register is going empty to allow time for the stop bit to transition 869 * through the transceiver before direction is changed to receive. 870 * 871 * Additionally there appears to be a 1 bit clock delay between writing 872 * to the THR register and transmission of the start bit, per page 8783 873 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 874 */ 875 if (priv->quot) { 876 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 877 baud = port->uartclk / (16 * priv->quot); 878 else 879 baud = port->uartclk / (13 * priv->quot); 880 881 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 882 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 883 } 884 885 /* 886 * Fall back to RS485 software emulation if the UART is missing 887 * hardware support, if the device tree specifies an mctrl_gpio 888 * (indicates that RTS is unavailable due to a pinmux conflict) 889 * or if the requested delays exceed the fixed hardware delays. 890 */ 891 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 892 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 893 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 894 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 895 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 896 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 897 898 port->rs485_config = serial8250_em485_config; 899 return serial8250_em485_config(port, termios, rs485); 900 } 901 902 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 903 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 904 905 if (rs485->flags & SER_RS485_ENABLED) 906 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 907 else 908 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 909 910 /* 911 * Retain same polarity semantics as RS485 software emulation, 912 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 913 */ 914 if (rs485->flags & SER_RS485_RTS_ON_SEND) 915 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 916 else 917 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 918 919 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 920 921 return 0; 922 } 923 924 #ifdef CONFIG_SERIAL_8250_DMA 925 static int omap_8250_rx_dma(struct uart_8250_port *p); 926 927 /* Must be called while priv->rx_dma_lock is held */ 928 static void __dma_rx_do_complete(struct uart_8250_port *p) 929 { 930 struct uart_8250_dma *dma = p->dma; 931 struct tty_port *tty_port = &p->port.state->port; 932 struct omap8250_priv *priv = p->port.private_data; 933 struct dma_chan *rxchan = dma->rxchan; 934 dma_cookie_t cookie; 935 struct dma_tx_state state; 936 int count; 937 int ret; 938 u32 reg; 939 940 if (!dma->rx_running) 941 goto out; 942 943 cookie = dma->rx_cookie; 944 dma->rx_running = 0; 945 946 /* Re-enable RX FIFO interrupt now that transfer is complete */ 947 if (priv->habit & UART_HAS_RHR_IT_DIS) { 948 reg = serial_in(p, UART_OMAP_IER2); 949 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 950 serial_out(p, UART_OMAP_IER2, reg); 951 } 952 953 dmaengine_tx_status(rxchan, cookie, &state); 954 955 count = dma->rx_size - state.residue + state.in_flight_bytes; 956 if (count < dma->rx_size) { 957 dmaengine_terminate_async(rxchan); 958 959 /* 960 * Poll for teardown to complete which guarantees in 961 * flight data is drained. 962 */ 963 if (state.in_flight_bytes) { 964 int poll_count = 25; 965 966 while (dmaengine_tx_status(rxchan, cookie, NULL) && 967 poll_count--) 968 cpu_relax(); 969 970 if (poll_count == -1) 971 dev_err(p->port.dev, "teardown incomplete\n"); 972 } 973 } 974 if (!count) 975 goto out; 976 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 977 978 p->port.icount.rx += ret; 979 p->port.icount.buf_overrun += count - ret; 980 out: 981 982 tty_flip_buffer_push(tty_port); 983 } 984 985 static void __dma_rx_complete(void *param) 986 { 987 struct uart_8250_port *p = param; 988 struct omap8250_priv *priv = p->port.private_data; 989 struct uart_8250_dma *dma = p->dma; 990 struct dma_tx_state state; 991 unsigned long flags; 992 993 /* Synchronize UART_IER access against the console. */ 994 uart_port_lock_irqsave(&p->port, &flags); 995 996 /* 997 * If the tx status is not DMA_COMPLETE, then this is a delayed 998 * completion callback. A previous RX timeout flush would have 999 * already pushed the data, so exit. 1000 */ 1001 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 1002 DMA_COMPLETE) { 1003 uart_port_unlock_irqrestore(&p->port, flags); 1004 return; 1005 } 1006 __dma_rx_do_complete(p); 1007 if (!priv->throttled) { 1008 p->ier |= UART_IER_RLSI | UART_IER_RDI; 1009 serial_out(p, UART_IER, p->ier); 1010 if (!(priv->habit & UART_HAS_EFR2)) 1011 omap_8250_rx_dma(p); 1012 } 1013 1014 uart_port_unlock_irqrestore(&p->port, flags); 1015 } 1016 1017 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 1018 { 1019 struct omap8250_priv *priv = p->port.private_data; 1020 struct uart_8250_dma *dma = p->dma; 1021 struct dma_tx_state state; 1022 unsigned long flags; 1023 int ret; 1024 1025 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1026 1027 if (!dma->rx_running) { 1028 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1029 return; 1030 } 1031 1032 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1033 if (ret == DMA_IN_PROGRESS) { 1034 ret = dmaengine_pause(dma->rxchan); 1035 if (WARN_ON_ONCE(ret)) 1036 priv->rx_dma_broken = true; 1037 } 1038 __dma_rx_do_complete(p); 1039 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1040 } 1041 1042 static int omap_8250_rx_dma(struct uart_8250_port *p) 1043 { 1044 struct omap8250_priv *priv = p->port.private_data; 1045 struct uart_8250_dma *dma = p->dma; 1046 int err = 0; 1047 struct dma_async_tx_descriptor *desc; 1048 unsigned long flags; 1049 u32 reg; 1050 1051 /* Port locked to synchronize UART_IER access against the console. */ 1052 lockdep_assert_held_once(&p->port.lock); 1053 1054 if (priv->rx_dma_broken) 1055 return -EINVAL; 1056 1057 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1058 1059 if (dma->rx_running) { 1060 enum dma_status state; 1061 1062 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1063 if (state == DMA_COMPLETE) { 1064 /* 1065 * Disable RX interrupts to allow RX DMA completion 1066 * callback to run. 1067 */ 1068 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1069 serial_out(p, UART_IER, p->ier); 1070 } 1071 goto out; 1072 } 1073 1074 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1075 dma->rx_size, DMA_DEV_TO_MEM, 1076 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1077 if (!desc) { 1078 err = -EBUSY; 1079 goto out; 1080 } 1081 1082 dma->rx_running = 1; 1083 desc->callback = __dma_rx_complete; 1084 desc->callback_param = p; 1085 1086 dma->rx_cookie = dmaengine_submit(desc); 1087 1088 /* 1089 * Disable RX FIFO interrupt while RX DMA is enabled, else 1090 * spurious interrupt may be raised when data is in the RX FIFO 1091 * but is yet to be drained by DMA. 1092 */ 1093 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1094 reg = serial_in(p, UART_OMAP_IER2); 1095 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1096 serial_out(p, UART_OMAP_IER2, reg); 1097 } 1098 1099 dma_async_issue_pending(dma->rxchan); 1100 out: 1101 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1102 return err; 1103 } 1104 1105 static int omap_8250_tx_dma(struct uart_8250_port *p); 1106 1107 static void omap_8250_dma_tx_complete(void *param) 1108 { 1109 struct uart_8250_port *p = param; 1110 struct uart_8250_dma *dma = p->dma; 1111 struct tty_port *tport = &p->port.state->port; 1112 unsigned long flags; 1113 bool en_thri = false; 1114 struct omap8250_priv *priv = p->port.private_data; 1115 1116 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1117 UART_XMIT_SIZE, DMA_TO_DEVICE); 1118 1119 uart_port_lock_irqsave(&p->port, &flags); 1120 1121 dma->tx_running = 0; 1122 1123 uart_xmit_advance(&p->port, dma->tx_size); 1124 1125 if (priv->delayed_restore) { 1126 priv->delayed_restore = 0; 1127 omap8250_restore_regs(p); 1128 } 1129 1130 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1131 uart_write_wakeup(&p->port); 1132 1133 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1134 int ret; 1135 1136 ret = omap_8250_tx_dma(p); 1137 if (ret) 1138 en_thri = true; 1139 } else if (p->capabilities & UART_CAP_RPM) { 1140 en_thri = true; 1141 } 1142 1143 if (en_thri) { 1144 dma->tx_err = 1; 1145 serial8250_set_THRI(p); 1146 } 1147 1148 uart_port_unlock_irqrestore(&p->port, flags); 1149 } 1150 1151 static int omap_8250_tx_dma(struct uart_8250_port *p) 1152 { 1153 struct uart_8250_dma *dma = p->dma; 1154 struct omap8250_priv *priv = p->port.private_data; 1155 struct tty_port *tport = &p->port.state->port; 1156 struct dma_async_tx_descriptor *desc; 1157 struct scatterlist sg; 1158 int skip_byte = -1; 1159 int ret; 1160 1161 if (dma->tx_running) 1162 return 0; 1163 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1164 1165 /* 1166 * Even if no data, we need to return an error for the two cases 1167 * below so serial8250_tx_chars() is invoked and properly clears 1168 * THRI and/or runtime suspend. 1169 */ 1170 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1171 ret = -EBUSY; 1172 goto err; 1173 } 1174 serial8250_clear_THRI(p); 1175 return 0; 1176 } 1177 1178 sg_init_table(&sg, 1); 1179 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1180 UART_XMIT_SIZE, dma->tx_addr); 1181 if (ret != 1) { 1182 serial8250_clear_THRI(p); 1183 return 0; 1184 } 1185 1186 dma->tx_size = sg_dma_len(&sg); 1187 1188 if (priv->habit & OMAP_DMA_TX_KICK) { 1189 unsigned char c; 1190 u8 tx_lvl; 1191 1192 /* 1193 * We need to put the first byte into the FIFO in order to start 1194 * the DMA transfer. For transfers smaller than four bytes we 1195 * don't bother doing DMA at all. It seem not matter if there 1196 * are still bytes in the FIFO from the last transfer (in case 1197 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1198 * leaving the FIFO seem not to trigger the DMA transfer. It is 1199 * really the byte that we put into the FIFO. 1200 * If the FIFO is already full then we most likely got here from 1201 * omap_8250_dma_tx_complete(). And this means the DMA engine 1202 * just completed its work. We don't have to wait the complete 1203 * 86us at 115200,8n1 but around 60us (not to mention lower 1204 * baudrates). So in that case we take the interrupt and try 1205 * again with an empty FIFO. 1206 */ 1207 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1208 if (tx_lvl == p->tx_loadsz) { 1209 ret = -EBUSY; 1210 goto err; 1211 } 1212 if (dma->tx_size < 4) { 1213 ret = -EINVAL; 1214 goto err; 1215 } 1216 if (!kfifo_get(&tport->xmit_fifo, &c)) { 1217 ret = -EINVAL; 1218 goto err; 1219 } 1220 skip_byte = c; 1221 /* now we need to recompute due to kfifo_get */ 1222 kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1223 UART_XMIT_SIZE, dma->tx_addr); 1224 } 1225 1226 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1227 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1228 if (!desc) { 1229 ret = -EBUSY; 1230 goto err; 1231 } 1232 1233 dma->tx_running = 1; 1234 1235 desc->callback = omap_8250_dma_tx_complete; 1236 desc->callback_param = p; 1237 1238 dma->tx_cookie = dmaengine_submit(desc); 1239 1240 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1241 UART_XMIT_SIZE, DMA_TO_DEVICE); 1242 1243 dma_async_issue_pending(dma->txchan); 1244 if (dma->tx_err) 1245 dma->tx_err = 0; 1246 1247 serial8250_clear_THRI(p); 1248 ret = 0; 1249 goto out_skip; 1250 err: 1251 dma->tx_err = 1; 1252 out_skip: 1253 if (skip_byte >= 0) 1254 serial_out(p, UART_TX, skip_byte); 1255 return ret; 1256 } 1257 1258 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1259 { 1260 switch (iir & 0x3f) { 1261 case UART_IIR_RLSI: 1262 case UART_IIR_RX_TIMEOUT: 1263 case UART_IIR_RDI: 1264 omap_8250_rx_dma_flush(up); 1265 return true; 1266 } 1267 return omap_8250_rx_dma(up); 1268 } 1269 1270 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1271 { 1272 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1273 (iir & UART_IIR_RDI)) { 1274 if (handle_rx_dma(up, iir)) { 1275 status = serial8250_rx_chars(up, status); 1276 omap_8250_rx_dma(up); 1277 } 1278 } 1279 1280 return status; 1281 } 1282 1283 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1284 u16 status) 1285 { 1286 /* Port locked to synchronize UART_IER access against the console. */ 1287 lockdep_assert_held_once(&up->port.lock); 1288 1289 /* 1290 * Queue a new transfer if FIFO has data. 1291 */ 1292 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1293 (up->ier & UART_IER_RDI)) { 1294 omap_8250_rx_dma(up); 1295 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1296 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1297 /* 1298 * Disable RX timeout, read IIR to clear 1299 * current timeout condition, clear EFR2 to 1300 * periodic timeouts, re-enable interrupts. 1301 */ 1302 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1303 serial_out(up, UART_IER, up->ier); 1304 omap_8250_rx_dma_flush(up); 1305 serial_in(up, UART_IIR); 1306 serial_out(up, UART_OMAP_EFR2, 0x0); 1307 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1308 serial_out(up, UART_IER, up->ier); 1309 } 1310 } 1311 1312 /* 1313 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1314 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1315 * use the default routine in the non-DMA case and this one for with DMA. 1316 */ 1317 static int omap_8250_dma_handle_irq(struct uart_port *port) 1318 { 1319 struct uart_8250_port *up = up_to_u8250p(port); 1320 struct omap8250_priv *priv = up->port.private_data; 1321 u16 status; 1322 u8 iir; 1323 1324 iir = serial_port_in(port, UART_IIR); 1325 if (iir & UART_IIR_NO_INT) { 1326 return IRQ_HANDLED; 1327 } 1328 1329 uart_port_lock(port); 1330 1331 status = serial_port_in(port, UART_LSR); 1332 1333 if ((iir & 0x3f) != UART_IIR_THRI) { 1334 if (priv->habit & UART_HAS_EFR2) 1335 am654_8250_handle_rx_dma(up, iir, status); 1336 else 1337 status = omap_8250_handle_rx_dma(up, iir, status); 1338 } 1339 1340 serial8250_modem_status(up); 1341 if (status & UART_LSR_THRE && up->dma->tx_err) { 1342 if (uart_tx_stopped(&up->port) || 1343 kfifo_is_empty(&up->port.state->port.xmit_fifo)) { 1344 up->dma->tx_err = 0; 1345 serial8250_tx_chars(up); 1346 } else { 1347 /* 1348 * try again due to an earlier failer which 1349 * might have been resolved by now. 1350 */ 1351 if (omap_8250_tx_dma(up)) 1352 serial8250_tx_chars(up); 1353 } 1354 } 1355 1356 uart_unlock_and_check_sysrq(port); 1357 1358 return 1; 1359 } 1360 1361 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1362 { 1363 return false; 1364 } 1365 1366 #else 1367 1368 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1369 { 1370 return -EINVAL; 1371 } 1372 #endif 1373 1374 static int omap8250_no_handle_irq(struct uart_port *port) 1375 { 1376 /* IRQ has not been requested but handling irq? */ 1377 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1378 return 0; 1379 } 1380 1381 static struct omap8250_dma_params am654_dma = { 1382 .rx_size = SZ_2K, 1383 .rx_trigger = 1, 1384 .tx_trigger = TX_TRIGGER, 1385 }; 1386 1387 static struct omap8250_dma_params am33xx_dma = { 1388 .rx_size = RX_TRIGGER, 1389 .rx_trigger = RX_TRIGGER, 1390 .tx_trigger = TX_TRIGGER, 1391 }; 1392 1393 static struct omap8250_platdata am654_platdata = { 1394 .dma_params = &am654_dma, 1395 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1396 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1397 }; 1398 1399 static struct omap8250_platdata am33xx_platdata = { 1400 .dma_params = &am33xx_dma, 1401 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1402 }; 1403 1404 static struct omap8250_platdata omap4_platdata = { 1405 .dma_params = &am33xx_dma, 1406 .habit = UART_ERRATA_CLOCK_DISABLE, 1407 }; 1408 1409 static const struct of_device_id omap8250_dt_ids[] = { 1410 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1411 { .compatible = "ti,omap2-uart" }, 1412 { .compatible = "ti,omap3-uart" }, 1413 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1414 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1415 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1416 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1417 {}, 1418 }; 1419 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1420 1421 static int omap8250_probe(struct platform_device *pdev) 1422 { 1423 struct device_node *np = pdev->dev.of_node; 1424 struct omap8250_priv *priv; 1425 const struct omap8250_platdata *pdata; 1426 struct uart_8250_port up; 1427 struct resource *regs; 1428 void __iomem *membase; 1429 int ret; 1430 1431 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1432 if (!regs) { 1433 dev_err(&pdev->dev, "missing registers\n"); 1434 return -EINVAL; 1435 } 1436 1437 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1438 if (!priv) 1439 return -ENOMEM; 1440 1441 membase = devm_ioremap(&pdev->dev, regs->start, 1442 resource_size(regs)); 1443 if (!membase) 1444 return -ENODEV; 1445 1446 memset(&up, 0, sizeof(up)); 1447 up.port.dev = &pdev->dev; 1448 up.port.mapbase = regs->start; 1449 up.port.membase = membase; 1450 /* 1451 * It claims to be 16C750 compatible however it is a little different. 1452 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1453 * have) is enabled via EFR instead of MCR. The type is set here 8250 1454 * just to get things going. UNKNOWN does not work for a few reasons and 1455 * we don't need our own type since we don't use 8250's set_termios() 1456 * or pm callback. 1457 */ 1458 up.port.type = PORT_8250; 1459 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1460 up.port.private_data = priv; 1461 1462 up.tx_loadsz = 64; 1463 up.capabilities = UART_CAP_FIFO; 1464 #ifdef CONFIG_PM 1465 /* 1466 * Runtime PM is mostly transparent. However to do it right we need to a 1467 * TX empty interrupt before we can put the device to auto idle. So if 1468 * PM is not enabled we don't add that flag and can spare that one extra 1469 * interrupt in the TX path. 1470 */ 1471 up.capabilities |= UART_CAP_RPM; 1472 #endif 1473 up.port.set_termios = omap_8250_set_termios; 1474 up.port.set_mctrl = omap8250_set_mctrl; 1475 up.port.pm = omap_8250_pm; 1476 up.port.startup = omap_8250_startup; 1477 up.port.shutdown = omap_8250_shutdown; 1478 up.port.throttle = omap_8250_throttle; 1479 up.port.unthrottle = omap_8250_unthrottle; 1480 up.port.rs485_config = omap8250_rs485_config; 1481 /* same rs485_supported for software emulation and native RS485 */ 1482 up.port.rs485_supported = serial8250_em485_supported; 1483 up.rs485_start_tx = serial8250_em485_start_tx; 1484 up.rs485_stop_tx = serial8250_em485_stop_tx; 1485 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1486 1487 ret = uart_read_port_properties(&up.port); 1488 if (ret) 1489 return ret; 1490 1491 up.port.regshift = OMAP_UART_REGSHIFT; 1492 up.port.fifosize = 64; 1493 1494 if (!up.port.uartclk) { 1495 struct clk *clk; 1496 1497 clk = devm_clk_get(&pdev->dev, NULL); 1498 if (IS_ERR(clk)) { 1499 if (PTR_ERR(clk) == -EPROBE_DEFER) 1500 return -EPROBE_DEFER; 1501 } else { 1502 up.port.uartclk = clk_get_rate(clk); 1503 } 1504 } 1505 1506 if (of_property_read_u32(np, "overrun-throttle-ms", 1507 &up.overrun_backoff_time_ms) != 0) 1508 up.overrun_backoff_time_ms = 0; 1509 1510 pdata = of_device_get_match_data(&pdev->dev); 1511 if (pdata) 1512 priv->habit |= pdata->habit; 1513 1514 if (!up.port.uartclk) { 1515 up.port.uartclk = DEFAULT_CLK_SPEED; 1516 dev_warn(&pdev->dev, 1517 "No clock speed specified: using default: %d\n", 1518 DEFAULT_CLK_SPEED); 1519 } 1520 1521 priv->membase = membase; 1522 priv->line = -ENODEV; 1523 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1524 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1525 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1526 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1527 1528 spin_lock_init(&priv->rx_dma_lock); 1529 1530 platform_set_drvdata(pdev, priv); 1531 1532 device_init_wakeup(&pdev->dev, true); 1533 pm_runtime_enable(&pdev->dev); 1534 pm_runtime_use_autosuspend(&pdev->dev); 1535 1536 /* 1537 * Disable runtime PM until autosuspend delay unless specifically 1538 * enabled by the user via sysfs. This is the historic way to 1539 * prevent an unsafe default policy with lossy characters on wake-up. 1540 * For serdev devices this is not needed, the policy can be managed by 1541 * the serdev driver. 1542 */ 1543 if (!of_get_available_child_count(pdev->dev.of_node)) 1544 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1545 1546 pm_runtime_get_sync(&pdev->dev); 1547 1548 omap_serial_fill_features_erratas(&up, priv); 1549 up.port.handle_irq = omap8250_no_handle_irq; 1550 priv->rx_trigger = RX_TRIGGER; 1551 priv->tx_trigger = TX_TRIGGER; 1552 #ifdef CONFIG_SERIAL_8250_DMA 1553 /* 1554 * Oh DMA support. If there are no DMA properties in the DT then 1555 * we will fall back to a generic DMA channel which does not 1556 * really work here. To ensure that we do not get a generic DMA 1557 * channel assigned, we have the the_no_dma_filter_fn() here. 1558 * To avoid "failed to request DMA" messages we check for DMA 1559 * properties in DT. 1560 */ 1561 ret = of_property_count_strings(np, "dma-names"); 1562 if (ret == 2) { 1563 struct omap8250_dma_params *dma_params = NULL; 1564 struct uart_8250_dma *dma = &priv->omap8250_dma; 1565 1566 dma->fn = the_no_dma_filter_fn; 1567 dma->tx_dma = omap_8250_tx_dma; 1568 dma->rx_dma = omap_8250_rx_dma; 1569 if (pdata) 1570 dma_params = pdata->dma_params; 1571 1572 if (dma_params) { 1573 dma->rx_size = dma_params->rx_size; 1574 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1575 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1576 priv->rx_trigger = dma_params->rx_trigger; 1577 priv->tx_trigger = dma_params->tx_trigger; 1578 } else { 1579 dma->rx_size = RX_TRIGGER; 1580 dma->rxconf.src_maxburst = RX_TRIGGER; 1581 dma->txconf.dst_maxburst = TX_TRIGGER; 1582 } 1583 } 1584 #endif 1585 1586 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1587 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1588 dev_name(&pdev->dev), priv); 1589 if (ret < 0) 1590 return ret; 1591 1592 priv->wakeirq = irq_of_parse_and_map(np, 1); 1593 1594 ret = serial8250_register_8250_port(&up); 1595 if (ret < 0) { 1596 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1597 goto err; 1598 } 1599 priv->line = ret; 1600 pm_runtime_mark_last_busy(&pdev->dev); 1601 pm_runtime_put_autosuspend(&pdev->dev); 1602 return 0; 1603 err: 1604 pm_runtime_dont_use_autosuspend(&pdev->dev); 1605 pm_runtime_put_sync(&pdev->dev); 1606 flush_work(&priv->qos_work); 1607 pm_runtime_disable(&pdev->dev); 1608 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1609 return ret; 1610 } 1611 1612 static void omap8250_remove(struct platform_device *pdev) 1613 { 1614 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1615 struct uart_8250_port *up; 1616 int err; 1617 1618 err = pm_runtime_resume_and_get(&pdev->dev); 1619 if (err) 1620 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1621 1622 up = serial8250_get_port(priv->line); 1623 omap_8250_shutdown(&up->port); 1624 serial8250_unregister_port(priv->line); 1625 priv->line = -ENODEV; 1626 pm_runtime_dont_use_autosuspend(&pdev->dev); 1627 pm_runtime_put_sync(&pdev->dev); 1628 flush_work(&priv->qos_work); 1629 pm_runtime_disable(&pdev->dev); 1630 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1631 device_init_wakeup(&pdev->dev, false); 1632 } 1633 1634 static int omap8250_prepare(struct device *dev) 1635 { 1636 struct omap8250_priv *priv = dev_get_drvdata(dev); 1637 1638 if (!priv) 1639 return 0; 1640 priv->is_suspending = true; 1641 return 0; 1642 } 1643 1644 static void omap8250_complete(struct device *dev) 1645 { 1646 struct omap8250_priv *priv = dev_get_drvdata(dev); 1647 1648 if (!priv) 1649 return; 1650 priv->is_suspending = false; 1651 } 1652 1653 static int omap8250_suspend(struct device *dev) 1654 { 1655 struct omap8250_priv *priv = dev_get_drvdata(dev); 1656 struct uart_8250_port *up = serial8250_get_port(priv->line); 1657 struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); 1658 int err = 0; 1659 1660 serial8250_suspend_port(priv->line); 1661 1662 err = pm_runtime_resume_and_get(dev); 1663 if (err) 1664 return err; 1665 if (!device_may_wakeup(dev)) 1666 priv->wer = 0; 1667 serial_out(up, UART_OMAP_WER, priv->wer); 1668 if (uart_console(&up->port)) { 1669 if (console_suspend_enabled) 1670 err = pm_runtime_force_suspend(dev); 1671 else { 1672 /* 1673 * The pd shall not be powered-off (no console suspend). 1674 * Make copy of genpd flags before to set it always on. 1675 * The original value is restored during the resume. 1676 */ 1677 genpd_flags_console = genpd->flags; 1678 genpd->flags |= GENPD_FLAG_ALWAYS_ON; 1679 } 1680 } 1681 flush_work(&priv->qos_work); 1682 1683 return err; 1684 } 1685 1686 static int omap8250_resume(struct device *dev) 1687 { 1688 struct omap8250_priv *priv = dev_get_drvdata(dev); 1689 struct uart_8250_port *up = serial8250_get_port(priv->line); 1690 struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); 1691 int err; 1692 1693 if (uart_console(&up->port) && console_suspend_enabled) { 1694 if (console_suspend_enabled) { 1695 err = pm_runtime_force_resume(dev); 1696 if (err) 1697 return err; 1698 } else 1699 genpd->flags = genpd_flags_console; 1700 } 1701 1702 serial8250_resume_port(priv->line); 1703 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1704 pm_runtime_mark_last_busy(dev); 1705 pm_runtime_put_autosuspend(dev); 1706 1707 return 0; 1708 } 1709 1710 static int omap8250_lost_context(struct uart_8250_port *up) 1711 { 1712 u32 val; 1713 1714 val = serial_in(up, UART_OMAP_SCR); 1715 /* 1716 * If we lose context, then SCR is set to its reset value of zero. 1717 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1718 * among other bits, to never set the register back to zero again. 1719 */ 1720 if (!val) 1721 return 1; 1722 return 0; 1723 } 1724 1725 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1726 { 1727 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1728 } 1729 1730 /* TODO: in future, this should happen via API in drivers/reset/ */ 1731 static int omap8250_soft_reset(struct device *dev) 1732 { 1733 struct omap8250_priv *priv = dev_get_drvdata(dev); 1734 int timeout = 100; 1735 int sysc; 1736 int syss; 1737 1738 /* 1739 * At least on omap4, unused uarts may not idle after reset without 1740 * a basic scr dma configuration even with no dma in use. The 1741 * module clkctrl status bits will be 1 instead of 3 blocking idle 1742 * for the whole clockdomain. The softreset below will clear scr, 1743 * and we restore it on resume so this is safe to do on all SoCs 1744 * needing omap8250_soft_reset() quirk. Do it in two writes as 1745 * recommended in the comment for omap8250_update_scr(). 1746 */ 1747 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1748 uart_write(priv, UART_OMAP_SCR, 1749 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1750 1751 sysc = uart_read(priv, UART_OMAP_SYSC); 1752 1753 /* softreset the UART */ 1754 sysc |= OMAP_UART_SYSC_SOFTRESET; 1755 uart_write(priv, UART_OMAP_SYSC, sysc); 1756 1757 /* By experiments, 1us enough for reset complete on AM335x */ 1758 do { 1759 udelay(1); 1760 syss = uart_read(priv, UART_OMAP_SYSS); 1761 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1762 1763 if (!timeout) { 1764 dev_err(dev, "timed out waiting for reset done\n"); 1765 return -ETIMEDOUT; 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int omap8250_runtime_suspend(struct device *dev) 1772 { 1773 struct omap8250_priv *priv = dev_get_drvdata(dev); 1774 struct uart_8250_port *up = NULL; 1775 1776 if (priv->line >= 0) 1777 up = serial8250_get_port(priv->line); 1778 1779 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1780 int ret; 1781 1782 ret = omap8250_soft_reset(dev); 1783 if (ret) 1784 return ret; 1785 1786 if (up) { 1787 /* Restore to UART mode after reset (for wakeup) */ 1788 omap8250_update_mdr1(up, priv); 1789 /* Restore wakeup enable register */ 1790 serial_out(up, UART_OMAP_WER, priv->wer); 1791 } 1792 } 1793 1794 if (up && up->dma && up->dma->rxchan) 1795 omap_8250_rx_dma_flush(up); 1796 1797 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1798 schedule_work(&priv->qos_work); 1799 atomic_set(&priv->active, 0); 1800 1801 return 0; 1802 } 1803 1804 static int omap8250_runtime_resume(struct device *dev) 1805 { 1806 struct omap8250_priv *priv = dev_get_drvdata(dev); 1807 struct uart_8250_port *up = NULL; 1808 1809 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1810 if (atomic_read(&priv->active)) 1811 return 0; 1812 1813 if (priv->line >= 0) 1814 up = serial8250_get_port(priv->line); 1815 1816 if (up && omap8250_lost_context(up)) { 1817 uart_port_lock_irq(&up->port); 1818 omap8250_restore_regs(up); 1819 uart_port_unlock_irq(&up->port); 1820 } 1821 1822 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1823 uart_port_lock_irq(&up->port); 1824 omap_8250_rx_dma(up); 1825 uart_port_unlock_irq(&up->port); 1826 } 1827 1828 atomic_set(&priv->active, 1); 1829 priv->latency = priv->calc_latency; 1830 schedule_work(&priv->qos_work); 1831 1832 return 0; 1833 } 1834 1835 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1836 static int __init omap8250_console_fixup(void) 1837 { 1838 char *omap_str; 1839 char *options; 1840 u8 idx; 1841 1842 if (strstr(boot_command_line, "console=ttyS")) 1843 /* user set a ttyS based name for the console */ 1844 return 0; 1845 1846 omap_str = strstr(boot_command_line, "console=ttyO"); 1847 if (!omap_str) 1848 /* user did not set ttyO based console, so we don't care */ 1849 return 0; 1850 1851 omap_str += 12; 1852 if ('0' <= *omap_str && *omap_str <= '9') 1853 idx = *omap_str - '0'; 1854 else 1855 return 0; 1856 1857 omap_str++; 1858 if (omap_str[0] == ',') { 1859 omap_str++; 1860 options = omap_str; 1861 } else { 1862 options = NULL; 1863 } 1864 1865 add_preferred_console("ttyS", idx, options); 1866 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1867 idx, idx); 1868 pr_err("This ensures that you still see kernel messages. Please\n"); 1869 pr_err("update your kernel commandline.\n"); 1870 return 0; 1871 } 1872 console_initcall(omap8250_console_fixup); 1873 #endif 1874 1875 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1876 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1877 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1878 omap8250_runtime_resume, NULL) 1879 .prepare = pm_sleep_ptr(omap8250_prepare), 1880 .complete = pm_sleep_ptr(omap8250_complete), 1881 }; 1882 1883 static struct platform_driver omap8250_platform_driver = { 1884 .driver = { 1885 .name = "omap8250", 1886 .pm = pm_ptr(&omap8250_dev_pm_ops), 1887 .of_match_table = omap8250_dt_ids, 1888 }, 1889 .probe = omap8250_probe, 1890 .remove_new = omap8250_remove, 1891 }; 1892 module_platform_driver(omap8250_platform_driver); 1893 1894 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1895 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1896 MODULE_LICENSE("GPL v2"); 1897