1 /* 2 * 8250-core based driver for the OMAP internal UART 3 * 4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 5 * 6 * Copyright (C) 2014 Sebastian Andrzej Siewior 7 * 8 */ 9 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/serial_8250.h> 14 #include <linux/serial_core.h> 15 #include <linux/serial_reg.h> 16 #include <linux/tty_flip.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/of.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_irq.h> 22 #include <linux/delay.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/console.h> 25 #include <linux/pm_qos.h> 26 #include <linux/dma-mapping.h> 27 28 #include "8250.h" 29 30 #define DEFAULT_CLK_SPEED 48000000 31 32 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 33 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 34 #define OMAP_DMA_TX_KICK (1 << 2) 35 36 #define OMAP_UART_FCR_RX_TRIG 6 37 #define OMAP_UART_FCR_TX_TRIG 4 38 39 /* SCR register bitmasks */ 40 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 41 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 42 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 43 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 44 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 45 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 46 47 /* MVR register bitmasks */ 48 #define OMAP_UART_MVR_SCHEME_SHIFT 30 49 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 50 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 51 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 52 #define OMAP_UART_MVR_MAJ_MASK 0x700 53 #define OMAP_UART_MVR_MAJ_SHIFT 8 54 #define OMAP_UART_MVR_MIN_MASK 0x3f 55 56 #define UART_TI752_TLR_TX 0 57 #define UART_TI752_TLR_RX 4 58 59 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 60 #define TRIGGER_FCR_MASK(x) (x & 3) 61 62 /* Enable XON/XOFF flow control on output */ 63 #define OMAP_UART_SW_TX 0x08 64 /* Enable XON/XOFF flow control on input */ 65 #define OMAP_UART_SW_RX 0x02 66 67 #define OMAP_UART_WER_MOD_WKUP 0x7f 68 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 69 70 #define TX_TRIGGER 1 71 #define RX_TRIGGER 48 72 73 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 74 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 75 76 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 77 78 #define OMAP_UART_REV_46 0x0406 79 #define OMAP_UART_REV_52 0x0502 80 #define OMAP_UART_REV_63 0x0603 81 82 struct omap8250_priv { 83 int line; 84 u8 habit; 85 u8 mdr1; 86 u8 efr; 87 u8 scr; 88 u8 wer; 89 u8 xon; 90 u8 xoff; 91 u8 delayed_restore; 92 u16 quot; 93 94 bool is_suspending; 95 int wakeirq; 96 int wakeups_enabled; 97 u32 latency; 98 u32 calc_latency; 99 struct pm_qos_request pm_qos_request; 100 struct work_struct qos_work; 101 struct uart_8250_dma omap8250_dma; 102 }; 103 104 static u32 uart_read(struct uart_8250_port *up, u32 reg) 105 { 106 return readl(up->port.membase + (reg << up->port.regshift)); 107 } 108 109 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 110 { 111 struct uart_8250_port *up = up_to_u8250p(port); 112 struct omap8250_priv *priv = up->port.private_data; 113 u8 lcr; 114 115 serial8250_do_set_mctrl(port, mctrl); 116 117 /* 118 * Turn off autoRTS if RTS is lowered and restore autoRTS setting 119 * if RTS is raised 120 */ 121 lcr = serial_in(up, UART_LCR); 122 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 123 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 124 priv->efr |= UART_EFR_RTS; 125 else 126 priv->efr &= ~UART_EFR_RTS; 127 serial_out(up, UART_EFR, priv->efr); 128 serial_out(up, UART_LCR, lcr); 129 } 130 131 /* 132 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 133 * The access to uart register after MDR1 Access 134 * causes UART to corrupt data. 135 * 136 * Need a delay = 137 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 138 * give 10 times as much 139 */ 140 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 141 struct omap8250_priv *priv) 142 { 143 u8 timeout = 255; 144 u8 old_mdr1; 145 146 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 147 if (old_mdr1 == priv->mdr1) 148 return; 149 150 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 151 udelay(2); 152 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 153 UART_FCR_CLEAR_RCVR); 154 /* 155 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 156 * TX_FIFO_E bit is 1. 157 */ 158 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 159 (UART_LSR_THRE | UART_LSR_DR))) { 160 timeout--; 161 if (!timeout) { 162 /* Should *never* happen. we warn and carry on */ 163 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 164 serial_in(up, UART_LSR)); 165 break; 166 } 167 udelay(1); 168 } 169 } 170 171 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 172 struct omap8250_priv *priv) 173 { 174 unsigned int uartclk = port->uartclk; 175 unsigned int div_13, div_16; 176 unsigned int abs_d13, abs_d16; 177 178 /* 179 * Old custom speed handling. 180 */ 181 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 182 priv->quot = port->custom_divisor & 0xffff; 183 /* 184 * I assume that nobody is using this. But hey, if somebody 185 * would like to specify the divisor _and_ the mode then the 186 * driver is ready and waiting for it. 187 */ 188 if (port->custom_divisor & (1 << 16)) 189 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 190 else 191 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 192 return; 193 } 194 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 195 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 196 197 if (!div_13) 198 div_13 = 1; 199 if (!div_16) 200 div_16 = 1; 201 202 abs_d13 = abs(baud - uartclk / 13 / div_13); 203 abs_d16 = abs(baud - uartclk / 16 / div_16); 204 205 if (abs_d13 >= abs_d16) { 206 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 207 priv->quot = div_16; 208 } else { 209 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 210 priv->quot = div_13; 211 } 212 } 213 214 static void omap8250_update_scr(struct uart_8250_port *up, 215 struct omap8250_priv *priv) 216 { 217 u8 old_scr; 218 219 old_scr = serial_in(up, UART_OMAP_SCR); 220 if (old_scr == priv->scr) 221 return; 222 223 /* 224 * The manual recommends not to enable the DMA mode selector in the SCR 225 * (instead of the FCR) register _and_ selecting the DMA mode as one 226 * register write because this may lead to malfunction. 227 */ 228 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 229 serial_out(up, UART_OMAP_SCR, 230 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 231 serial_out(up, UART_OMAP_SCR, priv->scr); 232 } 233 234 static void omap8250_restore_regs(struct uart_8250_port *up) 235 { 236 struct omap8250_priv *priv = up->port.private_data; 237 struct uart_8250_dma *dma = up->dma; 238 239 if (dma && dma->tx_running) { 240 /* 241 * TCSANOW requests the change to occur immediately however if 242 * we have a TX-DMA operation in progress then it has been 243 * observed that it might stall and never complete. Therefore we 244 * delay DMA completes to prevent this hang from happen. 245 */ 246 priv->delayed_restore = 1; 247 return; 248 } 249 250 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 251 serial_out(up, UART_EFR, UART_EFR_ECB); 252 253 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 254 serial_out(up, UART_MCR, UART_MCR_TCRTLR); 255 serial_out(up, UART_FCR, up->fcr); 256 257 omap8250_update_scr(up, priv); 258 259 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 260 261 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 262 OMAP_UART_TCR_HALT(52)); 263 serial_out(up, UART_TI752_TLR, 264 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 265 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 266 267 serial_out(up, UART_LCR, 0); 268 269 /* drop TCR + TLR access, we setup XON/XOFF later */ 270 serial_out(up, UART_MCR, up->mcr); 271 serial_out(up, UART_IER, up->ier); 272 273 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 274 serial_dl_write(up, priv->quot); 275 276 serial_out(up, UART_EFR, priv->efr); 277 278 /* Configure flow control */ 279 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 280 serial_out(up, UART_XON1, priv->xon); 281 serial_out(up, UART_XOFF1, priv->xoff); 282 283 serial_out(up, UART_LCR, up->lcr); 284 /* need mode A for FCR */ 285 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 286 omap_8250_mdr1_errataset(up, priv); 287 else 288 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 289 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 290 } 291 292 /* 293 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 294 * some differences in how we want to handle flow control. 295 */ 296 static void omap_8250_set_termios(struct uart_port *port, 297 struct ktermios *termios, 298 struct ktermios *old) 299 { 300 struct uart_8250_port *up = 301 container_of(port, struct uart_8250_port, port); 302 struct omap8250_priv *priv = up->port.private_data; 303 unsigned char cval = 0; 304 unsigned int baud; 305 306 switch (termios->c_cflag & CSIZE) { 307 case CS5: 308 cval = UART_LCR_WLEN5; 309 break; 310 case CS6: 311 cval = UART_LCR_WLEN6; 312 break; 313 case CS7: 314 cval = UART_LCR_WLEN7; 315 break; 316 default: 317 case CS8: 318 cval = UART_LCR_WLEN8; 319 break; 320 } 321 322 if (termios->c_cflag & CSTOPB) 323 cval |= UART_LCR_STOP; 324 if (termios->c_cflag & PARENB) 325 cval |= UART_LCR_PARITY; 326 if (!(termios->c_cflag & PARODD)) 327 cval |= UART_LCR_EPAR; 328 if (termios->c_cflag & CMSPAR) 329 cval |= UART_LCR_SPAR; 330 331 /* 332 * Ask the core to calculate the divisor for us. 333 */ 334 baud = uart_get_baud_rate(port, termios, old, 335 port->uartclk / 16 / 0xffff, 336 port->uartclk / 13); 337 omap_8250_get_divisor(port, baud, priv); 338 339 /* 340 * Ok, we're now changing the port state. Do it with 341 * interrupts disabled. 342 */ 343 pm_runtime_get_sync(port->dev); 344 spin_lock_irq(&port->lock); 345 346 /* 347 * Update the per-port timeout. 348 */ 349 uart_update_timeout(port, termios->c_cflag, baud); 350 351 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 352 if (termios->c_iflag & INPCK) 353 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 354 if (termios->c_iflag & (IGNBRK | PARMRK)) 355 up->port.read_status_mask |= UART_LSR_BI; 356 357 /* 358 * Characters to ignore 359 */ 360 up->port.ignore_status_mask = 0; 361 if (termios->c_iflag & IGNPAR) 362 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 363 if (termios->c_iflag & IGNBRK) { 364 up->port.ignore_status_mask |= UART_LSR_BI; 365 /* 366 * If we're ignoring parity and break indicators, 367 * ignore overruns too (for real raw support). 368 */ 369 if (termios->c_iflag & IGNPAR) 370 up->port.ignore_status_mask |= UART_LSR_OE; 371 } 372 373 /* 374 * ignore all characters if CREAD is not set 375 */ 376 if ((termios->c_cflag & CREAD) == 0) 377 up->port.ignore_status_mask |= UART_LSR_DR; 378 379 /* 380 * Modem status interrupts 381 */ 382 up->ier &= ~UART_IER_MSI; 383 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 384 up->ier |= UART_IER_MSI; 385 386 up->lcr = cval; 387 /* Up to here it was mostly serial8250_do_set_termios() */ 388 389 /* 390 * We enable TRIG_GRANU for RX and TX and additionaly we set 391 * SCR_TX_EMPTY bit. The result is the following: 392 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 393 * - less than RX_TRIGGER number of bytes will also cause an interrupt 394 * once the UART decides that there no new bytes arriving. 395 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 396 * empty - the trigger level is ignored here. 397 * 398 * Once DMA is enabled: 399 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 400 * bytes in the TX FIFO. On each assert the DMA engine will move 401 * TX_TRIGGER bytes into the FIFO. 402 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 403 * the FIFO and move RX_TRIGGER bytes. 404 * This is because threshold and trigger values are the same. 405 */ 406 up->fcr = UART_FCR_ENABLE_FIFO; 407 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 408 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 409 410 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 411 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 412 413 if (up->dma) 414 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 415 OMAP_UART_SCR_DMAMODE_CTL; 416 417 priv->xon = termios->c_cc[VSTART]; 418 priv->xoff = termios->c_cc[VSTOP]; 419 420 priv->efr = 0; 421 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); 422 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 423 424 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 425 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 426 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 427 priv->efr |= UART_EFR_CTS; 428 } else if (up->port.flags & UPF_SOFT_FLOW) { 429 /* 430 * IXON Flag: 431 * Enable XON/XOFF flow control on input. 432 * Receiver compares XON1, XOFF1. 433 */ 434 if (termios->c_iflag & IXON) 435 priv->efr |= OMAP_UART_SW_RX; 436 437 /* 438 * IXOFF Flag: 439 * Enable XON/XOFF flow control on output. 440 * Transmit XON1, XOFF1 441 */ 442 if (termios->c_iflag & IXOFF) { 443 up->port.status |= UPSTAT_AUTOXOFF; 444 priv->efr |= OMAP_UART_SW_TX; 445 } 446 447 /* 448 * IXANY Flag: 449 * Enable any character to restart output. 450 * Operation resumes after receiving any 451 * character after recognition of the XOFF character 452 */ 453 if (termios->c_iflag & IXANY) 454 up->mcr |= UART_MCR_XONANY; 455 } 456 omap8250_restore_regs(up); 457 458 spin_unlock_irq(&up->port.lock); 459 pm_runtime_mark_last_busy(port->dev); 460 pm_runtime_put_autosuspend(port->dev); 461 462 /* calculate wakeup latency constraint */ 463 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 464 priv->latency = priv->calc_latency; 465 466 schedule_work(&priv->qos_work); 467 468 /* Don't rewrite B0 */ 469 if (tty_termios_baud_rate(termios)) 470 tty_termios_encode_baud_rate(termios, baud, baud); 471 } 472 473 /* same as 8250 except that we may have extra flow bits set in EFR */ 474 static void omap_8250_pm(struct uart_port *port, unsigned int state, 475 unsigned int oldstate) 476 { 477 struct uart_8250_port *up = up_to_u8250p(port); 478 u8 efr; 479 480 pm_runtime_get_sync(port->dev); 481 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 482 efr = serial_in(up, UART_EFR); 483 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 484 serial_out(up, UART_LCR, 0); 485 486 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 487 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 488 serial_out(up, UART_EFR, efr); 489 serial_out(up, UART_LCR, 0); 490 491 pm_runtime_mark_last_busy(port->dev); 492 pm_runtime_put_autosuspend(port->dev); 493 } 494 495 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 496 struct omap8250_priv *priv) 497 { 498 u32 mvr, scheme; 499 u16 revision, major, minor; 500 501 mvr = uart_read(up, UART_OMAP_MVER); 502 503 /* Check revision register scheme */ 504 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 505 506 switch (scheme) { 507 case 0: /* Legacy Scheme: OMAP2/3 */ 508 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 509 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 510 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 511 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 512 break; 513 case 1: 514 /* New Scheme: OMAP4+ */ 515 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 516 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 517 OMAP_UART_MVR_MAJ_SHIFT; 518 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 519 break; 520 default: 521 dev_warn(up->port.dev, 522 "Unknown revision, defaulting to highest\n"); 523 /* highest possible revision */ 524 major = 0xff; 525 minor = 0xff; 526 } 527 /* normalize revision for the driver */ 528 revision = UART_BUILD_REVISION(major, minor); 529 530 switch (revision) { 531 case OMAP_UART_REV_46: 532 priv->habit = UART_ERRATA_i202_MDR1_ACCESS; 533 break; 534 case OMAP_UART_REV_52: 535 priv->habit = UART_ERRATA_i202_MDR1_ACCESS | 536 OMAP_UART_WER_HAS_TX_WAKEUP; 537 break; 538 case OMAP_UART_REV_63: 539 priv->habit = UART_ERRATA_i202_MDR1_ACCESS | 540 OMAP_UART_WER_HAS_TX_WAKEUP; 541 break; 542 default: 543 break; 544 } 545 } 546 547 static void omap8250_uart_qos_work(struct work_struct *work) 548 { 549 struct omap8250_priv *priv; 550 551 priv = container_of(work, struct omap8250_priv, qos_work); 552 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 553 } 554 555 static irqreturn_t omap_wake_irq(int irq, void *dev_id) 556 { 557 struct uart_port *port = dev_id; 558 int ret; 559 560 ret = port->handle_irq(port); 561 if (ret) 562 return IRQ_HANDLED; 563 return IRQ_NONE; 564 } 565 566 static int omap_8250_startup(struct uart_port *port) 567 { 568 struct uart_8250_port *up = 569 container_of(port, struct uart_8250_port, port); 570 struct omap8250_priv *priv = port->private_data; 571 572 int ret; 573 574 if (priv->wakeirq) { 575 ret = request_irq(priv->wakeirq, omap_wake_irq, 576 port->irqflags, "uart wakeup irq", port); 577 if (ret) 578 return ret; 579 disable_irq(priv->wakeirq); 580 } 581 582 pm_runtime_get_sync(port->dev); 583 584 ret = serial8250_do_startup(port); 585 if (ret) 586 goto err; 587 588 #ifdef CONFIG_PM 589 up->capabilities |= UART_CAP_RPM; 590 #endif 591 592 /* Enable module level wake up */ 593 priv->wer = OMAP_UART_WER_MOD_WKUP; 594 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 595 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 596 serial_out(up, UART_OMAP_WER, priv->wer); 597 598 if (up->dma) 599 up->dma->rx_dma(up, 0); 600 601 pm_runtime_mark_last_busy(port->dev); 602 pm_runtime_put_autosuspend(port->dev); 603 return 0; 604 err: 605 pm_runtime_mark_last_busy(port->dev); 606 pm_runtime_put_autosuspend(port->dev); 607 if (priv->wakeirq) 608 free_irq(priv->wakeirq, port); 609 return ret; 610 } 611 612 static void omap_8250_shutdown(struct uart_port *port) 613 { 614 struct uart_8250_port *up = 615 container_of(port, struct uart_8250_port, port); 616 struct omap8250_priv *priv = port->private_data; 617 618 flush_work(&priv->qos_work); 619 if (up->dma) 620 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); 621 622 pm_runtime_get_sync(port->dev); 623 624 serial_out(up, UART_OMAP_WER, 0); 625 serial8250_do_shutdown(port); 626 627 pm_runtime_mark_last_busy(port->dev); 628 pm_runtime_put_autosuspend(port->dev); 629 630 if (priv->wakeirq) 631 free_irq(priv->wakeirq, port); 632 } 633 634 static void omap_8250_throttle(struct uart_port *port) 635 { 636 unsigned long flags; 637 struct uart_8250_port *up = 638 container_of(port, struct uart_8250_port, port); 639 640 pm_runtime_get_sync(port->dev); 641 642 spin_lock_irqsave(&port->lock, flags); 643 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 644 serial_out(up, UART_IER, up->ier); 645 spin_unlock_irqrestore(&port->lock, flags); 646 647 pm_runtime_mark_last_busy(port->dev); 648 pm_runtime_put_autosuspend(port->dev); 649 } 650 651 static void omap_8250_unthrottle(struct uart_port *port) 652 { 653 unsigned long flags; 654 struct uart_8250_port *up = 655 container_of(port, struct uart_8250_port, port); 656 657 pm_runtime_get_sync(port->dev); 658 659 spin_lock_irqsave(&port->lock, flags); 660 up->ier |= UART_IER_RLSI | UART_IER_RDI; 661 serial_out(up, UART_IER, up->ier); 662 spin_unlock_irqrestore(&port->lock, flags); 663 664 pm_runtime_mark_last_busy(port->dev); 665 pm_runtime_put_autosuspend(port->dev); 666 } 667 668 #ifdef CONFIG_SERIAL_8250_DMA 669 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); 670 671 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) 672 { 673 struct uart_8250_dma *dma = p->dma; 674 struct tty_port *tty_port = &p->port.state->port; 675 struct dma_tx_state state; 676 int count; 677 678 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, 679 dma->rx_size, DMA_FROM_DEVICE); 680 681 dma->rx_running = 0; 682 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 683 dmaengine_terminate_all(dma->rxchan); 684 685 count = dma->rx_size - state.residue; 686 687 tty_insert_flip_string(tty_port, dma->rx_buf, count); 688 p->port.icount.rx += count; 689 if (!error) 690 omap_8250_rx_dma(p, 0); 691 692 tty_flip_buffer_push(tty_port); 693 } 694 695 static void __dma_rx_complete(void *param) 696 { 697 __dma_rx_do_complete(param, false); 698 } 699 700 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 701 { 702 struct uart_8250_dma *dma = p->dma; 703 struct dma_async_tx_descriptor *desc; 704 705 switch (iir & 0x3f) { 706 case UART_IIR_RLSI: 707 /* 8250_core handles errors and break interrupts */ 708 if (dma->rx_running) { 709 dmaengine_pause(dma->rxchan); 710 __dma_rx_do_complete(p, true); 711 } 712 return -EIO; 713 case UART_IIR_RX_TIMEOUT: 714 /* 715 * If RCVR FIFO trigger level was not reached, complete the 716 * transfer and let 8250_core copy the remaining data. 717 */ 718 if (dma->rx_running) { 719 dmaengine_pause(dma->rxchan); 720 __dma_rx_do_complete(p, true); 721 } 722 return -ETIMEDOUT; 723 case UART_IIR_RDI: 724 /* 725 * The OMAP UART is a special BEAST. If we receive RDI we _have_ 726 * a DMA transfer programmed but it didn't work. One reason is 727 * that we were too slow and there were too many bytes in the 728 * FIFO, the UART counted wrong and never kicked the DMA engine 729 * to do anything. That means once we receive RDI on OMAP then 730 * the DMA won't do anything soon so we have to cancel the DMA 731 * transfer and purge the FIFO manually. 732 */ 733 if (dma->rx_running) { 734 dmaengine_pause(dma->rxchan); 735 __dma_rx_do_complete(p, true); 736 } 737 return -ETIMEDOUT; 738 739 default: 740 break; 741 } 742 743 if (dma->rx_running) 744 return 0; 745 746 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 747 dma->rx_size, DMA_DEV_TO_MEM, 748 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 749 if (!desc) 750 return -EBUSY; 751 752 dma->rx_running = 1; 753 desc->callback = __dma_rx_complete; 754 desc->callback_param = p; 755 756 dma->rx_cookie = dmaengine_submit(desc); 757 758 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, 759 dma->rx_size, DMA_FROM_DEVICE); 760 761 dma_async_issue_pending(dma->rxchan); 762 return 0; 763 } 764 765 static int omap_8250_tx_dma(struct uart_8250_port *p); 766 767 static void omap_8250_dma_tx_complete(void *param) 768 { 769 struct uart_8250_port *p = param; 770 struct uart_8250_dma *dma = p->dma; 771 struct circ_buf *xmit = &p->port.state->xmit; 772 unsigned long flags; 773 bool en_thri = false; 774 struct omap8250_priv *priv = p->port.private_data; 775 776 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 777 UART_XMIT_SIZE, DMA_TO_DEVICE); 778 779 spin_lock_irqsave(&p->port.lock, flags); 780 781 dma->tx_running = 0; 782 783 xmit->tail += dma->tx_size; 784 xmit->tail &= UART_XMIT_SIZE - 1; 785 p->port.icount.tx += dma->tx_size; 786 787 if (priv->delayed_restore) { 788 priv->delayed_restore = 0; 789 omap8250_restore_regs(p); 790 } 791 792 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 793 uart_write_wakeup(&p->port); 794 795 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 796 int ret; 797 798 ret = omap_8250_tx_dma(p); 799 if (ret) 800 en_thri = true; 801 802 } else if (p->capabilities & UART_CAP_RPM) { 803 en_thri = true; 804 } 805 806 if (en_thri) { 807 dma->tx_err = 1; 808 p->ier |= UART_IER_THRI; 809 serial_port_out(&p->port, UART_IER, p->ier); 810 } 811 812 spin_unlock_irqrestore(&p->port.lock, flags); 813 } 814 815 static int omap_8250_tx_dma(struct uart_8250_port *p) 816 { 817 struct uart_8250_dma *dma = p->dma; 818 struct omap8250_priv *priv = p->port.private_data; 819 struct circ_buf *xmit = &p->port.state->xmit; 820 struct dma_async_tx_descriptor *desc; 821 unsigned int skip_byte = 0; 822 int ret; 823 824 if (dma->tx_running) 825 return 0; 826 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 827 828 /* 829 * Even if no data, we need to return an error for the two cases 830 * below so serial8250_tx_chars() is invoked and properly clears 831 * THRI and/or runtime suspend. 832 */ 833 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 834 ret = -EBUSY; 835 goto err; 836 } 837 if (p->ier & UART_IER_THRI) { 838 p->ier &= ~UART_IER_THRI; 839 serial_out(p, UART_IER, p->ier); 840 } 841 return 0; 842 } 843 844 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 845 if (priv->habit & OMAP_DMA_TX_KICK) { 846 u8 tx_lvl; 847 848 /* 849 * We need to put the first byte into the FIFO in order to start 850 * the DMA transfer. For transfers smaller than four bytes we 851 * don't bother doing DMA at all. It seem not matter if there 852 * are still bytes in the FIFO from the last transfer (in case 853 * we got here directly from omap_8250_dma_tx_complete()). Bytes 854 * leaving the FIFO seem not to trigger the DMA transfer. It is 855 * really the byte that we put into the FIFO. 856 * If the FIFO is already full then we most likely got here from 857 * omap_8250_dma_tx_complete(). And this means the DMA engine 858 * just completed its work. We don't have to wait the complete 859 * 86us at 115200,8n1 but around 60us (not to mention lower 860 * baudrates). So in that case we take the interrupt and try 861 * again with an empty FIFO. 862 */ 863 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 864 if (tx_lvl == p->tx_loadsz) { 865 ret = -EBUSY; 866 goto err; 867 } 868 if (dma->tx_size < 4) { 869 ret = -EINVAL; 870 goto err; 871 } 872 skip_byte = 1; 873 } 874 875 desc = dmaengine_prep_slave_single(dma->txchan, 876 dma->tx_addr + xmit->tail + skip_byte, 877 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 878 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 879 if (!desc) { 880 ret = -EBUSY; 881 goto err; 882 } 883 884 dma->tx_running = 1; 885 886 desc->callback = omap_8250_dma_tx_complete; 887 desc->callback_param = p; 888 889 dma->tx_cookie = dmaengine_submit(desc); 890 891 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 892 UART_XMIT_SIZE, DMA_TO_DEVICE); 893 894 dma_async_issue_pending(dma->txchan); 895 if (dma->tx_err) 896 dma->tx_err = 0; 897 898 if (p->ier & UART_IER_THRI) { 899 p->ier &= ~UART_IER_THRI; 900 serial_out(p, UART_IER, p->ier); 901 } 902 if (skip_byte) 903 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 904 return 0; 905 err: 906 dma->tx_err = 1; 907 return ret; 908 } 909 910 /* 911 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 912 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 913 * use the default routine in the non-DMA case and this one for with DMA. 914 */ 915 static int omap_8250_dma_handle_irq(struct uart_port *port) 916 { 917 struct uart_8250_port *up = up_to_u8250p(port); 918 unsigned char status; 919 unsigned long flags; 920 u8 iir; 921 int dma_err = 0; 922 923 serial8250_rpm_get(up); 924 925 iir = serial_port_in(port, UART_IIR); 926 if (iir & UART_IIR_NO_INT) { 927 serial8250_rpm_put(up); 928 return 0; 929 } 930 931 spin_lock_irqsave(&port->lock, flags); 932 933 status = serial_port_in(port, UART_LSR); 934 935 if (status & (UART_LSR_DR | UART_LSR_BI)) { 936 937 dma_err = omap_8250_rx_dma(up, iir); 938 if (dma_err) { 939 status = serial8250_rx_chars(up, status); 940 omap_8250_rx_dma(up, 0); 941 } 942 } 943 serial8250_modem_status(up); 944 if (status & UART_LSR_THRE && up->dma->tx_err) { 945 if (uart_tx_stopped(&up->port) || 946 uart_circ_empty(&up->port.state->xmit)) { 947 up->dma->tx_err = 0; 948 serial8250_tx_chars(up); 949 } else { 950 /* 951 * try again due to an earlier failer which 952 * might have been resolved by now. 953 */ 954 dma_err = omap_8250_tx_dma(up); 955 if (dma_err) 956 serial8250_tx_chars(up); 957 } 958 } 959 960 spin_unlock_irqrestore(&port->lock, flags); 961 serial8250_rpm_put(up); 962 return 1; 963 } 964 965 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 966 { 967 return false; 968 } 969 970 #else 971 972 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 973 { 974 return -EINVAL; 975 } 976 #endif 977 978 static int omap8250_probe(struct platform_device *pdev) 979 { 980 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 981 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 982 struct omap8250_priv *priv; 983 struct uart_8250_port up; 984 int ret; 985 void __iomem *membase; 986 987 if (!regs || !irq) { 988 dev_err(&pdev->dev, "missing registers or irq\n"); 989 return -EINVAL; 990 } 991 992 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 993 if (!priv) 994 return -ENOMEM; 995 996 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 997 resource_size(regs)); 998 if (!membase) 999 return -ENODEV; 1000 1001 memset(&up, 0, sizeof(up)); 1002 up.port.dev = &pdev->dev; 1003 up.port.mapbase = regs->start; 1004 up.port.membase = membase; 1005 up.port.irq = irq->start; 1006 /* 1007 * It claims to be 16C750 compatible however it is a little different. 1008 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1009 * have) is enabled via EFR instead of MCR. The type is set here 8250 1010 * just to get things going. UNKNOWN does not work for a few reasons and 1011 * we don't need our own type since we don't use 8250's set_termios() 1012 * or pm callback. 1013 */ 1014 up.port.type = PORT_8250; 1015 up.port.iotype = UPIO_MEM; 1016 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1017 UPF_HARD_FLOW; 1018 up.port.private_data = priv; 1019 1020 up.port.regshift = 2; 1021 up.port.fifosize = 64; 1022 up.tx_loadsz = 64; 1023 up.capabilities = UART_CAP_FIFO; 1024 #ifdef CONFIG_PM 1025 /* 1026 * Runtime PM is mostly transparent. However to do it right we need to a 1027 * TX empty interrupt before we can put the device to auto idle. So if 1028 * PM is not enabled we don't add that flag and can spare that one extra 1029 * interrupt in the TX path. 1030 */ 1031 up.capabilities |= UART_CAP_RPM; 1032 #endif 1033 up.port.set_termios = omap_8250_set_termios; 1034 up.port.set_mctrl = omap8250_set_mctrl; 1035 up.port.pm = omap_8250_pm; 1036 up.port.startup = omap_8250_startup; 1037 up.port.shutdown = omap_8250_shutdown; 1038 up.port.throttle = omap_8250_throttle; 1039 up.port.unthrottle = omap_8250_unthrottle; 1040 1041 if (pdev->dev.of_node) { 1042 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1043 1044 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1045 &up.port.uartclk); 1046 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1047 } else { 1048 ret = pdev->id; 1049 } 1050 if (ret < 0) { 1051 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1052 return ret; 1053 } 1054 up.port.line = ret; 1055 1056 if (!up.port.uartclk) { 1057 up.port.uartclk = DEFAULT_CLK_SPEED; 1058 dev_warn(&pdev->dev, 1059 "No clock speed specified: using default: %d\n", 1060 DEFAULT_CLK_SPEED); 1061 } 1062 1063 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1064 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1065 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1066 priv->latency); 1067 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1068 1069 device_init_wakeup(&pdev->dev, true); 1070 pm_runtime_use_autosuspend(&pdev->dev); 1071 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1072 1073 pm_runtime_irq_safe(&pdev->dev); 1074 pm_runtime_enable(&pdev->dev); 1075 1076 pm_runtime_get_sync(&pdev->dev); 1077 1078 omap_serial_fill_features_erratas(&up, priv); 1079 #ifdef CONFIG_SERIAL_8250_DMA 1080 if (pdev->dev.of_node) { 1081 /* 1082 * Oh DMA support. If there are no DMA properties in the DT then 1083 * we will fall back to a generic DMA channel which does not 1084 * really work here. To ensure that we do not get a generic DMA 1085 * channel assigned, we have the the_no_dma_filter_fn() here. 1086 * To avoid "failed to request DMA" messages we check for DMA 1087 * properties in DT. 1088 */ 1089 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1090 if (ret == 2) { 1091 up.dma = &priv->omap8250_dma; 1092 up.port.handle_irq = omap_8250_dma_handle_irq; 1093 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1094 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1095 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1096 priv->omap8250_dma.rx_size = RX_TRIGGER; 1097 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1098 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1099 1100 if (of_machine_is_compatible("ti,am33xx")) 1101 priv->habit |= OMAP_DMA_TX_KICK; 1102 } 1103 } 1104 #endif 1105 ret = serial8250_register_8250_port(&up); 1106 if (ret < 0) { 1107 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1108 goto err; 1109 } 1110 priv->line = ret; 1111 platform_set_drvdata(pdev, priv); 1112 pm_runtime_mark_last_busy(&pdev->dev); 1113 pm_runtime_put_autosuspend(&pdev->dev); 1114 return 0; 1115 err: 1116 pm_runtime_put(&pdev->dev); 1117 pm_runtime_disable(&pdev->dev); 1118 return ret; 1119 } 1120 1121 static int omap8250_remove(struct platform_device *pdev) 1122 { 1123 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1124 1125 pm_runtime_put_sync(&pdev->dev); 1126 pm_runtime_disable(&pdev->dev); 1127 serial8250_unregister_port(priv->line); 1128 pm_qos_remove_request(&priv->pm_qos_request); 1129 device_init_wakeup(&pdev->dev, false); 1130 return 0; 1131 } 1132 1133 #ifdef CONFIG_PM 1134 1135 static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv, 1136 bool enable) 1137 { 1138 if (!priv->wakeirq) 1139 return; 1140 1141 if (enable) 1142 enable_irq(priv->wakeirq); 1143 else 1144 disable_irq_nosync(priv->wakeirq); 1145 } 1146 1147 static void omap8250_enable_wakeup(struct omap8250_priv *priv, 1148 bool enable) 1149 { 1150 if (enable == priv->wakeups_enabled) 1151 return; 1152 1153 omap8250_enable_wakeirq(priv, enable); 1154 priv->wakeups_enabled = enable; 1155 } 1156 #endif 1157 1158 #ifdef CONFIG_PM_SLEEP 1159 static int omap8250_prepare(struct device *dev) 1160 { 1161 struct omap8250_priv *priv = dev_get_drvdata(dev); 1162 1163 if (!priv) 1164 return 0; 1165 priv->is_suspending = true; 1166 return 0; 1167 } 1168 1169 static void omap8250_complete(struct device *dev) 1170 { 1171 struct omap8250_priv *priv = dev_get_drvdata(dev); 1172 1173 if (!priv) 1174 return; 1175 priv->is_suspending = false; 1176 } 1177 1178 static int omap8250_suspend(struct device *dev) 1179 { 1180 struct omap8250_priv *priv = dev_get_drvdata(dev); 1181 1182 serial8250_suspend_port(priv->line); 1183 flush_work(&priv->qos_work); 1184 1185 if (device_may_wakeup(dev)) 1186 omap8250_enable_wakeup(priv, true); 1187 else 1188 omap8250_enable_wakeup(priv, false); 1189 return 0; 1190 } 1191 1192 static int omap8250_resume(struct device *dev) 1193 { 1194 struct omap8250_priv *priv = dev_get_drvdata(dev); 1195 1196 if (device_may_wakeup(dev)) 1197 omap8250_enable_wakeup(priv, false); 1198 1199 serial8250_resume_port(priv->line); 1200 return 0; 1201 } 1202 #else 1203 #define omap8250_prepare NULL 1204 #define omap8250_complete NULL 1205 #endif 1206 1207 #ifdef CONFIG_PM 1208 static int omap8250_lost_context(struct uart_8250_port *up) 1209 { 1210 u32 val; 1211 1212 val = serial_in(up, UART_OMAP_MDR1); 1213 /* 1214 * If we lose context, then MDR1 is set to its reset value which is 1215 * UART_OMAP_MDR1_DISABLE. After set_termios() we set it either to 13x 1216 * or 16x but never to disable again. 1217 */ 1218 if (val == UART_OMAP_MDR1_DISABLE) 1219 return 1; 1220 return 0; 1221 } 1222 1223 static int omap8250_runtime_suspend(struct device *dev) 1224 { 1225 struct omap8250_priv *priv = dev_get_drvdata(dev); 1226 struct uart_8250_port *up; 1227 1228 up = serial8250_get_port(priv->line); 1229 /* 1230 * When using 'no_console_suspend', the console UART must not be 1231 * suspended. Since driver suspend is managed by runtime suspend, 1232 * preventing runtime suspend (by returning error) will keep device 1233 * active during suspend. 1234 */ 1235 if (priv->is_suspending && !console_suspend_enabled) { 1236 if (uart_console(&up->port)) 1237 return -EBUSY; 1238 } 1239 1240 omap8250_enable_wakeup(priv, true); 1241 if (up->dma) 1242 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); 1243 1244 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1245 schedule_work(&priv->qos_work); 1246 1247 return 0; 1248 } 1249 1250 static int omap8250_runtime_resume(struct device *dev) 1251 { 1252 struct omap8250_priv *priv = dev_get_drvdata(dev); 1253 struct uart_8250_port *up; 1254 int loss_cntx; 1255 1256 /* In case runtime-pm tries this before we are setup */ 1257 if (!priv) 1258 return 0; 1259 1260 up = serial8250_get_port(priv->line); 1261 omap8250_enable_wakeup(priv, false); 1262 loss_cntx = omap8250_lost_context(up); 1263 1264 if (loss_cntx) 1265 omap8250_restore_regs(up); 1266 1267 if (up->dma) 1268 omap_8250_rx_dma(up, 0); 1269 1270 priv->latency = priv->calc_latency; 1271 schedule_work(&priv->qos_work); 1272 return 0; 1273 } 1274 #endif 1275 1276 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1277 static int __init omap8250_console_fixup(void) 1278 { 1279 char *omap_str; 1280 char *options; 1281 u8 idx; 1282 1283 if (strstr(boot_command_line, "console=ttyS")) 1284 /* user set a ttyS based name for the console */ 1285 return 0; 1286 1287 omap_str = strstr(boot_command_line, "console=ttyO"); 1288 if (!omap_str) 1289 /* user did not set ttyO based console, so we don't care */ 1290 return 0; 1291 1292 omap_str += 12; 1293 if ('0' <= *omap_str && *omap_str <= '9') 1294 idx = *omap_str - '0'; 1295 else 1296 return 0; 1297 1298 omap_str++; 1299 if (omap_str[0] == ',') { 1300 omap_str++; 1301 options = omap_str; 1302 } else { 1303 options = NULL; 1304 } 1305 1306 add_preferred_console("ttyS", idx, options); 1307 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1308 idx, idx); 1309 pr_err("This ensures that you still see kernel messages. Please\n"); 1310 pr_err("update your kernel commandline.\n"); 1311 return 0; 1312 } 1313 console_initcall(omap8250_console_fixup); 1314 #endif 1315 1316 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1317 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1318 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1319 omap8250_runtime_resume, NULL) 1320 .prepare = omap8250_prepare, 1321 .complete = omap8250_complete, 1322 }; 1323 1324 static const struct of_device_id omap8250_dt_ids[] = { 1325 { .compatible = "ti,omap2-uart" }, 1326 { .compatible = "ti,omap3-uart" }, 1327 { .compatible = "ti,omap4-uart" }, 1328 {}, 1329 }; 1330 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1331 1332 static struct platform_driver omap8250_platform_driver = { 1333 .driver = { 1334 .name = "omap8250", 1335 .pm = &omap8250_dev_pm_ops, 1336 .of_match_table = omap8250_dt_ids, 1337 }, 1338 .probe = omap8250_probe, 1339 .remove = omap8250_remove, 1340 }; 1341 module_platform_driver(omap8250_platform_driver); 1342 1343 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1344 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1345 MODULE_LICENSE("GPL v2"); 1346