1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 #include <linux/reboot.h> 31 #include <linux/pinctrl/consumer.h> 32 33 #include "8250.h" 34 35 #define DEFAULT_CLK_SPEED 48000000 36 #define OMAP_UART_REGSHIFT 2 37 38 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 39 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 40 #define OMAP_DMA_TX_KICK (1 << 2) 41 /* 42 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 43 * The same errata is applicable to AM335x and DRA7x processors too. 44 */ 45 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 46 #define UART_HAS_EFR2 BIT(4) 47 #define UART_HAS_RHR_IT_DIS BIT(5) 48 #define UART_RX_TIMEOUT_QUIRK BIT(6) 49 #define UART_HAS_NATIVE_RS485 BIT(7) 50 51 #define OMAP_UART_FCR_RX_TRIG 6 52 #define OMAP_UART_FCR_TX_TRIG 4 53 54 /* SCR register bitmasks */ 55 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 56 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 57 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 58 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 59 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 60 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 61 62 /* MVR register bitmasks */ 63 #define OMAP_UART_MVR_SCHEME_SHIFT 30 64 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 65 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 66 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 67 #define OMAP_UART_MVR_MAJ_MASK 0x700 68 #define OMAP_UART_MVR_MAJ_SHIFT 8 69 #define OMAP_UART_MVR_MIN_MASK 0x3f 70 71 /* SYSC register bitmasks */ 72 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 73 74 /* SYSS register bitmasks */ 75 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 76 77 #define UART_TI752_TLR_TX 0 78 #define UART_TI752_TLR_RX 4 79 80 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 81 #define TRIGGER_FCR_MASK(x) (x & 3) 82 83 /* Enable XON/XOFF flow control on output */ 84 #define OMAP_UART_SW_TX 0x08 85 /* Enable XON/XOFF flow control on input */ 86 #define OMAP_UART_SW_RX 0x02 87 88 #define OMAP_UART_WER_MOD_WKUP 0x7f 89 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 90 91 #define TX_TRIGGER 1 92 #define RX_TRIGGER 48 93 94 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 95 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 96 97 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 98 99 #define OMAP_UART_REV_46 0x0406 100 #define OMAP_UART_REV_52 0x0502 101 #define OMAP_UART_REV_63 0x0603 102 103 /* Resume register */ 104 #define UART_OMAP_RESUME 0x0B 105 106 /* Interrupt Enable Register 2 */ 107 #define UART_OMAP_IER2 0x1B 108 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 109 110 /* Mode Definition Register 3 */ 111 #define UART_OMAP_MDR3 0x20 112 #define UART_OMAP_MDR3_DIR_POL BIT(3) 113 #define UART_OMAP_MDR3_DIR_EN BIT(4) 114 115 /* Enhanced features register 2 */ 116 #define UART_OMAP_EFR2 0x23 117 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 118 119 /* RX FIFO occupancy indicator */ 120 #define UART_OMAP_RX_LVL 0x19 121 122 /* Timeout low and High */ 123 #define UART_OMAP_TO_L 0x26 124 #define UART_OMAP_TO_H 0x27 125 struct omap8250_priv { 126 void __iomem *membase; 127 int line; 128 u8 habit; 129 u8 mdr1; 130 u8 mdr3; 131 u8 efr; 132 u8 scr; 133 u8 wer; 134 u8 xon; 135 u8 xoff; 136 u8 delayed_restore; 137 u16 quot; 138 139 u8 tx_trigger; 140 u8 rx_trigger; 141 atomic_t active; 142 bool is_suspending; 143 int wakeirq; 144 u32 latency; 145 u32 calc_latency; 146 struct pm_qos_request pm_qos_request; 147 struct work_struct qos_work; 148 struct uart_8250_dma omap8250_dma; 149 spinlock_t rx_dma_lock; 150 bool rx_dma_broken; 151 bool throttled; 152 153 struct pinctrl *pinctrl; 154 struct pinctrl_state *pinctrl_wakeup; 155 }; 156 157 struct omap8250_dma_params { 158 u32 rx_size; 159 u8 rx_trigger; 160 u8 tx_trigger; 161 }; 162 163 struct omap8250_platdata { 164 struct omap8250_dma_params *dma_params; 165 u8 habit; 166 }; 167 168 #ifdef CONFIG_SERIAL_8250_DMA 169 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 170 #else 171 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 172 #endif 173 174 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 175 { 176 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 177 } 178 179 /* 180 * Called on runtime PM resume path from omap8250_restore_regs(), and 181 * omap8250_set_mctrl(). 182 */ 183 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 184 { 185 struct uart_8250_port *up = up_to_u8250p(port); 186 struct omap8250_priv *priv = port->private_data; 187 u8 lcr; 188 189 serial8250_do_set_mctrl(port, mctrl); 190 191 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 192 /* 193 * Turn off autoRTS if RTS is lowered and restore autoRTS 194 * setting if RTS is raised 195 */ 196 lcr = serial_in(up, UART_LCR); 197 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 198 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 199 priv->efr |= UART_EFR_RTS; 200 else 201 priv->efr &= ~UART_EFR_RTS; 202 serial_out(up, UART_EFR, priv->efr); 203 serial_out(up, UART_LCR, lcr); 204 } 205 } 206 207 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 208 { 209 int err; 210 211 err = pm_runtime_resume_and_get(port->dev); 212 if (err) 213 return; 214 215 __omap8250_set_mctrl(port, mctrl); 216 217 pm_runtime_mark_last_busy(port->dev); 218 pm_runtime_put_autosuspend(port->dev); 219 } 220 221 /* 222 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 223 * The access to uart register after MDR1 Access 224 * causes UART to corrupt data. 225 * 226 * Need a delay = 227 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 228 * give 10 times as much 229 */ 230 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 231 struct omap8250_priv *priv) 232 { 233 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 234 udelay(2); 235 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 236 UART_FCR_CLEAR_RCVR); 237 } 238 239 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 240 struct omap8250_priv *priv) 241 { 242 unsigned int uartclk = port->uartclk; 243 unsigned int div_13, div_16; 244 unsigned int abs_d13, abs_d16; 245 246 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 247 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 248 249 if (!div_13) 250 div_13 = 1; 251 if (!div_16) 252 div_16 = 1; 253 254 abs_d13 = abs(baud - uartclk / 13 / div_13); 255 abs_d16 = abs(baud - uartclk / 16 / div_16); 256 257 if (abs_d13 >= abs_d16) { 258 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 259 priv->quot = div_16; 260 } else { 261 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 262 priv->quot = div_13; 263 } 264 } 265 266 static void omap8250_update_scr(struct uart_8250_port *up, 267 struct omap8250_priv *priv) 268 { 269 u8 old_scr; 270 271 old_scr = serial_in(up, UART_OMAP_SCR); 272 if (old_scr == priv->scr) 273 return; 274 275 /* 276 * The manual recommends not to enable the DMA mode selector in the SCR 277 * (instead of the FCR) register _and_ selecting the DMA mode as one 278 * register write because this may lead to malfunction. 279 */ 280 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 281 serial_out(up, UART_OMAP_SCR, 282 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 283 serial_out(up, UART_OMAP_SCR, priv->scr); 284 } 285 286 static void omap8250_update_mdr1(struct uart_8250_port *up, 287 struct omap8250_priv *priv) 288 { 289 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 290 omap_8250_mdr1_errataset(up, priv); 291 else 292 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 293 } 294 295 static void omap8250_restore_regs(struct uart_8250_port *up) 296 { 297 struct uart_port *port = &up->port; 298 struct omap8250_priv *priv = port->private_data; 299 struct uart_8250_dma *dma = up->dma; 300 u8 mcr = serial8250_in_MCR(up); 301 302 /* Port locked to synchronize UART_IER access against the console. */ 303 lockdep_assert_held_once(&port->lock); 304 305 if (dma && dma->tx_running) { 306 /* 307 * TCSANOW requests the change to occur immediately however if 308 * we have a TX-DMA operation in progress then it has been 309 * observed that it might stall and never complete. Therefore we 310 * delay DMA completes to prevent this hang from happen. 311 */ 312 priv->delayed_restore = 1; 313 return; 314 } 315 316 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 317 serial_out(up, UART_EFR, UART_EFR_ECB); 318 319 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 320 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 321 serial_out(up, UART_FCR, up->fcr); 322 323 omap8250_update_scr(up, priv); 324 325 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 326 327 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 328 OMAP_UART_TCR_HALT(52)); 329 serial_out(up, UART_TI752_TLR, 330 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 331 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 332 333 serial_out(up, UART_LCR, 0); 334 335 /* drop TCR + TLR access, we setup XON/XOFF later */ 336 serial8250_out_MCR(up, mcr); 337 338 serial_out(up, UART_IER, up->ier); 339 340 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 341 serial_dl_write(up, priv->quot); 342 343 serial_out(up, UART_EFR, priv->efr); 344 345 /* Configure flow control */ 346 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 347 serial_out(up, UART_XON1, priv->xon); 348 serial_out(up, UART_XOFF1, priv->xoff); 349 350 serial_out(up, UART_LCR, up->lcr); 351 352 omap8250_update_mdr1(up, priv); 353 354 __omap8250_set_mctrl(port, port->mctrl); 355 356 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 357 358 if (port->rs485.flags & SER_RS485_ENABLED && 359 port->rs485_config == serial8250_em485_config) 360 serial8250_em485_stop_tx(up, true); 361 } 362 363 static void omap_8250_set_termios_atomic(struct uart_port *port, struct ktermios *termios, 364 const struct ktermios *old, unsigned int baud) 365 { 366 struct uart_8250_port *up = up_to_u8250p(port); 367 struct omap8250_priv *priv = port->private_data; 368 u8 cval; 369 370 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 371 372 if (termios->c_cflag & CSTOPB) 373 cval |= UART_LCR_STOP; 374 if (termios->c_cflag & PARENB) 375 cval |= UART_LCR_PARITY; 376 if (!(termios->c_cflag & PARODD)) 377 cval |= UART_LCR_EPAR; 378 if (termios->c_cflag & CMSPAR) 379 cval |= UART_LCR_SPAR; 380 381 omap_8250_get_divisor(port, baud, priv); 382 383 /* 384 * Ok, we're now changing the port state. Do it with 385 * interrupts disabled. 386 */ 387 guard(serial8250_rpm)(up); 388 guard(uart_port_lock_irq)(port); 389 390 /* 391 * Update the per-port timeout. 392 */ 393 uart_update_timeout(port, termios->c_cflag, baud); 394 395 /* 396 * Specify which conditions may be considered for error 397 * handling and the ignoring of characters. The actual 398 * ignoring of characters only occurs if the bit is set 399 * in @ignore_status_mask as well. 400 */ 401 port->read_status_mask = UART_LSR_OE | UART_LSR_DR; 402 if (termios->c_iflag & INPCK) 403 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 404 if (termios->c_iflag & (IGNBRK | PARMRK)) 405 port->read_status_mask |= UART_LSR_BI; 406 407 /* 408 * Characters to ignore 409 */ 410 port->ignore_status_mask = 0; 411 if (termios->c_iflag & IGNPAR) 412 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 413 if (termios->c_iflag & IGNBRK) { 414 port->ignore_status_mask |= UART_LSR_BI; 415 /* 416 * If we're ignoring parity and break indicators, 417 * ignore overruns too (for real raw support). 418 */ 419 if (termios->c_iflag & IGNPAR) 420 port->ignore_status_mask |= UART_LSR_OE; 421 } 422 423 /* 424 * ignore all characters if CREAD is not set 425 */ 426 if ((termios->c_cflag & CREAD) == 0) 427 port->ignore_status_mask |= UART_LSR_DR; 428 429 /* 430 * Modem status interrupts 431 */ 432 up->ier &= ~UART_IER_MSI; 433 if (UART_ENABLE_MS(port, termios->c_cflag)) 434 up->ier |= UART_IER_MSI; 435 436 up->lcr = cval; 437 /* Up to here it was mostly serial8250_do_set_termios() */ 438 439 /* 440 * We enable TRIG_GRANU for RX and TX and additionally we set 441 * SCR_TX_EMPTY bit. The result is the following: 442 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 443 * - less than RX_TRIGGER number of bytes will also cause an interrupt 444 * once the UART decides that there no new bytes arriving. 445 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 446 * empty - the trigger level is ignored here. 447 * 448 * Once DMA is enabled: 449 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 450 * bytes in the TX FIFO. On each assert the DMA engine will move 451 * TX_TRIGGER bytes into the FIFO. 452 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 453 * the FIFO and move RX_TRIGGER bytes. 454 * This is because threshold and trigger values are the same. 455 */ 456 up->fcr = UART_FCR_ENABLE_FIFO; 457 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 458 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 459 460 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 461 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 462 463 if (up->dma) 464 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 465 OMAP_UART_SCR_DMAMODE_CTL; 466 467 priv->xon = termios->c_cc[VSTART]; 468 priv->xoff = termios->c_cc[VSTOP]; 469 470 priv->efr = 0; 471 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 472 473 if (termios->c_cflag & CRTSCTS && port->flags & UPF_HARD_FLOW && 474 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 475 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 476 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 477 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 478 priv->efr |= UART_EFR_CTS; 479 } else if (port->flags & UPF_SOFT_FLOW) { 480 /* 481 * OMAP rx s/w flow control is borked; the transmitter remains 482 * stuck off even if rx flow control is subsequently disabled 483 */ 484 485 /* 486 * IXOFF Flag: 487 * Enable XON/XOFF flow control on output. 488 * Transmit XON1, XOFF1 489 */ 490 if (termios->c_iflag & IXOFF) { 491 port->status |= UPSTAT_AUTOXOFF; 492 priv->efr |= OMAP_UART_SW_TX; 493 } 494 } 495 omap8250_restore_regs(up); 496 } 497 498 /* 499 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 500 * some differences in how we want to handle flow control. 501 */ 502 static void omap_8250_set_termios(struct uart_port *port, 503 struct ktermios *termios, 504 const struct ktermios *old) 505 { 506 struct omap8250_priv *priv = port->private_data; 507 unsigned int baud; 508 509 /* 510 * Ask the core to calculate the divisor for us. 511 */ 512 baud = uart_get_baud_rate(port, termios, old, 513 port->uartclk / 16 / UART_DIV_MAX, 514 port->uartclk / 13); 515 516 omap_8250_set_termios_atomic(port, termios, old, baud); 517 518 /* calculate wakeup latency constraint */ 519 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 520 priv->latency = priv->calc_latency; 521 522 schedule_work(&priv->qos_work); 523 524 /* Don't rewrite B0 */ 525 if (tty_termios_baud_rate(termios)) 526 tty_termios_encode_baud_rate(termios, baud, baud); 527 } 528 529 /* same as 8250 except that we may have extra flow bits set in EFR */ 530 static void omap_8250_pm(struct uart_port *port, unsigned int state, 531 unsigned int oldstate) 532 { 533 struct uart_8250_port *up = up_to_u8250p(port); 534 u8 efr; 535 536 guard(serial8250_rpm)(up); 537 /* Synchronize UART_IER access against the console. */ 538 guard(uart_port_lock_irq)(port); 539 540 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 541 efr = serial_in(up, UART_EFR); 542 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 543 serial_out(up, UART_LCR, 0); 544 545 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 546 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 547 serial_out(up, UART_EFR, efr); 548 serial_out(up, UART_LCR, 0); 549 } 550 551 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 552 struct omap8250_priv *priv) 553 { 554 static const struct soc_device_attribute k3_soc_devices[] = { 555 { .family = "AM65X", }, 556 { .family = "J721E", .revision = "SR1.0" }, 557 { /* sentinel */ } 558 }; 559 u32 mvr, scheme; 560 u16 revision, major, minor; 561 562 mvr = uart_read(priv, UART_OMAP_MVER); 563 564 /* Check revision register scheme */ 565 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 566 567 switch (scheme) { 568 case 0: /* Legacy Scheme: OMAP2/3 */ 569 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 570 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 571 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 572 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 573 break; 574 case 1: 575 /* New Scheme: OMAP4+ */ 576 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 577 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 578 OMAP_UART_MVR_MAJ_SHIFT; 579 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 580 break; 581 default: 582 dev_warn(up->port.dev, 583 "Unknown revision, defaulting to highest\n"); 584 /* highest possible revision */ 585 major = 0xff; 586 minor = 0xff; 587 } 588 /* normalize revision for the driver */ 589 revision = UART_BUILD_REVISION(major, minor); 590 591 switch (revision) { 592 case OMAP_UART_REV_46: 593 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 594 break; 595 case OMAP_UART_REV_52: 596 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 597 OMAP_UART_WER_HAS_TX_WAKEUP; 598 break; 599 case OMAP_UART_REV_63: 600 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 601 OMAP_UART_WER_HAS_TX_WAKEUP; 602 break; 603 default: 604 break; 605 } 606 607 /* 608 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 609 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 610 * to enable errata workaround. 611 */ 612 if (soc_device_match(k3_soc_devices)) 613 priv->habit &= ~UART_HAS_RHR_IT_DIS; 614 } 615 616 static void omap8250_uart_qos_work(struct work_struct *work) 617 { 618 struct omap8250_priv *priv; 619 620 priv = container_of(work, struct omap8250_priv, qos_work); 621 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 622 } 623 624 #ifdef CONFIG_SERIAL_8250_DMA 625 static int omap_8250_dma_handle_irq(struct uart_port *port); 626 #endif 627 628 static irqreturn_t omap8250_irq(int irq, void *dev_id) 629 { 630 struct omap8250_priv *priv = dev_id; 631 struct uart_8250_port *up = serial8250_get_port(priv->line); 632 struct uart_port *port = &up->port; 633 unsigned int iir, lsr; 634 int ret; 635 636 pm_runtime_get_noresume(port->dev); 637 638 /* Shallow idle state wake-up to an IO interrupt? */ 639 if (atomic_add_unless(&priv->active, 1, 1)) { 640 priv->latency = priv->calc_latency; 641 schedule_work(&priv->qos_work); 642 } 643 644 #ifdef CONFIG_SERIAL_8250_DMA 645 if (up->dma) { 646 ret = omap_8250_dma_handle_irq(port); 647 pm_runtime_mark_last_busy(port->dev); 648 pm_runtime_put(port->dev); 649 return IRQ_RETVAL(ret); 650 } 651 #endif 652 653 lsr = serial_port_in(port, UART_LSR); 654 iir = serial_port_in(port, UART_IIR); 655 ret = serial8250_handle_irq(port, iir); 656 657 /* 658 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 659 * FIFO has been drained or erroneously. 660 * So apply solution of Errata i2310 as mentioned in 661 * https://www.ti.com/lit/pdf/sprz536 662 */ 663 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 664 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 665 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 666 unsigned char efr2, timeout_h, timeout_l; 667 668 efr2 = serial_in(up, UART_OMAP_EFR2); 669 timeout_h = serial_in(up, UART_OMAP_TO_H); 670 timeout_l = serial_in(up, UART_OMAP_TO_L); 671 serial_out(up, UART_OMAP_TO_H, 0xFF); 672 serial_out(up, UART_OMAP_TO_L, 0xFF); 673 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 674 serial_in(up, UART_IIR); 675 serial_out(up, UART_OMAP_EFR2, efr2); 676 serial_out(up, UART_OMAP_TO_H, timeout_h); 677 serial_out(up, UART_OMAP_TO_L, timeout_l); 678 } 679 680 /* Stop processing interrupts on input overrun */ 681 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 682 unsigned long delay; 683 684 /* Synchronize UART_IER access against the console. */ 685 uart_port_lock(port); 686 up->ier = serial_port_in(port, UART_IER); 687 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 688 port->ops->stop_rx(port); 689 } else { 690 /* Keep restarting the timer until 691 * the input overrun subsides. 692 */ 693 cancel_delayed_work(&up->overrun_backoff); 694 } 695 uart_port_unlock(port); 696 697 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 698 schedule_delayed_work(&up->overrun_backoff, delay); 699 } 700 701 pm_runtime_mark_last_busy(port->dev); 702 pm_runtime_put(port->dev); 703 704 return IRQ_RETVAL(ret); 705 } 706 707 static int omap_8250_startup(struct uart_port *port) 708 { 709 struct uart_8250_port *up = up_to_u8250p(port); 710 struct omap8250_priv *priv = port->private_data; 711 struct uart_8250_dma *dma = &priv->omap8250_dma; 712 int ret; 713 714 if (priv->wakeirq) { 715 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 716 if (ret) 717 return ret; 718 } 719 720 #ifdef CONFIG_PM 721 up->capabilities |= UART_CAP_RPM; 722 #endif 723 724 guard(serial8250_rpm)(up); 725 726 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 727 728 serial_out(up, UART_LCR, UART_LCR_WLEN8); 729 730 up->lsr_saved_flags = 0; 731 up->msr_saved_flags = 0; 732 733 /* Disable DMA for console UART */ 734 if (dma->fn && !uart_console(port)) { 735 up->dma = &priv->omap8250_dma; 736 ret = serial8250_request_dma(up); 737 if (ret) { 738 dev_warn_ratelimited(port->dev, 739 "failed to request DMA\n"); 740 up->dma = NULL; 741 } 742 } else { 743 up->dma = NULL; 744 } 745 746 /* Synchronize UART_IER access against the console. */ 747 scoped_guard(uart_port_lock_irq, port) { 748 up->ier = UART_IER_RLSI | UART_IER_RDI; 749 serial_out(up, UART_IER, up->ier); 750 } 751 752 /* Enable module level wake up */ 753 priv->wer = OMAP_UART_WER_MOD_WKUP; 754 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 755 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 756 serial_out(up, UART_OMAP_WER, priv->wer); 757 758 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 759 guard(uart_port_lock_irq)(port); 760 up->dma->rx_dma(up); 761 } 762 763 enable_irq(port->irq); 764 765 return 0; 766 } 767 768 static void omap_8250_shutdown(struct uart_port *port) 769 { 770 struct uart_8250_port *up = up_to_u8250p(port); 771 struct omap8250_priv *priv = port->private_data; 772 773 guard(serial8250_rpm)(up); 774 775 flush_work(&priv->qos_work); 776 if (up->dma) 777 omap_8250_rx_dma_flush(up); 778 779 serial_out(up, UART_OMAP_WER, 0); 780 if (priv->habit & UART_HAS_EFR2) 781 serial_out(up, UART_OMAP_EFR2, 0x0); 782 783 /* Synchronize UART_IER access against the console. */ 784 scoped_guard(uart_port_lock_irq, port) { 785 up->ier = 0; 786 serial_out(up, UART_IER, 0); 787 } 788 789 disable_irq_nosync(port->irq); 790 dev_pm_clear_wake_irq(port->dev); 791 792 serial8250_release_dma(up); 793 up->dma = NULL; 794 795 /* 796 * Disable break condition and FIFOs 797 */ 798 if (up->lcr & UART_LCR_SBC) 799 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 800 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 801 } 802 803 static void omap_8250_throttle(struct uart_port *port) 804 { 805 struct omap8250_priv *priv = port->private_data; 806 807 guard(serial8250_rpm)(up_to_u8250p(port)); 808 guard(uart_port_lock_irqsave)(port); 809 810 port->ops->stop_rx(port); 811 priv->throttled = true; 812 } 813 814 static void omap_8250_unthrottle(struct uart_port *port) 815 { 816 struct omap8250_priv *priv = port->private_data; 817 struct uart_8250_port *up = up_to_u8250p(port); 818 819 guard(serial8250_rpm)(up); 820 /* Synchronize UART_IER access against the console. */ 821 guard(uart_port_lock_irqsave)(port); 822 823 priv->throttled = false; 824 if (up->dma) 825 up->dma->rx_dma(up); 826 up->ier |= UART_IER_RLSI | UART_IER_RDI; 827 serial_out(up, UART_IER, up->ier); 828 } 829 830 static int omap8250_rs485_config(struct uart_port *port, 831 struct ktermios *termios, 832 struct serial_rs485 *rs485) 833 { 834 struct omap8250_priv *priv = port->private_data; 835 struct uart_8250_port *up = up_to_u8250p(port); 836 u32 fixed_delay_rts_before_send = 0; 837 u32 fixed_delay_rts_after_send = 0; 838 unsigned int baud; 839 840 /* 841 * There is a fixed delay of 3 bit clock cycles after the TX shift 842 * register is going empty to allow time for the stop bit to transition 843 * through the transceiver before direction is changed to receive. 844 * 845 * Additionally there appears to be a 1 bit clock delay between writing 846 * to the THR register and transmission of the start bit, per page 8783 847 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 848 */ 849 if (priv->quot) { 850 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 851 baud = port->uartclk / (16 * priv->quot); 852 else 853 baud = port->uartclk / (13 * priv->quot); 854 855 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 856 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 857 } 858 859 /* 860 * Fall back to RS485 software emulation if the UART is missing 861 * hardware support, if the device tree specifies an mctrl_gpio 862 * (indicates that RTS is unavailable due to a pinmux conflict) 863 * or if the requested delays exceed the fixed hardware delays. 864 */ 865 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 866 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 867 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 868 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 869 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 870 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 871 872 port->rs485_config = serial8250_em485_config; 873 return serial8250_em485_config(port, termios, rs485); 874 } 875 876 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 877 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 878 879 if (rs485->flags & SER_RS485_ENABLED) 880 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 881 else 882 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 883 884 /* 885 * Retain same polarity semantics as RS485 software emulation, 886 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 887 */ 888 if (rs485->flags & SER_RS485_RTS_ON_SEND) 889 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 890 else 891 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 892 893 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 894 895 return 0; 896 } 897 898 #ifdef CONFIG_SERIAL_8250_DMA 899 static int omap_8250_rx_dma(struct uart_8250_port *p); 900 901 /* Must be called while priv->rx_dma_lock is held */ 902 static void __dma_rx_do_complete(struct uart_8250_port *p) 903 { 904 struct uart_8250_dma *dma = p->dma; 905 struct tty_port *tty_port = &p->port.state->port; 906 struct omap8250_priv *priv = p->port.private_data; 907 struct dma_chan *rxchan = dma->rxchan; 908 dma_cookie_t cookie; 909 struct dma_tx_state state; 910 int count; 911 int ret; 912 u32 reg; 913 914 if (!dma->rx_running) 915 goto out; 916 917 cookie = dma->rx_cookie; 918 919 /* Re-enable RX FIFO interrupt now that transfer is complete */ 920 if (priv->habit & UART_HAS_RHR_IT_DIS) { 921 reg = serial_in(p, UART_OMAP_IER2); 922 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 923 serial_out(p, UART_OMAP_IER2, reg); 924 } 925 926 dmaengine_tx_status(rxchan, cookie, &state); 927 928 count = dma->rx_size - state.residue + state.in_flight_bytes; 929 if (count < dma->rx_size) { 930 dmaengine_terminate_async(rxchan); 931 932 /* 933 * Poll for teardown to complete which guarantees in 934 * flight data is drained. 935 */ 936 if (state.in_flight_bytes) { 937 int poll_count = 25; 938 939 while (dmaengine_tx_status(rxchan, cookie, NULL) && 940 poll_count--) 941 cpu_relax(); 942 943 if (poll_count == -1) 944 dev_err(p->port.dev, "teardown incomplete\n"); 945 } 946 } 947 948 dma->rx_running = 0; 949 if (!count) 950 goto out; 951 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 952 953 p->port.icount.rx += ret; 954 p->port.icount.buf_overrun += count - ret; 955 out: 956 957 tty_flip_buffer_push(tty_port); 958 } 959 960 static void __dma_rx_complete(void *param) 961 { 962 struct uart_8250_port *p = param; 963 struct omap8250_priv *priv = p->port.private_data; 964 struct uart_8250_dma *dma = p->dma; 965 struct dma_tx_state state; 966 967 /* Synchronize UART_IER access against the console. */ 968 guard(uart_port_lock_irqsave)(&p->port); 969 970 /* 971 * If the tx status is not DMA_COMPLETE, then this is a delayed 972 * completion callback. A previous RX timeout flush would have 973 * already pushed the data, so exit. 974 */ 975 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != DMA_COMPLETE) 976 return; 977 978 __dma_rx_do_complete(p); 979 if (priv->throttled) 980 return; 981 982 p->ier |= UART_IER_RLSI | UART_IER_RDI; 983 serial_out(p, UART_IER, p->ier); 984 if (!(priv->habit & UART_HAS_EFR2)) 985 omap_8250_rx_dma(p); 986 } 987 988 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 989 { 990 struct omap8250_priv *priv = p->port.private_data; 991 struct uart_8250_dma *dma = p->dma; 992 struct dma_tx_state state; 993 unsigned long flags; 994 int ret; 995 996 spin_lock_irqsave(&priv->rx_dma_lock, flags); 997 998 if (!dma->rx_running) { 999 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1000 return; 1001 } 1002 1003 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1004 if (ret == DMA_IN_PROGRESS) { 1005 ret = dmaengine_pause(dma->rxchan); 1006 if (WARN_ON_ONCE(ret)) 1007 priv->rx_dma_broken = true; 1008 } 1009 __dma_rx_do_complete(p); 1010 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1011 } 1012 1013 static int omap_8250_rx_dma(struct uart_8250_port *p) 1014 { 1015 struct omap8250_priv *priv = p->port.private_data; 1016 struct uart_8250_dma *dma = p->dma; 1017 int err = 0; 1018 struct dma_async_tx_descriptor *desc; 1019 unsigned long flags; 1020 u32 reg; 1021 1022 /* Port locked to synchronize UART_IER access against the console. */ 1023 lockdep_assert_held_once(&p->port.lock); 1024 1025 if (priv->rx_dma_broken) 1026 return -EINVAL; 1027 1028 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1029 1030 if (dma->rx_running) { 1031 enum dma_status state; 1032 1033 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1034 if (state == DMA_COMPLETE) { 1035 /* 1036 * Disable RX interrupts to allow RX DMA completion 1037 * callback to run. 1038 */ 1039 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1040 serial_out(p, UART_IER, p->ier); 1041 } 1042 goto out; 1043 } 1044 1045 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1046 dma->rx_size, DMA_DEV_TO_MEM, 1047 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1048 if (!desc) { 1049 err = -EBUSY; 1050 goto out; 1051 } 1052 1053 dma->rx_running = 1; 1054 desc->callback = __dma_rx_complete; 1055 desc->callback_param = p; 1056 1057 dma->rx_cookie = dmaengine_submit(desc); 1058 1059 /* 1060 * Disable RX FIFO interrupt while RX DMA is enabled, else 1061 * spurious interrupt may be raised when data is in the RX FIFO 1062 * but is yet to be drained by DMA. 1063 */ 1064 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1065 reg = serial_in(p, UART_OMAP_IER2); 1066 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1067 serial_out(p, UART_OMAP_IER2, reg); 1068 } 1069 1070 dma_async_issue_pending(dma->rxchan); 1071 out: 1072 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1073 return err; 1074 } 1075 1076 static int omap_8250_tx_dma(struct uart_8250_port *p); 1077 1078 static void omap_8250_dma_tx_complete(void *param) 1079 { 1080 struct uart_8250_port *p = param; 1081 struct uart_8250_dma *dma = p->dma; 1082 struct tty_port *tport = &p->port.state->port; 1083 bool en_thri = false; 1084 struct omap8250_priv *priv = p->port.private_data; 1085 1086 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1087 UART_XMIT_SIZE, DMA_TO_DEVICE); 1088 1089 guard(uart_port_lock_irqsave)(&p->port); 1090 1091 dma->tx_running = 0; 1092 1093 uart_xmit_advance(&p->port, dma->tx_size); 1094 1095 if (priv->delayed_restore) { 1096 priv->delayed_restore = 0; 1097 omap8250_restore_regs(p); 1098 } 1099 1100 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1101 uart_write_wakeup(&p->port); 1102 1103 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1104 int ret; 1105 1106 ret = omap_8250_tx_dma(p); 1107 if (ret) 1108 en_thri = true; 1109 } else if (p->capabilities & UART_CAP_RPM) { 1110 en_thri = true; 1111 } 1112 1113 if (en_thri) { 1114 dma->tx_err = 1; 1115 serial8250_set_THRI(p); 1116 } 1117 } 1118 1119 static int omap_8250_tx_dma(struct uart_8250_port *p) 1120 { 1121 struct uart_8250_dma *dma = p->dma; 1122 struct omap8250_priv *priv = p->port.private_data; 1123 struct tty_port *tport = &p->port.state->port; 1124 struct dma_async_tx_descriptor *desc; 1125 struct scatterlist sg; 1126 int skip_byte = -1; 1127 int ret; 1128 1129 if (dma->tx_running) 1130 return 0; 1131 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1132 1133 /* 1134 * Even if no data, we need to return an error for the two cases 1135 * below so serial8250_tx_chars() is invoked and properly clears 1136 * THRI and/or runtime suspend. 1137 */ 1138 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1139 ret = -EBUSY; 1140 goto err; 1141 } 1142 serial8250_clear_THRI(p); 1143 return 0; 1144 } 1145 1146 if (priv->habit & OMAP_DMA_TX_KICK) { 1147 unsigned char c; 1148 u8 tx_lvl; 1149 1150 /* 1151 * We need to put the first byte into the FIFO in order to start 1152 * the DMA transfer. For transfers smaller than four bytes we 1153 * don't bother doing DMA at all. It seem not matter if there 1154 * are still bytes in the FIFO from the last transfer (in case 1155 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1156 * leaving the FIFO seem not to trigger the DMA transfer. It is 1157 * really the byte that we put into the FIFO. 1158 * If the FIFO is already full then we most likely got here from 1159 * omap_8250_dma_tx_complete(). And this means the DMA engine 1160 * just completed its work. We don't have to wait the complete 1161 * 86us at 115200,8n1 but around 60us (not to mention lower 1162 * baudrates). So in that case we take the interrupt and try 1163 * again with an empty FIFO. 1164 */ 1165 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1166 if (tx_lvl == p->tx_loadsz) { 1167 ret = -EBUSY; 1168 goto err; 1169 } 1170 if (kfifo_len(&tport->xmit_fifo) < 4) { 1171 ret = -EINVAL; 1172 goto err; 1173 } 1174 if (!uart_fifo_out(&p->port, &c, 1)) { 1175 ret = -EINVAL; 1176 goto err; 1177 } 1178 skip_byte = c; 1179 } 1180 1181 sg_init_table(&sg, 1); 1182 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, UART_XMIT_SIZE, dma->tx_addr); 1183 if (ret != 1) { 1184 ret = -EINVAL; 1185 goto err; 1186 } 1187 1188 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1189 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1190 if (!desc) { 1191 ret = -EBUSY; 1192 goto err; 1193 } 1194 1195 dma->tx_size = sg_dma_len(&sg); 1196 dma->tx_running = 1; 1197 1198 desc->callback = omap_8250_dma_tx_complete; 1199 desc->callback_param = p; 1200 1201 dma->tx_cookie = dmaengine_submit(desc); 1202 1203 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1204 UART_XMIT_SIZE, DMA_TO_DEVICE); 1205 1206 dma_async_issue_pending(dma->txchan); 1207 if (dma->tx_err) 1208 dma->tx_err = 0; 1209 1210 serial8250_clear_THRI(p); 1211 ret = 0; 1212 goto out_skip; 1213 err: 1214 dma->tx_err = 1; 1215 out_skip: 1216 if (skip_byte >= 0) 1217 serial_out(p, UART_TX, skip_byte); 1218 return ret; 1219 } 1220 1221 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1222 { 1223 switch (iir & 0x3f) { 1224 case UART_IIR_RLSI: 1225 case UART_IIR_RX_TIMEOUT: 1226 case UART_IIR_RDI: 1227 omap_8250_rx_dma_flush(up); 1228 return true; 1229 } 1230 return omap_8250_rx_dma(up); 1231 } 1232 1233 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1234 { 1235 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1236 (iir & UART_IIR_RDI)) { 1237 if (handle_rx_dma(up, iir)) { 1238 status = serial8250_rx_chars(up, status); 1239 omap_8250_rx_dma(up); 1240 } 1241 } 1242 1243 return status; 1244 } 1245 1246 static void am654_8250_handle_uart_errors(struct uart_8250_port *up, u8 iir, u16 status) 1247 { 1248 if (status & UART_LSR_OE) { 1249 serial8250_clear_and_reinit_fifos(up); 1250 serial_in(up, UART_LSR); 1251 serial_in(up, UART_OMAP_RESUME); 1252 } else { 1253 if (status & (UART_LSR_FE | UART_LSR_PE | UART_LSR_BI)) 1254 serial_in(up, UART_RX); 1255 if (iir & UART_IIR_XOFF) 1256 serial_in(up, UART_IIR); 1257 } 1258 } 1259 1260 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1261 u16 status) 1262 { 1263 /* Port locked to synchronize UART_IER access against the console. */ 1264 lockdep_assert_held_once(&up->port.lock); 1265 1266 /* 1267 * Queue a new transfer if FIFO has data. 1268 */ 1269 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1270 (up->ier & UART_IER_RDI) && !(status & UART_LSR_OE)) { 1271 am654_8250_handle_uart_errors(up, iir, status); 1272 omap_8250_rx_dma(up); 1273 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1274 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1275 /* 1276 * Disable RX timeout, read IIR to clear 1277 * current timeout condition, clear EFR2 to 1278 * periodic timeouts, re-enable interrupts. 1279 */ 1280 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1281 serial_out(up, UART_IER, up->ier); 1282 omap_8250_rx_dma_flush(up); 1283 serial_in(up, UART_IIR); 1284 serial_out(up, UART_OMAP_EFR2, 0x0); 1285 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1286 serial_out(up, UART_IER, up->ier); 1287 } else { 1288 am654_8250_handle_uart_errors(up, iir, status); 1289 } 1290 } 1291 1292 /* 1293 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1294 * hook for RX/TX and need different logic for them in the ISR. Therefore we 1295 * use the default routine in the non-DMA case and this one for with DMA. 1296 */ 1297 static int omap_8250_dma_handle_irq(struct uart_port *port) 1298 { 1299 struct uart_8250_port *up = up_to_u8250p(port); 1300 struct omap8250_priv *priv = port->private_data; 1301 u16 status; 1302 u8 iir; 1303 1304 iir = serial_port_in(port, UART_IIR); 1305 if (iir & UART_IIR_NO_INT) { 1306 return IRQ_HANDLED; 1307 } 1308 1309 uart_port_lock(port); 1310 1311 status = serial_port_in(port, UART_LSR); 1312 1313 if ((iir & 0x3f) != UART_IIR_THRI) { 1314 if (priv->habit & UART_HAS_EFR2) 1315 am654_8250_handle_rx_dma(up, iir, status); 1316 else 1317 status = omap_8250_handle_rx_dma(up, iir, status); 1318 } 1319 1320 serial8250_modem_status(up); 1321 if (status & UART_LSR_THRE && up->dma->tx_err) { 1322 if (uart_tx_stopped(port) || 1323 kfifo_is_empty(&port->state->port.xmit_fifo)) { 1324 up->dma->tx_err = 0; 1325 serial8250_tx_chars(up); 1326 } else { 1327 /* 1328 * try again due to an earlier failure which 1329 * might have been resolved by now. 1330 */ 1331 if (omap_8250_tx_dma(up)) 1332 serial8250_tx_chars(up); 1333 } 1334 } 1335 1336 uart_unlock_and_check_sysrq(port); 1337 1338 return 1; 1339 } 1340 1341 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1342 { 1343 return false; 1344 } 1345 1346 #else 1347 1348 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1349 { 1350 return -EINVAL; 1351 } 1352 #endif 1353 1354 static int omap8250_no_handle_irq(struct uart_port *port) 1355 { 1356 /* IRQ has not been requested but handling irq? */ 1357 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1358 return 0; 1359 } 1360 1361 static int omap8250_select_wakeup_pinctrl(struct device *dev, 1362 struct omap8250_priv *priv) 1363 { 1364 if (IS_ERR_OR_NULL(priv->pinctrl_wakeup)) 1365 return 0; 1366 1367 if (!device_may_wakeup(dev)) 1368 return 0; 1369 1370 device_set_out_band_wakeup(dev); 1371 1372 return pinctrl_select_state(priv->pinctrl, priv->pinctrl_wakeup); 1373 } 1374 1375 static struct omap8250_dma_params am654_dma = { 1376 .rx_size = SZ_2K, 1377 .rx_trigger = 1, 1378 .tx_trigger = TX_TRIGGER, 1379 }; 1380 1381 static struct omap8250_dma_params am33xx_dma = { 1382 .rx_size = RX_TRIGGER, 1383 .rx_trigger = RX_TRIGGER, 1384 .tx_trigger = TX_TRIGGER, 1385 }; 1386 1387 static struct omap8250_platdata am654_platdata = { 1388 .dma_params = &am654_dma, 1389 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1390 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1391 }; 1392 1393 static struct omap8250_platdata am33xx_platdata = { 1394 .dma_params = &am33xx_dma, 1395 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1396 }; 1397 1398 static struct omap8250_platdata omap4_platdata = { 1399 .dma_params = &am33xx_dma, 1400 .habit = UART_ERRATA_CLOCK_DISABLE, 1401 }; 1402 1403 static const struct of_device_id omap8250_dt_ids[] = { 1404 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1405 { .compatible = "ti,omap2-uart" }, 1406 { .compatible = "ti,omap3-uart" }, 1407 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1408 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1409 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1410 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1411 {}, 1412 }; 1413 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1414 1415 static int omap8250_probe(struct platform_device *pdev) 1416 { 1417 struct device_node *np = pdev->dev.of_node; 1418 struct omap8250_priv *priv; 1419 const struct omap8250_platdata *pdata; 1420 struct uart_8250_port up; 1421 struct resource *regs; 1422 void __iomem *membase; 1423 int ret; 1424 1425 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1426 if (!regs) { 1427 dev_err(&pdev->dev, "missing registers\n"); 1428 return -EINVAL; 1429 } 1430 1431 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1432 if (!priv) 1433 return -ENOMEM; 1434 1435 membase = devm_ioremap(&pdev->dev, regs->start, 1436 resource_size(regs)); 1437 if (!membase) 1438 return -ENODEV; 1439 1440 memset(&up, 0, sizeof(up)); 1441 up.port.dev = &pdev->dev; 1442 up.port.mapbase = regs->start; 1443 up.port.membase = membase; 1444 /* 1445 * It claims to be 16C750 compatible however it is a little different. 1446 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1447 * have) is enabled via EFR instead of MCR. The type is set here 8250 1448 * just to get things going. UNKNOWN does not work for a few reasons and 1449 * we don't need our own type since we don't use 8250's set_termios() 1450 * or pm callback. 1451 */ 1452 up.port.type = PORT_8250; 1453 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1454 up.port.private_data = priv; 1455 1456 up.tx_loadsz = 64; 1457 up.capabilities = UART_CAP_FIFO; 1458 #ifdef CONFIG_PM 1459 /* 1460 * Runtime PM is mostly transparent. However to do it right we need to a 1461 * TX empty interrupt before we can put the device to auto idle. So if 1462 * PM is not enabled we don't add that flag and can spare that one extra 1463 * interrupt in the TX path. 1464 */ 1465 up.capabilities |= UART_CAP_RPM; 1466 #endif 1467 up.port.set_termios = omap_8250_set_termios; 1468 up.port.set_mctrl = omap8250_set_mctrl; 1469 up.port.pm = omap_8250_pm; 1470 up.port.startup = omap_8250_startup; 1471 up.port.shutdown = omap_8250_shutdown; 1472 up.port.throttle = omap_8250_throttle; 1473 up.port.unthrottle = omap_8250_unthrottle; 1474 up.port.rs485_config = omap8250_rs485_config; 1475 /* same rs485_supported for software emulation and native RS485 */ 1476 up.port.rs485_supported = serial8250_em485_supported; 1477 up.rs485_start_tx = serial8250_em485_start_tx; 1478 up.rs485_stop_tx = serial8250_em485_stop_tx; 1479 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1480 1481 ret = uart_read_port_properties(&up.port); 1482 if (ret) 1483 return ret; 1484 1485 up.port.regshift = OMAP_UART_REGSHIFT; 1486 up.port.fifosize = 64; 1487 1488 if (!up.port.uartclk) { 1489 struct clk *clk; 1490 1491 clk = devm_clk_get(&pdev->dev, NULL); 1492 if (IS_ERR(clk)) { 1493 if (PTR_ERR(clk) == -EPROBE_DEFER) 1494 return -EPROBE_DEFER; 1495 } else { 1496 up.port.uartclk = clk_get_rate(clk); 1497 } 1498 } 1499 1500 if (of_property_read_u32(np, "overrun-throttle-ms", 1501 &up.overrun_backoff_time_ms) != 0) 1502 up.overrun_backoff_time_ms = 0; 1503 1504 pdata = of_device_get_match_data(&pdev->dev); 1505 if (pdata) 1506 priv->habit |= pdata->habit; 1507 1508 if (!up.port.uartclk) { 1509 up.port.uartclk = DEFAULT_CLK_SPEED; 1510 dev_warn(&pdev->dev, 1511 "No clock speed specified: using default: %d\n", 1512 DEFAULT_CLK_SPEED); 1513 } 1514 1515 priv->membase = membase; 1516 priv->line = -ENODEV; 1517 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1518 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1519 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1520 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1521 1522 spin_lock_init(&priv->rx_dma_lock); 1523 1524 platform_set_drvdata(pdev, priv); 1525 1526 device_set_wakeup_capable(&pdev->dev, true); 1527 if (of_property_read_bool(np, "wakeup-source")) 1528 device_set_wakeup_enable(&pdev->dev, true); 1529 1530 pm_runtime_enable(&pdev->dev); 1531 pm_runtime_use_autosuspend(&pdev->dev); 1532 1533 /* 1534 * Disable runtime PM until autosuspend delay unless specifically 1535 * enabled by the user via sysfs. This is the historic way to 1536 * prevent an unsafe default policy with lossy characters on wake-up. 1537 * For serdev devices this is not needed, the policy can be managed by 1538 * the serdev driver. 1539 */ 1540 if (!of_get_available_child_count(pdev->dev.of_node)) 1541 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1542 1543 pm_runtime_get_sync(&pdev->dev); 1544 1545 omap_serial_fill_features_erratas(&up, priv); 1546 up.port.handle_irq = omap8250_no_handle_irq; 1547 priv->rx_trigger = RX_TRIGGER; 1548 priv->tx_trigger = TX_TRIGGER; 1549 #ifdef CONFIG_SERIAL_8250_DMA 1550 /* 1551 * Oh DMA support. If there are no DMA properties in the DT then 1552 * we will fall back to a generic DMA channel which does not 1553 * really work here. To ensure that we do not get a generic DMA 1554 * channel assigned, we have the the_no_dma_filter_fn() here. 1555 * To avoid "failed to request DMA" messages we check for DMA 1556 * properties in DT. 1557 */ 1558 ret = of_property_count_strings(np, "dma-names"); 1559 if (ret == 2) { 1560 struct omap8250_dma_params *dma_params = NULL; 1561 struct uart_8250_dma *dma = &priv->omap8250_dma; 1562 1563 dma->fn = the_no_dma_filter_fn; 1564 dma->tx_dma = omap_8250_tx_dma; 1565 dma->rx_dma = omap_8250_rx_dma; 1566 if (pdata) 1567 dma_params = pdata->dma_params; 1568 1569 if (dma_params) { 1570 dma->rx_size = dma_params->rx_size; 1571 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1572 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1573 priv->rx_trigger = dma_params->rx_trigger; 1574 priv->tx_trigger = dma_params->tx_trigger; 1575 } else { 1576 dma->rx_size = RX_TRIGGER; 1577 dma->rxconf.src_maxburst = RX_TRIGGER; 1578 dma->txconf.dst_maxburst = TX_TRIGGER; 1579 } 1580 } 1581 #endif 1582 1583 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1584 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1585 dev_name(&pdev->dev), priv); 1586 if (ret < 0) 1587 goto err; 1588 1589 priv->wakeirq = irq_of_parse_and_map(np, 1); 1590 1591 ret = serial8250_register_8250_port(&up); 1592 if (ret < 0) { 1593 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1594 goto err; 1595 } 1596 priv->line = ret; 1597 pm_runtime_mark_last_busy(&pdev->dev); 1598 pm_runtime_put_autosuspend(&pdev->dev); 1599 1600 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1601 if (!IS_ERR_OR_NULL(priv->pinctrl)) 1602 priv->pinctrl_wakeup = pinctrl_lookup_state(priv->pinctrl, "wakeup"); 1603 1604 return 0; 1605 err: 1606 pm_runtime_dont_use_autosuspend(&pdev->dev); 1607 pm_runtime_put_sync(&pdev->dev); 1608 flush_work(&priv->qos_work); 1609 pm_runtime_disable(&pdev->dev); 1610 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1611 return ret; 1612 } 1613 1614 static void omap8250_remove(struct platform_device *pdev) 1615 { 1616 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1617 struct uart_8250_port *up; 1618 int err; 1619 1620 err = pm_runtime_resume_and_get(&pdev->dev); 1621 if (err) 1622 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1623 1624 up = serial8250_get_port(priv->line); 1625 omap_8250_shutdown(&up->port); 1626 serial8250_unregister_port(priv->line); 1627 priv->line = -ENODEV; 1628 pm_runtime_dont_use_autosuspend(&pdev->dev); 1629 pm_runtime_put_sync(&pdev->dev); 1630 flush_work(&priv->qos_work); 1631 pm_runtime_disable(&pdev->dev); 1632 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1633 device_set_wakeup_capable(&pdev->dev, false); 1634 } 1635 1636 static int omap8250_prepare(struct device *dev) 1637 { 1638 struct omap8250_priv *priv = dev_get_drvdata(dev); 1639 1640 if (!priv) 1641 return 0; 1642 priv->is_suspending = true; 1643 return 0; 1644 } 1645 1646 static void omap8250_complete(struct device *dev) 1647 { 1648 struct omap8250_priv *priv = dev_get_drvdata(dev); 1649 1650 if (!priv) 1651 return; 1652 priv->is_suspending = false; 1653 } 1654 1655 static int omap8250_suspend(struct device *dev) 1656 { 1657 struct omap8250_priv *priv = dev_get_drvdata(dev); 1658 struct uart_8250_port *up = serial8250_get_port(priv->line); 1659 int err = 0; 1660 1661 err = omap8250_select_wakeup_pinctrl(dev, priv); 1662 if (err) { 1663 dev_err(dev, "Failed to select wakeup pinctrl, aborting suspend %pe\n", 1664 ERR_PTR(err)); 1665 return err; 1666 } 1667 1668 serial8250_suspend_port(priv->line); 1669 1670 err = pm_runtime_resume_and_get(dev); 1671 if (err) 1672 return err; 1673 if (!device_may_wakeup(dev)) 1674 priv->wer = 0; 1675 serial_out(up, UART_OMAP_WER, priv->wer); 1676 if (uart_console(&up->port) && console_suspend_enabled) 1677 err = pm_runtime_force_suspend(dev); 1678 flush_work(&priv->qos_work); 1679 1680 return err; 1681 } 1682 1683 static int omap8250_resume(struct device *dev) 1684 { 1685 struct omap8250_priv *priv = dev_get_drvdata(dev); 1686 struct uart_8250_port *up = serial8250_get_port(priv->line); 1687 int err; 1688 1689 err = pinctrl_select_default_state(dev); 1690 if (err) { 1691 dev_err(dev, "Failed to select default pinctrl state on resume: %pe\n", 1692 ERR_PTR(err)); 1693 return err; 1694 } 1695 1696 if (uart_console(&up->port) && console_suspend_enabled) { 1697 err = pm_runtime_force_resume(dev); 1698 if (err) 1699 return err; 1700 } 1701 1702 serial8250_resume_port(priv->line); 1703 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1704 pm_runtime_mark_last_busy(dev); 1705 pm_runtime_put_autosuspend(dev); 1706 1707 return 0; 1708 } 1709 1710 static int omap8250_lost_context(struct uart_8250_port *up) 1711 { 1712 u32 val; 1713 1714 val = serial_in(up, UART_OMAP_SCR); 1715 /* 1716 * If we lose context, then SCR is set to its reset value of zero. 1717 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1718 * among other bits, to never set the register back to zero again. 1719 */ 1720 if (!val) 1721 return 1; 1722 return 0; 1723 } 1724 1725 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1726 { 1727 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1728 } 1729 1730 /* TODO: in future, this should happen via API in drivers/reset/ */ 1731 static int omap8250_soft_reset(struct device *dev) 1732 { 1733 struct omap8250_priv *priv = dev_get_drvdata(dev); 1734 int timeout = 100; 1735 int sysc; 1736 int syss; 1737 1738 /* 1739 * At least on omap4, unused uarts may not idle after reset without 1740 * a basic scr dma configuration even with no dma in use. The 1741 * module clkctrl status bits will be 1 instead of 3 blocking idle 1742 * for the whole clockdomain. The softreset below will clear scr, 1743 * and we restore it on resume so this is safe to do on all SoCs 1744 * needing omap8250_soft_reset() quirk. Do it in two writes as 1745 * recommended in the comment for omap8250_update_scr(). 1746 */ 1747 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1748 uart_write(priv, UART_OMAP_SCR, 1749 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1750 1751 sysc = uart_read(priv, UART_OMAP_SYSC); 1752 1753 /* softreset the UART */ 1754 sysc |= OMAP_UART_SYSC_SOFTRESET; 1755 uart_write(priv, UART_OMAP_SYSC, sysc); 1756 1757 /* By experiments, 1us enough for reset complete on AM335x */ 1758 do { 1759 udelay(1); 1760 syss = uart_read(priv, UART_OMAP_SYSS); 1761 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1762 1763 if (!timeout) { 1764 dev_err(dev, "timed out waiting for reset done\n"); 1765 return -ETIMEDOUT; 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int omap8250_runtime_suspend(struct device *dev) 1772 { 1773 struct omap8250_priv *priv = dev_get_drvdata(dev); 1774 struct uart_8250_port *up = NULL; 1775 1776 if (priv->line >= 0) 1777 up = serial8250_get_port(priv->line); 1778 1779 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1780 int ret; 1781 1782 ret = omap8250_soft_reset(dev); 1783 if (ret) 1784 return ret; 1785 1786 if (up) { 1787 /* Restore to UART mode after reset (for wakeup) */ 1788 omap8250_update_mdr1(up, priv); 1789 /* Restore wakeup enable register */ 1790 serial_out(up, UART_OMAP_WER, priv->wer); 1791 } 1792 } 1793 1794 if (up && up->dma && up->dma->rxchan) 1795 omap_8250_rx_dma_flush(up); 1796 1797 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1798 schedule_work(&priv->qos_work); 1799 atomic_set(&priv->active, 0); 1800 1801 return 0; 1802 } 1803 1804 static int omap8250_runtime_resume(struct device *dev) 1805 { 1806 struct omap8250_priv *priv = dev_get_drvdata(dev); 1807 struct uart_8250_port *up = NULL; 1808 1809 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1810 if (atomic_read(&priv->active)) 1811 return 0; 1812 1813 if (priv->line >= 0) 1814 up = serial8250_get_port(priv->line); 1815 1816 if (up && omap8250_lost_context(up)) { 1817 guard(uart_port_lock_irq)(&up->port); 1818 omap8250_restore_regs(up); 1819 } 1820 1821 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1822 guard(uart_port_lock_irq)(&up->port); 1823 omap_8250_rx_dma(up); 1824 } 1825 1826 atomic_set(&priv->active, 1); 1827 priv->latency = priv->calc_latency; 1828 schedule_work(&priv->qos_work); 1829 1830 return 0; 1831 } 1832 1833 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1834 static int __init omap8250_console_fixup(void) 1835 { 1836 char *omap_str; 1837 char *options; 1838 u8 idx; 1839 1840 if (strstr(boot_command_line, "console=ttyS")) 1841 /* user set a ttyS based name for the console */ 1842 return 0; 1843 1844 omap_str = strstr(boot_command_line, "console=ttyO"); 1845 if (!omap_str) 1846 /* user did not set ttyO based console, so we don't care */ 1847 return 0; 1848 1849 omap_str += 12; 1850 if ('0' <= *omap_str && *omap_str <= '9') 1851 idx = *omap_str - '0'; 1852 else 1853 return 0; 1854 1855 omap_str++; 1856 if (omap_str[0] == ',') { 1857 omap_str++; 1858 options = omap_str; 1859 } else { 1860 options = NULL; 1861 } 1862 1863 add_preferred_console("ttyS", idx, options); 1864 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1865 idx, idx); 1866 pr_err("This ensures that you still see kernel messages. Please\n"); 1867 pr_err("update your kernel commandline.\n"); 1868 return 0; 1869 } 1870 console_initcall(omap8250_console_fixup); 1871 #endif 1872 1873 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1874 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1875 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1876 omap8250_runtime_resume, NULL) 1877 .prepare = pm_sleep_ptr(omap8250_prepare), 1878 .complete = pm_sleep_ptr(omap8250_complete), 1879 }; 1880 1881 static struct platform_driver omap8250_platform_driver = { 1882 .driver = { 1883 .name = "omap8250", 1884 .pm = pm_ptr(&omap8250_dev_pm_ops), 1885 .of_match_table = omap8250_dt_ids, 1886 }, 1887 .probe = omap8250_probe, 1888 .remove = omap8250_remove, 1889 }; 1890 module_platform_driver(omap8250_platform_driver); 1891 1892 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1893 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1894 MODULE_LICENSE("GPL v2"); 1895