1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 31 #include "8250.h" 32 33 #define DEFAULT_CLK_SPEED 48000000 34 #define OMAP_UART_REGSHIFT 2 35 36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 38 #define OMAP_DMA_TX_KICK (1 << 2) 39 /* 40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 41 * The same errata is applicable to AM335x and DRA7x processors too. 42 */ 43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 44 #define UART_HAS_EFR2 BIT(4) 45 #define UART_HAS_RHR_IT_DIS BIT(5) 46 #define UART_RX_TIMEOUT_QUIRK BIT(6) 47 #define UART_HAS_NATIVE_RS485 BIT(7) 48 49 #define OMAP_UART_FCR_RX_TRIG 6 50 #define OMAP_UART_FCR_TX_TRIG 4 51 52 /* SCR register bitmasks */ 53 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 54 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 55 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 56 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 57 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 58 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 59 60 /* MVR register bitmasks */ 61 #define OMAP_UART_MVR_SCHEME_SHIFT 30 62 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 63 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 64 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 65 #define OMAP_UART_MVR_MAJ_MASK 0x700 66 #define OMAP_UART_MVR_MAJ_SHIFT 8 67 #define OMAP_UART_MVR_MIN_MASK 0x3f 68 69 /* SYSC register bitmasks */ 70 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 71 72 /* SYSS register bitmasks */ 73 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 74 75 #define UART_TI752_TLR_TX 0 76 #define UART_TI752_TLR_RX 4 77 78 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 79 #define TRIGGER_FCR_MASK(x) (x & 3) 80 81 /* Enable XON/XOFF flow control on output */ 82 #define OMAP_UART_SW_TX 0x08 83 /* Enable XON/XOFF flow control on input */ 84 #define OMAP_UART_SW_RX 0x02 85 86 #define OMAP_UART_WER_MOD_WKUP 0x7f 87 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 88 89 #define TX_TRIGGER 1 90 #define RX_TRIGGER 48 91 92 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 93 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 94 95 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 96 97 #define OMAP_UART_REV_46 0x0406 98 #define OMAP_UART_REV_52 0x0502 99 #define OMAP_UART_REV_63 0x0603 100 101 /* Interrupt Enable Register 2 */ 102 #define UART_OMAP_IER2 0x1B 103 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 104 105 /* Mode Definition Register 3 */ 106 #define UART_OMAP_MDR3 0x20 107 #define UART_OMAP_MDR3_DIR_POL BIT(3) 108 #define UART_OMAP_MDR3_DIR_EN BIT(4) 109 110 /* Enhanced features register 2 */ 111 #define UART_OMAP_EFR2 0x23 112 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 113 114 /* RX FIFO occupancy indicator */ 115 #define UART_OMAP_RX_LVL 0x19 116 117 /* Timeout low and High */ 118 #define UART_OMAP_TO_L 0x26 119 #define UART_OMAP_TO_H 0x27 120 121 struct omap8250_priv { 122 void __iomem *membase; 123 int line; 124 u8 habit; 125 u8 mdr1; 126 u8 mdr3; 127 u8 efr; 128 u8 scr; 129 u8 wer; 130 u8 xon; 131 u8 xoff; 132 u8 delayed_restore; 133 u16 quot; 134 135 u8 tx_trigger; 136 u8 rx_trigger; 137 atomic_t active; 138 bool is_suspending; 139 int wakeirq; 140 u32 latency; 141 u32 calc_latency; 142 struct pm_qos_request pm_qos_request; 143 struct work_struct qos_work; 144 struct uart_8250_dma omap8250_dma; 145 spinlock_t rx_dma_lock; 146 bool rx_dma_broken; 147 bool throttled; 148 }; 149 150 struct omap8250_dma_params { 151 u32 rx_size; 152 u8 rx_trigger; 153 u8 tx_trigger; 154 }; 155 156 struct omap8250_platdata { 157 struct omap8250_dma_params *dma_params; 158 u8 habit; 159 }; 160 161 #ifdef CONFIG_SERIAL_8250_DMA 162 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 163 #else 164 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 165 #endif 166 167 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 168 { 169 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 170 } 171 172 /* 173 * Called on runtime PM resume path from omap8250_restore_regs(), and 174 * omap8250_set_mctrl(). 175 */ 176 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 177 { 178 struct uart_8250_port *up = up_to_u8250p(port); 179 struct omap8250_priv *priv = port->private_data; 180 u8 lcr; 181 182 serial8250_do_set_mctrl(port, mctrl); 183 184 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 185 /* 186 * Turn off autoRTS if RTS is lowered and restore autoRTS 187 * setting if RTS is raised 188 */ 189 lcr = serial_in(up, UART_LCR); 190 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 191 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 192 priv->efr |= UART_EFR_RTS; 193 else 194 priv->efr &= ~UART_EFR_RTS; 195 serial_out(up, UART_EFR, priv->efr); 196 serial_out(up, UART_LCR, lcr); 197 } 198 } 199 200 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 201 { 202 int err; 203 204 err = pm_runtime_resume_and_get(port->dev); 205 if (err) 206 return; 207 208 __omap8250_set_mctrl(port, mctrl); 209 210 pm_runtime_mark_last_busy(port->dev); 211 pm_runtime_put_autosuspend(port->dev); 212 } 213 214 /* 215 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 216 * The access to uart register after MDR1 Access 217 * causes UART to corrupt data. 218 * 219 * Need a delay = 220 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 221 * give 10 times as much 222 */ 223 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 224 struct omap8250_priv *priv) 225 { 226 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 227 udelay(2); 228 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 229 UART_FCR_CLEAR_RCVR); 230 } 231 232 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 233 struct omap8250_priv *priv) 234 { 235 unsigned int uartclk = port->uartclk; 236 unsigned int div_13, div_16; 237 unsigned int abs_d13, abs_d16; 238 239 /* 240 * Old custom speed handling. 241 */ 242 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 243 priv->quot = port->custom_divisor & UART_DIV_MAX; 244 /* 245 * I assume that nobody is using this. But hey, if somebody 246 * would like to specify the divisor _and_ the mode then the 247 * driver is ready and waiting for it. 248 */ 249 if (port->custom_divisor & (1 << 16)) 250 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 251 else 252 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 253 return; 254 } 255 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 256 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 257 258 if (!div_13) 259 div_13 = 1; 260 if (!div_16) 261 div_16 = 1; 262 263 abs_d13 = abs(baud - uartclk / 13 / div_13); 264 abs_d16 = abs(baud - uartclk / 16 / div_16); 265 266 if (abs_d13 >= abs_d16) { 267 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 268 priv->quot = div_16; 269 } else { 270 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 271 priv->quot = div_13; 272 } 273 } 274 275 static void omap8250_update_scr(struct uart_8250_port *up, 276 struct omap8250_priv *priv) 277 { 278 u8 old_scr; 279 280 old_scr = serial_in(up, UART_OMAP_SCR); 281 if (old_scr == priv->scr) 282 return; 283 284 /* 285 * The manual recommends not to enable the DMA mode selector in the SCR 286 * (instead of the FCR) register _and_ selecting the DMA mode as one 287 * register write because this may lead to malfunction. 288 */ 289 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 290 serial_out(up, UART_OMAP_SCR, 291 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 292 serial_out(up, UART_OMAP_SCR, priv->scr); 293 } 294 295 static void omap8250_update_mdr1(struct uart_8250_port *up, 296 struct omap8250_priv *priv) 297 { 298 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 299 omap_8250_mdr1_errataset(up, priv); 300 else 301 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 302 } 303 304 static void omap8250_restore_regs(struct uart_8250_port *up) 305 { 306 struct uart_port *port = &up->port; 307 struct omap8250_priv *priv = port->private_data; 308 struct uart_8250_dma *dma = up->dma; 309 u8 mcr = serial8250_in_MCR(up); 310 311 /* Port locked to synchronize UART_IER access against the console. */ 312 lockdep_assert_held_once(&port->lock); 313 314 if (dma && dma->tx_running) { 315 /* 316 * TCSANOW requests the change to occur immediately however if 317 * we have a TX-DMA operation in progress then it has been 318 * observed that it might stall and never complete. Therefore we 319 * delay DMA completes to prevent this hang from happen. 320 */ 321 priv->delayed_restore = 1; 322 return; 323 } 324 325 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 326 serial_out(up, UART_EFR, UART_EFR_ECB); 327 328 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 329 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 330 serial_out(up, UART_FCR, up->fcr); 331 332 omap8250_update_scr(up, priv); 333 334 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 335 336 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 337 OMAP_UART_TCR_HALT(52)); 338 serial_out(up, UART_TI752_TLR, 339 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 340 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 341 342 serial_out(up, UART_LCR, 0); 343 344 /* drop TCR + TLR access, we setup XON/XOFF later */ 345 serial8250_out_MCR(up, mcr); 346 347 serial_out(up, UART_IER, up->ier); 348 349 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 350 serial_dl_write(up, priv->quot); 351 352 serial_out(up, UART_EFR, priv->efr); 353 354 /* Configure flow control */ 355 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 356 serial_out(up, UART_XON1, priv->xon); 357 serial_out(up, UART_XOFF1, priv->xoff); 358 359 serial_out(up, UART_LCR, up->lcr); 360 361 omap8250_update_mdr1(up, priv); 362 363 __omap8250_set_mctrl(port, port->mctrl); 364 365 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 366 367 if (port->rs485.flags & SER_RS485_ENABLED && 368 port->rs485_config == serial8250_em485_config) 369 serial8250_em485_stop_tx(up, true); 370 } 371 372 /* 373 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 374 * some differences in how we want to handle flow control. 375 */ 376 static void omap_8250_set_termios(struct uart_port *port, 377 struct ktermios *termios, 378 const struct ktermios *old) 379 { 380 struct uart_8250_port *up = up_to_u8250p(port); 381 struct omap8250_priv *priv = port->private_data; 382 unsigned char cval = 0; 383 unsigned int baud; 384 385 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 386 387 if (termios->c_cflag & CSTOPB) 388 cval |= UART_LCR_STOP; 389 if (termios->c_cflag & PARENB) 390 cval |= UART_LCR_PARITY; 391 if (!(termios->c_cflag & PARODD)) 392 cval |= UART_LCR_EPAR; 393 if (termios->c_cflag & CMSPAR) 394 cval |= UART_LCR_SPAR; 395 396 /* 397 * Ask the core to calculate the divisor for us. 398 */ 399 baud = uart_get_baud_rate(port, termios, old, 400 port->uartclk / 16 / UART_DIV_MAX, 401 port->uartclk / 13); 402 omap_8250_get_divisor(port, baud, priv); 403 404 /* 405 * Ok, we're now changing the port state. Do it with 406 * interrupts disabled. 407 */ 408 pm_runtime_get_sync(port->dev); 409 uart_port_lock_irq(port); 410 411 /* 412 * Update the per-port timeout. 413 */ 414 uart_update_timeout(port, termios->c_cflag, baud); 415 416 /* 417 * Specify which conditions may be considered for error 418 * handling and the ignoring of characters. The actual 419 * ignoring of characters only occurs if the bit is set 420 * in @ignore_status_mask as well. 421 */ 422 port->read_status_mask = UART_LSR_OE | UART_LSR_DR; 423 if (termios->c_iflag & INPCK) 424 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 425 if (termios->c_iflag & (IGNBRK | PARMRK)) 426 port->read_status_mask |= UART_LSR_BI; 427 428 /* 429 * Characters to ignore 430 */ 431 port->ignore_status_mask = 0; 432 if (termios->c_iflag & IGNPAR) 433 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 434 if (termios->c_iflag & IGNBRK) { 435 port->ignore_status_mask |= UART_LSR_BI; 436 /* 437 * If we're ignoring parity and break indicators, 438 * ignore overruns too (for real raw support). 439 */ 440 if (termios->c_iflag & IGNPAR) 441 port->ignore_status_mask |= UART_LSR_OE; 442 } 443 444 /* 445 * ignore all characters if CREAD is not set 446 */ 447 if ((termios->c_cflag & CREAD) == 0) 448 port->ignore_status_mask |= UART_LSR_DR; 449 450 /* 451 * Modem status interrupts 452 */ 453 up->ier &= ~UART_IER_MSI; 454 if (UART_ENABLE_MS(port, termios->c_cflag)) 455 up->ier |= UART_IER_MSI; 456 457 up->lcr = cval; 458 /* Up to here it was mostly serial8250_do_set_termios() */ 459 460 /* 461 * We enable TRIG_GRANU for RX and TX and additionally we set 462 * SCR_TX_EMPTY bit. The result is the following: 463 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 464 * - less than RX_TRIGGER number of bytes will also cause an interrupt 465 * once the UART decides that there no new bytes arriving. 466 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 467 * empty - the trigger level is ignored here. 468 * 469 * Once DMA is enabled: 470 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 471 * bytes in the TX FIFO. On each assert the DMA engine will move 472 * TX_TRIGGER bytes into the FIFO. 473 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 474 * the FIFO and move RX_TRIGGER bytes. 475 * This is because threshold and trigger values are the same. 476 */ 477 up->fcr = UART_FCR_ENABLE_FIFO; 478 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 479 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 480 481 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 482 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 483 484 if (up->dma) 485 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 486 OMAP_UART_SCR_DMAMODE_CTL; 487 488 priv->xon = termios->c_cc[VSTART]; 489 priv->xoff = termios->c_cc[VSTOP]; 490 491 priv->efr = 0; 492 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 493 494 if (termios->c_cflag & CRTSCTS && port->flags & UPF_HARD_FLOW && 495 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 496 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 497 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 498 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 499 priv->efr |= UART_EFR_CTS; 500 } else if (port->flags & UPF_SOFT_FLOW) { 501 /* 502 * OMAP rx s/w flow control is borked; the transmitter remains 503 * stuck off even if rx flow control is subsequently disabled 504 */ 505 506 /* 507 * IXOFF Flag: 508 * Enable XON/XOFF flow control on output. 509 * Transmit XON1, XOFF1 510 */ 511 if (termios->c_iflag & IXOFF) { 512 port->status |= UPSTAT_AUTOXOFF; 513 priv->efr |= OMAP_UART_SW_TX; 514 } 515 } 516 omap8250_restore_regs(up); 517 518 uart_port_unlock_irq(&up->port); 519 pm_runtime_mark_last_busy(port->dev); 520 pm_runtime_put_autosuspend(port->dev); 521 522 /* calculate wakeup latency constraint */ 523 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 524 priv->latency = priv->calc_latency; 525 526 schedule_work(&priv->qos_work); 527 528 /* Don't rewrite B0 */ 529 if (tty_termios_baud_rate(termios)) 530 tty_termios_encode_baud_rate(termios, baud, baud); 531 } 532 533 /* same as 8250 except that we may have extra flow bits set in EFR */ 534 static void omap_8250_pm(struct uart_port *port, unsigned int state, 535 unsigned int oldstate) 536 { 537 struct uart_8250_port *up = up_to_u8250p(port); 538 u8 efr; 539 540 pm_runtime_get_sync(port->dev); 541 542 /* Synchronize UART_IER access against the console. */ 543 uart_port_lock_irq(port); 544 545 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 546 efr = serial_in(up, UART_EFR); 547 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 548 serial_out(up, UART_LCR, 0); 549 550 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 551 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 552 serial_out(up, UART_EFR, efr); 553 serial_out(up, UART_LCR, 0); 554 555 uart_port_unlock_irq(port); 556 557 pm_runtime_mark_last_busy(port->dev); 558 pm_runtime_put_autosuspend(port->dev); 559 } 560 561 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 562 struct omap8250_priv *priv) 563 { 564 static const struct soc_device_attribute k3_soc_devices[] = { 565 { .family = "AM65X", }, 566 { .family = "J721E", .revision = "SR1.0" }, 567 { /* sentinel */ } 568 }; 569 u32 mvr, scheme; 570 u16 revision, major, minor; 571 572 mvr = uart_read(priv, UART_OMAP_MVER); 573 574 /* Check revision register scheme */ 575 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 576 577 switch (scheme) { 578 case 0: /* Legacy Scheme: OMAP2/3 */ 579 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 580 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 581 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 582 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 583 break; 584 case 1: 585 /* New Scheme: OMAP4+ */ 586 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 587 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 588 OMAP_UART_MVR_MAJ_SHIFT; 589 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 590 break; 591 default: 592 dev_warn(up->port.dev, 593 "Unknown revision, defaulting to highest\n"); 594 /* highest possible revision */ 595 major = 0xff; 596 minor = 0xff; 597 } 598 /* normalize revision for the driver */ 599 revision = UART_BUILD_REVISION(major, minor); 600 601 switch (revision) { 602 case OMAP_UART_REV_46: 603 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 604 break; 605 case OMAP_UART_REV_52: 606 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 607 OMAP_UART_WER_HAS_TX_WAKEUP; 608 break; 609 case OMAP_UART_REV_63: 610 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 611 OMAP_UART_WER_HAS_TX_WAKEUP; 612 break; 613 default: 614 break; 615 } 616 617 /* 618 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 619 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 620 * to enable errata workaround. 621 */ 622 if (soc_device_match(k3_soc_devices)) 623 priv->habit &= ~UART_HAS_RHR_IT_DIS; 624 } 625 626 static void omap8250_uart_qos_work(struct work_struct *work) 627 { 628 struct omap8250_priv *priv; 629 630 priv = container_of(work, struct omap8250_priv, qos_work); 631 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 632 } 633 634 #ifdef CONFIG_SERIAL_8250_DMA 635 static int omap_8250_dma_handle_irq(struct uart_port *port); 636 #endif 637 638 static irqreturn_t omap8250_irq(int irq, void *dev_id) 639 { 640 struct omap8250_priv *priv = dev_id; 641 struct uart_8250_port *up = serial8250_get_port(priv->line); 642 struct uart_port *port = &up->port; 643 unsigned int iir, lsr; 644 int ret; 645 646 pm_runtime_get_noresume(port->dev); 647 648 /* Shallow idle state wake-up to an IO interrupt? */ 649 if (atomic_add_unless(&priv->active, 1, 1)) { 650 priv->latency = priv->calc_latency; 651 schedule_work(&priv->qos_work); 652 } 653 654 #ifdef CONFIG_SERIAL_8250_DMA 655 if (up->dma) { 656 ret = omap_8250_dma_handle_irq(port); 657 pm_runtime_mark_last_busy(port->dev); 658 pm_runtime_put(port->dev); 659 return IRQ_RETVAL(ret); 660 } 661 #endif 662 663 lsr = serial_port_in(port, UART_LSR); 664 iir = serial_port_in(port, UART_IIR); 665 ret = serial8250_handle_irq(port, iir); 666 667 /* 668 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 669 * FIFO has been drained or erroneously. 670 * So apply solution of Errata i2310 as mentioned in 671 * https://www.ti.com/lit/pdf/sprz536 672 */ 673 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 674 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 675 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 676 unsigned char efr2, timeout_h, timeout_l; 677 678 efr2 = serial_in(up, UART_OMAP_EFR2); 679 timeout_h = serial_in(up, UART_OMAP_TO_H); 680 timeout_l = serial_in(up, UART_OMAP_TO_L); 681 serial_out(up, UART_OMAP_TO_H, 0xFF); 682 serial_out(up, UART_OMAP_TO_L, 0xFF); 683 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 684 serial_in(up, UART_IIR); 685 serial_out(up, UART_OMAP_EFR2, efr2); 686 serial_out(up, UART_OMAP_TO_H, timeout_h); 687 serial_out(up, UART_OMAP_TO_L, timeout_l); 688 } 689 690 /* Stop processing interrupts on input overrun */ 691 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 692 unsigned long delay; 693 694 /* Synchronize UART_IER access against the console. */ 695 uart_port_lock(port); 696 up->ier = serial_port_in(port, UART_IER); 697 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 698 port->ops->stop_rx(port); 699 } else { 700 /* Keep restarting the timer until 701 * the input overrun subsides. 702 */ 703 cancel_delayed_work(&up->overrun_backoff); 704 } 705 uart_port_unlock(port); 706 707 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 708 schedule_delayed_work(&up->overrun_backoff, delay); 709 } 710 711 pm_runtime_mark_last_busy(port->dev); 712 pm_runtime_put(port->dev); 713 714 return IRQ_RETVAL(ret); 715 } 716 717 static int omap_8250_startup(struct uart_port *port) 718 { 719 struct uart_8250_port *up = up_to_u8250p(port); 720 struct omap8250_priv *priv = port->private_data; 721 struct uart_8250_dma *dma = &priv->omap8250_dma; 722 int ret; 723 724 if (priv->wakeirq) { 725 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 726 if (ret) 727 return ret; 728 } 729 730 pm_runtime_get_sync(port->dev); 731 732 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 733 734 serial_out(up, UART_LCR, UART_LCR_WLEN8); 735 736 up->lsr_saved_flags = 0; 737 up->msr_saved_flags = 0; 738 739 /* Disable DMA for console UART */ 740 if (dma->fn && !uart_console(port)) { 741 up->dma = &priv->omap8250_dma; 742 ret = serial8250_request_dma(up); 743 if (ret) { 744 dev_warn_ratelimited(port->dev, 745 "failed to request DMA\n"); 746 up->dma = NULL; 747 } 748 } else { 749 up->dma = NULL; 750 } 751 752 /* Synchronize UART_IER access against the console. */ 753 uart_port_lock_irq(port); 754 up->ier = UART_IER_RLSI | UART_IER_RDI; 755 serial_out(up, UART_IER, up->ier); 756 uart_port_unlock_irq(port); 757 758 #ifdef CONFIG_PM 759 up->capabilities |= UART_CAP_RPM; 760 #endif 761 762 /* Enable module level wake up */ 763 priv->wer = OMAP_UART_WER_MOD_WKUP; 764 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 765 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 766 serial_out(up, UART_OMAP_WER, priv->wer); 767 768 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 769 uart_port_lock_irq(port); 770 up->dma->rx_dma(up); 771 uart_port_unlock_irq(port); 772 } 773 774 enable_irq(port->irq); 775 776 pm_runtime_mark_last_busy(port->dev); 777 pm_runtime_put_autosuspend(port->dev); 778 return 0; 779 } 780 781 static void omap_8250_shutdown(struct uart_port *port) 782 { 783 struct uart_8250_port *up = up_to_u8250p(port); 784 struct omap8250_priv *priv = port->private_data; 785 786 pm_runtime_get_sync(port->dev); 787 788 flush_work(&priv->qos_work); 789 if (up->dma) 790 omap_8250_rx_dma_flush(up); 791 792 serial_out(up, UART_OMAP_WER, 0); 793 if (priv->habit & UART_HAS_EFR2) 794 serial_out(up, UART_OMAP_EFR2, 0x0); 795 796 /* Synchronize UART_IER access against the console. */ 797 uart_port_lock_irq(port); 798 up->ier = 0; 799 serial_out(up, UART_IER, 0); 800 uart_port_unlock_irq(port); 801 disable_irq_nosync(port->irq); 802 dev_pm_clear_wake_irq(port->dev); 803 804 serial8250_release_dma(up); 805 up->dma = NULL; 806 807 /* 808 * Disable break condition and FIFOs 809 */ 810 if (up->lcr & UART_LCR_SBC) 811 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 812 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 813 814 pm_runtime_mark_last_busy(port->dev); 815 pm_runtime_put_autosuspend(port->dev); 816 } 817 818 static void omap_8250_throttle(struct uart_port *port) 819 { 820 struct omap8250_priv *priv = port->private_data; 821 unsigned long flags; 822 823 pm_runtime_get_sync(port->dev); 824 825 uart_port_lock_irqsave(port, &flags); 826 port->ops->stop_rx(port); 827 priv->throttled = true; 828 uart_port_unlock_irqrestore(port, flags); 829 830 pm_runtime_mark_last_busy(port->dev); 831 pm_runtime_put_autosuspend(port->dev); 832 } 833 834 static void omap_8250_unthrottle(struct uart_port *port) 835 { 836 struct omap8250_priv *priv = port->private_data; 837 struct uart_8250_port *up = up_to_u8250p(port); 838 unsigned long flags; 839 840 pm_runtime_get_sync(port->dev); 841 842 /* Synchronize UART_IER access against the console. */ 843 uart_port_lock_irqsave(port, &flags); 844 priv->throttled = false; 845 if (up->dma) 846 up->dma->rx_dma(up); 847 up->ier |= UART_IER_RLSI | UART_IER_RDI; 848 serial_out(up, UART_IER, up->ier); 849 uart_port_unlock_irqrestore(port, flags); 850 851 pm_runtime_mark_last_busy(port->dev); 852 pm_runtime_put_autosuspend(port->dev); 853 } 854 855 static int omap8250_rs485_config(struct uart_port *port, 856 struct ktermios *termios, 857 struct serial_rs485 *rs485) 858 { 859 struct omap8250_priv *priv = port->private_data; 860 struct uart_8250_port *up = up_to_u8250p(port); 861 u32 fixed_delay_rts_before_send = 0; 862 u32 fixed_delay_rts_after_send = 0; 863 unsigned int baud; 864 865 /* 866 * There is a fixed delay of 3 bit clock cycles after the TX shift 867 * register is going empty to allow time for the stop bit to transition 868 * through the transceiver before direction is changed to receive. 869 * 870 * Additionally there appears to be a 1 bit clock delay between writing 871 * to the THR register and transmission of the start bit, per page 8783 872 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 873 */ 874 if (priv->quot) { 875 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 876 baud = port->uartclk / (16 * priv->quot); 877 else 878 baud = port->uartclk / (13 * priv->quot); 879 880 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 881 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 882 } 883 884 /* 885 * Fall back to RS485 software emulation if the UART is missing 886 * hardware support, if the device tree specifies an mctrl_gpio 887 * (indicates that RTS is unavailable due to a pinmux conflict) 888 * or if the requested delays exceed the fixed hardware delays. 889 */ 890 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 891 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 892 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 893 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 894 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 895 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 896 897 port->rs485_config = serial8250_em485_config; 898 return serial8250_em485_config(port, termios, rs485); 899 } 900 901 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 902 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 903 904 if (rs485->flags & SER_RS485_ENABLED) 905 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 906 else 907 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 908 909 /* 910 * Retain same polarity semantics as RS485 software emulation, 911 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 912 */ 913 if (rs485->flags & SER_RS485_RTS_ON_SEND) 914 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 915 else 916 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 917 918 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 919 920 return 0; 921 } 922 923 #ifdef CONFIG_SERIAL_8250_DMA 924 static int omap_8250_rx_dma(struct uart_8250_port *p); 925 926 /* Must be called while priv->rx_dma_lock is held */ 927 static void __dma_rx_do_complete(struct uart_8250_port *p) 928 { 929 struct uart_8250_dma *dma = p->dma; 930 struct tty_port *tty_port = &p->port.state->port; 931 struct omap8250_priv *priv = p->port.private_data; 932 struct dma_chan *rxchan = dma->rxchan; 933 dma_cookie_t cookie; 934 struct dma_tx_state state; 935 int count; 936 int ret; 937 u32 reg; 938 939 if (!dma->rx_running) 940 goto out; 941 942 cookie = dma->rx_cookie; 943 dma->rx_running = 0; 944 945 /* Re-enable RX FIFO interrupt now that transfer is complete */ 946 if (priv->habit & UART_HAS_RHR_IT_DIS) { 947 reg = serial_in(p, UART_OMAP_IER2); 948 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 949 serial_out(p, UART_OMAP_IER2, reg); 950 } 951 952 dmaengine_tx_status(rxchan, cookie, &state); 953 954 count = dma->rx_size - state.residue + state.in_flight_bytes; 955 if (count < dma->rx_size) { 956 dmaengine_terminate_async(rxchan); 957 958 /* 959 * Poll for teardown to complete which guarantees in 960 * flight data is drained. 961 */ 962 if (state.in_flight_bytes) { 963 int poll_count = 25; 964 965 while (dmaengine_tx_status(rxchan, cookie, NULL) && 966 poll_count--) 967 cpu_relax(); 968 969 if (poll_count == -1) 970 dev_err(p->port.dev, "teardown incomplete\n"); 971 } 972 } 973 if (!count) 974 goto out; 975 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 976 977 p->port.icount.rx += ret; 978 p->port.icount.buf_overrun += count - ret; 979 out: 980 981 tty_flip_buffer_push(tty_port); 982 } 983 984 static void __dma_rx_complete(void *param) 985 { 986 struct uart_8250_port *p = param; 987 struct omap8250_priv *priv = p->port.private_data; 988 struct uart_8250_dma *dma = p->dma; 989 struct dma_tx_state state; 990 unsigned long flags; 991 992 /* Synchronize UART_IER access against the console. */ 993 uart_port_lock_irqsave(&p->port, &flags); 994 995 /* 996 * If the tx status is not DMA_COMPLETE, then this is a delayed 997 * completion callback. A previous RX timeout flush would have 998 * already pushed the data, so exit. 999 */ 1000 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 1001 DMA_COMPLETE) { 1002 uart_port_unlock_irqrestore(&p->port, flags); 1003 return; 1004 } 1005 __dma_rx_do_complete(p); 1006 if (!priv->throttled) { 1007 p->ier |= UART_IER_RLSI | UART_IER_RDI; 1008 serial_out(p, UART_IER, p->ier); 1009 if (!(priv->habit & UART_HAS_EFR2)) 1010 omap_8250_rx_dma(p); 1011 } 1012 1013 uart_port_unlock_irqrestore(&p->port, flags); 1014 } 1015 1016 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 1017 { 1018 struct omap8250_priv *priv = p->port.private_data; 1019 struct uart_8250_dma *dma = p->dma; 1020 struct dma_tx_state state; 1021 unsigned long flags; 1022 int ret; 1023 1024 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1025 1026 if (!dma->rx_running) { 1027 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1028 return; 1029 } 1030 1031 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1032 if (ret == DMA_IN_PROGRESS) { 1033 ret = dmaengine_pause(dma->rxchan); 1034 if (WARN_ON_ONCE(ret)) 1035 priv->rx_dma_broken = true; 1036 } 1037 __dma_rx_do_complete(p); 1038 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1039 } 1040 1041 static int omap_8250_rx_dma(struct uart_8250_port *p) 1042 { 1043 struct omap8250_priv *priv = p->port.private_data; 1044 struct uart_8250_dma *dma = p->dma; 1045 int err = 0; 1046 struct dma_async_tx_descriptor *desc; 1047 unsigned long flags; 1048 u32 reg; 1049 1050 /* Port locked to synchronize UART_IER access against the console. */ 1051 lockdep_assert_held_once(&p->port.lock); 1052 1053 if (priv->rx_dma_broken) 1054 return -EINVAL; 1055 1056 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1057 1058 if (dma->rx_running) { 1059 enum dma_status state; 1060 1061 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1062 if (state == DMA_COMPLETE) { 1063 /* 1064 * Disable RX interrupts to allow RX DMA completion 1065 * callback to run. 1066 */ 1067 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1068 serial_out(p, UART_IER, p->ier); 1069 } 1070 goto out; 1071 } 1072 1073 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1074 dma->rx_size, DMA_DEV_TO_MEM, 1075 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1076 if (!desc) { 1077 err = -EBUSY; 1078 goto out; 1079 } 1080 1081 dma->rx_running = 1; 1082 desc->callback = __dma_rx_complete; 1083 desc->callback_param = p; 1084 1085 dma->rx_cookie = dmaengine_submit(desc); 1086 1087 /* 1088 * Disable RX FIFO interrupt while RX DMA is enabled, else 1089 * spurious interrupt may be raised when data is in the RX FIFO 1090 * but is yet to be drained by DMA. 1091 */ 1092 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1093 reg = serial_in(p, UART_OMAP_IER2); 1094 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1095 serial_out(p, UART_OMAP_IER2, reg); 1096 } 1097 1098 dma_async_issue_pending(dma->rxchan); 1099 out: 1100 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1101 return err; 1102 } 1103 1104 static int omap_8250_tx_dma(struct uart_8250_port *p); 1105 1106 static void omap_8250_dma_tx_complete(void *param) 1107 { 1108 struct uart_8250_port *p = param; 1109 struct uart_8250_dma *dma = p->dma; 1110 struct tty_port *tport = &p->port.state->port; 1111 unsigned long flags; 1112 bool en_thri = false; 1113 struct omap8250_priv *priv = p->port.private_data; 1114 1115 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1116 UART_XMIT_SIZE, DMA_TO_DEVICE); 1117 1118 uart_port_lock_irqsave(&p->port, &flags); 1119 1120 dma->tx_running = 0; 1121 1122 uart_xmit_advance(&p->port, dma->tx_size); 1123 1124 if (priv->delayed_restore) { 1125 priv->delayed_restore = 0; 1126 omap8250_restore_regs(p); 1127 } 1128 1129 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1130 uart_write_wakeup(&p->port); 1131 1132 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1133 int ret; 1134 1135 ret = omap_8250_tx_dma(p); 1136 if (ret) 1137 en_thri = true; 1138 } else if (p->capabilities & UART_CAP_RPM) { 1139 en_thri = true; 1140 } 1141 1142 if (en_thri) { 1143 dma->tx_err = 1; 1144 serial8250_set_THRI(p); 1145 } 1146 1147 uart_port_unlock_irqrestore(&p->port, flags); 1148 } 1149 1150 static int omap_8250_tx_dma(struct uart_8250_port *p) 1151 { 1152 struct uart_8250_dma *dma = p->dma; 1153 struct omap8250_priv *priv = p->port.private_data; 1154 struct tty_port *tport = &p->port.state->port; 1155 struct dma_async_tx_descriptor *desc; 1156 struct scatterlist sg; 1157 int skip_byte = -1; 1158 int ret; 1159 1160 if (dma->tx_running) 1161 return 0; 1162 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1163 1164 /* 1165 * Even if no data, we need to return an error for the two cases 1166 * below so serial8250_tx_chars() is invoked and properly clears 1167 * THRI and/or runtime suspend. 1168 */ 1169 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1170 ret = -EBUSY; 1171 goto err; 1172 } 1173 serial8250_clear_THRI(p); 1174 return 0; 1175 } 1176 1177 if (priv->habit & OMAP_DMA_TX_KICK) { 1178 unsigned char c; 1179 u8 tx_lvl; 1180 1181 /* 1182 * We need to put the first byte into the FIFO in order to start 1183 * the DMA transfer. For transfers smaller than four bytes we 1184 * don't bother doing DMA at all. It seem not matter if there 1185 * are still bytes in the FIFO from the last transfer (in case 1186 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1187 * leaving the FIFO seem not to trigger the DMA transfer. It is 1188 * really the byte that we put into the FIFO. 1189 * If the FIFO is already full then we most likely got here from 1190 * omap_8250_dma_tx_complete(). And this means the DMA engine 1191 * just completed its work. We don't have to wait the complete 1192 * 86us at 115200,8n1 but around 60us (not to mention lower 1193 * baudrates). So in that case we take the interrupt and try 1194 * again with an empty FIFO. 1195 */ 1196 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1197 if (tx_lvl == p->tx_loadsz) { 1198 ret = -EBUSY; 1199 goto err; 1200 } 1201 if (kfifo_len(&tport->xmit_fifo) < 4) { 1202 ret = -EINVAL; 1203 goto err; 1204 } 1205 if (!uart_fifo_out(&p->port, &c, 1)) { 1206 ret = -EINVAL; 1207 goto err; 1208 } 1209 skip_byte = c; 1210 } 1211 1212 sg_init_table(&sg, 1); 1213 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, UART_XMIT_SIZE, dma->tx_addr); 1214 if (ret != 1) { 1215 ret = -EINVAL; 1216 goto err; 1217 } 1218 1219 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1220 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1221 if (!desc) { 1222 ret = -EBUSY; 1223 goto err; 1224 } 1225 1226 dma->tx_size = sg_dma_len(&sg); 1227 dma->tx_running = 1; 1228 1229 desc->callback = omap_8250_dma_tx_complete; 1230 desc->callback_param = p; 1231 1232 dma->tx_cookie = dmaengine_submit(desc); 1233 1234 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1235 UART_XMIT_SIZE, DMA_TO_DEVICE); 1236 1237 dma_async_issue_pending(dma->txchan); 1238 if (dma->tx_err) 1239 dma->tx_err = 0; 1240 1241 serial8250_clear_THRI(p); 1242 ret = 0; 1243 goto out_skip; 1244 err: 1245 dma->tx_err = 1; 1246 out_skip: 1247 if (skip_byte >= 0) 1248 serial_out(p, UART_TX, skip_byte); 1249 return ret; 1250 } 1251 1252 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1253 { 1254 switch (iir & 0x3f) { 1255 case UART_IIR_RLSI: 1256 case UART_IIR_RX_TIMEOUT: 1257 case UART_IIR_RDI: 1258 omap_8250_rx_dma_flush(up); 1259 return true; 1260 } 1261 return omap_8250_rx_dma(up); 1262 } 1263 1264 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1265 { 1266 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1267 (iir & UART_IIR_RDI)) { 1268 if (handle_rx_dma(up, iir)) { 1269 status = serial8250_rx_chars(up, status); 1270 omap_8250_rx_dma(up); 1271 } 1272 } 1273 1274 return status; 1275 } 1276 1277 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1278 u16 status) 1279 { 1280 /* Port locked to synchronize UART_IER access against the console. */ 1281 lockdep_assert_held_once(&up->port.lock); 1282 1283 /* 1284 * Queue a new transfer if FIFO has data. 1285 */ 1286 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1287 (up->ier & UART_IER_RDI)) { 1288 omap_8250_rx_dma(up); 1289 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1290 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1291 /* 1292 * Disable RX timeout, read IIR to clear 1293 * current timeout condition, clear EFR2 to 1294 * periodic timeouts, re-enable interrupts. 1295 */ 1296 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1297 serial_out(up, UART_IER, up->ier); 1298 omap_8250_rx_dma_flush(up); 1299 serial_in(up, UART_IIR); 1300 serial_out(up, UART_OMAP_EFR2, 0x0); 1301 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1302 serial_out(up, UART_IER, up->ier); 1303 } 1304 } 1305 1306 /* 1307 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1308 * hook for RX/TX and need different logic for them in the ISR. Therefore we 1309 * use the default routine in the non-DMA case and this one for with DMA. 1310 */ 1311 static int omap_8250_dma_handle_irq(struct uart_port *port) 1312 { 1313 struct uart_8250_port *up = up_to_u8250p(port); 1314 struct omap8250_priv *priv = port->private_data; 1315 u16 status; 1316 u8 iir; 1317 1318 iir = serial_port_in(port, UART_IIR); 1319 if (iir & UART_IIR_NO_INT) { 1320 return IRQ_HANDLED; 1321 } 1322 1323 uart_port_lock(port); 1324 1325 status = serial_port_in(port, UART_LSR); 1326 1327 if ((iir & 0x3f) != UART_IIR_THRI) { 1328 if (priv->habit & UART_HAS_EFR2) 1329 am654_8250_handle_rx_dma(up, iir, status); 1330 else 1331 status = omap_8250_handle_rx_dma(up, iir, status); 1332 } 1333 1334 serial8250_modem_status(up); 1335 if (status & UART_LSR_THRE && up->dma->tx_err) { 1336 if (uart_tx_stopped(port) || 1337 kfifo_is_empty(&port->state->port.xmit_fifo)) { 1338 up->dma->tx_err = 0; 1339 serial8250_tx_chars(up); 1340 } else { 1341 /* 1342 * try again due to an earlier failure which 1343 * might have been resolved by now. 1344 */ 1345 if (omap_8250_tx_dma(up)) 1346 serial8250_tx_chars(up); 1347 } 1348 } 1349 1350 uart_unlock_and_check_sysrq(port); 1351 1352 return 1; 1353 } 1354 1355 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1356 { 1357 return false; 1358 } 1359 1360 #else 1361 1362 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1363 { 1364 return -EINVAL; 1365 } 1366 #endif 1367 1368 static int omap8250_no_handle_irq(struct uart_port *port) 1369 { 1370 /* IRQ has not been requested but handling irq? */ 1371 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1372 return 0; 1373 } 1374 1375 static struct omap8250_dma_params am654_dma = { 1376 .rx_size = SZ_2K, 1377 .rx_trigger = 1, 1378 .tx_trigger = TX_TRIGGER, 1379 }; 1380 1381 static struct omap8250_dma_params am33xx_dma = { 1382 .rx_size = RX_TRIGGER, 1383 .rx_trigger = RX_TRIGGER, 1384 .tx_trigger = TX_TRIGGER, 1385 }; 1386 1387 static struct omap8250_platdata am654_platdata = { 1388 .dma_params = &am654_dma, 1389 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1390 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1391 }; 1392 1393 static struct omap8250_platdata am33xx_platdata = { 1394 .dma_params = &am33xx_dma, 1395 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1396 }; 1397 1398 static struct omap8250_platdata omap4_platdata = { 1399 .dma_params = &am33xx_dma, 1400 .habit = UART_ERRATA_CLOCK_DISABLE, 1401 }; 1402 1403 static const struct of_device_id omap8250_dt_ids[] = { 1404 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1405 { .compatible = "ti,omap2-uart" }, 1406 { .compatible = "ti,omap3-uart" }, 1407 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1408 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1409 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1410 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1411 {}, 1412 }; 1413 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1414 1415 static int omap8250_probe(struct platform_device *pdev) 1416 { 1417 struct device_node *np = pdev->dev.of_node; 1418 struct omap8250_priv *priv; 1419 const struct omap8250_platdata *pdata; 1420 struct uart_8250_port up; 1421 struct resource *regs; 1422 void __iomem *membase; 1423 int ret; 1424 1425 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1426 if (!regs) { 1427 dev_err(&pdev->dev, "missing registers\n"); 1428 return -EINVAL; 1429 } 1430 1431 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1432 if (!priv) 1433 return -ENOMEM; 1434 1435 membase = devm_ioremap(&pdev->dev, regs->start, 1436 resource_size(regs)); 1437 if (!membase) 1438 return -ENODEV; 1439 1440 memset(&up, 0, sizeof(up)); 1441 up.port.dev = &pdev->dev; 1442 up.port.mapbase = regs->start; 1443 up.port.membase = membase; 1444 /* 1445 * It claims to be 16C750 compatible however it is a little different. 1446 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1447 * have) is enabled via EFR instead of MCR. The type is set here 8250 1448 * just to get things going. UNKNOWN does not work for a few reasons and 1449 * we don't need our own type since we don't use 8250's set_termios() 1450 * or pm callback. 1451 */ 1452 up.port.type = PORT_8250; 1453 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1454 up.port.private_data = priv; 1455 1456 up.tx_loadsz = 64; 1457 up.capabilities = UART_CAP_FIFO; 1458 #ifdef CONFIG_PM 1459 /* 1460 * Runtime PM is mostly transparent. However to do it right we need to a 1461 * TX empty interrupt before we can put the device to auto idle. So if 1462 * PM is not enabled we don't add that flag and can spare that one extra 1463 * interrupt in the TX path. 1464 */ 1465 up.capabilities |= UART_CAP_RPM; 1466 #endif 1467 up.port.set_termios = omap_8250_set_termios; 1468 up.port.set_mctrl = omap8250_set_mctrl; 1469 up.port.pm = omap_8250_pm; 1470 up.port.startup = omap_8250_startup; 1471 up.port.shutdown = omap_8250_shutdown; 1472 up.port.throttle = omap_8250_throttle; 1473 up.port.unthrottle = omap_8250_unthrottle; 1474 up.port.rs485_config = omap8250_rs485_config; 1475 /* same rs485_supported for software emulation and native RS485 */ 1476 up.port.rs485_supported = serial8250_em485_supported; 1477 up.rs485_start_tx = serial8250_em485_start_tx; 1478 up.rs485_stop_tx = serial8250_em485_stop_tx; 1479 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1480 1481 ret = uart_read_port_properties(&up.port); 1482 if (ret) 1483 return ret; 1484 1485 up.port.regshift = OMAP_UART_REGSHIFT; 1486 up.port.fifosize = 64; 1487 1488 if (!up.port.uartclk) { 1489 struct clk *clk; 1490 1491 clk = devm_clk_get(&pdev->dev, NULL); 1492 if (IS_ERR(clk)) { 1493 if (PTR_ERR(clk) == -EPROBE_DEFER) 1494 return -EPROBE_DEFER; 1495 } else { 1496 up.port.uartclk = clk_get_rate(clk); 1497 } 1498 } 1499 1500 if (of_property_read_u32(np, "overrun-throttle-ms", 1501 &up.overrun_backoff_time_ms) != 0) 1502 up.overrun_backoff_time_ms = 0; 1503 1504 pdata = of_device_get_match_data(&pdev->dev); 1505 if (pdata) 1506 priv->habit |= pdata->habit; 1507 1508 if (!up.port.uartclk) { 1509 up.port.uartclk = DEFAULT_CLK_SPEED; 1510 dev_warn(&pdev->dev, 1511 "No clock speed specified: using default: %d\n", 1512 DEFAULT_CLK_SPEED); 1513 } 1514 1515 priv->membase = membase; 1516 priv->line = -ENODEV; 1517 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1518 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1519 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1520 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1521 1522 spin_lock_init(&priv->rx_dma_lock); 1523 1524 platform_set_drvdata(pdev, priv); 1525 1526 device_set_wakeup_capable(&pdev->dev, true); 1527 if (of_property_read_bool(np, "wakeup-source")) 1528 device_set_wakeup_enable(&pdev->dev, true); 1529 1530 pm_runtime_enable(&pdev->dev); 1531 pm_runtime_use_autosuspend(&pdev->dev); 1532 1533 /* 1534 * Disable runtime PM until autosuspend delay unless specifically 1535 * enabled by the user via sysfs. This is the historic way to 1536 * prevent an unsafe default policy with lossy characters on wake-up. 1537 * For serdev devices this is not needed, the policy can be managed by 1538 * the serdev driver. 1539 */ 1540 if (!of_get_available_child_count(pdev->dev.of_node)) 1541 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1542 1543 pm_runtime_get_sync(&pdev->dev); 1544 1545 omap_serial_fill_features_erratas(&up, priv); 1546 up.port.handle_irq = omap8250_no_handle_irq; 1547 priv->rx_trigger = RX_TRIGGER; 1548 priv->tx_trigger = TX_TRIGGER; 1549 #ifdef CONFIG_SERIAL_8250_DMA 1550 /* 1551 * Oh DMA support. If there are no DMA properties in the DT then 1552 * we will fall back to a generic DMA channel which does not 1553 * really work here. To ensure that we do not get a generic DMA 1554 * channel assigned, we have the the_no_dma_filter_fn() here. 1555 * To avoid "failed to request DMA" messages we check for DMA 1556 * properties in DT. 1557 */ 1558 ret = of_property_count_strings(np, "dma-names"); 1559 if (ret == 2) { 1560 struct omap8250_dma_params *dma_params = NULL; 1561 struct uart_8250_dma *dma = &priv->omap8250_dma; 1562 1563 dma->fn = the_no_dma_filter_fn; 1564 dma->tx_dma = omap_8250_tx_dma; 1565 dma->rx_dma = omap_8250_rx_dma; 1566 if (pdata) 1567 dma_params = pdata->dma_params; 1568 1569 if (dma_params) { 1570 dma->rx_size = dma_params->rx_size; 1571 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1572 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1573 priv->rx_trigger = dma_params->rx_trigger; 1574 priv->tx_trigger = dma_params->tx_trigger; 1575 } else { 1576 dma->rx_size = RX_TRIGGER; 1577 dma->rxconf.src_maxburst = RX_TRIGGER; 1578 dma->txconf.dst_maxburst = TX_TRIGGER; 1579 } 1580 } 1581 #endif 1582 1583 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1584 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1585 dev_name(&pdev->dev), priv); 1586 if (ret < 0) 1587 goto err; 1588 1589 priv->wakeirq = irq_of_parse_and_map(np, 1); 1590 1591 ret = serial8250_register_8250_port(&up); 1592 if (ret < 0) { 1593 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1594 goto err; 1595 } 1596 priv->line = ret; 1597 pm_runtime_mark_last_busy(&pdev->dev); 1598 pm_runtime_put_autosuspend(&pdev->dev); 1599 return 0; 1600 err: 1601 pm_runtime_dont_use_autosuspend(&pdev->dev); 1602 pm_runtime_put_sync(&pdev->dev); 1603 flush_work(&priv->qos_work); 1604 pm_runtime_disable(&pdev->dev); 1605 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1606 return ret; 1607 } 1608 1609 static void omap8250_remove(struct platform_device *pdev) 1610 { 1611 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1612 struct uart_8250_port *up; 1613 int err; 1614 1615 err = pm_runtime_resume_and_get(&pdev->dev); 1616 if (err) 1617 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1618 1619 up = serial8250_get_port(priv->line); 1620 omap_8250_shutdown(&up->port); 1621 serial8250_unregister_port(priv->line); 1622 priv->line = -ENODEV; 1623 pm_runtime_dont_use_autosuspend(&pdev->dev); 1624 pm_runtime_put_sync(&pdev->dev); 1625 flush_work(&priv->qos_work); 1626 pm_runtime_disable(&pdev->dev); 1627 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1628 device_set_wakeup_capable(&pdev->dev, false); 1629 } 1630 1631 static int omap8250_prepare(struct device *dev) 1632 { 1633 struct omap8250_priv *priv = dev_get_drvdata(dev); 1634 1635 if (!priv) 1636 return 0; 1637 priv->is_suspending = true; 1638 return 0; 1639 } 1640 1641 static void omap8250_complete(struct device *dev) 1642 { 1643 struct omap8250_priv *priv = dev_get_drvdata(dev); 1644 1645 if (!priv) 1646 return; 1647 priv->is_suspending = false; 1648 } 1649 1650 static int omap8250_suspend(struct device *dev) 1651 { 1652 struct omap8250_priv *priv = dev_get_drvdata(dev); 1653 struct uart_8250_port *up = serial8250_get_port(priv->line); 1654 int err = 0; 1655 1656 serial8250_suspend_port(priv->line); 1657 1658 err = pm_runtime_resume_and_get(dev); 1659 if (err) 1660 return err; 1661 if (!device_may_wakeup(dev)) 1662 priv->wer = 0; 1663 serial_out(up, UART_OMAP_WER, priv->wer); 1664 if (uart_console(&up->port) && console_suspend_enabled) 1665 err = pm_runtime_force_suspend(dev); 1666 flush_work(&priv->qos_work); 1667 1668 return err; 1669 } 1670 1671 static int omap8250_resume(struct device *dev) 1672 { 1673 struct omap8250_priv *priv = dev_get_drvdata(dev); 1674 struct uart_8250_port *up = serial8250_get_port(priv->line); 1675 int err; 1676 1677 if (uart_console(&up->port) && console_suspend_enabled) { 1678 err = pm_runtime_force_resume(dev); 1679 if (err) 1680 return err; 1681 } 1682 1683 serial8250_resume_port(priv->line); 1684 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1685 pm_runtime_mark_last_busy(dev); 1686 pm_runtime_put_autosuspend(dev); 1687 1688 return 0; 1689 } 1690 1691 static int omap8250_lost_context(struct uart_8250_port *up) 1692 { 1693 u32 val; 1694 1695 val = serial_in(up, UART_OMAP_SCR); 1696 /* 1697 * If we lose context, then SCR is set to its reset value of zero. 1698 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1699 * among other bits, to never set the register back to zero again. 1700 */ 1701 if (!val) 1702 return 1; 1703 return 0; 1704 } 1705 1706 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1707 { 1708 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1709 } 1710 1711 /* TODO: in future, this should happen via API in drivers/reset/ */ 1712 static int omap8250_soft_reset(struct device *dev) 1713 { 1714 struct omap8250_priv *priv = dev_get_drvdata(dev); 1715 int timeout = 100; 1716 int sysc; 1717 int syss; 1718 1719 /* 1720 * At least on omap4, unused uarts may not idle after reset without 1721 * a basic scr dma configuration even with no dma in use. The 1722 * module clkctrl status bits will be 1 instead of 3 blocking idle 1723 * for the whole clockdomain. The softreset below will clear scr, 1724 * and we restore it on resume so this is safe to do on all SoCs 1725 * needing omap8250_soft_reset() quirk. Do it in two writes as 1726 * recommended in the comment for omap8250_update_scr(). 1727 */ 1728 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1729 uart_write(priv, UART_OMAP_SCR, 1730 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1731 1732 sysc = uart_read(priv, UART_OMAP_SYSC); 1733 1734 /* softreset the UART */ 1735 sysc |= OMAP_UART_SYSC_SOFTRESET; 1736 uart_write(priv, UART_OMAP_SYSC, sysc); 1737 1738 /* By experiments, 1us enough for reset complete on AM335x */ 1739 do { 1740 udelay(1); 1741 syss = uart_read(priv, UART_OMAP_SYSS); 1742 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1743 1744 if (!timeout) { 1745 dev_err(dev, "timed out waiting for reset done\n"); 1746 return -ETIMEDOUT; 1747 } 1748 1749 return 0; 1750 } 1751 1752 static int omap8250_runtime_suspend(struct device *dev) 1753 { 1754 struct omap8250_priv *priv = dev_get_drvdata(dev); 1755 struct uart_8250_port *up = NULL; 1756 1757 if (priv->line >= 0) 1758 up = serial8250_get_port(priv->line); 1759 1760 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1761 int ret; 1762 1763 ret = omap8250_soft_reset(dev); 1764 if (ret) 1765 return ret; 1766 1767 if (up) { 1768 /* Restore to UART mode after reset (for wakeup) */ 1769 omap8250_update_mdr1(up, priv); 1770 /* Restore wakeup enable register */ 1771 serial_out(up, UART_OMAP_WER, priv->wer); 1772 } 1773 } 1774 1775 if (up && up->dma && up->dma->rxchan) 1776 omap_8250_rx_dma_flush(up); 1777 1778 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1779 schedule_work(&priv->qos_work); 1780 atomic_set(&priv->active, 0); 1781 1782 return 0; 1783 } 1784 1785 static int omap8250_runtime_resume(struct device *dev) 1786 { 1787 struct omap8250_priv *priv = dev_get_drvdata(dev); 1788 struct uart_8250_port *up = NULL; 1789 1790 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1791 if (atomic_read(&priv->active)) 1792 return 0; 1793 1794 if (priv->line >= 0) 1795 up = serial8250_get_port(priv->line); 1796 1797 if (up && omap8250_lost_context(up)) { 1798 uart_port_lock_irq(&up->port); 1799 omap8250_restore_regs(up); 1800 uart_port_unlock_irq(&up->port); 1801 } 1802 1803 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1804 uart_port_lock_irq(&up->port); 1805 omap_8250_rx_dma(up); 1806 uart_port_unlock_irq(&up->port); 1807 } 1808 1809 atomic_set(&priv->active, 1); 1810 priv->latency = priv->calc_latency; 1811 schedule_work(&priv->qos_work); 1812 1813 return 0; 1814 } 1815 1816 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1817 static int __init omap8250_console_fixup(void) 1818 { 1819 char *omap_str; 1820 char *options; 1821 u8 idx; 1822 1823 if (strstr(boot_command_line, "console=ttyS")) 1824 /* user set a ttyS based name for the console */ 1825 return 0; 1826 1827 omap_str = strstr(boot_command_line, "console=ttyO"); 1828 if (!omap_str) 1829 /* user did not set ttyO based console, so we don't care */ 1830 return 0; 1831 1832 omap_str += 12; 1833 if ('0' <= *omap_str && *omap_str <= '9') 1834 idx = *omap_str - '0'; 1835 else 1836 return 0; 1837 1838 omap_str++; 1839 if (omap_str[0] == ',') { 1840 omap_str++; 1841 options = omap_str; 1842 } else { 1843 options = NULL; 1844 } 1845 1846 add_preferred_console("ttyS", idx, options); 1847 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1848 idx, idx); 1849 pr_err("This ensures that you still see kernel messages. Please\n"); 1850 pr_err("update your kernel commandline.\n"); 1851 return 0; 1852 } 1853 console_initcall(omap8250_console_fixup); 1854 #endif 1855 1856 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1857 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1858 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1859 omap8250_runtime_resume, NULL) 1860 .prepare = pm_sleep_ptr(omap8250_prepare), 1861 .complete = pm_sleep_ptr(omap8250_complete), 1862 }; 1863 1864 static struct platform_driver omap8250_platform_driver = { 1865 .driver = { 1866 .name = "omap8250", 1867 .pm = pm_ptr(&omap8250_dev_pm_ops), 1868 .of_match_table = omap8250_dt_ids, 1869 }, 1870 .probe = omap8250_probe, 1871 .remove = omap8250_remove, 1872 }; 1873 module_platform_driver(omap8250_platform_driver); 1874 1875 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1876 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1877 MODULE_LICENSE("GPL v2"); 1878