1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/sys_soc.h> 30 #include <linux/pm_domain.h> 31 32 #include "8250.h" 33 34 #define DEFAULT_CLK_SPEED 48000000 35 #define OMAP_UART_REGSHIFT 2 36 37 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 38 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 39 #define OMAP_DMA_TX_KICK (1 << 2) 40 /* 41 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 42 * The same errata is applicable to AM335x and DRA7x processors too. 43 */ 44 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 45 #define UART_HAS_EFR2 BIT(4) 46 #define UART_HAS_RHR_IT_DIS BIT(5) 47 #define UART_RX_TIMEOUT_QUIRK BIT(6) 48 #define UART_HAS_NATIVE_RS485 BIT(7) 49 50 #define OMAP_UART_FCR_RX_TRIG 6 51 #define OMAP_UART_FCR_TX_TRIG 4 52 53 /* SCR register bitmasks */ 54 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 55 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 56 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 57 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 58 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 59 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 60 61 /* MVR register bitmasks */ 62 #define OMAP_UART_MVR_SCHEME_SHIFT 30 63 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 64 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 65 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 66 #define OMAP_UART_MVR_MAJ_MASK 0x700 67 #define OMAP_UART_MVR_MAJ_SHIFT 8 68 #define OMAP_UART_MVR_MIN_MASK 0x3f 69 70 /* SYSC register bitmasks */ 71 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 72 73 /* SYSS register bitmasks */ 74 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 75 76 #define UART_TI752_TLR_TX 0 77 #define UART_TI752_TLR_RX 4 78 79 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 80 #define TRIGGER_FCR_MASK(x) (x & 3) 81 82 /* Enable XON/XOFF flow control on output */ 83 #define OMAP_UART_SW_TX 0x08 84 /* Enable XON/XOFF flow control on input */ 85 #define OMAP_UART_SW_RX 0x02 86 87 #define OMAP_UART_WER_MOD_WKUP 0x7f 88 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 89 90 #define TX_TRIGGER 1 91 #define RX_TRIGGER 48 92 93 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 94 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 95 96 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 97 98 #define OMAP_UART_REV_46 0x0406 99 #define OMAP_UART_REV_52 0x0502 100 #define OMAP_UART_REV_63 0x0603 101 102 /* Interrupt Enable Register 2 */ 103 #define UART_OMAP_IER2 0x1B 104 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 105 106 /* Mode Definition Register 3 */ 107 #define UART_OMAP_MDR3 0x20 108 #define UART_OMAP_MDR3_DIR_POL BIT(3) 109 #define UART_OMAP_MDR3_DIR_EN BIT(4) 110 111 /* Enhanced features register 2 */ 112 #define UART_OMAP_EFR2 0x23 113 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 114 115 /* RX FIFO occupancy indicator */ 116 #define UART_OMAP_RX_LVL 0x19 117 118 /* 119 * Copy of the genpd flags for the console. 120 * Only used if console suspend is disabled 121 */ 122 static unsigned int genpd_flags_console; 123 124 struct omap8250_priv { 125 void __iomem *membase; 126 int line; 127 u8 habit; 128 u8 mdr1; 129 u8 mdr3; 130 u8 efr; 131 u8 scr; 132 u8 wer; 133 u8 xon; 134 u8 xoff; 135 u8 delayed_restore; 136 u16 quot; 137 138 u8 tx_trigger; 139 u8 rx_trigger; 140 atomic_t active; 141 bool is_suspending; 142 int wakeirq; 143 int wakeups_enabled; 144 u32 latency; 145 u32 calc_latency; 146 struct pm_qos_request pm_qos_request; 147 struct work_struct qos_work; 148 struct uart_8250_dma omap8250_dma; 149 spinlock_t rx_dma_lock; 150 bool rx_dma_broken; 151 bool throttled; 152 }; 153 154 struct omap8250_dma_params { 155 u32 rx_size; 156 u8 rx_trigger; 157 u8 tx_trigger; 158 }; 159 160 struct omap8250_platdata { 161 struct omap8250_dma_params *dma_params; 162 u8 habit; 163 }; 164 165 #ifdef CONFIG_SERIAL_8250_DMA 166 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 167 #else 168 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 169 #endif 170 171 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 172 { 173 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 174 } 175 176 /* 177 * Called on runtime PM resume path from omap8250_restore_regs(), and 178 * omap8250_set_mctrl(). 179 */ 180 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 181 { 182 struct uart_8250_port *up = up_to_u8250p(port); 183 struct omap8250_priv *priv = up->port.private_data; 184 u8 lcr; 185 186 serial8250_do_set_mctrl(port, mctrl); 187 188 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 189 /* 190 * Turn off autoRTS if RTS is lowered and restore autoRTS 191 * setting if RTS is raised 192 */ 193 lcr = serial_in(up, UART_LCR); 194 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 195 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 196 priv->efr |= UART_EFR_RTS; 197 else 198 priv->efr &= ~UART_EFR_RTS; 199 serial_out(up, UART_EFR, priv->efr); 200 serial_out(up, UART_LCR, lcr); 201 } 202 } 203 204 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 205 { 206 int err; 207 208 err = pm_runtime_resume_and_get(port->dev); 209 if (err) 210 return; 211 212 __omap8250_set_mctrl(port, mctrl); 213 214 pm_runtime_mark_last_busy(port->dev); 215 pm_runtime_put_autosuspend(port->dev); 216 } 217 218 /* 219 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 220 * The access to uart register after MDR1 Access 221 * causes UART to corrupt data. 222 * 223 * Need a delay = 224 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 225 * give 10 times as much 226 */ 227 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 228 struct omap8250_priv *priv) 229 { 230 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 231 udelay(2); 232 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 233 UART_FCR_CLEAR_RCVR); 234 } 235 236 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 237 struct omap8250_priv *priv) 238 { 239 unsigned int uartclk = port->uartclk; 240 unsigned int div_13, div_16; 241 unsigned int abs_d13, abs_d16; 242 243 /* 244 * Old custom speed handling. 245 */ 246 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 247 priv->quot = port->custom_divisor & UART_DIV_MAX; 248 /* 249 * I assume that nobody is using this. But hey, if somebody 250 * would like to specify the divisor _and_ the mode then the 251 * driver is ready and waiting for it. 252 */ 253 if (port->custom_divisor & (1 << 16)) 254 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 255 else 256 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 257 return; 258 } 259 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 260 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 261 262 if (!div_13) 263 div_13 = 1; 264 if (!div_16) 265 div_16 = 1; 266 267 abs_d13 = abs(baud - uartclk / 13 / div_13); 268 abs_d16 = abs(baud - uartclk / 16 / div_16); 269 270 if (abs_d13 >= abs_d16) { 271 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 272 priv->quot = div_16; 273 } else { 274 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 275 priv->quot = div_13; 276 } 277 } 278 279 static void omap8250_update_scr(struct uart_8250_port *up, 280 struct omap8250_priv *priv) 281 { 282 u8 old_scr; 283 284 old_scr = serial_in(up, UART_OMAP_SCR); 285 if (old_scr == priv->scr) 286 return; 287 288 /* 289 * The manual recommends not to enable the DMA mode selector in the SCR 290 * (instead of the FCR) register _and_ selecting the DMA mode as one 291 * register write because this may lead to malfunction. 292 */ 293 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 294 serial_out(up, UART_OMAP_SCR, 295 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 296 serial_out(up, UART_OMAP_SCR, priv->scr); 297 } 298 299 static void omap8250_update_mdr1(struct uart_8250_port *up, 300 struct omap8250_priv *priv) 301 { 302 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 303 omap_8250_mdr1_errataset(up, priv); 304 else 305 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 306 } 307 308 static void omap8250_restore_regs(struct uart_8250_port *up) 309 { 310 struct omap8250_priv *priv = up->port.private_data; 311 struct uart_8250_dma *dma = up->dma; 312 u8 mcr = serial8250_in_MCR(up); 313 314 /* Port locked to synchronize UART_IER access against the console. */ 315 lockdep_assert_held_once(&up->port.lock); 316 317 if (dma && dma->tx_running) { 318 /* 319 * TCSANOW requests the change to occur immediately however if 320 * we have a TX-DMA operation in progress then it has been 321 * observed that it might stall and never complete. Therefore we 322 * delay DMA completes to prevent this hang from happen. 323 */ 324 priv->delayed_restore = 1; 325 return; 326 } 327 328 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 329 serial_out(up, UART_EFR, UART_EFR_ECB); 330 331 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 332 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 333 serial_out(up, UART_FCR, up->fcr); 334 335 omap8250_update_scr(up, priv); 336 337 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 338 339 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 340 OMAP_UART_TCR_HALT(52)); 341 serial_out(up, UART_TI752_TLR, 342 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 343 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 344 345 serial_out(up, UART_LCR, 0); 346 347 /* drop TCR + TLR access, we setup XON/XOFF later */ 348 serial8250_out_MCR(up, mcr); 349 350 serial_out(up, UART_IER, up->ier); 351 352 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 353 serial_dl_write(up, priv->quot); 354 355 serial_out(up, UART_EFR, priv->efr); 356 357 /* Configure flow control */ 358 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 359 serial_out(up, UART_XON1, priv->xon); 360 serial_out(up, UART_XOFF1, priv->xoff); 361 362 serial_out(up, UART_LCR, up->lcr); 363 364 omap8250_update_mdr1(up, priv); 365 366 __omap8250_set_mctrl(&up->port, up->port.mctrl); 367 368 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 369 370 if (up->port.rs485.flags & SER_RS485_ENABLED && 371 up->port.rs485_config == serial8250_em485_config) 372 serial8250_em485_stop_tx(up); 373 } 374 375 /* 376 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 377 * some differences in how we want to handle flow control. 378 */ 379 static void omap_8250_set_termios(struct uart_port *port, 380 struct ktermios *termios, 381 const struct ktermios *old) 382 { 383 struct uart_8250_port *up = up_to_u8250p(port); 384 struct omap8250_priv *priv = up->port.private_data; 385 unsigned char cval = 0; 386 unsigned int baud; 387 388 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 389 390 if (termios->c_cflag & CSTOPB) 391 cval |= UART_LCR_STOP; 392 if (termios->c_cflag & PARENB) 393 cval |= UART_LCR_PARITY; 394 if (!(termios->c_cflag & PARODD)) 395 cval |= UART_LCR_EPAR; 396 if (termios->c_cflag & CMSPAR) 397 cval |= UART_LCR_SPAR; 398 399 /* 400 * Ask the core to calculate the divisor for us. 401 */ 402 baud = uart_get_baud_rate(port, termios, old, 403 port->uartclk / 16 / UART_DIV_MAX, 404 port->uartclk / 13); 405 omap_8250_get_divisor(port, baud, priv); 406 407 /* 408 * Ok, we're now changing the port state. Do it with 409 * interrupts disabled. 410 */ 411 pm_runtime_get_sync(port->dev); 412 uart_port_lock_irq(port); 413 414 /* 415 * Update the per-port timeout. 416 */ 417 uart_update_timeout(port, termios->c_cflag, baud); 418 419 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 420 if (termios->c_iflag & INPCK) 421 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 422 if (termios->c_iflag & (IGNBRK | PARMRK)) 423 up->port.read_status_mask |= UART_LSR_BI; 424 425 /* 426 * Characters to ignore 427 */ 428 up->port.ignore_status_mask = 0; 429 if (termios->c_iflag & IGNPAR) 430 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 431 if (termios->c_iflag & IGNBRK) { 432 up->port.ignore_status_mask |= UART_LSR_BI; 433 /* 434 * If we're ignoring parity and break indicators, 435 * ignore overruns too (for real raw support). 436 */ 437 if (termios->c_iflag & IGNPAR) 438 up->port.ignore_status_mask |= UART_LSR_OE; 439 } 440 441 /* 442 * ignore all characters if CREAD is not set 443 */ 444 if ((termios->c_cflag & CREAD) == 0) 445 up->port.ignore_status_mask |= UART_LSR_DR; 446 447 /* 448 * Modem status interrupts 449 */ 450 up->ier &= ~UART_IER_MSI; 451 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 452 up->ier |= UART_IER_MSI; 453 454 up->lcr = cval; 455 /* Up to here it was mostly serial8250_do_set_termios() */ 456 457 /* 458 * We enable TRIG_GRANU for RX and TX and additionally we set 459 * SCR_TX_EMPTY bit. The result is the following: 460 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 461 * - less than RX_TRIGGER number of bytes will also cause an interrupt 462 * once the UART decides that there no new bytes arriving. 463 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 464 * empty - the trigger level is ignored here. 465 * 466 * Once DMA is enabled: 467 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 468 * bytes in the TX FIFO. On each assert the DMA engine will move 469 * TX_TRIGGER bytes into the FIFO. 470 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 471 * the FIFO and move RX_TRIGGER bytes. 472 * This is because threshold and trigger values are the same. 473 */ 474 up->fcr = UART_FCR_ENABLE_FIFO; 475 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 476 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 477 478 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 479 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 480 481 if (up->dma) 482 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 483 OMAP_UART_SCR_DMAMODE_CTL; 484 485 priv->xon = termios->c_cc[VSTART]; 486 priv->xoff = termios->c_cc[VSTOP]; 487 488 priv->efr = 0; 489 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 490 491 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 492 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 493 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 494 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 495 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 496 priv->efr |= UART_EFR_CTS; 497 } else if (up->port.flags & UPF_SOFT_FLOW) { 498 /* 499 * OMAP rx s/w flow control is borked; the transmitter remains 500 * stuck off even if rx flow control is subsequently disabled 501 */ 502 503 /* 504 * IXOFF Flag: 505 * Enable XON/XOFF flow control on output. 506 * Transmit XON1, XOFF1 507 */ 508 if (termios->c_iflag & IXOFF) { 509 up->port.status |= UPSTAT_AUTOXOFF; 510 priv->efr |= OMAP_UART_SW_TX; 511 } 512 } 513 omap8250_restore_regs(up); 514 515 uart_port_unlock_irq(&up->port); 516 pm_runtime_mark_last_busy(port->dev); 517 pm_runtime_put_autosuspend(port->dev); 518 519 /* calculate wakeup latency constraint */ 520 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 521 priv->latency = priv->calc_latency; 522 523 schedule_work(&priv->qos_work); 524 525 /* Don't rewrite B0 */ 526 if (tty_termios_baud_rate(termios)) 527 tty_termios_encode_baud_rate(termios, baud, baud); 528 } 529 530 /* same as 8250 except that we may have extra flow bits set in EFR */ 531 static void omap_8250_pm(struct uart_port *port, unsigned int state, 532 unsigned int oldstate) 533 { 534 struct uart_8250_port *up = up_to_u8250p(port); 535 u8 efr; 536 537 pm_runtime_get_sync(port->dev); 538 539 /* Synchronize UART_IER access against the console. */ 540 uart_port_lock_irq(port); 541 542 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 543 efr = serial_in(up, UART_EFR); 544 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 545 serial_out(up, UART_LCR, 0); 546 547 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 548 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 549 serial_out(up, UART_EFR, efr); 550 serial_out(up, UART_LCR, 0); 551 552 uart_port_unlock_irq(port); 553 554 pm_runtime_mark_last_busy(port->dev); 555 pm_runtime_put_autosuspend(port->dev); 556 } 557 558 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 559 struct omap8250_priv *priv) 560 { 561 static const struct soc_device_attribute k3_soc_devices[] = { 562 { .family = "AM65X", }, 563 { .family = "J721E", .revision = "SR1.0" }, 564 { /* sentinel */ } 565 }; 566 u32 mvr, scheme; 567 u16 revision, major, minor; 568 569 mvr = uart_read(priv, UART_OMAP_MVER); 570 571 /* Check revision register scheme */ 572 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 573 574 switch (scheme) { 575 case 0: /* Legacy Scheme: OMAP2/3 */ 576 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 577 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 578 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 579 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 580 break; 581 case 1: 582 /* New Scheme: OMAP4+ */ 583 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 584 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 585 OMAP_UART_MVR_MAJ_SHIFT; 586 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 587 break; 588 default: 589 dev_warn(up->port.dev, 590 "Unknown revision, defaulting to highest\n"); 591 /* highest possible revision */ 592 major = 0xff; 593 minor = 0xff; 594 } 595 /* normalize revision for the driver */ 596 revision = UART_BUILD_REVISION(major, minor); 597 598 switch (revision) { 599 case OMAP_UART_REV_46: 600 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 601 break; 602 case OMAP_UART_REV_52: 603 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 604 OMAP_UART_WER_HAS_TX_WAKEUP; 605 break; 606 case OMAP_UART_REV_63: 607 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 608 OMAP_UART_WER_HAS_TX_WAKEUP; 609 break; 610 default: 611 break; 612 } 613 614 /* 615 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 616 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 617 * to enable errata workaround. 618 */ 619 if (soc_device_match(k3_soc_devices)) 620 priv->habit &= ~UART_HAS_RHR_IT_DIS; 621 } 622 623 static void omap8250_uart_qos_work(struct work_struct *work) 624 { 625 struct omap8250_priv *priv; 626 627 priv = container_of(work, struct omap8250_priv, qos_work); 628 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 629 } 630 631 #ifdef CONFIG_SERIAL_8250_DMA 632 static int omap_8250_dma_handle_irq(struct uart_port *port); 633 #endif 634 635 static irqreturn_t omap8250_irq(int irq, void *dev_id) 636 { 637 struct omap8250_priv *priv = dev_id; 638 struct uart_8250_port *up = serial8250_get_port(priv->line); 639 struct uart_port *port = &up->port; 640 unsigned int iir, lsr; 641 int ret; 642 643 pm_runtime_get_noresume(port->dev); 644 645 /* Shallow idle state wake-up to an IO interrupt? */ 646 if (atomic_add_unless(&priv->active, 1, 1)) { 647 priv->latency = priv->calc_latency; 648 schedule_work(&priv->qos_work); 649 } 650 651 #ifdef CONFIG_SERIAL_8250_DMA 652 if (up->dma) { 653 ret = omap_8250_dma_handle_irq(port); 654 pm_runtime_mark_last_busy(port->dev); 655 pm_runtime_put(port->dev); 656 return IRQ_RETVAL(ret); 657 } 658 #endif 659 660 lsr = serial_port_in(port, UART_LSR); 661 iir = serial_port_in(port, UART_IIR); 662 ret = serial8250_handle_irq(port, iir); 663 664 /* 665 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 666 * FIFO has been drained, in which case a dummy read of RX FIFO 667 * is required to clear RX TIMEOUT condition. 668 */ 669 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 670 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 671 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 672 serial_port_in(port, UART_RX); 673 } 674 675 /* Stop processing interrupts on input overrun */ 676 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 677 unsigned long delay; 678 679 /* Synchronize UART_IER access against the console. */ 680 uart_port_lock(port); 681 up->ier = port->serial_in(port, UART_IER); 682 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 683 port->ops->stop_rx(port); 684 } else { 685 /* Keep restarting the timer until 686 * the input overrun subsides. 687 */ 688 cancel_delayed_work(&up->overrun_backoff); 689 } 690 uart_port_unlock(port); 691 692 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 693 schedule_delayed_work(&up->overrun_backoff, delay); 694 } 695 696 pm_runtime_mark_last_busy(port->dev); 697 pm_runtime_put(port->dev); 698 699 return IRQ_RETVAL(ret); 700 } 701 702 static int omap_8250_startup(struct uart_port *port) 703 { 704 struct uart_8250_port *up = up_to_u8250p(port); 705 struct omap8250_priv *priv = port->private_data; 706 struct uart_8250_dma *dma = &priv->omap8250_dma; 707 int ret; 708 709 if (priv->wakeirq) { 710 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 711 if (ret) 712 return ret; 713 } 714 715 pm_runtime_get_sync(port->dev); 716 717 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 718 719 serial_out(up, UART_LCR, UART_LCR_WLEN8); 720 721 up->lsr_saved_flags = 0; 722 up->msr_saved_flags = 0; 723 724 /* Disable DMA for console UART */ 725 if (dma->fn && !uart_console(port)) { 726 up->dma = &priv->omap8250_dma; 727 ret = serial8250_request_dma(up); 728 if (ret) { 729 dev_warn_ratelimited(port->dev, 730 "failed to request DMA\n"); 731 up->dma = NULL; 732 } 733 } else { 734 up->dma = NULL; 735 } 736 737 /* Synchronize UART_IER access against the console. */ 738 uart_port_lock_irq(port); 739 up->ier = UART_IER_RLSI | UART_IER_RDI; 740 serial_out(up, UART_IER, up->ier); 741 uart_port_unlock_irq(port); 742 743 #ifdef CONFIG_PM 744 up->capabilities |= UART_CAP_RPM; 745 #endif 746 747 /* Enable module level wake up */ 748 priv->wer = OMAP_UART_WER_MOD_WKUP; 749 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 750 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 751 serial_out(up, UART_OMAP_WER, priv->wer); 752 753 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 754 uart_port_lock_irq(port); 755 up->dma->rx_dma(up); 756 uart_port_unlock_irq(port); 757 } 758 759 enable_irq(up->port.irq); 760 761 pm_runtime_mark_last_busy(port->dev); 762 pm_runtime_put_autosuspend(port->dev); 763 return 0; 764 } 765 766 static void omap_8250_shutdown(struct uart_port *port) 767 { 768 struct uart_8250_port *up = up_to_u8250p(port); 769 struct omap8250_priv *priv = port->private_data; 770 771 flush_work(&priv->qos_work); 772 if (up->dma) 773 omap_8250_rx_dma_flush(up); 774 775 pm_runtime_get_sync(port->dev); 776 777 serial_out(up, UART_OMAP_WER, 0); 778 if (priv->habit & UART_HAS_EFR2) 779 serial_out(up, UART_OMAP_EFR2, 0x0); 780 781 /* Synchronize UART_IER access against the console. */ 782 uart_port_lock_irq(port); 783 up->ier = 0; 784 serial_out(up, UART_IER, 0); 785 uart_port_unlock_irq(port); 786 disable_irq_nosync(up->port.irq); 787 dev_pm_clear_wake_irq(port->dev); 788 789 serial8250_release_dma(up); 790 up->dma = NULL; 791 792 /* 793 * Disable break condition and FIFOs 794 */ 795 if (up->lcr & UART_LCR_SBC) 796 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 797 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 798 799 pm_runtime_mark_last_busy(port->dev); 800 pm_runtime_put_autosuspend(port->dev); 801 } 802 803 static void omap_8250_throttle(struct uart_port *port) 804 { 805 struct omap8250_priv *priv = port->private_data; 806 unsigned long flags; 807 808 pm_runtime_get_sync(port->dev); 809 810 uart_port_lock_irqsave(port, &flags); 811 port->ops->stop_rx(port); 812 priv->throttled = true; 813 uart_port_unlock_irqrestore(port, flags); 814 815 pm_runtime_mark_last_busy(port->dev); 816 pm_runtime_put_autosuspend(port->dev); 817 } 818 819 static void omap_8250_unthrottle(struct uart_port *port) 820 { 821 struct omap8250_priv *priv = port->private_data; 822 struct uart_8250_port *up = up_to_u8250p(port); 823 unsigned long flags; 824 825 pm_runtime_get_sync(port->dev); 826 827 /* Synchronize UART_IER access against the console. */ 828 uart_port_lock_irqsave(port, &flags); 829 priv->throttled = false; 830 if (up->dma) 831 up->dma->rx_dma(up); 832 up->ier |= UART_IER_RLSI | UART_IER_RDI; 833 port->read_status_mask |= UART_LSR_DR; 834 serial_out(up, UART_IER, up->ier); 835 uart_port_unlock_irqrestore(port, flags); 836 837 pm_runtime_mark_last_busy(port->dev); 838 pm_runtime_put_autosuspend(port->dev); 839 } 840 841 static int omap8250_rs485_config(struct uart_port *port, 842 struct ktermios *termios, 843 struct serial_rs485 *rs485) 844 { 845 struct omap8250_priv *priv = port->private_data; 846 struct uart_8250_port *up = up_to_u8250p(port); 847 u32 fixed_delay_rts_before_send = 0; 848 u32 fixed_delay_rts_after_send = 0; 849 unsigned int baud; 850 851 /* 852 * There is a fixed delay of 3 bit clock cycles after the TX shift 853 * register is going empty to allow time for the stop bit to transition 854 * through the transceiver before direction is changed to receive. 855 * 856 * Additionally there appears to be a 1 bit clock delay between writing 857 * to the THR register and transmission of the start bit, per page 8783 858 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 859 */ 860 if (priv->quot) { 861 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 862 baud = port->uartclk / (16 * priv->quot); 863 else 864 baud = port->uartclk / (13 * priv->quot); 865 866 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 867 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 868 } 869 870 /* 871 * Fall back to RS485 software emulation if the UART is missing 872 * hardware support, if the device tree specifies an mctrl_gpio 873 * (indicates that RTS is unavailable due to a pinmux conflict) 874 * or if the requested delays exceed the fixed hardware delays. 875 */ 876 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 877 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 878 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 879 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 880 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 881 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 882 883 port->rs485_config = serial8250_em485_config; 884 return serial8250_em485_config(port, termios, rs485); 885 } 886 887 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 888 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 889 890 if (rs485->flags & SER_RS485_ENABLED) 891 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 892 else 893 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 894 895 /* 896 * Retain same polarity semantics as RS485 software emulation, 897 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 898 */ 899 if (rs485->flags & SER_RS485_RTS_ON_SEND) 900 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 901 else 902 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 903 904 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 905 906 return 0; 907 } 908 909 #ifdef CONFIG_SERIAL_8250_DMA 910 static int omap_8250_rx_dma(struct uart_8250_port *p); 911 912 /* Must be called while priv->rx_dma_lock is held */ 913 static void __dma_rx_do_complete(struct uart_8250_port *p) 914 { 915 struct uart_8250_dma *dma = p->dma; 916 struct tty_port *tty_port = &p->port.state->port; 917 struct omap8250_priv *priv = p->port.private_data; 918 struct dma_chan *rxchan = dma->rxchan; 919 dma_cookie_t cookie; 920 struct dma_tx_state state; 921 int count; 922 int ret; 923 u32 reg; 924 925 if (!dma->rx_running) 926 goto out; 927 928 cookie = dma->rx_cookie; 929 dma->rx_running = 0; 930 931 /* Re-enable RX FIFO interrupt now that transfer is complete */ 932 if (priv->habit & UART_HAS_RHR_IT_DIS) { 933 reg = serial_in(p, UART_OMAP_IER2); 934 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 935 serial_out(p, UART_OMAP_IER2, reg); 936 } 937 938 dmaengine_tx_status(rxchan, cookie, &state); 939 940 count = dma->rx_size - state.residue + state.in_flight_bytes; 941 if (count < dma->rx_size) { 942 dmaengine_terminate_async(rxchan); 943 944 /* 945 * Poll for teardown to complete which guarantees in 946 * flight data is drained. 947 */ 948 if (state.in_flight_bytes) { 949 int poll_count = 25; 950 951 while (dmaengine_tx_status(rxchan, cookie, NULL) && 952 poll_count--) 953 cpu_relax(); 954 955 if (poll_count == -1) 956 dev_err(p->port.dev, "teardown incomplete\n"); 957 } 958 } 959 if (!count) 960 goto out; 961 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 962 963 p->port.icount.rx += ret; 964 p->port.icount.buf_overrun += count - ret; 965 out: 966 967 tty_flip_buffer_push(tty_port); 968 } 969 970 static void __dma_rx_complete(void *param) 971 { 972 struct uart_8250_port *p = param; 973 struct omap8250_priv *priv = p->port.private_data; 974 struct uart_8250_dma *dma = p->dma; 975 struct dma_tx_state state; 976 unsigned long flags; 977 978 /* Synchronize UART_IER access against the console. */ 979 uart_port_lock_irqsave(&p->port, &flags); 980 981 /* 982 * If the tx status is not DMA_COMPLETE, then this is a delayed 983 * completion callback. A previous RX timeout flush would have 984 * already pushed the data, so exit. 985 */ 986 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 987 DMA_COMPLETE) { 988 uart_port_unlock_irqrestore(&p->port, flags); 989 return; 990 } 991 __dma_rx_do_complete(p); 992 if (!priv->throttled) { 993 p->ier |= UART_IER_RLSI | UART_IER_RDI; 994 serial_out(p, UART_IER, p->ier); 995 if (!(priv->habit & UART_HAS_EFR2)) 996 omap_8250_rx_dma(p); 997 } 998 999 uart_port_unlock_irqrestore(&p->port, flags); 1000 } 1001 1002 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 1003 { 1004 struct omap8250_priv *priv = p->port.private_data; 1005 struct uart_8250_dma *dma = p->dma; 1006 struct dma_tx_state state; 1007 unsigned long flags; 1008 int ret; 1009 1010 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1011 1012 if (!dma->rx_running) { 1013 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1014 return; 1015 } 1016 1017 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1018 if (ret == DMA_IN_PROGRESS) { 1019 ret = dmaengine_pause(dma->rxchan); 1020 if (WARN_ON_ONCE(ret)) 1021 priv->rx_dma_broken = true; 1022 } 1023 __dma_rx_do_complete(p); 1024 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1025 } 1026 1027 static int omap_8250_rx_dma(struct uart_8250_port *p) 1028 { 1029 struct omap8250_priv *priv = p->port.private_data; 1030 struct uart_8250_dma *dma = p->dma; 1031 int err = 0; 1032 struct dma_async_tx_descriptor *desc; 1033 unsigned long flags; 1034 u32 reg; 1035 1036 /* Port locked to synchronize UART_IER access against the console. */ 1037 lockdep_assert_held_once(&p->port.lock); 1038 1039 if (priv->rx_dma_broken) 1040 return -EINVAL; 1041 1042 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1043 1044 if (dma->rx_running) { 1045 enum dma_status state; 1046 1047 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1048 if (state == DMA_COMPLETE) { 1049 /* 1050 * Disable RX interrupts to allow RX DMA completion 1051 * callback to run. 1052 */ 1053 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1054 serial_out(p, UART_IER, p->ier); 1055 } 1056 goto out; 1057 } 1058 1059 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1060 dma->rx_size, DMA_DEV_TO_MEM, 1061 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1062 if (!desc) { 1063 err = -EBUSY; 1064 goto out; 1065 } 1066 1067 dma->rx_running = 1; 1068 desc->callback = __dma_rx_complete; 1069 desc->callback_param = p; 1070 1071 dma->rx_cookie = dmaengine_submit(desc); 1072 1073 /* 1074 * Disable RX FIFO interrupt while RX DMA is enabled, else 1075 * spurious interrupt may be raised when data is in the RX FIFO 1076 * but is yet to be drained by DMA. 1077 */ 1078 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1079 reg = serial_in(p, UART_OMAP_IER2); 1080 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1081 serial_out(p, UART_OMAP_IER2, reg); 1082 } 1083 1084 dma_async_issue_pending(dma->rxchan); 1085 out: 1086 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1087 return err; 1088 } 1089 1090 static int omap_8250_tx_dma(struct uart_8250_port *p); 1091 1092 static void omap_8250_dma_tx_complete(void *param) 1093 { 1094 struct uart_8250_port *p = param; 1095 struct uart_8250_dma *dma = p->dma; 1096 struct tty_port *tport = &p->port.state->port; 1097 unsigned long flags; 1098 bool en_thri = false; 1099 struct omap8250_priv *priv = p->port.private_data; 1100 1101 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1102 UART_XMIT_SIZE, DMA_TO_DEVICE); 1103 1104 uart_port_lock_irqsave(&p->port, &flags); 1105 1106 dma->tx_running = 0; 1107 1108 uart_xmit_advance(&p->port, dma->tx_size); 1109 1110 if (priv->delayed_restore) { 1111 priv->delayed_restore = 0; 1112 omap8250_restore_regs(p); 1113 } 1114 1115 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1116 uart_write_wakeup(&p->port); 1117 1118 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1119 int ret; 1120 1121 ret = omap_8250_tx_dma(p); 1122 if (ret) 1123 en_thri = true; 1124 } else if (p->capabilities & UART_CAP_RPM) { 1125 en_thri = true; 1126 } 1127 1128 if (en_thri) { 1129 dma->tx_err = 1; 1130 serial8250_set_THRI(p); 1131 } 1132 1133 uart_port_unlock_irqrestore(&p->port, flags); 1134 } 1135 1136 static int omap_8250_tx_dma(struct uart_8250_port *p) 1137 { 1138 struct uart_8250_dma *dma = p->dma; 1139 struct omap8250_priv *priv = p->port.private_data; 1140 struct tty_port *tport = &p->port.state->port; 1141 struct dma_async_tx_descriptor *desc; 1142 struct scatterlist sg; 1143 int skip_byte = -1; 1144 int ret; 1145 1146 if (dma->tx_running) 1147 return 0; 1148 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1149 1150 /* 1151 * Even if no data, we need to return an error for the two cases 1152 * below so serial8250_tx_chars() is invoked and properly clears 1153 * THRI and/or runtime suspend. 1154 */ 1155 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1156 ret = -EBUSY; 1157 goto err; 1158 } 1159 serial8250_clear_THRI(p); 1160 return 0; 1161 } 1162 1163 sg_init_table(&sg, 1); 1164 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1165 UART_XMIT_SIZE, dma->tx_addr); 1166 if (ret != 1) { 1167 serial8250_clear_THRI(p); 1168 return 0; 1169 } 1170 1171 dma->tx_size = sg_dma_len(&sg); 1172 1173 if (priv->habit & OMAP_DMA_TX_KICK) { 1174 unsigned char c; 1175 u8 tx_lvl; 1176 1177 /* 1178 * We need to put the first byte into the FIFO in order to start 1179 * the DMA transfer. For transfers smaller than four bytes we 1180 * don't bother doing DMA at all. It seem not matter if there 1181 * are still bytes in the FIFO from the last transfer (in case 1182 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1183 * leaving the FIFO seem not to trigger the DMA transfer. It is 1184 * really the byte that we put into the FIFO. 1185 * If the FIFO is already full then we most likely got here from 1186 * omap_8250_dma_tx_complete(). And this means the DMA engine 1187 * just completed its work. We don't have to wait the complete 1188 * 86us at 115200,8n1 but around 60us (not to mention lower 1189 * baudrates). So in that case we take the interrupt and try 1190 * again with an empty FIFO. 1191 */ 1192 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1193 if (tx_lvl == p->tx_loadsz) { 1194 ret = -EBUSY; 1195 goto err; 1196 } 1197 if (dma->tx_size < 4) { 1198 ret = -EINVAL; 1199 goto err; 1200 } 1201 if (!kfifo_get(&tport->xmit_fifo, &c)) { 1202 ret = -EINVAL; 1203 goto err; 1204 } 1205 skip_byte = c; 1206 /* now we need to recompute due to kfifo_get */ 1207 kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, 1208 UART_XMIT_SIZE, dma->tx_addr); 1209 } 1210 1211 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1212 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1213 if (!desc) { 1214 ret = -EBUSY; 1215 goto err; 1216 } 1217 1218 dma->tx_running = 1; 1219 1220 desc->callback = omap_8250_dma_tx_complete; 1221 desc->callback_param = p; 1222 1223 dma->tx_cookie = dmaengine_submit(desc); 1224 1225 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1226 UART_XMIT_SIZE, DMA_TO_DEVICE); 1227 1228 dma_async_issue_pending(dma->txchan); 1229 if (dma->tx_err) 1230 dma->tx_err = 0; 1231 1232 serial8250_clear_THRI(p); 1233 ret = 0; 1234 goto out_skip; 1235 err: 1236 dma->tx_err = 1; 1237 out_skip: 1238 if (skip_byte >= 0) 1239 serial_out(p, UART_TX, skip_byte); 1240 return ret; 1241 } 1242 1243 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1244 { 1245 switch (iir & 0x3f) { 1246 case UART_IIR_RLSI: 1247 case UART_IIR_RX_TIMEOUT: 1248 case UART_IIR_RDI: 1249 omap_8250_rx_dma_flush(up); 1250 return true; 1251 } 1252 return omap_8250_rx_dma(up); 1253 } 1254 1255 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1256 { 1257 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1258 (iir & UART_IIR_RDI)) { 1259 if (handle_rx_dma(up, iir)) { 1260 status = serial8250_rx_chars(up, status); 1261 omap_8250_rx_dma(up); 1262 } 1263 } 1264 1265 return status; 1266 } 1267 1268 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1269 u16 status) 1270 { 1271 /* Port locked to synchronize UART_IER access against the console. */ 1272 lockdep_assert_held_once(&up->port.lock); 1273 1274 /* 1275 * Queue a new transfer if FIFO has data. 1276 */ 1277 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1278 (up->ier & UART_IER_RDI)) { 1279 omap_8250_rx_dma(up); 1280 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1281 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1282 /* 1283 * Disable RX timeout, read IIR to clear 1284 * current timeout condition, clear EFR2 to 1285 * periodic timeouts, re-enable interrupts. 1286 */ 1287 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1288 serial_out(up, UART_IER, up->ier); 1289 omap_8250_rx_dma_flush(up); 1290 serial_in(up, UART_IIR); 1291 serial_out(up, UART_OMAP_EFR2, 0x0); 1292 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1293 serial_out(up, UART_IER, up->ier); 1294 } 1295 } 1296 1297 /* 1298 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1299 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1300 * use the default routine in the non-DMA case and this one for with DMA. 1301 */ 1302 static int omap_8250_dma_handle_irq(struct uart_port *port) 1303 { 1304 struct uart_8250_port *up = up_to_u8250p(port); 1305 struct omap8250_priv *priv = up->port.private_data; 1306 u16 status; 1307 u8 iir; 1308 1309 iir = serial_port_in(port, UART_IIR); 1310 if (iir & UART_IIR_NO_INT) { 1311 return IRQ_HANDLED; 1312 } 1313 1314 uart_port_lock(port); 1315 1316 status = serial_port_in(port, UART_LSR); 1317 1318 if ((iir & 0x3f) != UART_IIR_THRI) { 1319 if (priv->habit & UART_HAS_EFR2) 1320 am654_8250_handle_rx_dma(up, iir, status); 1321 else 1322 status = omap_8250_handle_rx_dma(up, iir, status); 1323 } 1324 1325 serial8250_modem_status(up); 1326 if (status & UART_LSR_THRE && up->dma->tx_err) { 1327 if (uart_tx_stopped(&up->port) || 1328 kfifo_is_empty(&up->port.state->port.xmit_fifo)) { 1329 up->dma->tx_err = 0; 1330 serial8250_tx_chars(up); 1331 } else { 1332 /* 1333 * try again due to an earlier failer which 1334 * might have been resolved by now. 1335 */ 1336 if (omap_8250_tx_dma(up)) 1337 serial8250_tx_chars(up); 1338 } 1339 } 1340 1341 uart_unlock_and_check_sysrq(port); 1342 1343 return 1; 1344 } 1345 1346 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1347 { 1348 return false; 1349 } 1350 1351 #else 1352 1353 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1354 { 1355 return -EINVAL; 1356 } 1357 #endif 1358 1359 static int omap8250_no_handle_irq(struct uart_port *port) 1360 { 1361 /* IRQ has not been requested but handling irq? */ 1362 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1363 return 0; 1364 } 1365 1366 static struct omap8250_dma_params am654_dma = { 1367 .rx_size = SZ_2K, 1368 .rx_trigger = 1, 1369 .tx_trigger = TX_TRIGGER, 1370 }; 1371 1372 static struct omap8250_dma_params am33xx_dma = { 1373 .rx_size = RX_TRIGGER, 1374 .rx_trigger = RX_TRIGGER, 1375 .tx_trigger = TX_TRIGGER, 1376 }; 1377 1378 static struct omap8250_platdata am654_platdata = { 1379 .dma_params = &am654_dma, 1380 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1381 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1382 }; 1383 1384 static struct omap8250_platdata am33xx_platdata = { 1385 .dma_params = &am33xx_dma, 1386 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1387 }; 1388 1389 static struct omap8250_platdata omap4_platdata = { 1390 .dma_params = &am33xx_dma, 1391 .habit = UART_ERRATA_CLOCK_DISABLE, 1392 }; 1393 1394 static const struct of_device_id omap8250_dt_ids[] = { 1395 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1396 { .compatible = "ti,omap2-uart" }, 1397 { .compatible = "ti,omap3-uart" }, 1398 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1399 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1400 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1401 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1402 {}, 1403 }; 1404 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1405 1406 static int omap8250_probe(struct platform_device *pdev) 1407 { 1408 struct device_node *np = pdev->dev.of_node; 1409 struct omap8250_priv *priv; 1410 const struct omap8250_platdata *pdata; 1411 struct uart_8250_port up; 1412 struct resource *regs; 1413 void __iomem *membase; 1414 int ret; 1415 1416 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1417 if (!regs) { 1418 dev_err(&pdev->dev, "missing registers\n"); 1419 return -EINVAL; 1420 } 1421 1422 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1423 if (!priv) 1424 return -ENOMEM; 1425 1426 membase = devm_ioremap(&pdev->dev, regs->start, 1427 resource_size(regs)); 1428 if (!membase) 1429 return -ENODEV; 1430 1431 memset(&up, 0, sizeof(up)); 1432 up.port.dev = &pdev->dev; 1433 up.port.mapbase = regs->start; 1434 up.port.membase = membase; 1435 /* 1436 * It claims to be 16C750 compatible however it is a little different. 1437 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1438 * have) is enabled via EFR instead of MCR. The type is set here 8250 1439 * just to get things going. UNKNOWN does not work for a few reasons and 1440 * we don't need our own type since we don't use 8250's set_termios() 1441 * or pm callback. 1442 */ 1443 up.port.type = PORT_8250; 1444 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1445 up.port.private_data = priv; 1446 1447 up.tx_loadsz = 64; 1448 up.capabilities = UART_CAP_FIFO; 1449 #ifdef CONFIG_PM 1450 /* 1451 * Runtime PM is mostly transparent. However to do it right we need to a 1452 * TX empty interrupt before we can put the device to auto idle. So if 1453 * PM is not enabled we don't add that flag and can spare that one extra 1454 * interrupt in the TX path. 1455 */ 1456 up.capabilities |= UART_CAP_RPM; 1457 #endif 1458 up.port.set_termios = omap_8250_set_termios; 1459 up.port.set_mctrl = omap8250_set_mctrl; 1460 up.port.pm = omap_8250_pm; 1461 up.port.startup = omap_8250_startup; 1462 up.port.shutdown = omap_8250_shutdown; 1463 up.port.throttle = omap_8250_throttle; 1464 up.port.unthrottle = omap_8250_unthrottle; 1465 up.port.rs485_config = omap8250_rs485_config; 1466 /* same rs485_supported for software emulation and native RS485 */ 1467 up.port.rs485_supported = serial8250_em485_supported; 1468 up.rs485_start_tx = serial8250_em485_start_tx; 1469 up.rs485_stop_tx = serial8250_em485_stop_tx; 1470 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1471 1472 ret = uart_read_port_properties(&up.port); 1473 if (ret) 1474 return ret; 1475 1476 up.port.regshift = OMAP_UART_REGSHIFT; 1477 up.port.fifosize = 64; 1478 1479 if (!up.port.uartclk) { 1480 struct clk *clk; 1481 1482 clk = devm_clk_get(&pdev->dev, NULL); 1483 if (IS_ERR(clk)) { 1484 if (PTR_ERR(clk) == -EPROBE_DEFER) 1485 return -EPROBE_DEFER; 1486 } else { 1487 up.port.uartclk = clk_get_rate(clk); 1488 } 1489 } 1490 1491 if (of_property_read_u32(np, "overrun-throttle-ms", 1492 &up.overrun_backoff_time_ms) != 0) 1493 up.overrun_backoff_time_ms = 0; 1494 1495 pdata = of_device_get_match_data(&pdev->dev); 1496 if (pdata) 1497 priv->habit |= pdata->habit; 1498 1499 if (!up.port.uartclk) { 1500 up.port.uartclk = DEFAULT_CLK_SPEED; 1501 dev_warn(&pdev->dev, 1502 "No clock speed specified: using default: %d\n", 1503 DEFAULT_CLK_SPEED); 1504 } 1505 1506 priv->membase = membase; 1507 priv->line = -ENODEV; 1508 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1509 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1510 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1511 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1512 1513 spin_lock_init(&priv->rx_dma_lock); 1514 1515 platform_set_drvdata(pdev, priv); 1516 1517 device_init_wakeup(&pdev->dev, true); 1518 pm_runtime_enable(&pdev->dev); 1519 pm_runtime_use_autosuspend(&pdev->dev); 1520 1521 /* 1522 * Disable runtime PM until autosuspend delay unless specifically 1523 * enabled by the user via sysfs. This is the historic way to 1524 * prevent an unsafe default policy with lossy characters on wake-up. 1525 * For serdev devices this is not needed, the policy can be managed by 1526 * the serdev driver. 1527 */ 1528 if (!of_get_available_child_count(pdev->dev.of_node)) 1529 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1530 1531 pm_runtime_get_sync(&pdev->dev); 1532 1533 omap_serial_fill_features_erratas(&up, priv); 1534 up.port.handle_irq = omap8250_no_handle_irq; 1535 priv->rx_trigger = RX_TRIGGER; 1536 priv->tx_trigger = TX_TRIGGER; 1537 #ifdef CONFIG_SERIAL_8250_DMA 1538 /* 1539 * Oh DMA support. If there are no DMA properties in the DT then 1540 * we will fall back to a generic DMA channel which does not 1541 * really work here. To ensure that we do not get a generic DMA 1542 * channel assigned, we have the the_no_dma_filter_fn() here. 1543 * To avoid "failed to request DMA" messages we check for DMA 1544 * properties in DT. 1545 */ 1546 ret = of_property_count_strings(np, "dma-names"); 1547 if (ret == 2) { 1548 struct omap8250_dma_params *dma_params = NULL; 1549 struct uart_8250_dma *dma = &priv->omap8250_dma; 1550 1551 dma->fn = the_no_dma_filter_fn; 1552 dma->tx_dma = omap_8250_tx_dma; 1553 dma->rx_dma = omap_8250_rx_dma; 1554 if (pdata) 1555 dma_params = pdata->dma_params; 1556 1557 if (dma_params) { 1558 dma->rx_size = dma_params->rx_size; 1559 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1560 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1561 priv->rx_trigger = dma_params->rx_trigger; 1562 priv->tx_trigger = dma_params->tx_trigger; 1563 } else { 1564 dma->rx_size = RX_TRIGGER; 1565 dma->rxconf.src_maxburst = RX_TRIGGER; 1566 dma->txconf.dst_maxburst = TX_TRIGGER; 1567 } 1568 } 1569 #endif 1570 1571 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1572 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1573 dev_name(&pdev->dev), priv); 1574 if (ret < 0) 1575 return ret; 1576 1577 priv->wakeirq = irq_of_parse_and_map(np, 1); 1578 1579 ret = serial8250_register_8250_port(&up); 1580 if (ret < 0) { 1581 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1582 goto err; 1583 } 1584 priv->line = ret; 1585 pm_runtime_mark_last_busy(&pdev->dev); 1586 pm_runtime_put_autosuspend(&pdev->dev); 1587 return 0; 1588 err: 1589 pm_runtime_dont_use_autosuspend(&pdev->dev); 1590 pm_runtime_put_sync(&pdev->dev); 1591 flush_work(&priv->qos_work); 1592 pm_runtime_disable(&pdev->dev); 1593 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1594 return ret; 1595 } 1596 1597 static void omap8250_remove(struct platform_device *pdev) 1598 { 1599 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1600 struct uart_8250_port *up; 1601 int err; 1602 1603 err = pm_runtime_resume_and_get(&pdev->dev); 1604 if (err) 1605 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1606 1607 up = serial8250_get_port(priv->line); 1608 omap_8250_shutdown(&up->port); 1609 serial8250_unregister_port(priv->line); 1610 priv->line = -ENODEV; 1611 pm_runtime_dont_use_autosuspend(&pdev->dev); 1612 pm_runtime_put_sync(&pdev->dev); 1613 flush_work(&priv->qos_work); 1614 pm_runtime_disable(&pdev->dev); 1615 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1616 device_init_wakeup(&pdev->dev, false); 1617 } 1618 1619 static int omap8250_prepare(struct device *dev) 1620 { 1621 struct omap8250_priv *priv = dev_get_drvdata(dev); 1622 1623 if (!priv) 1624 return 0; 1625 priv->is_suspending = true; 1626 return 0; 1627 } 1628 1629 static void omap8250_complete(struct device *dev) 1630 { 1631 struct omap8250_priv *priv = dev_get_drvdata(dev); 1632 1633 if (!priv) 1634 return; 1635 priv->is_suspending = false; 1636 } 1637 1638 static int omap8250_suspend(struct device *dev) 1639 { 1640 struct omap8250_priv *priv = dev_get_drvdata(dev); 1641 struct uart_8250_port *up = serial8250_get_port(priv->line); 1642 struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); 1643 int err = 0; 1644 1645 serial8250_suspend_port(priv->line); 1646 1647 err = pm_runtime_resume_and_get(dev); 1648 if (err) 1649 return err; 1650 if (!device_may_wakeup(dev)) 1651 priv->wer = 0; 1652 serial_out(up, UART_OMAP_WER, priv->wer); 1653 if (uart_console(&up->port)) { 1654 if (console_suspend_enabled) 1655 err = pm_runtime_force_suspend(dev); 1656 else { 1657 /* 1658 * The pd shall not be powered-off (no console suspend). 1659 * Make copy of genpd flags before to set it always on. 1660 * The original value is restored during the resume. 1661 */ 1662 genpd_flags_console = genpd->flags; 1663 genpd->flags |= GENPD_FLAG_ALWAYS_ON; 1664 } 1665 } 1666 flush_work(&priv->qos_work); 1667 1668 return err; 1669 } 1670 1671 static int omap8250_resume(struct device *dev) 1672 { 1673 struct omap8250_priv *priv = dev_get_drvdata(dev); 1674 struct uart_8250_port *up = serial8250_get_port(priv->line); 1675 struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); 1676 int err; 1677 1678 if (uart_console(&up->port) && console_suspend_enabled) { 1679 if (console_suspend_enabled) { 1680 err = pm_runtime_force_resume(dev); 1681 if (err) 1682 return err; 1683 } else 1684 genpd->flags = genpd_flags_console; 1685 } 1686 1687 serial8250_resume_port(priv->line); 1688 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1689 pm_runtime_mark_last_busy(dev); 1690 pm_runtime_put_autosuspend(dev); 1691 1692 return 0; 1693 } 1694 1695 static int omap8250_lost_context(struct uart_8250_port *up) 1696 { 1697 u32 val; 1698 1699 val = serial_in(up, UART_OMAP_SCR); 1700 /* 1701 * If we lose context, then SCR is set to its reset value of zero. 1702 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1703 * among other bits, to never set the register back to zero again. 1704 */ 1705 if (!val) 1706 return 1; 1707 return 0; 1708 } 1709 1710 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1711 { 1712 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1713 } 1714 1715 /* TODO: in future, this should happen via API in drivers/reset/ */ 1716 static int omap8250_soft_reset(struct device *dev) 1717 { 1718 struct omap8250_priv *priv = dev_get_drvdata(dev); 1719 int timeout = 100; 1720 int sysc; 1721 int syss; 1722 1723 /* 1724 * At least on omap4, unused uarts may not idle after reset without 1725 * a basic scr dma configuration even with no dma in use. The 1726 * module clkctrl status bits will be 1 instead of 3 blocking idle 1727 * for the whole clockdomain. The softreset below will clear scr, 1728 * and we restore it on resume so this is safe to do on all SoCs 1729 * needing omap8250_soft_reset() quirk. Do it in two writes as 1730 * recommended in the comment for omap8250_update_scr(). 1731 */ 1732 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1733 uart_write(priv, UART_OMAP_SCR, 1734 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1735 1736 sysc = uart_read(priv, UART_OMAP_SYSC); 1737 1738 /* softreset the UART */ 1739 sysc |= OMAP_UART_SYSC_SOFTRESET; 1740 uart_write(priv, UART_OMAP_SYSC, sysc); 1741 1742 /* By experiments, 1us enough for reset complete on AM335x */ 1743 do { 1744 udelay(1); 1745 syss = uart_read(priv, UART_OMAP_SYSS); 1746 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1747 1748 if (!timeout) { 1749 dev_err(dev, "timed out waiting for reset done\n"); 1750 return -ETIMEDOUT; 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int omap8250_runtime_suspend(struct device *dev) 1757 { 1758 struct omap8250_priv *priv = dev_get_drvdata(dev); 1759 struct uart_8250_port *up = NULL; 1760 1761 if (priv->line >= 0) 1762 up = serial8250_get_port(priv->line); 1763 1764 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1765 int ret; 1766 1767 ret = omap8250_soft_reset(dev); 1768 if (ret) 1769 return ret; 1770 1771 if (up) { 1772 /* Restore to UART mode after reset (for wakeup) */ 1773 omap8250_update_mdr1(up, priv); 1774 /* Restore wakeup enable register */ 1775 serial_out(up, UART_OMAP_WER, priv->wer); 1776 } 1777 } 1778 1779 if (up && up->dma && up->dma->rxchan) 1780 omap_8250_rx_dma_flush(up); 1781 1782 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1783 schedule_work(&priv->qos_work); 1784 atomic_set(&priv->active, 0); 1785 1786 return 0; 1787 } 1788 1789 static int omap8250_runtime_resume(struct device *dev) 1790 { 1791 struct omap8250_priv *priv = dev_get_drvdata(dev); 1792 struct uart_8250_port *up = NULL; 1793 1794 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1795 if (atomic_read(&priv->active)) 1796 return 0; 1797 1798 if (priv->line >= 0) 1799 up = serial8250_get_port(priv->line); 1800 1801 if (up && omap8250_lost_context(up)) { 1802 uart_port_lock_irq(&up->port); 1803 omap8250_restore_regs(up); 1804 uart_port_unlock_irq(&up->port); 1805 } 1806 1807 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1808 uart_port_lock_irq(&up->port); 1809 omap_8250_rx_dma(up); 1810 uart_port_unlock_irq(&up->port); 1811 } 1812 1813 atomic_set(&priv->active, 1); 1814 priv->latency = priv->calc_latency; 1815 schedule_work(&priv->qos_work); 1816 1817 return 0; 1818 } 1819 1820 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1821 static int __init omap8250_console_fixup(void) 1822 { 1823 char *omap_str; 1824 char *options; 1825 u8 idx; 1826 1827 if (strstr(boot_command_line, "console=ttyS")) 1828 /* user set a ttyS based name for the console */ 1829 return 0; 1830 1831 omap_str = strstr(boot_command_line, "console=ttyO"); 1832 if (!omap_str) 1833 /* user did not set ttyO based console, so we don't care */ 1834 return 0; 1835 1836 omap_str += 12; 1837 if ('0' <= *omap_str && *omap_str <= '9') 1838 idx = *omap_str - '0'; 1839 else 1840 return 0; 1841 1842 omap_str++; 1843 if (omap_str[0] == ',') { 1844 omap_str++; 1845 options = omap_str; 1846 } else { 1847 options = NULL; 1848 } 1849 1850 add_preferred_console("ttyS", idx, options); 1851 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1852 idx, idx); 1853 pr_err("This ensures that you still see kernel messages. Please\n"); 1854 pr_err("update your kernel commandline.\n"); 1855 return 0; 1856 } 1857 console_initcall(omap8250_console_fixup); 1858 #endif 1859 1860 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1861 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1862 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1863 omap8250_runtime_resume, NULL) 1864 .prepare = pm_sleep_ptr(omap8250_prepare), 1865 .complete = pm_sleep_ptr(omap8250_complete), 1866 }; 1867 1868 static struct platform_driver omap8250_platform_driver = { 1869 .driver = { 1870 .name = "omap8250", 1871 .pm = pm_ptr(&omap8250_dev_pm_ops), 1872 .of_match_table = omap8250_dt_ids, 1873 }, 1874 .probe = omap8250_probe, 1875 .remove_new = omap8250_remove, 1876 }; 1877 module_platform_driver(omap8250_platform_driver); 1878 1879 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1880 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1881 MODULE_LICENSE("GPL v2"); 1882