1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type Exar chips PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved. 8 */ 9 #include <linux/acpi.h> 10 #include <linux/dmi.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/property.h> 16 #include <linux/serial_core.h> 17 #include <linux/serial_reg.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/tty.h> 21 #include <linux/delay.h> 22 23 #include <asm/byteorder.h> 24 25 #include "8250.h" 26 27 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052 28 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d 29 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c 30 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8 31 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2 32 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db 33 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea 34 35 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 36 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 37 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 38 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 39 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 40 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 41 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 42 43 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 44 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 45 46 #define PCI_SUBDEVICE_ID_USR_2980 0x0128 47 #define PCI_SUBDEVICE_ID_USR_2981 0x0129 48 49 #define UART_EXAR_INT0 0x80 50 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ 51 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ 52 #define UART_EXAR_DVID 0x8d /* Device identification */ 53 54 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */ 55 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */ 56 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */ 57 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ 58 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ 59 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ 60 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ 61 62 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ 63 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ 64 65 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */ 66 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */ 67 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */ 68 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */ 69 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */ 70 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */ 71 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */ 72 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */ 73 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */ 74 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */ 75 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */ 76 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ 77 78 #define UART_EXAR_RS485_DLY(x) ((x) << 4) 79 80 #define UART_EXAR_DLD 0x02 /* Divisor Fractional */ 81 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */ 82 83 /* 84 * IOT2040 MPIO wiring semantics: 85 * 86 * MPIO Port Function 87 * ---- ---- -------- 88 * 0 2 Mode bit 0 89 * 1 2 Mode bit 1 90 * 2 2 Terminate bus 91 * 3 - <reserved> 92 * 4 3 Mode bit 0 93 * 5 3 Mode bit 1 94 * 6 3 Terminate bus 95 * 7 - <reserved> 96 * 8 2 Enable 97 * 9 3 Enable 98 * 10 - Red LED 99 * 11..15 - <unused> 100 */ 101 102 /* IOT2040 MPIOs 0..7 */ 103 #define IOT2040_UART_MODE_RS232 0x01 104 #define IOT2040_UART_MODE_RS485 0x02 105 #define IOT2040_UART_MODE_RS422 0x03 106 #define IOT2040_UART_TERMINATE_BUS 0x04 107 108 #define IOT2040_UART1_MASK 0x0f 109 #define IOT2040_UART2_SHIFT 4 110 111 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */ 112 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */ 113 114 /* IOT2040 MPIOs 8..15 */ 115 #define IOT2040_UARTS_ENABLE 0x03 116 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ 117 118 struct exar8250; 119 120 struct exar8250_platform { 121 int (*rs485_config)(struct uart_port *port, struct ktermios *termios, 122 struct serial_rs485 *rs485); 123 const struct serial_rs485 *rs485_supported; 124 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); 125 void (*unregister_gpio)(struct uart_8250_port *); 126 }; 127 128 /** 129 * struct exar8250_board - board information 130 * @num_ports: number of serial ports 131 * @reg_shift: describes UART register mapping in PCI memory 132 * @setup: quirk run at ->probe() stage 133 * @exit: quirk run at ->remove() stage 134 */ 135 struct exar8250_board { 136 unsigned int num_ports; 137 unsigned int reg_shift; 138 int (*setup)(struct exar8250 *, struct pci_dev *, 139 struct uart_8250_port *, int); 140 void (*exit)(struct pci_dev *pcidev); 141 }; 142 143 struct exar8250 { 144 unsigned int nr; 145 struct exar8250_board *board; 146 void __iomem *virt; 147 int line[]; 148 }; 149 150 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old) 151 { 152 /* 153 * Exar UARTs have a SLEEP register that enables or disables each UART 154 * to enter sleep mode separately. On the XR17V35x the register 155 * is accessible to each UART at the UART_EXAR_SLEEP offset, but 156 * the UART channel may only write to the corresponding bit. 157 */ 158 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0); 159 } 160 161 /* 162 * XR17V35x UARTs have an extra fractional divisor register (DLD) 163 * Calculate divisor with extra 4-bit fractional portion 164 */ 165 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud, 166 unsigned int *frac) 167 { 168 unsigned int quot_16; 169 170 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud); 171 *frac = quot_16 & 0x0f; 172 173 return quot_16 >> 4; 174 } 175 176 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud, 177 unsigned int quot, unsigned int quot_frac) 178 { 179 serial8250_do_set_divisor(p, baud, quot, quot_frac); 180 181 /* Preserve bits not related to baudrate; DLD[7:4]. */ 182 quot_frac |= serial_port_in(p, 0x2) & 0xf0; 183 serial_port_out(p, 0x2, quot_frac); 184 } 185 186 static int xr17v35x_startup(struct uart_port *port) 187 { 188 /* 189 * First enable access to IER [7:5], ISR [5:4], FCR [5:4], 190 * MCR [7:5] and MSR [7:0] 191 */ 192 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB); 193 194 /* 195 * Make sure all interrups are masked until initialization is 196 * complete and the FIFOs are cleared 197 * 198 * Synchronize UART_IER access against the console. 199 */ 200 uart_port_lock_irq(port); 201 serial_port_out(port, UART_IER, 0); 202 uart_port_unlock_irq(port); 203 204 return serial8250_do_startup(port); 205 } 206 207 static void exar_shutdown(struct uart_port *port) 208 { 209 bool tx_complete = false; 210 struct uart_8250_port *up = up_to_u8250p(port); 211 struct circ_buf *xmit = &port->state->xmit; 212 int i = 0; 213 u16 lsr; 214 215 do { 216 lsr = serial_in(up, UART_LSR); 217 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE)) 218 tx_complete = true; 219 else 220 tx_complete = false; 221 usleep_range(1000, 1100); 222 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000); 223 224 serial8250_do_shutdown(port); 225 } 226 227 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev, 228 int idx, unsigned int offset, 229 struct uart_8250_port *port) 230 { 231 const struct exar8250_board *board = priv->board; 232 unsigned int bar = 0; 233 unsigned char status; 234 235 port->port.iotype = UPIO_MEM; 236 port->port.mapbase = pci_resource_start(pcidev, bar) + offset; 237 port->port.membase = priv->virt + offset; 238 port->port.regshift = board->reg_shift; 239 240 /* 241 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled 242 * with when DLAB is set which will cause the device to incorrectly match 243 * and assign port type to PORT_16650. The EFR for this UART is found 244 * at offset 0x09. Instead check the Deice ID (DVID) register 245 * for a 2, 4 or 8 port UART. 246 */ 247 status = readb(port->port.membase + UART_EXAR_DVID); 248 if (status == 0x82 || status == 0x84 || status == 0x88) { 249 port->port.type = PORT_XR17V35X; 250 251 port->port.get_divisor = xr17v35x_get_divisor; 252 port->port.set_divisor = xr17v35x_set_divisor; 253 254 port->port.startup = xr17v35x_startup; 255 } else { 256 port->port.type = PORT_XR17D15X; 257 } 258 259 port->port.pm = exar_pm; 260 port->port.shutdown = exar_shutdown; 261 262 return 0; 263 } 264 265 static int 266 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev, 267 struct uart_8250_port *port, int idx) 268 { 269 unsigned int offset = idx * 0x200; 270 unsigned int baud = 1843200; 271 u8 __iomem *p; 272 int err; 273 274 port->port.uartclk = baud * 16; 275 276 err = default_setup(priv, pcidev, idx, offset, port); 277 if (err) 278 return err; 279 280 p = port->port.membase; 281 282 writeb(0x00, p + UART_EXAR_8XMODE); 283 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 284 writeb(32, p + UART_EXAR_TXTRG); 285 writeb(32, p + UART_EXAR_RXTRG); 286 287 /* 288 * Setup Multipurpose Input/Output pins. 289 */ 290 if (idx == 0) { 291 switch (pcidev->device) { 292 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 293 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 294 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0); 295 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 296 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 297 break; 298 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 299 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 300 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 301 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0); 302 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0); 303 break; 304 } 305 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 306 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 307 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 308 } 309 310 return 0; 311 } 312 313 static int 314 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, 315 struct uart_8250_port *port, int idx) 316 { 317 unsigned int offset = idx * 0x200; 318 unsigned int baud = 1843200; 319 320 port->port.uartclk = baud * 16; 321 return default_setup(priv, pcidev, idx, offset, port); 322 } 323 324 static int 325 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, 326 struct uart_8250_port *port, int idx) 327 { 328 unsigned int offset = idx * 0x200; 329 unsigned int baud = 921600; 330 331 port->port.uartclk = baud * 16; 332 return default_setup(priv, pcidev, idx, offset, port); 333 } 334 335 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p) 336 { 337 /* 338 * The Commtech adapters required the MPIOs to be driven low. The Exar 339 * devices will export them as GPIOs, so we pre-configure them safely 340 * as inputs. 341 */ 342 343 u8 dir = 0x00; 344 345 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) && 346 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) { 347 // Configure GPIO as inputs for Commtech adapters 348 dir = 0xff; 349 } else { 350 // Configure GPIO as outputs for SeaLevel adapters 351 dir = 0x00; 352 } 353 354 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 355 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 356 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 357 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 358 writeb(dir, p + UART_EXAR_MPIOSEL_7_0); 359 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 360 writeb(0x00, p + UART_EXAR_MPIOINT_15_8); 361 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8); 362 writeb(0x00, p + UART_EXAR_MPIO3T_15_8); 363 writeb(0x00, p + UART_EXAR_MPIOINV_15_8); 364 writeb(dir, p + UART_EXAR_MPIOSEL_15_8); 365 writeb(0x00, p + UART_EXAR_MPIOOD_15_8); 366 } 367 368 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev, 369 const struct software_node *node) 370 { 371 struct platform_device *pdev; 372 373 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO); 374 if (!pdev) 375 return NULL; 376 377 pdev->dev.parent = &pcidev->dev; 378 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev)); 379 380 if (device_add_software_node(&pdev->dev, node) < 0 || 381 platform_device_add(pdev) < 0) { 382 platform_device_put(pdev); 383 return NULL; 384 } 385 386 return pdev; 387 } 388 389 static void __xr17v35x_unregister_gpio(struct platform_device *pdev) 390 { 391 device_remove_software_node(&pdev->dev); 392 platform_device_unregister(pdev); 393 } 394 395 static const struct property_entry exar_gpio_properties[] = { 396 PROPERTY_ENTRY_U32("exar,first-pin", 0), 397 PROPERTY_ENTRY_U32("ngpios", 16), 398 { } 399 }; 400 401 static const struct software_node exar_gpio_node = { 402 .properties = exar_gpio_properties, 403 }; 404 405 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port) 406 { 407 if (pcidev->vendor == PCI_VENDOR_ID_EXAR) 408 port->port.private_data = 409 __xr17v35x_register_gpio(pcidev, &exar_gpio_node); 410 411 return 0; 412 } 413 414 static void xr17v35x_unregister_gpio(struct uart_8250_port *port) 415 { 416 if (!port->port.private_data) 417 return; 418 419 __xr17v35x_unregister_gpio(port->port.private_data); 420 port->port.private_data = NULL; 421 } 422 423 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios, 424 struct serial_rs485 *rs485) 425 { 426 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 427 u8 __iomem *p = port->membase; 428 u8 value; 429 430 value = readb(p + UART_EXAR_FCTR); 431 if (is_rs485) 432 value |= UART_FCTR_EXAR_485; 433 else 434 value &= ~UART_FCTR_EXAR_485; 435 436 writeb(value, p + UART_EXAR_FCTR); 437 438 if (is_rs485) 439 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); 440 441 return 0; 442 } 443 444 static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios, 445 struct serial_rs485 *rs485) 446 { 447 u8 __iomem *p = port->membase; 448 u8 old_lcr; 449 u8 efr; 450 u8 dld; 451 int ret; 452 453 ret = generic_rs485_config(port, termios, rs485); 454 if (ret) 455 return ret; 456 457 if (rs485->flags & SER_RS485_ENABLED) { 458 old_lcr = readb(p + UART_LCR); 459 460 /* Set EFR[4]=1 to enable enhanced feature registers */ 461 efr = readb(p + UART_XR_EFR); 462 efr |= UART_EFR_ECB; 463 writeb(efr, p + UART_XR_EFR); 464 465 /* Set MCR to use DTR as Auto-RS485 Enable signal */ 466 writeb(UART_MCR_OUT1, p + UART_MCR); 467 468 /* Set LCR[7]=1 to enable access to DLD register */ 469 writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR); 470 471 /* Set DLD[7]=1 for inverted RS485 Enable logic */ 472 dld = readb(p + UART_EXAR_DLD); 473 dld |= UART_EXAR_DLD_485_POLARITY; 474 writeb(dld, p + UART_EXAR_DLD); 475 476 writeb(old_lcr, p + UART_LCR); 477 } 478 479 return 0; 480 } 481 482 static const struct serial_rs485 generic_rs485_supported = { 483 .flags = SER_RS485_ENABLED, 484 }; 485 486 static const struct exar8250_platform exar8250_default_platform = { 487 .register_gpio = xr17v35x_register_gpio, 488 .unregister_gpio = xr17v35x_unregister_gpio, 489 .rs485_config = generic_rs485_config, 490 .rs485_supported = &generic_rs485_supported, 491 }; 492 493 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios, 494 struct serial_rs485 *rs485) 495 { 496 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 497 u8 __iomem *p = port->membase; 498 u8 mask = IOT2040_UART1_MASK; 499 u8 mode, value; 500 501 if (is_rs485) { 502 if (rs485->flags & SER_RS485_RX_DURING_TX) 503 mode = IOT2040_UART_MODE_RS422; 504 else 505 mode = IOT2040_UART_MODE_RS485; 506 507 if (rs485->flags & SER_RS485_TERMINATE_BUS) 508 mode |= IOT2040_UART_TERMINATE_BUS; 509 } else { 510 mode = IOT2040_UART_MODE_RS232; 511 } 512 513 if (port->line == 3) { 514 mask <<= IOT2040_UART2_SHIFT; 515 mode <<= IOT2040_UART2_SHIFT; 516 } 517 518 value = readb(p + UART_EXAR_MPIOLVL_7_0); 519 value &= ~mask; 520 value |= mode; 521 writeb(value, p + UART_EXAR_MPIOLVL_7_0); 522 523 return generic_rs485_config(port, termios, rs485); 524 } 525 526 static const struct serial_rs485 iot2040_rs485_supported = { 527 .flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS, 528 }; 529 530 static const struct property_entry iot2040_gpio_properties[] = { 531 PROPERTY_ENTRY_U32("exar,first-pin", 10), 532 PROPERTY_ENTRY_U32("ngpios", 1), 533 { } 534 }; 535 536 static const struct software_node iot2040_gpio_node = { 537 .properties = iot2040_gpio_properties, 538 }; 539 540 static int iot2040_register_gpio(struct pci_dev *pcidev, 541 struct uart_8250_port *port) 542 { 543 u8 __iomem *p = port->port.membase; 544 545 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0); 546 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0); 547 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8); 548 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8); 549 550 port->port.private_data = 551 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node); 552 553 return 0; 554 } 555 556 static const struct exar8250_platform iot2040_platform = { 557 .rs485_config = iot2040_rs485_config, 558 .rs485_supported = &iot2040_rs485_supported, 559 .register_gpio = iot2040_register_gpio, 560 .unregister_gpio = xr17v35x_unregister_gpio, 561 }; 562 563 /* 564 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device, 565 * IOT2020 doesn't have. Therefore it is sufficient to match on the common 566 * board name after the device was found. 567 */ 568 static const struct dmi_system_id exar_platforms[] = { 569 { 570 .matches = { 571 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 572 }, 573 .driver_data = (void *)&iot2040_platform, 574 }, 575 {} 576 }; 577 578 static const struct exar8250_platform *exar_get_platform(void) 579 { 580 const struct dmi_system_id *dmi_match; 581 582 dmi_match = dmi_first_match(exar_platforms); 583 if (dmi_match) 584 return dmi_match->driver_data; 585 586 return &exar8250_default_platform; 587 } 588 589 static int 590 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev, 591 struct uart_8250_port *port, int idx) 592 { 593 const struct exar8250_platform *platform = exar_get_platform(); 594 unsigned int offset = idx * 0x400; 595 unsigned int baud = 7812500; 596 u8 __iomem *p; 597 int ret; 598 599 port->port.uartclk = baud * 16; 600 port->port.rs485_config = platform->rs485_config; 601 port->port.rs485_supported = *(platform->rs485_supported); 602 603 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL) 604 port->port.rs485_config = sealevel_rs485_config; 605 606 /* 607 * Setup the UART clock for the devices on expansion slot to 608 * half the clock speed of the main chip (which is 125MHz) 609 */ 610 if (idx >= 8) 611 port->port.uartclk /= 2; 612 613 ret = default_setup(priv, pcidev, idx, offset, port); 614 if (ret) 615 return ret; 616 617 p = port->port.membase; 618 619 writeb(0x00, p + UART_EXAR_8XMODE); 620 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 621 writeb(128, p + UART_EXAR_TXTRG); 622 writeb(128, p + UART_EXAR_RXTRG); 623 624 if (idx == 0) { 625 /* Setup Multipurpose Input/Output pins. */ 626 setup_gpio(pcidev, p); 627 628 ret = platform->register_gpio(pcidev, port); 629 } 630 631 return ret; 632 } 633 634 static void pci_xr17v35x_exit(struct pci_dev *pcidev) 635 { 636 const struct exar8250_platform *platform = exar_get_platform(); 637 struct exar8250 *priv = pci_get_drvdata(pcidev); 638 struct uart_8250_port *port = serial8250_get_port(priv->line[0]); 639 640 platform->unregister_gpio(port); 641 } 642 643 static inline void exar_misc_clear(struct exar8250 *priv) 644 { 645 /* Clear all PCI interrupts by reading INT0. No effect on IIR */ 646 readb(priv->virt + UART_EXAR_INT0); 647 648 /* Clear INT0 for Expansion Interface slave ports, too */ 649 if (priv->board->num_ports > 8) 650 readb(priv->virt + 0x2000 + UART_EXAR_INT0); 651 } 652 653 /* 654 * These Exar UARTs have an extra interrupt indicator that could fire for a 655 * few interrupts that are not presented/cleared through IIR. One of which is 656 * a wakeup interrupt when coming out of sleep. These interrupts are only 657 * cleared by reading global INT0 or INT1 registers as interrupts are 658 * associated with channel 0. The INT[3:0] registers _are_ accessible from each 659 * channel's address space, but for the sake of bus efficiency we register a 660 * dedicated handler at the PCI device level to handle them. 661 */ 662 static irqreturn_t exar_misc_handler(int irq, void *data) 663 { 664 exar_misc_clear(data); 665 666 return IRQ_HANDLED; 667 } 668 669 static int 670 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) 671 { 672 unsigned int nr_ports, i, bar = 0, maxnr; 673 struct exar8250_board *board; 674 struct uart_8250_port uart; 675 struct exar8250 *priv; 676 int rc; 677 678 board = (struct exar8250_board *)ent->driver_data; 679 if (!board) 680 return -EINVAL; 681 682 rc = pcim_enable_device(pcidev); 683 if (rc) 684 return rc; 685 686 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); 687 688 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO) 689 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1); 690 else if (board->num_ports) 691 nr_ports = board->num_ports; 692 else 693 nr_ports = pcidev->device & 0x0f; 694 695 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL); 696 if (!priv) 697 return -ENOMEM; 698 699 priv->board = board; 700 priv->virt = pcim_iomap(pcidev, bar, 0); 701 if (!priv->virt) 702 return -ENOMEM; 703 704 pci_set_master(pcidev); 705 706 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES); 707 if (rc < 0) 708 return rc; 709 710 memset(&uart, 0, sizeof(uart)); 711 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT; 712 uart.port.irq = pci_irq_vector(pcidev, 0); 713 uart.port.dev = &pcidev->dev; 714 715 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler, 716 IRQF_SHARED, "exar_uart", priv); 717 if (rc) 718 return rc; 719 720 /* Clear interrupts */ 721 exar_misc_clear(priv); 722 723 for (i = 0; i < nr_ports && i < maxnr; i++) { 724 rc = board->setup(priv, pcidev, &uart, i); 725 if (rc) { 726 dev_err(&pcidev->dev, "Failed to setup port %u\n", i); 727 break; 728 } 729 730 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 731 uart.port.iobase, uart.port.irq, uart.port.iotype); 732 733 priv->line[i] = serial8250_register_8250_port(&uart); 734 if (priv->line[i] < 0) { 735 dev_err(&pcidev->dev, 736 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 737 uart.port.iobase, uart.port.irq, 738 uart.port.iotype, priv->line[i]); 739 break; 740 } 741 } 742 priv->nr = i; 743 pci_set_drvdata(pcidev, priv); 744 return 0; 745 } 746 747 static void exar_pci_remove(struct pci_dev *pcidev) 748 { 749 struct exar8250 *priv = pci_get_drvdata(pcidev); 750 unsigned int i; 751 752 for (i = 0; i < priv->nr; i++) 753 serial8250_unregister_port(priv->line[i]); 754 755 if (priv->board->exit) 756 priv->board->exit(pcidev); 757 } 758 759 static int __maybe_unused exar_suspend(struct device *dev) 760 { 761 struct pci_dev *pcidev = to_pci_dev(dev); 762 struct exar8250 *priv = pci_get_drvdata(pcidev); 763 unsigned int i; 764 765 for (i = 0; i < priv->nr; i++) 766 if (priv->line[i] >= 0) 767 serial8250_suspend_port(priv->line[i]); 768 769 /* Ensure that every init quirk is properly torn down */ 770 if (priv->board->exit) 771 priv->board->exit(pcidev); 772 773 return 0; 774 } 775 776 static int __maybe_unused exar_resume(struct device *dev) 777 { 778 struct exar8250 *priv = dev_get_drvdata(dev); 779 unsigned int i; 780 781 exar_misc_clear(priv); 782 783 for (i = 0; i < priv->nr; i++) 784 if (priv->line[i] >= 0) 785 serial8250_resume_port(priv->line[i]); 786 787 return 0; 788 } 789 790 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume); 791 792 static const struct exar8250_board pbn_fastcom335_2 = { 793 .num_ports = 2, 794 .setup = pci_fastcom335_setup, 795 }; 796 797 static const struct exar8250_board pbn_fastcom335_4 = { 798 .num_ports = 4, 799 .setup = pci_fastcom335_setup, 800 }; 801 802 static const struct exar8250_board pbn_fastcom335_8 = { 803 .num_ports = 8, 804 .setup = pci_fastcom335_setup, 805 }; 806 807 static const struct exar8250_board pbn_connect = { 808 .setup = pci_connect_tech_setup, 809 }; 810 811 static const struct exar8250_board pbn_exar_ibm_saturn = { 812 .num_ports = 1, 813 .setup = pci_xr17c154_setup, 814 }; 815 816 static const struct exar8250_board pbn_exar_XR17C15x = { 817 .setup = pci_xr17c154_setup, 818 }; 819 820 static const struct exar8250_board pbn_exar_XR17V35x = { 821 .setup = pci_xr17v35x_setup, 822 .exit = pci_xr17v35x_exit, 823 }; 824 825 static const struct exar8250_board pbn_fastcom35x_2 = { 826 .num_ports = 2, 827 .setup = pci_xr17v35x_setup, 828 .exit = pci_xr17v35x_exit, 829 }; 830 831 static const struct exar8250_board pbn_fastcom35x_4 = { 832 .num_ports = 4, 833 .setup = pci_xr17v35x_setup, 834 .exit = pci_xr17v35x_exit, 835 }; 836 837 static const struct exar8250_board pbn_fastcom35x_8 = { 838 .num_ports = 8, 839 .setup = pci_xr17v35x_setup, 840 .exit = pci_xr17v35x_exit, 841 }; 842 843 static const struct exar8250_board pbn_exar_XR17V4358 = { 844 .num_ports = 12, 845 .setup = pci_xr17v35x_setup, 846 .exit = pci_xr17v35x_exit, 847 }; 848 849 static const struct exar8250_board pbn_exar_XR17V8358 = { 850 .num_ports = 16, 851 .setup = pci_xr17v35x_setup, 852 .exit = pci_xr17v35x_exit, 853 }; 854 855 #define CONNECT_DEVICE(devid, sdevid, bd) { \ 856 PCI_DEVICE_SUB( \ 857 PCI_VENDOR_ID_EXAR, \ 858 PCI_DEVICE_ID_EXAR_##devid, \ 859 PCI_SUBVENDOR_ID_CONNECT_TECH, \ 860 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ 861 (kernel_ulong_t)&bd \ 862 } 863 864 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } 865 866 #define IBM_DEVICE(devid, sdevid, bd) { \ 867 PCI_DEVICE_SUB( \ 868 PCI_VENDOR_ID_EXAR, \ 869 PCI_DEVICE_ID_EXAR_##devid, \ 870 PCI_VENDOR_ID_IBM, \ 871 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \ 872 (kernel_ulong_t)&bd \ 873 } 874 875 #define USR_DEVICE(devid, sdevid, bd) { \ 876 PCI_DEVICE_SUB( \ 877 PCI_VENDOR_ID_USR, \ 878 PCI_DEVICE_ID_EXAR_##devid, \ 879 PCI_VENDOR_ID_EXAR, \ 880 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \ 881 (kernel_ulong_t)&bd \ 882 } 883 884 static const struct pci_device_id exar_pci_tbl[] = { 885 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x), 886 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x), 887 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x), 888 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x), 889 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x), 890 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), 891 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), 892 893 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), 894 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), 895 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), 896 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), 897 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), 898 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), 899 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), 900 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), 901 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), 902 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), 903 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), 904 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), 905 906 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), 907 908 /* USRobotics USR298x-OEM PCI Modems */ 909 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x), 910 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x), 911 912 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */ 913 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x), 914 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x), 915 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x), 916 917 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */ 918 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x), 919 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x), 920 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x), 921 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358), 922 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358), 923 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2), 924 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4), 925 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8), 926 927 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2), 928 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4), 929 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4), 930 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8), 931 { 0, } 932 }; 933 MODULE_DEVICE_TABLE(pci, exar_pci_tbl); 934 935 static struct pci_driver exar_pci_driver = { 936 .name = "exar_serial", 937 .probe = exar_pci_probe, 938 .remove = exar_pci_remove, 939 .driver = { 940 .pm = &exar_pci_pm, 941 }, 942 .id_table = exar_pci_tbl, 943 }; 944 module_pci_driver(exar_pci_driver); 945 946 MODULE_LICENSE("GPL"); 947 MODULE_DESCRIPTION("Exar Serial Driver"); 948 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>"); 949