1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Synopsys DesignWare 8250 library. */ 3 4 #include <linux/bitops.h> 5 #include <linux/bitfield.h> 6 #include <linux/delay.h> 7 #include <linux/device.h> 8 #include <linux/kernel.h> 9 #include <linux/math.h> 10 #include <linux/property.h> 11 #include <linux/serial_8250.h> 12 #include <linux/serial_core.h> 13 14 #include "8250_dwlib.h" 15 16 /* Offsets for the DesignWare specific registers */ 17 #define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */ 18 #define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */ 19 #define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */ 20 #define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ 21 #define DW_UART_RAR 0xc4 /* Receive Address Register */ 22 #define DW_UART_TAR 0xc8 /* Transmit Address Register */ 23 #define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */ 24 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 25 #define DW_UART_UCV 0xf8 /* UART Component Version */ 26 27 /* Receive / Transmit Address Register bits */ 28 #define DW_UART_ADDR_MASK GENMASK(7, 0) 29 30 /* Line Status Register bits */ 31 #define DW_UART_LSR_ADDR_RCVD BIT(8) 32 33 /* Transceiver Control Register bits */ 34 #define DW_UART_TCR_RS485_EN BIT(0) 35 #define DW_UART_TCR_RE_POL BIT(1) 36 #define DW_UART_TCR_DE_POL BIT(2) 37 #define DW_UART_TCR_XFER_MODE GENMASK(4, 3) 38 #define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0) 39 #define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1) 40 #define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2) 41 42 /* Line Extended Control Register bits */ 43 #define DW_UART_LCR_EXT_DLS_E BIT(0) 44 #define DW_UART_LCR_EXT_ADDR_MATCH BIT(1) 45 #define DW_UART_LCR_EXT_SEND_ADDR BIT(2) 46 #define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3) 47 48 /* Component Parameter Register bits */ 49 #define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0) 50 #define DW_UART_CPR_AFCE_MODE BIT(4) 51 #define DW_UART_CPR_THRE_MODE BIT(5) 52 #define DW_UART_CPR_SIR_MODE BIT(6) 53 #define DW_UART_CPR_SIR_LP_MODE BIT(7) 54 #define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8) 55 #define DW_UART_CPR_FIFO_ACCESS BIT(9) 56 #define DW_UART_CPR_FIFO_STAT BIT(10) 57 #define DW_UART_CPR_SHADOW BIT(11) 58 #define DW_UART_CPR_ENCODED_PARMS BIT(12) 59 #define DW_UART_CPR_DMA_EXTRA BIT(13) 60 #define DW_UART_CPR_FIFO_MODE GENMASK(23, 16) 61 62 /* Helper for FIFO size calculation */ 63 #define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16) 64 65 /* 66 * divisor = div(I) + div(F) 67 * "I" means integer, "F" means fractional 68 * quot = div(I) = clk / (16 * baud) 69 * frac = div(F) * 2^dlf_size 70 * 71 * let rem = clk % (16 * baud) 72 * we have: div(F) * (16 * baud) = rem 73 * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud) 74 */ 75 static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud, 76 unsigned int *frac) 77 { 78 unsigned int quot, rem, base_baud = baud * 16; 79 struct dw8250_port_data *d = p->private_data; 80 81 quot = p->uartclk / base_baud; 82 rem = p->uartclk % base_baud; 83 *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud); 84 85 return quot; 86 } 87 88 static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, 89 unsigned int quot, unsigned int quot_frac) 90 { 91 dw8250_writel_ext(p, DW_UART_DLF, quot_frac); 92 serial8250_do_set_divisor(p, baud, quot, quot_frac); 93 } 94 95 void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old) 96 { 97 p->status &= ~UPSTAT_AUTOCTS; 98 if (termios->c_cflag & CRTSCTS) 99 p->status |= UPSTAT_AUTOCTS; 100 101 serial8250_do_set_termios(p, termios, old); 102 103 /* Filter addresses which have 9th bit set */ 104 p->ignore_status_mask |= DW_UART_LSR_ADDR_RCVD; 105 p->read_status_mask |= DW_UART_LSR_ADDR_RCVD; 106 } 107 EXPORT_SYMBOL_GPL(dw8250_do_set_termios); 108 109 /* 110 * Wait until re is de-asserted for sure. An ongoing receive will keep 111 * re asserted until end of frame. Without BUSY indication available, 112 * only available course of action is to wait for the time it takes to 113 * receive one frame (there might nothing to receive but w/o BUSY the 114 * driver cannot know). 115 */ 116 static void dw8250_wait_re_deassert(struct uart_port *p) 117 { 118 ndelay(p->frame_time); 119 } 120 121 static void dw8250_update_rar(struct uart_port *p, u32 addr) 122 { 123 u32 re_en = dw8250_readl_ext(p, DW_UART_RE_EN); 124 125 /* 126 * RAR shouldn't be changed while receiving. Thus, de-assert RE_EN 127 * if asserted and wait. 128 */ 129 if (re_en) 130 dw8250_writel_ext(p, DW_UART_RE_EN, 0); 131 dw8250_wait_re_deassert(p); 132 dw8250_writel_ext(p, DW_UART_RAR, addr); 133 if (re_en) 134 dw8250_writel_ext(p, DW_UART_RE_EN, re_en); 135 } 136 137 static void dw8250_rs485_set_addr(struct uart_port *p, struct serial_rs485 *rs485, 138 struct ktermios *termios) 139 { 140 u32 lcr = dw8250_readl_ext(p, DW_UART_LCR_EXT); 141 142 if (rs485->flags & SER_RS485_ADDRB) { 143 lcr |= DW_UART_LCR_EXT_DLS_E; 144 if (termios) 145 termios->c_cflag |= ADDRB; 146 147 if (rs485->flags & SER_RS485_ADDR_RECV) { 148 u32 delta = p->rs485.flags ^ rs485->flags; 149 150 /* 151 * rs485 (param) is equal to uart_port's rs485 only during init 152 * (during init, delta is not yet applicable). 153 */ 154 if (unlikely(&p->rs485 == rs485)) 155 delta = rs485->flags; 156 157 if ((delta & SER_RS485_ADDR_RECV) || 158 (p->rs485.addr_recv != rs485->addr_recv)) 159 dw8250_update_rar(p, rs485->addr_recv); 160 lcr |= DW_UART_LCR_EXT_ADDR_MATCH; 161 } else { 162 lcr &= ~DW_UART_LCR_EXT_ADDR_MATCH; 163 } 164 if (rs485->flags & SER_RS485_ADDR_DEST) { 165 /* 166 * Don't skip writes here as another endpoint could 167 * have changed communication line's destination 168 * address in between. 169 */ 170 dw8250_writel_ext(p, DW_UART_TAR, rs485->addr_dest); 171 lcr |= DW_UART_LCR_EXT_SEND_ADDR; 172 } 173 } else { 174 lcr = 0; 175 } 176 dw8250_writel_ext(p, DW_UART_LCR_EXT, lcr); 177 } 178 179 static int dw8250_rs485_config(struct uart_port *p, struct ktermios *termios, 180 struct serial_rs485 *rs485) 181 { 182 u32 tcr; 183 184 tcr = dw8250_readl_ext(p, DW_UART_TCR); 185 tcr &= ~DW_UART_TCR_XFER_MODE; 186 187 if (rs485->flags & SER_RS485_ENABLED) { 188 tcr |= DW_UART_TCR_RS485_EN; 189 190 if (rs485->flags & SER_RS485_RX_DURING_TX) { 191 tcr |= DW_UART_TCR_XFER_MODE_DE_DURING_RE; 192 } else { 193 /* HW does not support same DE level for tx and rx */ 194 if (!(rs485->flags & SER_RS485_RTS_ON_SEND) == 195 !(rs485->flags & SER_RS485_RTS_AFTER_SEND)) 196 return -EINVAL; 197 198 tcr |= DW_UART_TCR_XFER_MODE_DE_OR_RE; 199 } 200 dw8250_writel_ext(p, DW_UART_DE_EN, 1); 201 dw8250_writel_ext(p, DW_UART_RE_EN, 1); 202 } else { 203 if (termios) 204 termios->c_cflag &= ~ADDRB; 205 206 tcr &= ~DW_UART_TCR_RS485_EN; 207 } 208 209 /* Reset to default polarity */ 210 tcr |= DW_UART_TCR_DE_POL; 211 tcr &= ~DW_UART_TCR_RE_POL; 212 213 if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) 214 tcr &= ~DW_UART_TCR_DE_POL; 215 if (device_property_read_bool(p->dev, "rs485-rx-active-high")) 216 tcr |= DW_UART_TCR_RE_POL; 217 218 dw8250_writel_ext(p, DW_UART_TCR, tcr); 219 220 /* Addressing mode can only be set up after TCR */ 221 if (rs485->flags & SER_RS485_ENABLED) 222 dw8250_rs485_set_addr(p, rs485, termios); 223 224 return 0; 225 } 226 227 /* 228 * Tests if RE_EN register can have non-zero value to see if RS-485 HW support 229 * is present. 230 */ 231 static bool dw8250_detect_rs485_hw(struct uart_port *p) 232 { 233 u32 reg; 234 235 dw8250_writel_ext(p, DW_UART_RE_EN, 1); 236 reg = dw8250_readl_ext(p, DW_UART_RE_EN); 237 dw8250_writel_ext(p, DW_UART_RE_EN, 0); 238 return reg; 239 } 240 241 static const struct serial_rs485 dw8250_rs485_supported = { 242 .flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_RTS_ON_SEND | 243 SER_RS485_RTS_AFTER_SEND | SER_RS485_ADDRB | SER_RS485_ADDR_RECV | 244 SER_RS485_ADDR_DEST, 245 }; 246 247 void dw8250_setup_port(struct uart_port *p) 248 { 249 struct dw8250_port_data *pd = p->private_data; 250 struct dw8250_data *data = to_dw8250_data(pd); 251 struct uart_8250_port *up = up_to_u8250p(p); 252 u32 reg; 253 254 pd->hw_rs485_support = dw8250_detect_rs485_hw(p); 255 if (pd->hw_rs485_support) { 256 p->rs485_config = dw8250_rs485_config; 257 up->lsr_save_mask = LSR_SAVE_FLAGS | DW_UART_LSR_ADDR_RCVD; 258 p->rs485_supported = &dw8250_rs485_supported; 259 } else { 260 p->rs485_config = serial8250_em485_config; 261 p->rs485_supported = &serial8250_em485_supported; 262 up->rs485_start_tx = serial8250_em485_start_tx; 263 up->rs485_stop_tx = serial8250_em485_stop_tx; 264 } 265 up->capabilities |= UART_CAP_NOTEMT; 266 267 /* 268 * If the Component Version Register returns zero, we know that 269 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 270 */ 271 reg = dw8250_readl_ext(p, DW_UART_UCV); 272 if (!reg) 273 return; 274 275 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", 276 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 277 278 dw8250_writel_ext(p, DW_UART_DLF, ~0U); 279 reg = dw8250_readl_ext(p, DW_UART_DLF); 280 dw8250_writel_ext(p, DW_UART_DLF, 0); 281 282 if (reg) { 283 pd->dlf_size = fls(reg); 284 p->get_divisor = dw8250_get_divisor; 285 p->set_divisor = dw8250_set_divisor; 286 } 287 288 reg = dw8250_readl_ext(p, DW_UART_CPR); 289 if (!reg) { 290 reg = data->pdata->cpr_val; 291 dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg); 292 } 293 if (!reg) 294 return; 295 296 /* Select the type based on FIFO */ 297 if (reg & DW_UART_CPR_FIFO_MODE) { 298 p->type = PORT_16550A; 299 p->flags |= UPF_FIXED_TYPE; 300 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 301 up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT; 302 } 303 304 if (reg & DW_UART_CPR_AFCE_MODE) 305 up->capabilities |= UART_CAP_AFE; 306 307 if (reg & DW_UART_CPR_SIR_MODE) 308 up->capabilities |= UART_CAP_IRDA; 309 } 310 EXPORT_SYMBOL_GPL(dw8250_setup_port); 311