1 /* 2 * Synopsys DesignWare 8250 driver. 3 * 4 * Copyright 2011 Picochip, Jamie Iles. 5 * Copyright 2013 Intel Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 13 * LCR is written whilst busy. If it is, then a busy detect interrupt is 14 * raised, the LCR needs to be rewritten and the uart status register read. 15 */ 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/serial_8250.h> 20 #include <linux/serial_core.h> 21 #include <linux/serial_reg.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/acpi.h> 28 #include <linux/clk.h> 29 #include <linux/reset.h> 30 #include <linux/pm_runtime.h> 31 32 #include <asm/byteorder.h> 33 34 #include "8250.h" 35 36 /* Offsets for the DesignWare specific registers */ 37 #define DW_UART_USR 0x1f /* UART Status Register */ 38 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 39 #define DW_UART_UCV 0xf8 /* UART Component Version */ 40 41 /* Component Parameter Register bits */ 42 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 43 #define DW_UART_CPR_AFCE_MODE (1 << 4) 44 #define DW_UART_CPR_THRE_MODE (1 << 5) 45 #define DW_UART_CPR_SIR_MODE (1 << 6) 46 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 48 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 49 #define DW_UART_CPR_FIFO_STAT (1 << 10) 50 #define DW_UART_CPR_SHADOW (1 << 11) 51 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 52 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 53 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 54 /* Helper for fifo size calculation */ 55 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 56 57 58 struct dw8250_data { 59 u8 usr_reg; 60 int last_mcr; 61 int line; 62 struct clk *clk; 63 struct clk *pclk; 64 struct reset_control *rst; 65 struct uart_8250_dma dma; 66 }; 67 68 #define BYT_PRV_CLK 0x800 69 #define BYT_PRV_CLK_EN (1 << 0) 70 #define BYT_PRV_CLK_M_VAL_SHIFT 1 71 #define BYT_PRV_CLK_N_VAL_SHIFT 16 72 #define BYT_PRV_CLK_UPDATE (1 << 31) 73 74 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 75 { 76 struct dw8250_data *d = p->private_data; 77 78 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */ 79 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) { 80 value |= UART_MSR_CTS; 81 value &= ~UART_MSR_DCTS; 82 } 83 84 return value; 85 } 86 87 static void dw8250_force_idle(struct uart_port *p) 88 { 89 struct uart_8250_port *up = up_to_u8250p(p); 90 91 serial8250_clear_and_reinit_fifos(up); 92 (void)p->serial_in(p, UART_RX); 93 } 94 95 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 96 { 97 struct dw8250_data *d = p->private_data; 98 99 if (offset == UART_MCR) 100 d->last_mcr = value; 101 102 writeb(value, p->membase + (offset << p->regshift)); 103 104 /* Make sure LCR write wasn't ignored */ 105 if (offset == UART_LCR) { 106 int tries = 1000; 107 while (tries--) { 108 unsigned int lcr = p->serial_in(p, UART_LCR); 109 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 110 return; 111 dw8250_force_idle(p); 112 writeb(value, p->membase + (UART_LCR << p->regshift)); 113 } 114 dev_err(p->dev, "Couldn't set LCR to %d\n", value); 115 } 116 } 117 118 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 119 { 120 unsigned int value = readb(p->membase + (offset << p->regshift)); 121 122 return dw8250_modify_msr(p, offset, value); 123 } 124 125 /* Read Back (rb) version to ensure register access ording. */ 126 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value) 127 { 128 dw8250_serial_out(p, offset, value); 129 dw8250_serial_in(p, UART_LCR); 130 } 131 132 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 133 { 134 struct dw8250_data *d = p->private_data; 135 136 if (offset == UART_MCR) 137 d->last_mcr = value; 138 139 writel(value, p->membase + (offset << p->regshift)); 140 141 /* Make sure LCR write wasn't ignored */ 142 if (offset == UART_LCR) { 143 int tries = 1000; 144 while (tries--) { 145 unsigned int lcr = p->serial_in(p, UART_LCR); 146 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 147 return; 148 dw8250_force_idle(p); 149 writel(value, p->membase + (UART_LCR << p->regshift)); 150 } 151 dev_err(p->dev, "Couldn't set LCR to %d\n", value); 152 } 153 } 154 155 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 156 { 157 unsigned int value = readl(p->membase + (offset << p->regshift)); 158 159 return dw8250_modify_msr(p, offset, value); 160 } 161 162 static int dw8250_handle_irq(struct uart_port *p) 163 { 164 struct dw8250_data *d = p->private_data; 165 unsigned int iir = p->serial_in(p, UART_IIR); 166 167 if (serial8250_handle_irq(p, iir)) { 168 return 1; 169 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 170 /* Clear the USR */ 171 (void)p->serial_in(p, d->usr_reg); 172 173 return 1; 174 } 175 176 return 0; 177 } 178 179 static void 180 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 181 { 182 if (!state) 183 pm_runtime_get_sync(port->dev); 184 185 serial8250_do_pm(port, state, old); 186 187 if (state) 188 pm_runtime_put_sync_suspend(port->dev); 189 } 190 191 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 192 struct ktermios *old) 193 { 194 unsigned int baud = tty_termios_baud_rate(termios); 195 struct dw8250_data *d = p->private_data; 196 unsigned int rate; 197 int ret; 198 199 if (IS_ERR(d->clk) || !old) 200 goto out; 201 202 /* Not requesting clock rates below 1.8432Mhz */ 203 if (baud < 115200) 204 baud = 115200; 205 206 clk_disable_unprepare(d->clk); 207 rate = clk_round_rate(d->clk, baud * 16); 208 ret = clk_set_rate(d->clk, rate); 209 clk_prepare_enable(d->clk); 210 211 if (!ret) 212 p->uartclk = rate; 213 out: 214 serial8250_do_set_termios(p, termios, old); 215 } 216 217 static bool dw8250_dma_filter(struct dma_chan *chan, void *param) 218 { 219 struct dw8250_data *data = param; 220 221 return chan->chan_id == data->dma.tx_chan_id || 222 chan->chan_id == data->dma.rx_chan_id; 223 } 224 225 static void dw8250_setup_port(struct uart_8250_port *up) 226 { 227 struct uart_port *p = &up->port; 228 u32 reg = readl(p->membase + DW_UART_UCV); 229 230 /* 231 * If the Component Version Register returns zero, we know that 232 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 233 */ 234 if (!reg) 235 return; 236 237 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n", 238 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 239 240 reg = readl(p->membase + DW_UART_CPR); 241 if (!reg) 242 return; 243 244 /* Select the type based on fifo */ 245 if (reg & DW_UART_CPR_FIFO_MODE) { 246 p->type = PORT_16550A; 247 p->flags |= UPF_FIXED_TYPE; 248 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 249 up->tx_loadsz = p->fifosize; 250 up->capabilities = UART_CAP_FIFO; 251 } 252 253 if (reg & DW_UART_CPR_AFCE_MODE) 254 up->capabilities |= UART_CAP_AFE; 255 } 256 257 static int dw8250_probe_of(struct uart_port *p, 258 struct dw8250_data *data) 259 { 260 struct device_node *np = p->dev->of_node; 261 struct uart_8250_port *up = up_to_u8250p(p); 262 u32 val; 263 bool has_ucv = true; 264 265 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 266 #ifdef __BIG_ENDIAN 267 /* 268 * Low order bits of these 64-bit registers, when 269 * accessed as a byte, are 7 bytes further down in the 270 * address space in big endian mode. 271 */ 272 p->membase += 7; 273 #endif 274 p->serial_out = dw8250_serial_out_rb; 275 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 276 p->type = PORT_OCTEON; 277 data->usr_reg = 0x27; 278 has_ucv = false; 279 } else if (!of_property_read_u32(np, "reg-io-width", &val)) { 280 switch (val) { 281 case 1: 282 break; 283 case 4: 284 p->iotype = UPIO_MEM32; 285 p->serial_in = dw8250_serial_in32; 286 p->serial_out = dw8250_serial_out32; 287 break; 288 default: 289 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val); 290 return -EINVAL; 291 } 292 } 293 if (has_ucv) 294 dw8250_setup_port(up); 295 296 if (!of_property_read_u32(np, "reg-shift", &val)) 297 p->regshift = val; 298 299 /* clock got configured through clk api, all done */ 300 if (p->uartclk) 301 return 0; 302 303 /* try to find out clock frequency from DT as fallback */ 304 if (of_property_read_u32(np, "clock-frequency", &val)) { 305 dev_err(p->dev, "clk or clock-frequency not defined\n"); 306 return -EINVAL; 307 } 308 p->uartclk = val; 309 310 return 0; 311 } 312 313 static int dw8250_probe_acpi(struct uart_8250_port *up, 314 struct dw8250_data *data) 315 { 316 struct uart_port *p = &up->port; 317 318 dw8250_setup_port(up); 319 320 p->iotype = UPIO_MEM32; 321 p->serial_in = dw8250_serial_in32; 322 p->serial_out = dw8250_serial_out32; 323 p->regshift = 2; 324 325 up->dma = &data->dma; 326 327 up->dma->rxconf.src_maxburst = p->fifosize / 4; 328 up->dma->txconf.dst_maxburst = p->fifosize / 4; 329 330 up->port.set_termios = dw8250_set_termios; 331 332 return 0; 333 } 334 335 static int dw8250_probe(struct platform_device *pdev) 336 { 337 struct uart_8250_port uart = {}; 338 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 339 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 340 struct dw8250_data *data; 341 int err; 342 343 if (!regs || !irq) { 344 dev_err(&pdev->dev, "no registers/irq defined\n"); 345 return -EINVAL; 346 } 347 348 spin_lock_init(&uart.port.lock); 349 uart.port.mapbase = regs->start; 350 uart.port.irq = irq->start; 351 uart.port.handle_irq = dw8250_handle_irq; 352 uart.port.pm = dw8250_do_pm; 353 uart.port.type = PORT_8250; 354 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; 355 uart.port.dev = &pdev->dev; 356 357 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, 358 resource_size(regs)); 359 if (!uart.port.membase) 360 return -ENOMEM; 361 362 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 363 if (!data) 364 return -ENOMEM; 365 366 data->usr_reg = DW_UART_USR; 367 data->clk = devm_clk_get(&pdev->dev, "baudclk"); 368 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 369 data->clk = devm_clk_get(&pdev->dev, NULL); 370 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 371 return -EPROBE_DEFER; 372 if (!IS_ERR(data->clk)) { 373 err = clk_prepare_enable(data->clk); 374 if (err) 375 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n", 376 err); 377 else 378 uart.port.uartclk = clk_get_rate(data->clk); 379 } 380 381 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 382 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) { 383 err = -EPROBE_DEFER; 384 goto err_clk; 385 } 386 if (!IS_ERR(data->pclk)) { 387 err = clk_prepare_enable(data->pclk); 388 if (err) { 389 dev_err(&pdev->dev, "could not enable apb_pclk\n"); 390 goto err_clk; 391 } 392 } 393 394 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL); 395 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) { 396 err = -EPROBE_DEFER; 397 goto err_pclk; 398 } 399 if (!IS_ERR(data->rst)) 400 reset_control_deassert(data->rst); 401 402 data->dma.rx_chan_id = -1; 403 data->dma.tx_chan_id = -1; 404 data->dma.rx_param = data; 405 data->dma.tx_param = data; 406 data->dma.fn = dw8250_dma_filter; 407 408 uart.port.iotype = UPIO_MEM; 409 uart.port.serial_in = dw8250_serial_in; 410 uart.port.serial_out = dw8250_serial_out; 411 uart.port.private_data = data; 412 413 if (pdev->dev.of_node) { 414 err = dw8250_probe_of(&uart.port, data); 415 if (err) 416 goto err_reset; 417 } else if (ACPI_HANDLE(&pdev->dev)) { 418 err = dw8250_probe_acpi(&uart, data); 419 if (err) 420 goto err_reset; 421 } else { 422 err = -ENODEV; 423 goto err_reset; 424 } 425 426 data->line = serial8250_register_8250_port(&uart); 427 if (data->line < 0) { 428 err = data->line; 429 goto err_reset; 430 } 431 432 platform_set_drvdata(pdev, data); 433 434 pm_runtime_set_active(&pdev->dev); 435 pm_runtime_enable(&pdev->dev); 436 437 return 0; 438 439 err_reset: 440 if (!IS_ERR(data->rst)) 441 reset_control_assert(data->rst); 442 443 err_pclk: 444 if (!IS_ERR(data->pclk)) 445 clk_disable_unprepare(data->pclk); 446 447 err_clk: 448 if (!IS_ERR(data->clk)) 449 clk_disable_unprepare(data->clk); 450 451 return err; 452 } 453 454 static int dw8250_remove(struct platform_device *pdev) 455 { 456 struct dw8250_data *data = platform_get_drvdata(pdev); 457 458 pm_runtime_get_sync(&pdev->dev); 459 460 serial8250_unregister_port(data->line); 461 462 if (!IS_ERR(data->rst)) 463 reset_control_assert(data->rst); 464 465 if (!IS_ERR(data->pclk)) 466 clk_disable_unprepare(data->pclk); 467 468 if (!IS_ERR(data->clk)) 469 clk_disable_unprepare(data->clk); 470 471 pm_runtime_disable(&pdev->dev); 472 pm_runtime_put_noidle(&pdev->dev); 473 474 return 0; 475 } 476 477 #ifdef CONFIG_PM_SLEEP 478 static int dw8250_suspend(struct device *dev) 479 { 480 struct dw8250_data *data = dev_get_drvdata(dev); 481 482 serial8250_suspend_port(data->line); 483 484 return 0; 485 } 486 487 static int dw8250_resume(struct device *dev) 488 { 489 struct dw8250_data *data = dev_get_drvdata(dev); 490 491 serial8250_resume_port(data->line); 492 493 return 0; 494 } 495 #endif /* CONFIG_PM_SLEEP */ 496 497 #ifdef CONFIG_PM_RUNTIME 498 static int dw8250_runtime_suspend(struct device *dev) 499 { 500 struct dw8250_data *data = dev_get_drvdata(dev); 501 502 if (!IS_ERR(data->clk)) 503 clk_disable_unprepare(data->clk); 504 505 if (!IS_ERR(data->pclk)) 506 clk_disable_unprepare(data->pclk); 507 508 return 0; 509 } 510 511 static int dw8250_runtime_resume(struct device *dev) 512 { 513 struct dw8250_data *data = dev_get_drvdata(dev); 514 515 if (!IS_ERR(data->pclk)) 516 clk_prepare_enable(data->pclk); 517 518 if (!IS_ERR(data->clk)) 519 clk_prepare_enable(data->clk); 520 521 return 0; 522 } 523 #endif 524 525 static const struct dev_pm_ops dw8250_pm_ops = { 526 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 527 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 528 }; 529 530 static const struct of_device_id dw8250_of_match[] = { 531 { .compatible = "snps,dw-apb-uart" }, 532 { .compatible = "cavium,octeon-3860-uart" }, 533 { /* Sentinel */ } 534 }; 535 MODULE_DEVICE_TABLE(of, dw8250_of_match); 536 537 static const struct acpi_device_id dw8250_acpi_match[] = { 538 { "INT33C4", 0 }, 539 { "INT33C5", 0 }, 540 { "INT3434", 0 }, 541 { "INT3435", 0 }, 542 { "80860F0A", 0 }, 543 { "8086228A", 0 }, 544 { }, 545 }; 546 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 547 548 static struct platform_driver dw8250_platform_driver = { 549 .driver = { 550 .name = "dw-apb-uart", 551 .owner = THIS_MODULE, 552 .pm = &dw8250_pm_ops, 553 .of_match_table = dw8250_of_match, 554 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 555 }, 556 .probe = dw8250_probe, 557 .remove = dw8250_remove, 558 }; 559 560 module_platform_driver(dw8250_platform_driver); 561 562 MODULE_AUTHOR("Jamie Iles"); 563 MODULE_LICENSE("GPL"); 564 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 565