1 /* 2 * Synopsys DesignWare 8250 driver. 3 * 4 * Copyright 2011 Picochip, Jamie Iles. 5 * Copyright 2013 Intel Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 13 * LCR is written whilst busy. If it is, then a busy detect interrupt is 14 * raised, the LCR needs to be rewritten and the uart status register read. 15 */ 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/serial_8250.h> 20 #include <linux/serial_reg.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 #include <linux/acpi.h> 27 #include <linux/clk.h> 28 #include <linux/reset.h> 29 #include <linux/pm_runtime.h> 30 31 #include <asm/byteorder.h> 32 33 #include "8250.h" 34 35 /* Offsets for the DesignWare specific registers */ 36 #define DW_UART_USR 0x1f /* UART Status Register */ 37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 38 #define DW_UART_UCV 0xf8 /* UART Component Version */ 39 40 /* Component Parameter Register bits */ 41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 42 #define DW_UART_CPR_AFCE_MODE (1 << 4) 43 #define DW_UART_CPR_THRE_MODE (1 << 5) 44 #define DW_UART_CPR_SIR_MODE (1 << 6) 45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 48 #define DW_UART_CPR_FIFO_STAT (1 << 10) 49 #define DW_UART_CPR_SHADOW (1 << 11) 50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 51 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 52 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 53 /* Helper for fifo size calculation */ 54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 55 56 57 struct dw8250_data { 58 u8 usr_reg; 59 int line; 60 int msr_mask_on; 61 int msr_mask_off; 62 struct clk *clk; 63 struct clk *pclk; 64 struct reset_control *rst; 65 struct uart_8250_dma dma; 66 }; 67 68 #define BYT_PRV_CLK 0x800 69 #define BYT_PRV_CLK_EN (1 << 0) 70 #define BYT_PRV_CLK_M_VAL_SHIFT 1 71 #define BYT_PRV_CLK_N_VAL_SHIFT 16 72 #define BYT_PRV_CLK_UPDATE (1 << 31) 73 74 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 75 { 76 struct dw8250_data *d = p->private_data; 77 78 /* Override any modem control signals if needed */ 79 if (offset == UART_MSR) { 80 value |= d->msr_mask_on; 81 value &= ~d->msr_mask_off; 82 } 83 84 return value; 85 } 86 87 static void dw8250_force_idle(struct uart_port *p) 88 { 89 struct uart_8250_port *up = up_to_u8250p(p); 90 91 serial8250_clear_and_reinit_fifos(up); 92 (void)p->serial_in(p, UART_RX); 93 } 94 95 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 96 { 97 writeb(value, p->membase + (offset << p->regshift)); 98 99 /* Make sure LCR write wasn't ignored */ 100 if (offset == UART_LCR) { 101 int tries = 1000; 102 while (tries--) { 103 unsigned int lcr = p->serial_in(p, UART_LCR); 104 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 105 return; 106 dw8250_force_idle(p); 107 writeb(value, p->membase + (UART_LCR << p->regshift)); 108 } 109 /* 110 * FIXME: this deadlocks if port->lock is already held 111 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 112 */ 113 } 114 } 115 116 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 117 { 118 unsigned int value = readb(p->membase + (offset << p->regshift)); 119 120 return dw8250_modify_msr(p, offset, value); 121 } 122 123 #ifdef CONFIG_64BIT 124 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 125 { 126 unsigned int value; 127 128 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 129 130 return dw8250_modify_msr(p, offset, value); 131 } 132 133 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 134 { 135 value &= 0xff; 136 __raw_writeq(value, p->membase + (offset << p->regshift)); 137 /* Read back to ensure register write ordering. */ 138 __raw_readq(p->membase + (UART_LCR << p->regshift)); 139 140 /* Make sure LCR write wasn't ignored */ 141 if (offset == UART_LCR) { 142 int tries = 1000; 143 while (tries--) { 144 unsigned int lcr = p->serial_in(p, UART_LCR); 145 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 146 return; 147 dw8250_force_idle(p); 148 __raw_writeq(value & 0xff, 149 p->membase + (UART_LCR << p->regshift)); 150 } 151 /* 152 * FIXME: this deadlocks if port->lock is already held 153 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 154 */ 155 } 156 } 157 #endif /* CONFIG_64BIT */ 158 159 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 160 { 161 writel(value, p->membase + (offset << p->regshift)); 162 163 /* Make sure LCR write wasn't ignored */ 164 if (offset == UART_LCR) { 165 int tries = 1000; 166 while (tries--) { 167 unsigned int lcr = p->serial_in(p, UART_LCR); 168 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 169 return; 170 dw8250_force_idle(p); 171 writel(value, p->membase + (UART_LCR << p->regshift)); 172 } 173 /* 174 * FIXME: this deadlocks if port->lock is already held 175 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 176 */ 177 } 178 } 179 180 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 181 { 182 unsigned int value = readl(p->membase + (offset << p->regshift)); 183 184 return dw8250_modify_msr(p, offset, value); 185 } 186 187 static int dw8250_handle_irq(struct uart_port *p) 188 { 189 struct dw8250_data *d = p->private_data; 190 unsigned int iir = p->serial_in(p, UART_IIR); 191 192 if (serial8250_handle_irq(p, iir)) { 193 return 1; 194 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 195 /* Clear the USR */ 196 (void)p->serial_in(p, d->usr_reg); 197 198 return 1; 199 } 200 201 return 0; 202 } 203 204 static void 205 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 206 { 207 if (!state) 208 pm_runtime_get_sync(port->dev); 209 210 serial8250_do_pm(port, state, old); 211 212 if (state) 213 pm_runtime_put_sync_suspend(port->dev); 214 } 215 216 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 217 struct ktermios *old) 218 { 219 unsigned int baud = tty_termios_baud_rate(termios); 220 struct dw8250_data *d = p->private_data; 221 unsigned int rate; 222 int ret; 223 224 if (IS_ERR(d->clk) || !old) 225 goto out; 226 227 clk_disable_unprepare(d->clk); 228 rate = clk_round_rate(d->clk, baud * 16); 229 ret = clk_set_rate(d->clk, rate); 230 clk_prepare_enable(d->clk); 231 232 if (!ret) 233 p->uartclk = rate; 234 235 p->status &= ~UPSTAT_AUTOCTS; 236 if (termios->c_cflag & CRTSCTS) 237 p->status |= UPSTAT_AUTOCTS; 238 239 out: 240 serial8250_do_set_termios(p, termios, old); 241 } 242 243 static bool dw8250_dma_filter(struct dma_chan *chan, void *param) 244 { 245 return false; 246 } 247 248 static void dw8250_setup_port(struct uart_8250_port *up) 249 { 250 struct uart_port *p = &up->port; 251 u32 reg = readl(p->membase + DW_UART_UCV); 252 253 /* 254 * If the Component Version Register returns zero, we know that 255 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 256 */ 257 if (!reg) 258 return; 259 260 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n", 261 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 262 263 reg = readl(p->membase + DW_UART_CPR); 264 if (!reg) 265 return; 266 267 /* Select the type based on fifo */ 268 if (reg & DW_UART_CPR_FIFO_MODE) { 269 p->type = PORT_16550A; 270 p->flags |= UPF_FIXED_TYPE; 271 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 272 up->tx_loadsz = p->fifosize; 273 up->capabilities = UART_CAP_FIFO; 274 } 275 276 if (reg & DW_UART_CPR_AFCE_MODE) 277 up->capabilities |= UART_CAP_AFE; 278 } 279 280 static int dw8250_probe_of(struct uart_port *p, 281 struct dw8250_data *data) 282 { 283 struct device_node *np = p->dev->of_node; 284 struct uart_8250_port *up = up_to_u8250p(p); 285 u32 val; 286 bool has_ucv = true; 287 int id; 288 289 #ifdef CONFIG_64BIT 290 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 291 p->serial_in = dw8250_serial_inq; 292 p->serial_out = dw8250_serial_outq; 293 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 294 p->type = PORT_OCTEON; 295 data->usr_reg = 0x27; 296 has_ucv = false; 297 } else 298 #endif 299 if (!of_property_read_u32(np, "reg-io-width", &val)) { 300 switch (val) { 301 case 1: 302 break; 303 case 4: 304 p->iotype = UPIO_MEM32; 305 p->serial_in = dw8250_serial_in32; 306 p->serial_out = dw8250_serial_out32; 307 break; 308 default: 309 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val); 310 return -EINVAL; 311 } 312 } 313 if (has_ucv) 314 dw8250_setup_port(up); 315 316 /* if we have a valid fifosize, try hooking up DMA here */ 317 if (p->fifosize) { 318 up->dma = &data->dma; 319 320 up->dma->rxconf.src_maxburst = p->fifosize / 4; 321 up->dma->txconf.dst_maxburst = p->fifosize / 4; 322 } 323 324 if (!of_property_read_u32(np, "reg-shift", &val)) 325 p->regshift = val; 326 327 /* get index of serial line, if found in DT aliases */ 328 id = of_alias_get_id(np, "serial"); 329 if (id >= 0) 330 p->line = id; 331 332 if (of_property_read_bool(np, "dcd-override")) { 333 /* Always report DCD as active */ 334 data->msr_mask_on |= UART_MSR_DCD; 335 data->msr_mask_off |= UART_MSR_DDCD; 336 } 337 338 if (of_property_read_bool(np, "dsr-override")) { 339 /* Always report DSR as active */ 340 data->msr_mask_on |= UART_MSR_DSR; 341 data->msr_mask_off |= UART_MSR_DDSR; 342 } 343 344 if (of_property_read_bool(np, "cts-override")) { 345 /* Always report CTS as active */ 346 data->msr_mask_on |= UART_MSR_CTS; 347 data->msr_mask_off |= UART_MSR_DCTS; 348 } 349 350 if (of_property_read_bool(np, "ri-override")) { 351 /* Always report Ring indicator as inactive */ 352 data->msr_mask_off |= UART_MSR_RI; 353 data->msr_mask_off |= UART_MSR_TERI; 354 } 355 356 return 0; 357 } 358 359 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 360 { 361 struct device *dev = param; 362 363 if (dev != chan->device->dev->parent) 364 return false; 365 366 return true; 367 } 368 369 static int dw8250_probe_acpi(struct uart_8250_port *up, 370 struct dw8250_data *data) 371 { 372 struct uart_port *p = &up->port; 373 374 dw8250_setup_port(up); 375 376 p->iotype = UPIO_MEM32; 377 p->serial_in = dw8250_serial_in32; 378 p->serial_out = dw8250_serial_out32; 379 p->regshift = 2; 380 381 /* Platforms with iDMA */ 382 if (platform_get_resource_byname(to_platform_device(up->port.dev), 383 IORESOURCE_MEM, "lpss_priv")) { 384 data->dma.rx_param = up->port.dev->parent; 385 data->dma.tx_param = up->port.dev->parent; 386 data->dma.fn = dw8250_idma_filter; 387 } 388 389 up->dma = &data->dma; 390 up->dma->rxconf.src_maxburst = p->fifosize / 4; 391 up->dma->txconf.dst_maxburst = p->fifosize / 4; 392 393 up->port.set_termios = dw8250_set_termios; 394 395 return 0; 396 } 397 398 static int dw8250_probe(struct platform_device *pdev) 399 { 400 struct uart_8250_port uart = {}; 401 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 402 int irq = platform_get_irq(pdev, 0); 403 struct dw8250_data *data; 404 int err; 405 406 if (!regs) { 407 dev_err(&pdev->dev, "no registers defined\n"); 408 return -EINVAL; 409 } 410 411 if (irq < 0) { 412 if (irq != -EPROBE_DEFER) 413 dev_err(&pdev->dev, "cannot get irq\n"); 414 return irq; 415 } 416 417 spin_lock_init(&uart.port.lock); 418 uart.port.mapbase = regs->start; 419 uart.port.irq = irq; 420 uart.port.handle_irq = dw8250_handle_irq; 421 uart.port.pm = dw8250_do_pm; 422 uart.port.type = PORT_8250; 423 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; 424 uart.port.dev = &pdev->dev; 425 426 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, 427 resource_size(regs)); 428 if (!uart.port.membase) 429 return -ENOMEM; 430 431 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 432 if (!data) 433 return -ENOMEM; 434 435 data->usr_reg = DW_UART_USR; 436 437 /* Always ask for fixed clock rate from a property. */ 438 device_property_read_u32(&pdev->dev, "clock-frequency", 439 &uart.port.uartclk); 440 441 /* If there is separate baudclk, get the rate from it. */ 442 data->clk = devm_clk_get(&pdev->dev, "baudclk"); 443 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 444 data->clk = devm_clk_get(&pdev->dev, NULL); 445 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 446 return -EPROBE_DEFER; 447 if (!IS_ERR_OR_NULL(data->clk)) { 448 err = clk_prepare_enable(data->clk); 449 if (err) 450 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n", 451 err); 452 else 453 uart.port.uartclk = clk_get_rate(data->clk); 454 } 455 456 /* If no clock rate is defined, fail. */ 457 if (!uart.port.uartclk) { 458 dev_err(&pdev->dev, "clock rate not defined\n"); 459 return -EINVAL; 460 } 461 462 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 463 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) { 464 err = -EPROBE_DEFER; 465 goto err_clk; 466 } 467 if (!IS_ERR(data->pclk)) { 468 err = clk_prepare_enable(data->pclk); 469 if (err) { 470 dev_err(&pdev->dev, "could not enable apb_pclk\n"); 471 goto err_clk; 472 } 473 } 474 475 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL); 476 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) { 477 err = -EPROBE_DEFER; 478 goto err_pclk; 479 } 480 if (!IS_ERR(data->rst)) 481 reset_control_deassert(data->rst); 482 483 data->dma.rx_param = data; 484 data->dma.tx_param = data; 485 data->dma.fn = dw8250_dma_filter; 486 487 uart.port.iotype = UPIO_MEM; 488 uart.port.serial_in = dw8250_serial_in; 489 uart.port.serial_out = dw8250_serial_out; 490 uart.port.private_data = data; 491 492 if (pdev->dev.of_node) { 493 err = dw8250_probe_of(&uart.port, data); 494 if (err) 495 goto err_reset; 496 } else if (ACPI_HANDLE(&pdev->dev)) { 497 err = dw8250_probe_acpi(&uart, data); 498 if (err) 499 goto err_reset; 500 } else { 501 err = -ENODEV; 502 goto err_reset; 503 } 504 505 data->line = serial8250_register_8250_port(&uart); 506 if (data->line < 0) { 507 err = data->line; 508 goto err_reset; 509 } 510 511 platform_set_drvdata(pdev, data); 512 513 pm_runtime_set_active(&pdev->dev); 514 pm_runtime_enable(&pdev->dev); 515 516 return 0; 517 518 err_reset: 519 if (!IS_ERR(data->rst)) 520 reset_control_assert(data->rst); 521 522 err_pclk: 523 if (!IS_ERR(data->pclk)) 524 clk_disable_unprepare(data->pclk); 525 526 err_clk: 527 if (!IS_ERR(data->clk)) 528 clk_disable_unprepare(data->clk); 529 530 return err; 531 } 532 533 static int dw8250_remove(struct platform_device *pdev) 534 { 535 struct dw8250_data *data = platform_get_drvdata(pdev); 536 537 pm_runtime_get_sync(&pdev->dev); 538 539 serial8250_unregister_port(data->line); 540 541 if (!IS_ERR(data->rst)) 542 reset_control_assert(data->rst); 543 544 if (!IS_ERR(data->pclk)) 545 clk_disable_unprepare(data->pclk); 546 547 if (!IS_ERR(data->clk)) 548 clk_disable_unprepare(data->clk); 549 550 pm_runtime_disable(&pdev->dev); 551 pm_runtime_put_noidle(&pdev->dev); 552 553 return 0; 554 } 555 556 #ifdef CONFIG_PM_SLEEP 557 static int dw8250_suspend(struct device *dev) 558 { 559 struct dw8250_data *data = dev_get_drvdata(dev); 560 561 serial8250_suspend_port(data->line); 562 563 return 0; 564 } 565 566 static int dw8250_resume(struct device *dev) 567 { 568 struct dw8250_data *data = dev_get_drvdata(dev); 569 570 serial8250_resume_port(data->line); 571 572 return 0; 573 } 574 #endif /* CONFIG_PM_SLEEP */ 575 576 #ifdef CONFIG_PM 577 static int dw8250_runtime_suspend(struct device *dev) 578 { 579 struct dw8250_data *data = dev_get_drvdata(dev); 580 581 if (!IS_ERR(data->clk)) 582 clk_disable_unprepare(data->clk); 583 584 if (!IS_ERR(data->pclk)) 585 clk_disable_unprepare(data->pclk); 586 587 return 0; 588 } 589 590 static int dw8250_runtime_resume(struct device *dev) 591 { 592 struct dw8250_data *data = dev_get_drvdata(dev); 593 594 if (!IS_ERR(data->pclk)) 595 clk_prepare_enable(data->pclk); 596 597 if (!IS_ERR(data->clk)) 598 clk_prepare_enable(data->clk); 599 600 return 0; 601 } 602 #endif 603 604 static const struct dev_pm_ops dw8250_pm_ops = { 605 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 606 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 607 }; 608 609 static const struct of_device_id dw8250_of_match[] = { 610 { .compatible = "snps,dw-apb-uart" }, 611 { .compatible = "cavium,octeon-3860-uart" }, 612 { /* Sentinel */ } 613 }; 614 MODULE_DEVICE_TABLE(of, dw8250_of_match); 615 616 static const struct acpi_device_id dw8250_acpi_match[] = { 617 { "INT33C4", 0 }, 618 { "INT33C5", 0 }, 619 { "INT3434", 0 }, 620 { "INT3435", 0 }, 621 { "80860F0A", 0 }, 622 { "8086228A", 0 }, 623 { "APMC0D08", 0}, 624 { "AMD0020", 0 }, 625 { }, 626 }; 627 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 628 629 static struct platform_driver dw8250_platform_driver = { 630 .driver = { 631 .name = "dw-apb-uart", 632 .pm = &dw8250_pm_ops, 633 .of_match_table = dw8250_of_match, 634 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 635 }, 636 .probe = dw8250_probe, 637 .remove = dw8250_remove, 638 }; 639 640 module_platform_driver(dw8250_platform_driver); 641 642 MODULE_AUTHOR("Jamie Iles"); 643 MODULE_LICENSE("GPL"); 644 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 645 MODULE_ALIAS("platform:dw-apb-uart"); 646