1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 8250_dma.c - DMA Engine API support for 8250.c 4 * 5 * Copyright (C) 2013 Intel Corporation 6 */ 7 #include <linux/tty.h> 8 #include <linux/tty_flip.h> 9 #include <linux/serial_reg.h> 10 #include <linux/dma-mapping.h> 11 12 #include "8250.h" 13 14 static void __dma_tx_complete(void *param) 15 { 16 struct uart_8250_port *p = param; 17 struct uart_8250_dma *dma = p->dma; 18 struct tty_port *tport = &p->port.state->port; 19 unsigned long flags; 20 int ret; 21 22 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 23 UART_XMIT_SIZE, DMA_TO_DEVICE); 24 25 uart_port_lock_irqsave(&p->port, &flags); 26 27 dma->tx_running = 0; 28 29 uart_xmit_advance(&p->port, dma->tx_size); 30 31 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 32 uart_write_wakeup(&p->port); 33 34 ret = serial8250_tx_dma(p); 35 if (ret || !dma->tx_running) 36 serial8250_set_THRI(p); 37 38 uart_port_unlock_irqrestore(&p->port, flags); 39 } 40 41 static void __dma_rx_complete(struct uart_8250_port *p) 42 { 43 struct uart_8250_dma *dma = p->dma; 44 struct tty_port *tty_port = &p->port.state->port; 45 struct dma_tx_state state; 46 enum dma_status dma_status; 47 int count; 48 49 /* 50 * New DMA Rx can be started during the completion handler before it 51 * could acquire port's lock and it might still be ongoing. Don't to 52 * anything in such case. 53 */ 54 dma_status = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 55 if (dma_status == DMA_IN_PROGRESS) 56 return; 57 58 count = dma->rx_size - state.residue; 59 60 tty_insert_flip_string(tty_port, dma->rx_buf, count); 61 p->port.icount.rx += count; 62 dma->rx_running = 0; 63 64 tty_flip_buffer_push(tty_port); 65 } 66 67 static void dma_rx_complete(void *param) 68 { 69 struct uart_8250_port *p = param; 70 struct uart_8250_dma *dma = p->dma; 71 unsigned long flags; 72 73 uart_port_lock_irqsave(&p->port, &flags); 74 if (dma->rx_running) 75 __dma_rx_complete(p); 76 77 /* 78 * Cannot be combined with the previous check because __dma_rx_complete() 79 * changes dma->rx_running. 80 */ 81 if (!dma->rx_running && (serial_lsr_in(p) & UART_LSR_DR)) 82 p->dma->rx_dma(p); 83 uart_port_unlock_irqrestore(&p->port, flags); 84 } 85 86 int serial8250_tx_dma(struct uart_8250_port *p) 87 { 88 struct uart_8250_dma *dma = p->dma; 89 struct tty_port *tport = &p->port.state->port; 90 struct dma_async_tx_descriptor *desc; 91 struct uart_port *up = &p->port; 92 struct scatterlist *sg; 93 struct scatterlist sgl[2]; 94 int i; 95 int ret; 96 97 if (dma->tx_running) { 98 if (up->x_char) { 99 dmaengine_pause(dma->txchan); 100 uart_xchar_out(up, UART_TX); 101 dmaengine_resume(dma->txchan); 102 } 103 return 0; 104 } else if (up->x_char) { 105 uart_xchar_out(up, UART_TX); 106 } 107 108 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 109 /* We have been called from __dma_tx_complete() */ 110 return 0; 111 } 112 113 serial8250_do_prepare_tx_dma(p); 114 115 sg_init_table(sgl, ARRAY_SIZE(sgl)); 116 117 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, sgl, ARRAY_SIZE(sgl), 118 UART_XMIT_SIZE, dma->tx_addr); 119 120 dma->tx_size = 0; 121 122 for_each_sg(sgl, sg, ret, i) 123 dma->tx_size += sg_dma_len(sg); 124 125 desc = dmaengine_prep_slave_sg(dma->txchan, sgl, ret, 126 DMA_MEM_TO_DEV, 127 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 128 if (!desc) { 129 ret = -EBUSY; 130 goto err; 131 } 132 133 dma->tx_running = 1; 134 desc->callback = __dma_tx_complete; 135 desc->callback_param = p; 136 137 dma->tx_cookie = dmaengine_submit(desc); 138 139 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 140 UART_XMIT_SIZE, DMA_TO_DEVICE); 141 142 dma_async_issue_pending(dma->txchan); 143 serial8250_clear_THRI(p); 144 dma->tx_err = 0; 145 146 return 0; 147 err: 148 dma->tx_err = 1; 149 return ret; 150 } 151 152 void serial8250_tx_dma_flush(struct uart_8250_port *p) 153 { 154 struct uart_8250_dma *dma = p->dma; 155 156 if (!dma->tx_running) 157 return; 158 159 /* 160 * kfifo_reset() has been called by the serial core, avoid 161 * advancing and underflowing in __dma_tx_complete(). 162 */ 163 dma->tx_size = 0; 164 165 /* 166 * We can't use `dmaengine_terminate_sync` because `uart_flush_buffer` is 167 * holding the uart port spinlock. 168 */ 169 dmaengine_terminate_async(dma->txchan); 170 171 /* 172 * The callback might or might not run. If it doesn't run, we need to ensure 173 * that `tx_running` is cleared so that we can schedule new transactions. 174 * If it does run, then the zombie callback will clear `tx_running` again 175 * and perform a no-op since `tx_size` was cleared above. 176 * 177 * In either case, we ASSUME the DMA transaction will terminate before we 178 * issue a new `serial8250_tx_dma`. 179 */ 180 dma->tx_running = 0; 181 } 182 183 int serial8250_rx_dma(struct uart_8250_port *p) 184 { 185 struct uart_8250_dma *dma = p->dma; 186 struct dma_async_tx_descriptor *desc; 187 188 if (dma->rx_running) 189 return 0; 190 191 serial8250_do_prepare_rx_dma(p); 192 193 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 194 dma->rx_size, DMA_DEV_TO_MEM, 195 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 196 if (!desc) 197 return -EBUSY; 198 199 dma->rx_running = 1; 200 desc->callback = dma_rx_complete; 201 desc->callback_param = p; 202 203 dma->rx_cookie = dmaengine_submit(desc); 204 205 dma_async_issue_pending(dma->rxchan); 206 207 return 0; 208 } 209 210 void serial8250_rx_dma_flush(struct uart_8250_port *p) 211 { 212 struct uart_8250_dma *dma = p->dma; 213 214 if (dma->rx_running) { 215 dmaengine_pause(dma->rxchan); 216 __dma_rx_complete(p); 217 dmaengine_terminate_async(dma->rxchan); 218 } 219 } 220 EXPORT_SYMBOL_GPL(serial8250_rx_dma_flush); 221 222 int serial8250_request_dma(struct uart_8250_port *p) 223 { 224 struct uart_8250_dma *dma = p->dma; 225 phys_addr_t rx_dma_addr = dma->rx_dma_addr ? 226 dma->rx_dma_addr : p->port.mapbase; 227 phys_addr_t tx_dma_addr = dma->tx_dma_addr ? 228 dma->tx_dma_addr : p->port.mapbase; 229 dma_cap_mask_t mask; 230 struct dma_slave_caps caps; 231 int ret; 232 233 /* Default slave configuration parameters */ 234 dma->rxconf.direction = DMA_DEV_TO_MEM; 235 dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 236 dma->rxconf.src_addr = rx_dma_addr + UART_RX; 237 238 dma->txconf.direction = DMA_MEM_TO_DEV; 239 dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 240 dma->txconf.dst_addr = tx_dma_addr + UART_TX; 241 242 dma_cap_zero(mask); 243 dma_cap_set(DMA_SLAVE, mask); 244 245 /* Get a channel for RX */ 246 dma->rxchan = dma_request_slave_channel_compat(mask, 247 dma->fn, dma->rx_param, 248 p->port.dev, "rx"); 249 if (!dma->rxchan) 250 return -ENODEV; 251 252 /* 8250 rx dma requires dmaengine driver to support pause/terminate */ 253 ret = dma_get_slave_caps(dma->rxchan, &caps); 254 if (ret) 255 goto release_rx; 256 if (!caps.cmd_pause || !caps.cmd_terminate || 257 caps.residue_granularity == DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { 258 ret = -EINVAL; 259 goto release_rx; 260 } 261 262 dmaengine_slave_config(dma->rxchan, &dma->rxconf); 263 264 /* Get a channel for TX */ 265 dma->txchan = dma_request_slave_channel_compat(mask, 266 dma->fn, dma->tx_param, 267 p->port.dev, "tx"); 268 if (!dma->txchan) { 269 ret = -ENODEV; 270 goto release_rx; 271 } 272 273 /* 8250 tx dma requires dmaengine driver to support terminate */ 274 ret = dma_get_slave_caps(dma->txchan, &caps); 275 if (ret) 276 goto err; 277 if (!caps.cmd_terminate) { 278 ret = -EINVAL; 279 goto err; 280 } 281 282 dmaengine_slave_config(dma->txchan, &dma->txconf); 283 284 /* RX buffer */ 285 if (!dma->rx_size) 286 dma->rx_size = PAGE_SIZE; 287 288 dma->rx_buf = dma_alloc_coherent(dma->rxchan->device->dev, dma->rx_size, 289 &dma->rx_addr, GFP_KERNEL); 290 if (!dma->rx_buf) { 291 ret = -ENOMEM; 292 goto err; 293 } 294 295 /* TX buffer */ 296 dma->tx_addr = dma_map_single(dma->txchan->device->dev, 297 p->port.state->port.xmit_buf, 298 UART_XMIT_SIZE, 299 DMA_TO_DEVICE); 300 if (dma_mapping_error(dma->txchan->device->dev, dma->tx_addr)) { 301 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, 302 dma->rx_buf, dma->rx_addr); 303 ret = -ENOMEM; 304 goto err; 305 } 306 307 dev_dbg_ratelimited(p->port.dev, "got both dma channels\n"); 308 309 return 0; 310 err: 311 dma_release_channel(dma->txchan); 312 release_rx: 313 dma_release_channel(dma->rxchan); 314 return ret; 315 } 316 EXPORT_SYMBOL_GPL(serial8250_request_dma); 317 318 void serial8250_release_dma(struct uart_8250_port *p) 319 { 320 struct uart_8250_dma *dma = p->dma; 321 322 if (!dma) 323 return; 324 325 /* Release RX resources */ 326 dmaengine_terminate_sync(dma->rxchan); 327 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, dma->rx_buf, 328 dma->rx_addr); 329 dma_release_channel(dma->rxchan); 330 dma->rxchan = NULL; 331 332 /* Release TX resources */ 333 dmaengine_terminate_sync(dma->txchan); 334 dma_unmap_single(dma->txchan->device->dev, dma->tx_addr, 335 UART_XMIT_SIZE, DMA_TO_DEVICE); 336 dma_release_channel(dma->txchan); 337 dma->txchan = NULL; 338 dma->tx_running = 0; 339 340 dev_dbg_ratelimited(p->port.dev, "dma channels released\n"); 341 } 342 EXPORT_SYMBOL_GPL(serial8250_release_dma); 343