1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Serial port driver for BCM2835AUX UART 4 * 5 * Copyright (C) 2016 Martin Sperl <kernel@martin.sperl.org> 6 * 7 * Based on 8250_lpc18xx.c: 8 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com> 9 * 10 * The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't 11 * take advantage of it yet. When adding support, be sure not to enable it 12 * simultaneously to rs485. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/console.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/property.h> 22 23 #include "8250.h" 24 25 #define BCM2835_AUX_UART_CNTL 8 26 #define BCM2835_AUX_UART_CNTL_RXEN 0x01 /* Receiver enable */ 27 #define BCM2835_AUX_UART_CNTL_TXEN 0x02 /* Transmitter enable */ 28 #define BCM2835_AUX_UART_CNTL_AUTORTS 0x04 /* RTS set by RX fill level */ 29 #define BCM2835_AUX_UART_CNTL_AUTOCTS 0x08 /* CTS stops transmitter */ 30 #define BCM2835_AUX_UART_CNTL_RTS3 0x00 /* RTS set until 3 chars left */ 31 #define BCM2835_AUX_UART_CNTL_RTS2 0x10 /* RTS set until 2 chars left */ 32 #define BCM2835_AUX_UART_CNTL_RTS1 0x20 /* RTS set until 1 chars left */ 33 #define BCM2835_AUX_UART_CNTL_RTS4 0x30 /* RTS set until 4 chars left */ 34 #define BCM2835_AUX_UART_CNTL_RTSINV 0x40 /* Invert auto RTS polarity */ 35 #define BCM2835_AUX_UART_CNTL_CTSINV 0x80 /* Invert auto CTS polarity */ 36 37 /** 38 * struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART 39 * @clk: clock producer of the port's uartclk 40 * @line: index of the port's serial8250_ports[] entry 41 * @cntl: cached copy of CNTL register 42 */ 43 struct bcm2835aux_data { 44 struct clk *clk; 45 int line; 46 u32 cntl; 47 }; 48 49 static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up) 50 { 51 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) { 52 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev); 53 54 data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN; 55 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl); 56 } 57 58 /* 59 * On the bcm2835aux, the MCR register contains no other 60 * flags besides RTS. So no need for a read-modify-write. 61 */ 62 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) 63 serial8250_out_MCR(up, 0); 64 else 65 serial8250_out_MCR(up, UART_MCR_RTS); 66 } 67 68 static void bcm2835aux_rs485_stop_tx(struct uart_8250_port *up) 69 { 70 if (up->port.rs485.flags & SER_RS485_RTS_AFTER_SEND) 71 serial8250_out_MCR(up, 0); 72 else 73 serial8250_out_MCR(up, UART_MCR_RTS); 74 75 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) { 76 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev); 77 78 data->cntl |= BCM2835_AUX_UART_CNTL_RXEN; 79 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl); 80 } 81 } 82 83 static int bcm2835aux_serial_probe(struct platform_device *pdev) 84 { 85 const struct software_node *bcm2835_swnode; 86 struct uart_8250_port up = { }; 87 struct bcm2835aux_data *data; 88 struct resource *res; 89 unsigned int uartclk; 90 int ret; 91 92 /* allocate the custom structure */ 93 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 94 if (!data) 95 return -ENOMEM; 96 97 /* initialize data */ 98 up.capabilities = UART_CAP_FIFO | UART_CAP_MINI; 99 up.port.dev = &pdev->dev; 100 up.port.type = PORT_16550; 101 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SKIP_TEST | UPF_IOREMAP; 102 up.port.rs485_config = serial8250_em485_config; 103 up.port.rs485_supported = serial8250_em485_supported; 104 up.rs485_start_tx = bcm2835aux_rs485_start_tx; 105 up.rs485_stop_tx = bcm2835aux_rs485_stop_tx; 106 107 /* initialize cached copy with power-on reset value */ 108 data->cntl = BCM2835_AUX_UART_CNTL_RXEN | BCM2835_AUX_UART_CNTL_TXEN; 109 110 platform_set_drvdata(pdev, data); 111 112 /* get the clock - this also enables the HW */ 113 data->clk = devm_clk_get_optional(&pdev->dev, NULL); 114 if (IS_ERR(data->clk)) 115 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk), "could not get clk\n"); 116 117 /* map the main registers */ 118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 119 if (!res) { 120 dev_err(&pdev->dev, "memory resource not found"); 121 return -EINVAL; 122 } 123 124 up.port.mapbase = res->start; 125 up.port.mapsize = resource_size(res); 126 127 bcm2835_swnode = device_get_match_data(&pdev->dev); 128 if (bcm2835_swnode) { 129 ret = device_add_software_node(&pdev->dev, bcm2835_swnode); 130 if (ret) 131 return ret; 132 } 133 134 ret = uart_read_port_properties(&up.port); 135 if (ret) 136 goto rm_swnode; 137 138 up.port.regshift = 2; 139 up.port.fifosize = 8; 140 141 /* enable the clock as a last step */ 142 ret = clk_prepare_enable(data->clk); 143 if (ret) { 144 dev_err_probe(&pdev->dev, ret, "unable to enable uart clock\n"); 145 goto rm_swnode; 146 } 147 148 uartclk = clk_get_rate(data->clk); 149 if (uartclk) 150 up.port.uartclk = uartclk; 151 152 /* the HW-clock divider for bcm2835aux is 8, 153 * but 8250 expects a divider of 16, 154 * so we have to multiply the actual clock by 2 155 * to get identical baudrates. 156 */ 157 up.port.uartclk *= 2; 158 159 /* register the port */ 160 ret = serial8250_register_8250_port(&up); 161 if (ret < 0) { 162 dev_err_probe(&pdev->dev, ret, "unable to register 8250 port\n"); 163 goto dis_clk; 164 } 165 data->line = ret; 166 167 return 0; 168 169 dis_clk: 170 clk_disable_unprepare(data->clk); 171 rm_swnode: 172 device_remove_software_node(&pdev->dev); 173 return ret; 174 } 175 176 static void bcm2835aux_serial_remove(struct platform_device *pdev) 177 { 178 struct bcm2835aux_data *data = platform_get_drvdata(pdev); 179 180 serial8250_unregister_port(data->line); 181 clk_disable_unprepare(data->clk); 182 device_remove_software_node(&pdev->dev); 183 } 184 185 /* 186 * Some UEFI implementations (e.g. tianocore/edk2 for the Raspberry Pi) 187 * describe the miniuart with a base address that encompasses the auxiliary 188 * registers shared between the miniuart and spi. 189 * 190 * This is due to historical reasons, see discussion here: 191 * https://edk2.groups.io/g/devel/topic/87501357#84349 192 * 193 * We need to add the offset between the miniuart and auxiliary registers 194 * to get the real miniuart base address. 195 */ 196 static const struct property_entry bcm2835_acpi_properties[] = { 197 PROPERTY_ENTRY_U32("reg-offset", 0x40), 198 { } 199 }; 200 201 static const struct software_node bcm2835_acpi_node = { 202 .properties = bcm2835_acpi_properties, 203 }; 204 205 static const struct of_device_id bcm2835aux_serial_match[] = { 206 { .compatible = "brcm,bcm2835-aux-uart" }, 207 { }, 208 }; 209 MODULE_DEVICE_TABLE(of, bcm2835aux_serial_match); 210 211 static const struct acpi_device_id bcm2835aux_serial_acpi_match[] = { 212 { "BCM2836", (kernel_ulong_t)&bcm2835_acpi_node }, 213 { } 214 }; 215 MODULE_DEVICE_TABLE(acpi, bcm2835aux_serial_acpi_match); 216 217 static bool bcm2835aux_can_disable_clock(struct device *dev) 218 { 219 struct bcm2835aux_data *data = dev_get_drvdata(dev); 220 struct uart_8250_port *up = serial8250_get_port(data->line); 221 222 if (device_may_wakeup(dev)) 223 return false; 224 225 if (uart_console(&up->port) && !console_suspend_enabled) 226 return false; 227 228 return true; 229 } 230 231 static int bcm2835aux_suspend(struct device *dev) 232 { 233 struct bcm2835aux_data *data = dev_get_drvdata(dev); 234 235 serial8250_suspend_port(data->line); 236 237 if (!bcm2835aux_can_disable_clock(dev)) 238 return 0; 239 240 clk_disable_unprepare(data->clk); 241 return 0; 242 } 243 244 static int bcm2835aux_resume(struct device *dev) 245 { 246 struct bcm2835aux_data *data = dev_get_drvdata(dev); 247 int ret; 248 249 if (bcm2835aux_can_disable_clock(dev)) { 250 ret = clk_prepare_enable(data->clk); 251 if (ret) 252 return ret; 253 } 254 255 serial8250_resume_port(data->line); 256 257 return 0; 258 } 259 260 static DEFINE_SIMPLE_DEV_PM_OPS(bcm2835aux_dev_pm_ops, bcm2835aux_suspend, bcm2835aux_resume); 261 262 static struct platform_driver bcm2835aux_serial_driver = { 263 .driver = { 264 .name = "bcm2835-aux-uart", 265 .of_match_table = bcm2835aux_serial_match, 266 .acpi_match_table = bcm2835aux_serial_acpi_match, 267 .pm = pm_ptr(&bcm2835aux_dev_pm_ops), 268 }, 269 .probe = bcm2835aux_serial_probe, 270 .remove_new = bcm2835aux_serial_remove, 271 }; 272 module_platform_driver(bcm2835aux_serial_driver); 273 274 #ifdef CONFIG_SERIAL_8250_CONSOLE 275 276 static int __init early_bcm2835aux_setup(struct earlycon_device *device, 277 const char *options) 278 { 279 if (!device->port.membase) 280 return -ENODEV; 281 282 device->port.iotype = UPIO_MEM32; 283 device->port.regshift = 2; 284 285 return early_serial8250_setup(device, NULL); 286 } 287 288 OF_EARLYCON_DECLARE(bcm2835aux, "brcm,bcm2835-aux-uart", 289 early_bcm2835aux_setup); 290 #endif 291 292 MODULE_DESCRIPTION("BCM2835 auxiliar UART driver"); 293 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); 294 MODULE_LICENSE("GPL v2"); 295