1 /* 2 * Driver for 8250/16550-type serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/serial_8250.h> 15 #include <linux/serial_reg.h> 16 #include <linux/dmaengine.h> 17 18 #include "../serial_mctrl_gpio.h" 19 20 struct uart_8250_dma { 21 int (*tx_dma)(struct uart_8250_port *p); 22 int (*rx_dma)(struct uart_8250_port *p); 23 24 /* Filter function */ 25 dma_filter_fn fn; 26 /* Parameter to the filter function */ 27 void *rx_param; 28 void *tx_param; 29 30 struct dma_slave_config rxconf; 31 struct dma_slave_config txconf; 32 33 struct dma_chan *rxchan; 34 struct dma_chan *txchan; 35 36 dma_addr_t rx_addr; 37 dma_addr_t tx_addr; 38 39 dma_cookie_t rx_cookie; 40 dma_cookie_t tx_cookie; 41 42 void *rx_buf; 43 44 size_t rx_size; 45 size_t tx_size; 46 47 unsigned char tx_running; 48 unsigned char tx_err; 49 unsigned char rx_running; 50 }; 51 52 struct old_serial_port { 53 unsigned int uart; 54 unsigned int baud_base; 55 unsigned int port; 56 unsigned int irq; 57 upf_t flags; 58 unsigned char io_type; 59 unsigned char __iomem *iomem_base; 60 unsigned short iomem_reg_shift; 61 }; 62 63 struct serial8250_config { 64 const char *name; 65 unsigned short fifo_size; 66 unsigned short tx_loadsz; 67 unsigned char fcr; 68 unsigned char rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE]; 69 unsigned int flags; 70 }; 71 72 #define UART_CAP_FIFO (1 << 8) /* UART has FIFO */ 73 #define UART_CAP_EFR (1 << 9) /* UART has EFR */ 74 #define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */ 75 #define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */ 76 #define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */ 77 #define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */ 78 #define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */ 79 #define UART_CAP_RPM (1 << 15) /* Runtime PM is active while idle */ 80 81 #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */ 82 #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ 83 #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */ 84 #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ 85 #define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */ 86 87 88 #ifdef CONFIG_SERIAL_8250_SHARE_IRQ 89 #define SERIAL8250_SHARE_IRQS 1 90 #else 91 #define SERIAL8250_SHARE_IRQS 0 92 #endif 93 94 #define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \ 95 { \ 96 .iobase = _base, \ 97 .irq = _irq, \ 98 .uartclk = 1843200, \ 99 .iotype = UPIO_PORT, \ 100 .flags = UPF_BOOT_AUTOCONF | (_flags), \ 101 } 102 103 #define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0) 104 105 106 static inline int serial_in(struct uart_8250_port *up, int offset) 107 { 108 return up->port.serial_in(&up->port, offset); 109 } 110 111 static inline void serial_out(struct uart_8250_port *up, int offset, int value) 112 { 113 up->port.serial_out(&up->port, offset, value); 114 } 115 116 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p); 117 118 static inline int serial_dl_read(struct uart_8250_port *up) 119 { 120 return up->dl_read(up); 121 } 122 123 static inline void serial_dl_write(struct uart_8250_port *up, int value) 124 { 125 up->dl_write(up, value); 126 } 127 128 struct uart_8250_port *serial8250_get_port(int line); 129 void serial8250_rpm_get(struct uart_8250_port *p); 130 void serial8250_rpm_put(struct uart_8250_port *p); 131 int serial8250_em485_init(struct uart_8250_port *p); 132 void serial8250_em485_destroy(struct uart_8250_port *p); 133 134 static inline void serial8250_out_MCR(struct uart_8250_port *up, int value) 135 { 136 int mctrl_gpio = 0; 137 138 serial_out(up, UART_MCR, value); 139 140 if (value & UART_MCR_RTS) 141 mctrl_gpio |= TIOCM_RTS; 142 if (value & UART_MCR_DTR) 143 mctrl_gpio |= TIOCM_DTR; 144 145 mctrl_gpio_set(up->gpios, mctrl_gpio); 146 } 147 148 static inline int serial8250_in_MCR(struct uart_8250_port *up) 149 { 150 int mctrl, mctrl_gpio = 0; 151 152 mctrl = serial_in(up, UART_MCR); 153 154 /* save current MCR values */ 155 if (mctrl & UART_MCR_RTS) 156 mctrl_gpio |= TIOCM_RTS; 157 if (mctrl & UART_MCR_DTR) 158 mctrl_gpio |= TIOCM_DTR; 159 160 mctrl_gpio = mctrl_gpio_get_outputs(up->gpios, &mctrl_gpio); 161 162 if (mctrl_gpio & TIOCM_RTS) 163 mctrl |= UART_MCR_RTS; 164 else 165 mctrl &= ~UART_MCR_RTS; 166 167 if (mctrl_gpio & TIOCM_DTR) 168 mctrl |= UART_MCR_DTR; 169 else 170 mctrl &= ~UART_MCR_DTR; 171 172 return mctrl; 173 } 174 175 #if defined(__alpha__) && !defined(CONFIG_PCI) 176 /* 177 * Digital did something really horribly wrong with the OUT1 and OUT2 178 * lines on at least some ALPHA's. The failure mode is that if either 179 * is cleared, the machine locks up with endless interrupts. 180 */ 181 #define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 | UART_MCR_OUT1) 182 #else 183 #define ALPHA_KLUDGE_MCR 0 184 #endif 185 186 #ifdef CONFIG_SERIAL_8250_PNP 187 int serial8250_pnp_init(void); 188 void serial8250_pnp_exit(void); 189 #else 190 static inline int serial8250_pnp_init(void) { return 0; } 191 static inline void serial8250_pnp_exit(void) { } 192 #endif 193 194 #ifdef CONFIG_SERIAL_8250_FINTEK 195 int fintek_8250_probe(struct uart_8250_port *uart); 196 #else 197 static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; } 198 #endif 199 200 #ifdef CONFIG_ARCH_OMAP1 201 static inline int is_omap1_8250(struct uart_8250_port *pt) 202 { 203 int res; 204 205 switch (pt->port.mapbase) { 206 case OMAP1_UART1_BASE: 207 case OMAP1_UART2_BASE: 208 case OMAP1_UART3_BASE: 209 res = 1; 210 break; 211 default: 212 res = 0; 213 break; 214 } 215 216 return res; 217 } 218 219 static inline int is_omap1510_8250(struct uart_8250_port *pt) 220 { 221 if (!cpu_is_omap1510()) 222 return 0; 223 224 return is_omap1_8250(pt); 225 } 226 #else 227 static inline int is_omap1_8250(struct uart_8250_port *pt) 228 { 229 return 0; 230 } 231 static inline int is_omap1510_8250(struct uart_8250_port *pt) 232 { 233 return 0; 234 } 235 #endif 236 237 #ifdef CONFIG_SERIAL_8250_DMA 238 extern int serial8250_tx_dma(struct uart_8250_port *); 239 extern int serial8250_rx_dma(struct uart_8250_port *); 240 extern void serial8250_rx_dma_flush(struct uart_8250_port *); 241 extern int serial8250_request_dma(struct uart_8250_port *); 242 extern void serial8250_release_dma(struct uart_8250_port *); 243 #else 244 static inline int serial8250_tx_dma(struct uart_8250_port *p) 245 { 246 return -1; 247 } 248 static inline int serial8250_rx_dma(struct uart_8250_port *p) 249 { 250 return -1; 251 } 252 static inline void serial8250_rx_dma_flush(struct uart_8250_port *p) { } 253 static inline int serial8250_request_dma(struct uart_8250_port *p) 254 { 255 return -1; 256 } 257 static inline void serial8250_release_dma(struct uart_8250_port *p) { } 258 #endif 259 260 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) 261 { 262 unsigned char status; 263 264 status = serial_in(up, 0x04); /* EXCR2 */ 265 #define PRESL(x) ((x) & 0x30) 266 if (PRESL(status) == 0x10) { 267 /* already in high speed mode */ 268 return 0; 269 } else { 270 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ 271 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ 272 serial_out(up, 0x04, status); 273 } 274 return 1; 275 } 276 277 static inline int serial_index(struct uart_port *port) 278 { 279 return port->minor - 64; 280 } 281